1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
66 // described for so_imm_notSext def below, with sign extension from 16
68 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
69 APInt apIntN = N->getAPIntValue();
70 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
71 return CurDAG->getTargetConstant(~N16bitSignExt, MVT::i32);
74 // t2_so_imm - Match a 32-bit immediate operand, which is an
75 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
76 // immediate splatted into multiple bytes of the word.
77 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
78 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
79 return ARM_AM::getT2SOImmVal(Imm) != -1;
81 let ParserMatchClass = t2_so_imm_asmoperand;
82 let EncoderMethod = "getT2SOImmOpValue";
83 let DecoderMethod = "DecodeT2SOImm";
86 // t2_so_imm_not - Match an immediate that is a complement
88 // Note: this pattern doesn't require an encoder method and such, as it's
89 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
90 // is handled by the destination instructions, which use t2_so_imm.
91 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
92 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
93 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
94 }], t2_so_imm_not_XFORM> {
95 let ParserMatchClass = t2_so_imm_not_asmoperand;
98 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
99 // if the upper 16 bits are zero.
100 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
101 APInt apIntN = N->getAPIntValue();
102 if (!apIntN.isIntN(16)) return false;
103 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
104 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
105 }], t2_so_imm_notSext16_XFORM> {
106 let ParserMatchClass = t2_so_imm_not_asmoperand;
109 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
110 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
111 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
112 int64_t Value = -(int)N->getZExtValue();
113 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
114 }], t2_so_imm_neg_XFORM> {
115 let ParserMatchClass = t2_so_imm_neg_asmoperand;
118 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
119 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
120 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
121 return Imm >= 0 && Imm < 4096;
123 let ParserMatchClass = imm0_4095_asmoperand;
126 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
127 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
128 return (uint32_t)(-N->getZExtValue()) < 4096;
130 let ParserMatchClass = imm0_4095_neg_asmoperand;
133 def imm1_255_neg : PatLeaf<(i32 imm), [{
134 uint32_t Val = -N->getZExtValue();
135 return (Val > 0 && Val < 255);
138 def imm0_255_not : PatLeaf<(i32 imm), [{
139 return (uint32_t)(~N->getZExtValue()) < 255;
142 def lo5AllOne : PatLeaf<(i32 imm), [{
143 // Returns true if all low 5-bits are 1.
144 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
147 // Define Thumb2 specific addressing modes.
149 // t2addrmode_imm12 := reg + imm12
150 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
151 def t2addrmode_imm12 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
153 let PrintMethod = "printAddrModeImm12Operand<false>";
154 let EncoderMethod = "getAddrModeImm12OpValue";
155 let DecoderMethod = "DecodeT2AddrModeImm12";
156 let ParserMatchClass = t2addrmode_imm12_asmoperand;
157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
160 // t2ldrlabel := imm12
161 def t2ldrlabel : Operand<i32> {
162 let EncoderMethod = "getAddrModeImm12OpValue";
163 let PrintMethod = "printThumbLdrLabelOperand";
166 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
167 def t2ldr_pcrel_imm12 : Operand<i32> {
168 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
169 // used for assembler pseudo instruction and maps to t2ldrlabel, so
170 // doesn't need encoder or print methods of its own.
173 // ADR instruction labels.
174 def t2adrlabel : Operand<i32> {
175 let EncoderMethod = "getT2AdrLabelOpValue";
176 let PrintMethod = "printAdrLabelOperand<0>";
179 // t2addrmode_posimm8 := reg + imm8
180 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
181 def t2addrmode_posimm8 : Operand<i32> {
182 let PrintMethod = "printT2AddrModeImm8Operand<false>";
183 let EncoderMethod = "getT2AddrModeImm8OpValue";
184 let DecoderMethod = "DecodeT2AddrModeImm8";
185 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
189 // t2addrmode_negimm8 := reg - imm8
190 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
191 def t2addrmode_negimm8 : Operand<i32>,
192 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
193 let PrintMethod = "printT2AddrModeImm8Operand<false>";
194 let EncoderMethod = "getT2AddrModeImm8OpValue";
195 let DecoderMethod = "DecodeT2AddrModeImm8";
196 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
197 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
200 // t2addrmode_imm8 := reg +/- imm8
201 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
202 class T2AddrMode_Imm8 : Operand<i32>,
203 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
204 let EncoderMethod = "getT2AddrModeImm8OpValue";
205 let DecoderMethod = "DecodeT2AddrModeImm8";
206 let ParserMatchClass = MemImm8OffsetAsmOperand;
207 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
210 def t2addrmode_imm8 : T2AddrMode_Imm8 {
211 let PrintMethod = "printT2AddrModeImm8Operand<false>";
214 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
215 let PrintMethod = "printT2AddrModeImm8Operand<true>";
218 def t2am_imm8_offset : Operand<i32>,
219 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
220 [], [SDNPWantRoot]> {
221 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
222 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
223 let DecoderMethod = "DecodeT2Imm8";
226 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
227 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
228 class T2AddrMode_Imm8s4 : Operand<i32> {
229 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
230 let DecoderMethod = "DecodeT2AddrModeImm8s4";
231 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
232 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
235 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
236 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
239 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
240 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
243 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
244 def t2am_imm8s4_offset : Operand<i32> {
245 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
246 let EncoderMethod = "getT2Imm8s4OpValue";
247 let DecoderMethod = "DecodeT2Imm8S4";
250 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
251 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
252 let Name = "MemImm0_1020s4Offset";
254 def t2addrmode_imm0_1020s4 : Operand<i32>,
255 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
256 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
257 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
258 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
259 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
260 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
263 // t2addrmode_so_reg := reg + (reg << imm2)
264 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
265 def t2addrmode_so_reg : Operand<i32>,
266 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
267 let PrintMethod = "printT2AddrModeSoRegOperand";
268 let EncoderMethod = "getT2AddrModeSORegOpValue";
269 let DecoderMethod = "DecodeT2AddrModeSOReg";
270 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
271 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
274 // Addresses for the TBB/TBH instructions.
275 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
276 def addrmode_tbb : Operand<i32> {
277 let PrintMethod = "printAddrModeTBB";
278 let ParserMatchClass = addrmode_tbb_asmoperand;
279 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
281 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
282 def addrmode_tbh : Operand<i32> {
283 let PrintMethod = "printAddrModeTBH";
284 let ParserMatchClass = addrmode_tbh_asmoperand;
285 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
288 //===----------------------------------------------------------------------===//
289 // Multiclass helpers...
293 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
294 string opc, string asm, list<dag> pattern>
295 : T2I<oops, iops, itin, opc, asm, pattern> {
300 let Inst{26} = imm{11};
301 let Inst{14-12} = imm{10-8};
302 let Inst{7-0} = imm{7-0};
306 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
307 string opc, string asm, list<dag> pattern>
308 : T2sI<oops, iops, itin, opc, asm, pattern> {
314 let Inst{26} = imm{11};
315 let Inst{14-12} = imm{10-8};
316 let Inst{7-0} = imm{7-0};
319 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
320 string opc, string asm, list<dag> pattern>
321 : T2I<oops, iops, itin, opc, asm, pattern> {
325 let Inst{19-16} = Rn;
326 let Inst{26} = imm{11};
327 let Inst{14-12} = imm{10-8};
328 let Inst{7-0} = imm{7-0};
332 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
333 string opc, string asm, list<dag> pattern>
334 : T2I<oops, iops, itin, opc, asm, pattern> {
339 let Inst{3-0} = ShiftedRm{3-0};
340 let Inst{5-4} = ShiftedRm{6-5};
341 let Inst{14-12} = ShiftedRm{11-9};
342 let Inst{7-6} = ShiftedRm{8-7};
345 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
346 string opc, string asm, list<dag> pattern>
347 : T2sI<oops, iops, itin, opc, asm, pattern> {
352 let Inst{3-0} = ShiftedRm{3-0};
353 let Inst{5-4} = ShiftedRm{6-5};
354 let Inst{14-12} = ShiftedRm{11-9};
355 let Inst{7-6} = ShiftedRm{8-7};
358 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
359 string opc, string asm, list<dag> pattern>
360 : T2I<oops, iops, itin, opc, asm, pattern> {
364 let Inst{19-16} = Rn;
365 let Inst{3-0} = ShiftedRm{3-0};
366 let Inst{5-4} = ShiftedRm{6-5};
367 let Inst{14-12} = ShiftedRm{11-9};
368 let Inst{7-6} = ShiftedRm{8-7};
371 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
372 string opc, string asm, list<dag> pattern>
373 : T2I<oops, iops, itin, opc, asm, pattern> {
381 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
382 string opc, string asm, list<dag> pattern>
383 : T2sI<oops, iops, itin, opc, asm, pattern> {
391 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
392 string opc, string asm, list<dag> pattern>
393 : T2I<oops, iops, itin, opc, asm, pattern> {
397 let Inst{19-16} = Rn;
402 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : T2I<oops, iops, itin, opc, asm, pattern> {
410 let Inst{19-16} = Rn;
411 let Inst{26} = imm{11};
412 let Inst{14-12} = imm{10-8};
413 let Inst{7-0} = imm{7-0};
416 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
417 string opc, string asm, list<dag> pattern>
418 : T2sI<oops, iops, itin, opc, asm, pattern> {
424 let Inst{19-16} = Rn;
425 let Inst{26} = imm{11};
426 let Inst{14-12} = imm{10-8};
427 let Inst{7-0} = imm{7-0};
430 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
431 string opc, string asm, list<dag> pattern>
432 : T2I<oops, iops, itin, opc, asm, pattern> {
439 let Inst{14-12} = imm{4-2};
440 let Inst{7-6} = imm{1-0};
443 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
444 string opc, string asm, list<dag> pattern>
445 : T2sI<oops, iops, itin, opc, asm, pattern> {
452 let Inst{14-12} = imm{4-2};
453 let Inst{7-6} = imm{1-0};
456 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
457 string opc, string asm, list<dag> pattern>
458 : T2I<oops, iops, itin, opc, asm, pattern> {
464 let Inst{19-16} = Rn;
468 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : T2sI<oops, iops, itin, opc, asm, pattern> {
476 let Inst{19-16} = Rn;
480 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
481 string opc, string asm, list<dag> pattern>
482 : T2I<oops, iops, itin, opc, asm, pattern> {
488 let Inst{19-16} = Rn;
489 let Inst{3-0} = ShiftedRm{3-0};
490 let Inst{5-4} = ShiftedRm{6-5};
491 let Inst{14-12} = ShiftedRm{11-9};
492 let Inst{7-6} = ShiftedRm{8-7};
495 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
496 string opc, string asm, list<dag> pattern>
497 : T2sI<oops, iops, itin, opc, asm, pattern> {
503 let Inst{19-16} = Rn;
504 let Inst{3-0} = ShiftedRm{3-0};
505 let Inst{5-4} = ShiftedRm{6-5};
506 let Inst{14-12} = ShiftedRm{11-9};
507 let Inst{7-6} = ShiftedRm{8-7};
510 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
511 string opc, string asm, list<dag> pattern>
512 : T2I<oops, iops, itin, opc, asm, pattern> {
518 let Inst{19-16} = Rn;
519 let Inst{15-12} = Ra;
524 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
525 dag oops, dag iops, InstrItinClass itin,
526 string opc, string asm, list<dag> pattern>
527 : T2I<oops, iops, itin, opc, asm, pattern> {
533 let Inst{31-23} = 0b111110111;
534 let Inst{22-20} = opc22_20;
535 let Inst{19-16} = Rn;
536 let Inst{15-12} = RdLo;
537 let Inst{11-8} = RdHi;
538 let Inst{7-4} = opc7_4;
541 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
542 dag oops, dag iops, InstrItinClass itin,
543 string opc, string asm, list<dag> pattern>
544 : T2I<oops, iops, itin, opc, asm, pattern> {
550 let Inst{31-23} = 0b111110111;
551 let Inst{22-20} = opc22_20;
552 let Inst{19-16} = Rn;
553 let Inst{15-12} = RdLo;
554 let Inst{11-8} = RdHi;
555 let Inst{7-4} = opc7_4;
560 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
561 /// binary operation that produces a value. These are predicable and can be
562 /// changed to modify CPSR.
563 multiclass T2I_bin_irs<bits<4> opcod, string opc,
564 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
565 PatFrag opnode, bit Commutable = 0,
568 def ri : T2sTwoRegImm<
569 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
570 opc, "\t$Rd, $Rn, $imm",
571 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
572 Sched<[WriteALU, ReadALU]> {
573 let Inst{31-27} = 0b11110;
575 let Inst{24-21} = opcod;
579 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
580 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
581 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
582 Sched<[WriteALU, ReadALU, ReadALU]> {
583 let isCommutable = Commutable;
584 let Inst{31-27} = 0b11101;
585 let Inst{26-25} = 0b01;
586 let Inst{24-21} = opcod;
587 let Inst{14-12} = 0b000; // imm3
588 let Inst{7-6} = 0b00; // imm2
589 let Inst{5-4} = 0b00; // type
592 def rs : T2sTwoRegShiftedReg<
593 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
594 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
595 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
596 Sched<[WriteALUsi, ReadALU]> {
597 let Inst{31-27} = 0b11101;
598 let Inst{26-25} = 0b01;
599 let Inst{24-21} = opcod;
601 // Assembly aliases for optional destination operand when it's the same
602 // as the source operand.
603 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
604 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
605 t2_so_imm:$imm, pred:$p,
607 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
608 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
611 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
612 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
613 t2_so_reg:$shift, pred:$p,
617 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
618 // the ".w" suffix to indicate that they are wide.
619 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
620 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
621 PatFrag opnode, bit Commutable = 0> :
622 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
623 // Assembler aliases w/ the ".w" suffix.
624 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
625 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
627 // Assembler aliases w/o the ".w" suffix.
628 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
629 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
631 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
632 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
633 pred:$p, cc_out:$s)>;
635 // and with the optional destination operand, too.
636 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
637 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
638 pred:$p, cc_out:$s)>;
639 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
640 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
642 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
643 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
644 pred:$p, cc_out:$s)>;
647 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
648 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
649 /// it is equivalent to the T2I_bin_irs counterpart.
650 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
652 def ri : T2sTwoRegImm<
653 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
654 opc, ".w\t$Rd, $Rn, $imm",
655 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
656 Sched<[WriteALU, ReadALU]> {
657 let Inst{31-27} = 0b11110;
659 let Inst{24-21} = opcod;
663 def rr : T2sThreeReg<
664 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
665 opc, "\t$Rd, $Rn, $Rm",
666 [/* For disassembly only; pattern left blank */]>,
667 Sched<[WriteALU, ReadALU, ReadALU]> {
668 let Inst{31-27} = 0b11101;
669 let Inst{26-25} = 0b01;
670 let Inst{24-21} = opcod;
671 let Inst{14-12} = 0b000; // imm3
672 let Inst{7-6} = 0b00; // imm2
673 let Inst{5-4} = 0b00; // type
676 def rs : T2sTwoRegShiftedReg<
677 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
678 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
679 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
680 Sched<[WriteALUsi, ReadALU]> {
681 let Inst{31-27} = 0b11101;
682 let Inst{26-25} = 0b01;
683 let Inst{24-21} = opcod;
687 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
688 /// instruction modifies the CPSR register.
690 /// These opcodes will be converted to the real non-S opcodes by
691 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
692 let hasPostISelHook = 1, Defs = [CPSR] in {
693 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
694 InstrItinClass iis, PatFrag opnode,
695 bit Commutable = 0> {
697 def ri : t2PseudoInst<(outs rGPR:$Rd),
698 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
700 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
702 Sched<[WriteALU, ReadALU]>;
704 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
706 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
708 Sched<[WriteALU, ReadALU, ReadALU]> {
709 let isCommutable = Commutable;
712 def rs : t2PseudoInst<(outs rGPR:$Rd),
713 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
715 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
716 t2_so_reg:$ShiftedRm))]>,
717 Sched<[WriteALUsi, ReadALUsr]>;
721 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
722 /// operands are reversed.
723 let hasPostISelHook = 1, Defs = [CPSR] in {
724 multiclass T2I_rbin_s_is<PatFrag opnode> {
726 def ri : t2PseudoInst<(outs rGPR:$Rd),
727 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
729 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
731 Sched<[WriteALU, ReadALU]>;
733 def rs : t2PseudoInst<(outs rGPR:$Rd),
734 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
736 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
738 Sched<[WriteALUsi, ReadALU]>;
742 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
743 /// patterns for a binary operation that produces a value.
744 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
745 bit Commutable = 0> {
747 // The register-immediate version is re-materializable. This is useful
748 // in particular for taking the address of a local.
749 let isReMaterializable = 1 in {
750 def ri : T2sTwoRegImm<
751 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
752 opc, ".w\t$Rd, $Rn, $imm",
753 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
754 Sched<[WriteALU, ReadALU]> {
755 let Inst{31-27} = 0b11110;
758 let Inst{23-21} = op23_21;
764 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
765 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
766 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
767 Sched<[WriteALU, ReadALU]> {
771 let Inst{31-27} = 0b11110;
772 let Inst{26} = imm{11};
773 let Inst{25-24} = 0b10;
774 let Inst{23-21} = op23_21;
775 let Inst{20} = 0; // The S bit.
776 let Inst{19-16} = Rn;
778 let Inst{14-12} = imm{10-8};
780 let Inst{7-0} = imm{7-0};
783 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
784 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
785 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
786 Sched<[WriteALU, ReadALU, ReadALU]> {
787 let isCommutable = Commutable;
788 let Inst{31-27} = 0b11101;
789 let Inst{26-25} = 0b01;
791 let Inst{23-21} = op23_21;
792 let Inst{14-12} = 0b000; // imm3
793 let Inst{7-6} = 0b00; // imm2
794 let Inst{5-4} = 0b00; // type
797 def rs : T2sTwoRegShiftedReg<
798 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
799 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
800 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
801 Sched<[WriteALUsi, ReadALU]> {
802 let Inst{31-27} = 0b11101;
803 let Inst{26-25} = 0b01;
805 let Inst{23-21} = op23_21;
809 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
810 /// for a binary operation that produces a value and use the carry
811 /// bit. It's not predicable.
812 let Defs = [CPSR], Uses = [CPSR] in {
813 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
814 bit Commutable = 0> {
816 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
817 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
818 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
819 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
820 let Inst{31-27} = 0b11110;
822 let Inst{24-21} = opcod;
826 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
827 opc, ".w\t$Rd, $Rn, $Rm",
828 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
829 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
830 let isCommutable = Commutable;
831 let Inst{31-27} = 0b11101;
832 let Inst{26-25} = 0b01;
833 let Inst{24-21} = opcod;
834 let Inst{14-12} = 0b000; // imm3
835 let Inst{7-6} = 0b00; // imm2
836 let Inst{5-4} = 0b00; // type
839 def rs : T2sTwoRegShiftedReg<
840 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
841 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
842 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
843 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
844 let Inst{31-27} = 0b11101;
845 let Inst{26-25} = 0b01;
846 let Inst{24-21} = opcod;
851 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
852 // rotate operation that produces a value.
853 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
855 def ri : T2sTwoRegShiftImm<
856 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
857 opc, ".w\t$Rd, $Rm, $imm",
858 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
860 let Inst{31-27} = 0b11101;
861 let Inst{26-21} = 0b010010;
862 let Inst{19-16} = 0b1111; // Rn
863 let Inst{5-4} = opcod;
866 def rr : T2sThreeReg<
867 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
868 opc, ".w\t$Rd, $Rn, $Rm",
869 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
871 let Inst{31-27} = 0b11111;
872 let Inst{26-23} = 0b0100;
873 let Inst{22-21} = opcod;
874 let Inst{15-12} = 0b1111;
875 let Inst{7-4} = 0b0000;
878 // Optional destination register
879 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
880 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
882 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
883 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
886 // Assembler aliases w/o the ".w" suffix.
887 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
888 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
890 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
891 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
894 // and with the optional destination operand, too.
895 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
896 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
898 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
899 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
903 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
904 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
905 /// a explicit result, only implicitly set CPSR.
906 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
907 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
909 let isCompare = 1, Defs = [CPSR] in {
911 def ri : T2OneRegCmpImm<
912 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
913 opc, ".w\t$Rn, $imm",
914 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
915 let Inst{31-27} = 0b11110;
917 let Inst{24-21} = opcod;
918 let Inst{20} = 1; // The S bit.
920 let Inst{11-8} = 0b1111; // Rd
923 def rr : T2TwoRegCmp<
924 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
926 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
927 let Inst{31-27} = 0b11101;
928 let Inst{26-25} = 0b01;
929 let Inst{24-21} = opcod;
930 let Inst{20} = 1; // The S bit.
931 let Inst{14-12} = 0b000; // imm3
932 let Inst{11-8} = 0b1111; // Rd
933 let Inst{7-6} = 0b00; // imm2
934 let Inst{5-4} = 0b00; // type
937 def rs : T2OneRegCmpShiftedReg<
938 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
939 opc, ".w\t$Rn, $ShiftedRm",
940 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
941 Sched<[WriteCMPsi]> {
942 let Inst{31-27} = 0b11101;
943 let Inst{26-25} = 0b01;
944 let Inst{24-21} = opcod;
945 let Inst{20} = 1; // The S bit.
946 let Inst{11-8} = 0b1111; // Rd
950 // Assembler aliases w/o the ".w" suffix.
951 // No alias here for 'rr' version as not all instantiations of this
952 // multiclass want one (CMP in particular, does not).
953 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
954 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
955 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
956 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
959 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
960 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
961 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
963 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
964 opc, ".w\t$Rt, $addr",
965 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
968 let Inst{31-25} = 0b1111100;
969 let Inst{24} = signed;
971 let Inst{22-21} = opcod;
972 let Inst{20} = 1; // load
973 let Inst{19-16} = addr{16-13}; // Rn
974 let Inst{15-12} = Rt;
975 let Inst{11-0} = addr{11-0}; // imm
977 let DecoderMethod = "DecodeT2LoadImm12";
979 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
981 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
984 let Inst{31-27} = 0b11111;
985 let Inst{26-25} = 0b00;
986 let Inst{24} = signed;
988 let Inst{22-21} = opcod;
989 let Inst{20} = 1; // load
990 let Inst{19-16} = addr{12-9}; // Rn
991 let Inst{15-12} = Rt;
993 // Offset: index==TRUE, wback==FALSE
994 let Inst{10} = 1; // The P bit.
995 let Inst{9} = addr{8}; // U
996 let Inst{8} = 0; // The W bit.
997 let Inst{7-0} = addr{7-0}; // imm
999 let DecoderMethod = "DecodeT2LoadImm8";
1001 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1002 opc, ".w\t$Rt, $addr",
1003 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
1004 let Inst{31-27} = 0b11111;
1005 let Inst{26-25} = 0b00;
1006 let Inst{24} = signed;
1008 let Inst{22-21} = opcod;
1009 let Inst{20} = 1; // load
1010 let Inst{11-6} = 0b000000;
1013 let Inst{15-12} = Rt;
1016 let Inst{19-16} = addr{9-6}; // Rn
1017 let Inst{3-0} = addr{5-2}; // Rm
1018 let Inst{5-4} = addr{1-0}; // imm
1020 let DecoderMethod = "DecodeT2LoadShift";
1023 // pci variant is very similar to i12, but supports negative offsets
1025 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1026 opc, ".w\t$Rt, $addr",
1027 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
1028 let isReMaterializable = 1;
1029 let Inst{31-27} = 0b11111;
1030 let Inst{26-25} = 0b00;
1031 let Inst{24} = signed;
1032 let Inst{22-21} = opcod;
1033 let Inst{20} = 1; // load
1034 let Inst{19-16} = 0b1111; // Rn
1037 let Inst{15-12} = Rt{3-0};
1040 let Inst{23} = addr{12}; // add = (U == '1')
1041 let Inst{11-0} = addr{11-0};
1043 let DecoderMethod = "DecodeT2LoadLabel";
1047 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1048 multiclass T2I_st<bits<2> opcod, string opc,
1049 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1051 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1052 opc, ".w\t$Rt, $addr",
1053 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1054 let Inst{31-27} = 0b11111;
1055 let Inst{26-23} = 0b0001;
1056 let Inst{22-21} = opcod;
1057 let Inst{20} = 0; // !load
1060 let Inst{15-12} = Rt;
1063 let addr{12} = 1; // add = TRUE
1064 let Inst{19-16} = addr{16-13}; // Rn
1065 let Inst{23} = addr{12}; // U
1066 let Inst{11-0} = addr{11-0}; // imm
1068 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1069 opc, "\t$Rt, $addr",
1070 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1071 let Inst{31-27} = 0b11111;
1072 let Inst{26-23} = 0b0000;
1073 let Inst{22-21} = opcod;
1074 let Inst{20} = 0; // !load
1076 // Offset: index==TRUE, wback==FALSE
1077 let Inst{10} = 1; // The P bit.
1078 let Inst{8} = 0; // The W bit.
1081 let Inst{15-12} = Rt;
1084 let Inst{19-16} = addr{12-9}; // Rn
1085 let Inst{9} = addr{8}; // U
1086 let Inst{7-0} = addr{7-0}; // imm
1088 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1089 opc, ".w\t$Rt, $addr",
1090 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1091 let Inst{31-27} = 0b11111;
1092 let Inst{26-23} = 0b0000;
1093 let Inst{22-21} = opcod;
1094 let Inst{20} = 0; // !load
1095 let Inst{11-6} = 0b000000;
1098 let Inst{15-12} = Rt;
1101 let Inst{19-16} = addr{9-6}; // Rn
1102 let Inst{3-0} = addr{5-2}; // Rm
1103 let Inst{5-4} = addr{1-0}; // imm
1107 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1108 /// register and one whose operand is a register rotated by 8/16/24.
1109 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1110 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1111 opc, ".w\t$Rd, $Rm$rot",
1112 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1113 Requires<[IsThumb2]> {
1114 let Inst{31-27} = 0b11111;
1115 let Inst{26-23} = 0b0100;
1116 let Inst{22-20} = opcod;
1117 let Inst{19-16} = 0b1111; // Rn
1118 let Inst{15-12} = 0b1111;
1122 let Inst{5-4} = rot{1-0}; // rotate
1125 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1126 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1127 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1128 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1129 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1130 Requires<[HasT2ExtractPack, IsThumb2]> {
1132 let Inst{31-27} = 0b11111;
1133 let Inst{26-23} = 0b0100;
1134 let Inst{22-20} = opcod;
1135 let Inst{19-16} = 0b1111; // Rn
1136 let Inst{15-12} = 0b1111;
1138 let Inst{5-4} = rot;
1141 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1143 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1144 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1145 opc, "\t$Rd, $Rm$rot", []>,
1146 Requires<[IsThumb2, HasT2ExtractPack]> {
1148 let Inst{31-27} = 0b11111;
1149 let Inst{26-23} = 0b0100;
1150 let Inst{22-20} = opcod;
1151 let Inst{19-16} = 0b1111; // Rn
1152 let Inst{15-12} = 0b1111;
1154 let Inst{5-4} = rot;
1157 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1158 /// register and one whose operand is a register rotated by 8/16/24.
1159 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1160 : T2ThreeReg<(outs rGPR:$Rd),
1161 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1162 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1163 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1164 Requires<[HasT2ExtractPack, IsThumb2]> {
1166 let Inst{31-27} = 0b11111;
1167 let Inst{26-23} = 0b0100;
1168 let Inst{22-20} = opcod;
1169 let Inst{15-12} = 0b1111;
1171 let Inst{5-4} = rot;
1174 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1175 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1176 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1178 let Inst{31-27} = 0b11111;
1179 let Inst{26-23} = 0b0100;
1180 let Inst{22-20} = opcod;
1181 let Inst{15-12} = 0b1111;
1183 let Inst{5-4} = rot;
1186 //===----------------------------------------------------------------------===//
1188 //===----------------------------------------------------------------------===//
1190 //===----------------------------------------------------------------------===//
1191 // Miscellaneous Instructions.
1194 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1195 string asm, list<dag> pattern>
1196 : T2XI<oops, iops, itin, asm, pattern> {
1200 let Inst{11-8} = Rd;
1201 let Inst{26} = label{11};
1202 let Inst{14-12} = label{10-8};
1203 let Inst{7-0} = label{7-0};
1206 // LEApcrel - Load a pc-relative address into a register without offending the
1208 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1209 (ins t2adrlabel:$addr, pred:$p),
1210 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1211 Sched<[WriteALU, ReadALU]> {
1212 let Inst{31-27} = 0b11110;
1213 let Inst{25-24} = 0b10;
1214 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1217 let Inst{19-16} = 0b1111; // Rn
1222 let Inst{11-8} = Rd;
1223 let Inst{23} = addr{12};
1224 let Inst{21} = addr{12};
1225 let Inst{26} = addr{11};
1226 let Inst{14-12} = addr{10-8};
1227 let Inst{7-0} = addr{7-0};
1229 let DecoderMethod = "DecodeT2Adr";
1232 let neverHasSideEffects = 1, isReMaterializable = 1 in
1233 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1234 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1235 let hasSideEffects = 1 in
1236 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1237 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1239 []>, Sched<[WriteALU, ReadALU]>;
1242 //===----------------------------------------------------------------------===//
1243 // Load / store Instructions.
1247 let canFoldAsLoad = 1, isReMaterializable = 1 in
1248 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1249 UnOpFrag<(load node:$Src)>>;
1251 // Loads with zero extension
1252 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1253 GPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1254 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1255 GPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1257 // Loads with sign extension
1258 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1259 GPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1260 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1261 GPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1263 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1265 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1266 (ins t2addrmode_imm8s4:$addr),
1267 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1268 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1270 // zextload i1 -> zextload i8
1271 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1272 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1273 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1274 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1275 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1276 (t2LDRBs t2addrmode_so_reg:$addr)>;
1277 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1278 (t2LDRBpci tconstpool:$addr)>;
1280 // extload -> zextload
1281 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1283 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1284 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1285 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1286 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1287 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1288 (t2LDRBs t2addrmode_so_reg:$addr)>;
1289 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1290 (t2LDRBpci tconstpool:$addr)>;
1292 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1293 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1294 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1295 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1296 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1297 (t2LDRBs t2addrmode_so_reg:$addr)>;
1298 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1299 (t2LDRBpci tconstpool:$addr)>;
1301 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1302 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1303 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1304 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1305 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1306 (t2LDRHs t2addrmode_so_reg:$addr)>;
1307 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1308 (t2LDRHpci tconstpool:$addr)>;
1310 // FIXME: The destination register of the loads and stores can't be PC, but
1311 // can be SP. We need another regclass (similar to rGPR) to represent
1312 // that. Not a pressing issue since these are selected manually,
1317 let mayLoad = 1, neverHasSideEffects = 1 in {
1318 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1319 (ins t2addrmode_imm8_pre:$addr),
1320 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1321 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1323 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1324 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1325 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1326 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1328 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1329 (ins t2addrmode_imm8_pre:$addr),
1330 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1331 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1333 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1334 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1335 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1336 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1338 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1339 (ins t2addrmode_imm8_pre:$addr),
1340 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1341 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1343 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1344 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1345 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1346 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1348 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1349 (ins t2addrmode_imm8_pre:$addr),
1350 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1351 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1354 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1355 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1356 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1357 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1359 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1360 (ins t2addrmode_imm8_pre:$addr),
1361 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1362 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1365 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1366 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1367 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1368 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1369 } // mayLoad = 1, neverHasSideEffects = 1
1371 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1372 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1373 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1374 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1375 "\t$Rt, $addr", []> {
1378 let Inst{31-27} = 0b11111;
1379 let Inst{26-25} = 0b00;
1380 let Inst{24} = signed;
1382 let Inst{22-21} = type;
1383 let Inst{20} = 1; // load
1384 let Inst{19-16} = addr{12-9};
1385 let Inst{15-12} = Rt;
1387 let Inst{10-8} = 0b110; // PUW.
1388 let Inst{7-0} = addr{7-0};
1390 let DecoderMethod = "DecodeT2LoadT";
1393 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1394 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1395 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1396 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1397 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1399 class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops, string opc, string asm, list<dag> pattern>
1400 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc, asm, "", pattern> {
1404 let Inst{31-27} = 0b11101;
1405 let Inst{26-24} = 0b000;
1406 let Inst{23-20} = bits23_20;
1407 let Inst{11-6} = 0b111110;
1408 let Inst{5-4} = bit54;
1409 let Inst{3-0} = 0b1111;
1411 // Encode instruction operands
1412 let Inst{19-16} = addr;
1413 let Inst{15-12} = Rt;
1416 def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt), (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>;
1417 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>;
1418 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>;
1422 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1423 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1424 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1425 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1426 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1427 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1430 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1431 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1432 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1433 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1437 let mayStore = 1, neverHasSideEffects = 1 in {
1438 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1439 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1440 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1441 "str", "\t$Rt, $addr!",
1442 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1444 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1445 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1446 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1447 "strh", "\t$Rt, $addr!",
1448 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1450 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1451 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1452 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1453 "strb", "\t$Rt, $addr!",
1454 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1455 } // mayStore = 1, neverHasSideEffects = 1
1457 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1458 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1459 t2am_imm8_offset:$offset),
1460 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1461 "str", "\t$Rt, $Rn$offset",
1462 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1463 [(set GPRnopc:$Rn_wb,
1464 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1465 t2am_imm8_offset:$offset))]>;
1467 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1468 (ins rGPR:$Rt, addr_offset_none:$Rn,
1469 t2am_imm8_offset:$offset),
1470 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1471 "strh", "\t$Rt, $Rn$offset",
1472 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1473 [(set GPRnopc:$Rn_wb,
1474 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1475 t2am_imm8_offset:$offset))]>;
1477 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1478 (ins rGPR:$Rt, addr_offset_none:$Rn,
1479 t2am_imm8_offset:$offset),
1480 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1481 "strb", "\t$Rt, $Rn$offset",
1482 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1483 [(set GPRnopc:$Rn_wb,
1484 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1485 t2am_imm8_offset:$offset))]>;
1487 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1488 // put the patterns on the instruction definitions directly as ISel wants
1489 // the address base and offset to be separate operands, not a single
1490 // complex operand like we represent the instructions themselves. The
1491 // pseudos map between the two.
1492 let usesCustomInserter = 1,
1493 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1494 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1495 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1497 [(set GPRnopc:$Rn_wb,
1498 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1499 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1500 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1502 [(set GPRnopc:$Rn_wb,
1503 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1504 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1505 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1507 [(set GPRnopc:$Rn_wb,
1508 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1511 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1513 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1514 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1515 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1516 "\t$Rt, $addr", []> {
1517 let Inst{31-27} = 0b11111;
1518 let Inst{26-25} = 0b00;
1519 let Inst{24} = 0; // not signed
1521 let Inst{22-21} = type;
1522 let Inst{20} = 0; // store
1524 let Inst{10-8} = 0b110; // PUW
1528 let Inst{15-12} = Rt;
1529 let Inst{19-16} = addr{12-9};
1530 let Inst{7-0} = addr{7-0};
1533 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1534 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1535 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1537 // ldrd / strd pre / post variants
1538 // For disassembly only.
1540 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1541 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1542 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1543 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1546 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1547 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1548 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1549 "$addr.base = $wb", []>;
1551 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1552 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1553 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1554 "$addr.base = $wb", []> {
1555 let DecoderMethod = "DecodeT2STRDPreInstruction";
1558 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1559 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1560 t2am_imm8s4_offset:$imm),
1561 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1562 "$addr.base = $wb", []>;
1564 class T2Istrrel<bits<2> bit54, dag oops, dag iops, string opc, string asm, list<dag> pattern>
1565 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc, asm, "", pattern> {
1569 let Inst{31-27} = 0b11101;
1570 let Inst{26-20} = 0b0001100;
1571 let Inst{11-6} = 0b111110;
1572 let Inst{5-4} = bit54;
1573 let Inst{3-0} = 0b1111;
1575 // Encode instruction operands
1576 let Inst{19-16} = addr;
1577 let Inst{15-12} = Rt;
1580 def t2STL : T2Istrrel<0b10, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
1581 "stl", "\t$Rt, $addr", []>;
1582 def t2STLB : T2Istrrel<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
1583 "stlb", "\t$Rt, $addr", []>;
1584 def t2STLH : T2Istrrel<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
1585 "stlh", "\t$Rt, $addr", []>;
1587 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1588 // data/instruction access.
1589 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1590 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1591 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1593 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1595 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1596 Sched<[WritePreLd]> {
1597 let Inst{31-25} = 0b1111100;
1598 let Inst{24} = instr;
1601 let Inst{21} = write;
1603 let Inst{15-12} = 0b1111;
1606 let Inst{19-16} = addr{16-13}; // Rn
1607 let Inst{11-0} = addr{11-0}; // imm12
1609 let DecoderMethod = "DecodeT2LoadImm12";
1612 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1614 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1615 Sched<[WritePreLd]> {
1616 let Inst{31-25} = 0b1111100;
1617 let Inst{24} = instr;
1618 let Inst{23} = 0; // U = 0
1620 let Inst{21} = write;
1622 let Inst{15-12} = 0b1111;
1623 let Inst{11-8} = 0b1100;
1626 let Inst{19-16} = addr{12-9}; // Rn
1627 let Inst{7-0} = addr{7-0}; // imm8
1629 let DecoderMethod = "DecodeT2LoadImm8";
1632 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1634 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1635 Sched<[WritePreLd]> {
1636 let Inst{31-25} = 0b1111100;
1637 let Inst{24} = instr;
1638 let Inst{23} = 0; // add = TRUE for T1
1640 let Inst{21} = write;
1642 let Inst{15-12} = 0b1111;
1643 let Inst{11-6} = 0b000000;
1646 let Inst{19-16} = addr{9-6}; // Rn
1647 let Inst{3-0} = addr{5-2}; // Rm
1648 let Inst{5-4} = addr{1-0}; // imm2
1650 let DecoderMethod = "DecodeT2LoadShift";
1654 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1655 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1656 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1658 // pci variant is very similar to i12, but supports negative offsets
1659 // from the PC. Only PLD and PLI have pci variants (not PLDW)
1660 class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
1661 IIC_Preload, opc, "\t$addr",
1662 [(ARMPreload (ARMWrapper tconstpool:$addr),
1663 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
1664 let Inst{31-25} = 0b1111100;
1665 let Inst{24} = inst;
1666 let Inst{22-20} = 0b001;
1667 let Inst{19-16} = 0b1111;
1668 let Inst{15-12} = 0b1111;
1671 let Inst{23} = addr{12}; // add = (U == '1')
1672 let Inst{11-0} = addr{11-0}; // imm12
1674 let DecoderMethod = "DecodeT2LoadLabel";
1677 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1678 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1680 //===----------------------------------------------------------------------===//
1681 // Load / store multiple Instructions.
1684 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1685 InstrItinClass itin_upd, bit L_bit> {
1687 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1688 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1692 let Inst{31-27} = 0b11101;
1693 let Inst{26-25} = 0b00;
1694 let Inst{24-23} = 0b01; // Increment After
1696 let Inst{21} = 0; // No writeback
1697 let Inst{20} = L_bit;
1698 let Inst{19-16} = Rn;
1699 let Inst{15-0} = regs;
1702 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1703 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1707 let Inst{31-27} = 0b11101;
1708 let Inst{26-25} = 0b00;
1709 let Inst{24-23} = 0b01; // Increment After
1711 let Inst{21} = 1; // Writeback
1712 let Inst{20} = L_bit;
1713 let Inst{19-16} = Rn;
1714 let Inst{15-0} = regs;
1717 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1718 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1722 let Inst{31-27} = 0b11101;
1723 let Inst{26-25} = 0b00;
1724 let Inst{24-23} = 0b10; // Decrement Before
1726 let Inst{21} = 0; // No writeback
1727 let Inst{20} = L_bit;
1728 let Inst{19-16} = Rn;
1729 let Inst{15-0} = regs;
1732 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1733 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1737 let Inst{31-27} = 0b11101;
1738 let Inst{26-25} = 0b00;
1739 let Inst{24-23} = 0b10; // Decrement Before
1741 let Inst{21} = 1; // Writeback
1742 let Inst{20} = L_bit;
1743 let Inst{19-16} = Rn;
1744 let Inst{15-0} = regs;
1748 let neverHasSideEffects = 1 in {
1750 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1751 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1753 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1754 InstrItinClass itin_upd, bit L_bit> {
1756 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1757 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1761 let Inst{31-27} = 0b11101;
1762 let Inst{26-25} = 0b00;
1763 let Inst{24-23} = 0b01; // Increment After
1765 let Inst{21} = 0; // No writeback
1766 let Inst{20} = L_bit;
1767 let Inst{19-16} = Rn;
1769 let Inst{14} = regs{14};
1771 let Inst{12-0} = regs{12-0};
1774 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1775 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1779 let Inst{31-27} = 0b11101;
1780 let Inst{26-25} = 0b00;
1781 let Inst{24-23} = 0b01; // Increment After
1783 let Inst{21} = 1; // Writeback
1784 let Inst{20} = L_bit;
1785 let Inst{19-16} = Rn;
1787 let Inst{14} = regs{14};
1789 let Inst{12-0} = regs{12-0};
1792 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1793 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1797 let Inst{31-27} = 0b11101;
1798 let Inst{26-25} = 0b00;
1799 let Inst{24-23} = 0b10; // Decrement Before
1801 let Inst{21} = 0; // No writeback
1802 let Inst{20} = L_bit;
1803 let Inst{19-16} = Rn;
1805 let Inst{14} = regs{14};
1807 let Inst{12-0} = regs{12-0};
1810 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1811 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1815 let Inst{31-27} = 0b11101;
1816 let Inst{26-25} = 0b00;
1817 let Inst{24-23} = 0b10; // Decrement Before
1819 let Inst{21} = 1; // Writeback
1820 let Inst{20} = L_bit;
1821 let Inst{19-16} = Rn;
1823 let Inst{14} = regs{14};
1825 let Inst{12-0} = regs{12-0};
1830 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1831 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1833 } // neverHasSideEffects
1836 //===----------------------------------------------------------------------===//
1837 // Move Instructions.
1840 let neverHasSideEffects = 1 in
1841 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1842 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1843 let Inst{31-27} = 0b11101;
1844 let Inst{26-25} = 0b01;
1845 let Inst{24-21} = 0b0010;
1846 let Inst{19-16} = 0b1111; // Rn
1847 let Inst{14-12} = 0b000;
1848 let Inst{7-4} = 0b0000;
1850 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1851 pred:$p, zero_reg)>;
1852 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1854 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1857 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1858 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1859 AddedComplexity = 1 in
1860 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1861 "mov", ".w\t$Rd, $imm",
1862 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1863 let Inst{31-27} = 0b11110;
1865 let Inst{24-21} = 0b0010;
1866 let Inst{19-16} = 0b1111; // Rn
1870 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1871 // Use aliases to get that to play nice here.
1872 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1874 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1877 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1878 pred:$p, zero_reg)>;
1879 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1880 pred:$p, zero_reg)>;
1882 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1883 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1884 "movw", "\t$Rd, $imm",
1885 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> {
1886 let Inst{31-27} = 0b11110;
1888 let Inst{24-21} = 0b0010;
1889 let Inst{20} = 0; // The S bit.
1895 let Inst{11-8} = Rd;
1896 let Inst{19-16} = imm{15-12};
1897 let Inst{26} = imm{11};
1898 let Inst{14-12} = imm{10-8};
1899 let Inst{7-0} = imm{7-0};
1900 let DecoderMethod = "DecodeT2MOVTWInstruction";
1903 def : t2InstAlias<"mov${p} $Rd, $imm",
1904 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>;
1906 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1907 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1909 let Constraints = "$src = $Rd" in {
1910 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1911 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1912 "movt", "\t$Rd, $imm",
1914 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1916 let Inst{31-27} = 0b11110;
1918 let Inst{24-21} = 0b0110;
1919 let Inst{20} = 0; // The S bit.
1925 let Inst{11-8} = Rd;
1926 let Inst{19-16} = imm{15-12};
1927 let Inst{26} = imm{11};
1928 let Inst{14-12} = imm{10-8};
1929 let Inst{7-0} = imm{7-0};
1930 let DecoderMethod = "DecodeT2MOVTWInstruction";
1933 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1934 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1938 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1940 //===----------------------------------------------------------------------===//
1941 // Extend Instructions.
1946 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1947 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1948 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1949 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1950 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1952 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1953 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1954 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1955 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1956 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1960 let AddedComplexity = 16 in {
1961 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1962 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1963 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1964 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1965 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1966 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1968 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1969 // The transformation should probably be done as a combiner action
1970 // instead so we can include a check for masking back in the upper
1971 // eight bits of the source into the lower eight bits of the result.
1972 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1973 // (t2UXTB16 rGPR:$Src, 3)>,
1974 // Requires<[HasT2ExtractPack, IsThumb2]>;
1975 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1976 (t2UXTB16 rGPR:$Src, 1)>,
1977 Requires<[HasT2ExtractPack, IsThumb2]>;
1979 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1980 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1981 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1982 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1983 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1986 //===----------------------------------------------------------------------===//
1987 // Arithmetic Instructions.
1990 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1991 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1992 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1993 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1995 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1997 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1998 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1999 // AdjustInstrPostInstrSelection where we determine whether or not to
2000 // set the "s" bit based on CPSR liveness.
2002 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
2003 // support for an optional CPSR definition that corresponds to the DAG
2004 // node's second value. We can then eliminate the implicit def of CPSR.
2005 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
2006 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
2007 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
2008 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
2010 let hasPostISelHook = 1 in {
2011 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
2012 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
2013 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
2014 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
2018 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
2019 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2021 // FIXME: Eliminate them if we can write def : Pat patterns which defines
2022 // CPSR and the implicit def of CPSR is not needed.
2023 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
2025 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2026 // The assume-no-carry-in form uses the negation of the input since add/sub
2027 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2028 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2030 // The AddedComplexity preferences the first variant over the others since
2031 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2032 let AddedComplexity = 1 in
2033 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2034 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2035 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2036 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2037 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2038 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2039 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2040 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2042 let AddedComplexity = 1 in
2043 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2044 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2045 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2046 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2047 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2048 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2049 // The with-carry-in form matches bitwise not instead of the negation.
2050 // Effectively, the inverse interpretation of the carry flag already accounts
2051 // for part of the negation.
2052 let AddedComplexity = 1 in
2053 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2054 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2055 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2056 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2057 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2058 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2060 // Select Bytes -- for disassembly only
2062 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2063 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
2064 Requires<[IsThumb2, HasThumb2DSP]> {
2065 let Inst{31-27} = 0b11111;
2066 let Inst{26-24} = 0b010;
2068 let Inst{22-20} = 0b010;
2069 let Inst{15-12} = 0b1111;
2071 let Inst{6-4} = 0b000;
2074 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2075 // And Miscellaneous operations -- for disassembly only
2076 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2077 list<dag> pat = [/* For disassembly only; pattern left blank */],
2078 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
2079 string asm = "\t$Rd, $Rn, $Rm">
2080 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2081 Requires<[IsThumb2, HasThumb2DSP]> {
2082 let Inst{31-27} = 0b11111;
2083 let Inst{26-23} = 0b0101;
2084 let Inst{22-20} = op22_20;
2085 let Inst{15-12} = 0b1111;
2086 let Inst{7-4} = op7_4;
2092 let Inst{11-8} = Rd;
2093 let Inst{19-16} = Rn;
2097 // Saturating add/subtract -- for disassembly only
2099 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2100 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
2101 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2102 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2103 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2104 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2105 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2106 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2107 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2108 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2109 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2110 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2111 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2112 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2113 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2114 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2115 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2116 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2117 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2118 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2119 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2120 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2122 // Signed/Unsigned add/subtract -- for disassembly only
2124 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2125 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2126 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2127 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2128 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2129 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2130 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2131 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2132 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2133 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2134 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2135 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2137 // Signed/Unsigned halving add/subtract -- for disassembly only
2139 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2140 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2141 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2142 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2143 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2144 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2145 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2146 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2147 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2148 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2149 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2150 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2152 // Helper class for disassembly only
2153 // A6.3.16 & A6.3.17
2154 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2155 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2156 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2157 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2158 let Inst{31-27} = 0b11111;
2159 let Inst{26-24} = 0b011;
2160 let Inst{23} = long;
2161 let Inst{22-20} = op22_20;
2162 let Inst{7-4} = op7_4;
2165 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2166 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2167 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2168 let Inst{31-27} = 0b11111;
2169 let Inst{26-24} = 0b011;
2170 let Inst{23} = long;
2171 let Inst{22-20} = op22_20;
2172 let Inst{7-4} = op7_4;
2175 // Unsigned Sum of Absolute Differences [and Accumulate].
2176 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2177 (ins rGPR:$Rn, rGPR:$Rm),
2178 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2179 Requires<[IsThumb2, HasThumb2DSP]> {
2180 let Inst{15-12} = 0b1111;
2182 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2183 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2184 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2185 Requires<[IsThumb2, HasThumb2DSP]>;
2187 // Signed/Unsigned saturate.
2188 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2189 string opc, string asm, list<dag> pattern>
2190 : T2I<oops, iops, itin, opc, asm, pattern> {
2196 let Inst{11-8} = Rd;
2197 let Inst{19-16} = Rn;
2198 let Inst{4-0} = sat_imm;
2199 let Inst{21} = sh{5};
2200 let Inst{14-12} = sh{4-2};
2201 let Inst{7-6} = sh{1-0};
2206 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2207 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2208 let Inst{31-27} = 0b11110;
2209 let Inst{25-22} = 0b1100;
2215 def t2SSAT16: T2SatI<
2216 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2217 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2218 Requires<[IsThumb2, HasThumb2DSP]> {
2219 let Inst{31-27} = 0b11110;
2220 let Inst{25-22} = 0b1100;
2223 let Inst{21} = 1; // sh = '1'
2224 let Inst{14-12} = 0b000; // imm3 = '000'
2225 let Inst{7-6} = 0b00; // imm2 = '00'
2226 let Inst{5-4} = 0b00;
2231 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2232 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2233 let Inst{31-27} = 0b11110;
2234 let Inst{25-22} = 0b1110;
2239 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2241 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2242 Requires<[IsThumb2, HasThumb2DSP]> {
2243 let Inst{31-22} = 0b1111001110;
2246 let Inst{21} = 1; // sh = '1'
2247 let Inst{14-12} = 0b000; // imm3 = '000'
2248 let Inst{7-6} = 0b00; // imm2 = '00'
2249 let Inst{5-4} = 0b00;
2252 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2253 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2255 //===----------------------------------------------------------------------===//
2256 // Shift and rotate Instructions.
2259 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2260 BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2261 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2262 BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2263 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2264 BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2265 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2266 BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2268 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2269 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2270 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2272 let Uses = [CPSR] in {
2273 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2274 "rrx", "\t$Rd, $Rm",
2275 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2276 let Inst{31-27} = 0b11101;
2277 let Inst{26-25} = 0b01;
2278 let Inst{24-21} = 0b0010;
2279 let Inst{19-16} = 0b1111; // Rn
2280 let Inst{14-12} = 0b000;
2281 let Inst{7-4} = 0b0011;
2285 let isCodeGenOnly = 1, Defs = [CPSR] in {
2286 def t2MOVsrl_flag : T2TwoRegShiftImm<
2287 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2288 "lsrs", ".w\t$Rd, $Rm, #1",
2289 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2291 let Inst{31-27} = 0b11101;
2292 let Inst{26-25} = 0b01;
2293 let Inst{24-21} = 0b0010;
2294 let Inst{20} = 1; // The S bit.
2295 let Inst{19-16} = 0b1111; // Rn
2296 let Inst{5-4} = 0b01; // Shift type.
2297 // Shift amount = Inst{14-12:7-6} = 1.
2298 let Inst{14-12} = 0b000;
2299 let Inst{7-6} = 0b01;
2301 def t2MOVsra_flag : T2TwoRegShiftImm<
2302 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2303 "asrs", ".w\t$Rd, $Rm, #1",
2304 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2306 let Inst{31-27} = 0b11101;
2307 let Inst{26-25} = 0b01;
2308 let Inst{24-21} = 0b0010;
2309 let Inst{20} = 1; // The S bit.
2310 let Inst{19-16} = 0b1111; // Rn
2311 let Inst{5-4} = 0b10; // Shift type.
2312 // Shift amount = Inst{14-12:7-6} = 1.
2313 let Inst{14-12} = 0b000;
2314 let Inst{7-6} = 0b01;
2318 //===----------------------------------------------------------------------===//
2319 // Bitwise Instructions.
2322 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2323 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2324 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2325 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2326 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2327 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2328 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2329 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2330 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2332 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2333 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2334 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2336 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2337 string opc, string asm, list<dag> pattern>
2338 : T2I<oops, iops, itin, opc, asm, pattern> {
2343 let Inst{11-8} = Rd;
2344 let Inst{4-0} = msb{4-0};
2345 let Inst{14-12} = lsb{4-2};
2346 let Inst{7-6} = lsb{1-0};
2349 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2350 string opc, string asm, list<dag> pattern>
2351 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2354 let Inst{19-16} = Rn;
2357 let Constraints = "$src = $Rd" in
2358 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2359 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2360 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2361 let Inst{31-27} = 0b11110;
2362 let Inst{26} = 0; // should be 0.
2364 let Inst{24-20} = 0b10110;
2365 let Inst{19-16} = 0b1111; // Rn
2367 let Inst{5} = 0; // should be 0.
2370 let msb{4-0} = imm{9-5};
2371 let lsb{4-0} = imm{4-0};
2374 def t2SBFX: T2TwoRegBitFI<
2375 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2376 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2377 let Inst{31-27} = 0b11110;
2379 let Inst{24-20} = 0b10100;
2383 def t2UBFX: T2TwoRegBitFI<
2384 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2385 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2386 let Inst{31-27} = 0b11110;
2388 let Inst{24-20} = 0b11100;
2392 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2393 let Constraints = "$src = $Rd" in {
2394 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2395 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2396 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2397 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2398 bf_inv_mask_imm:$imm))]> {
2399 let Inst{31-27} = 0b11110;
2400 let Inst{26} = 0; // should be 0.
2402 let Inst{24-20} = 0b10110;
2404 let Inst{5} = 0; // should be 0.
2407 let msb{4-0} = imm{9-5};
2408 let lsb{4-0} = imm{4-0};
2412 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2413 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2414 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2416 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2417 /// unary operation that produces a value. These are predicable and can be
2418 /// changed to modify CPSR.
2419 multiclass T2I_un_irs<bits<4> opcod, string opc,
2420 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2422 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2424 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2426 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2427 let isAsCheapAsAMove = Cheap;
2428 let isReMaterializable = ReMat;
2429 let isMoveImm = MoveImm;
2430 let Inst{31-27} = 0b11110;
2432 let Inst{24-21} = opcod;
2433 let Inst{19-16} = 0b1111; // Rn
2437 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2438 opc, ".w\t$Rd, $Rm",
2439 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2440 let Inst{31-27} = 0b11101;
2441 let Inst{26-25} = 0b01;
2442 let Inst{24-21} = opcod;
2443 let Inst{19-16} = 0b1111; // Rn
2444 let Inst{14-12} = 0b000; // imm3
2445 let Inst{7-6} = 0b00; // imm2
2446 let Inst{5-4} = 0b00; // type
2449 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2450 opc, ".w\t$Rd, $ShiftedRm",
2451 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2453 let Inst{31-27} = 0b11101;
2454 let Inst{26-25} = 0b01;
2455 let Inst{24-21} = opcod;
2456 let Inst{19-16} = 0b1111; // Rn
2460 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2461 let AddedComplexity = 1 in
2462 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2463 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2464 UnOpFrag<(not node:$Src)>, 1, 1, 1>;
2466 let AddedComplexity = 1 in
2467 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2468 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2470 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2471 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2472 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2475 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2476 // will match the extended, not the original bitWidth for $src.
2477 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2478 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2481 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2482 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2483 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2484 Requires<[IsThumb2]>;
2486 def : T2Pat<(t2_so_imm_not:$src),
2487 (t2MVNi t2_so_imm_not:$src)>;
2489 //===----------------------------------------------------------------------===//
2490 // Multiply Instructions.
2492 let isCommutable = 1 in
2493 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2494 "mul", "\t$Rd, $Rn, $Rm",
2495 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2496 let Inst{31-27} = 0b11111;
2497 let Inst{26-23} = 0b0110;
2498 let Inst{22-20} = 0b000;
2499 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2500 let Inst{7-4} = 0b0000; // Multiply
2503 def t2MLA: T2FourReg<
2504 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2505 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2506 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
2507 Requires<[IsThumb2, UseMulOps]> {
2508 let Inst{31-27} = 0b11111;
2509 let Inst{26-23} = 0b0110;
2510 let Inst{22-20} = 0b000;
2511 let Inst{7-4} = 0b0000; // Multiply
2514 def t2MLS: T2FourReg<
2515 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2516 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2517 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
2518 Requires<[IsThumb2, UseMulOps]> {
2519 let Inst{31-27} = 0b11111;
2520 let Inst{26-23} = 0b0110;
2521 let Inst{22-20} = 0b000;
2522 let Inst{7-4} = 0b0001; // Multiply and Subtract
2525 // Extra precision multiplies with low / high results
2526 let neverHasSideEffects = 1 in {
2527 let isCommutable = 1 in {
2528 def t2SMULL : T2MulLong<0b000, 0b0000,
2529 (outs rGPR:$RdLo, rGPR:$RdHi),
2530 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2531 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2533 def t2UMULL : T2MulLong<0b010, 0b0000,
2534 (outs rGPR:$RdLo, rGPR:$RdHi),
2535 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2536 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2539 // Multiply + accumulate
2540 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2541 (outs rGPR:$RdLo, rGPR:$RdHi),
2542 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2543 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2544 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2546 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2547 (outs rGPR:$RdLo, rGPR:$RdHi),
2548 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2549 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2550 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2552 def t2UMAAL : T2MulLong<0b110, 0b0110,
2553 (outs rGPR:$RdLo, rGPR:$RdHi),
2554 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2555 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2556 Requires<[IsThumb2, HasThumb2DSP]>;
2557 } // neverHasSideEffects
2559 // Rounding variants of the below included for disassembly only
2561 // Most significant word multiply
2562 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2563 "smmul", "\t$Rd, $Rn, $Rm",
2564 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2565 Requires<[IsThumb2, HasThumb2DSP]> {
2566 let Inst{31-27} = 0b11111;
2567 let Inst{26-23} = 0b0110;
2568 let Inst{22-20} = 0b101;
2569 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2570 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2573 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2574 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2575 Requires<[IsThumb2, HasThumb2DSP]> {
2576 let Inst{31-27} = 0b11111;
2577 let Inst{26-23} = 0b0110;
2578 let Inst{22-20} = 0b101;
2579 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2580 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2583 def t2SMMLA : T2FourReg<
2584 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2585 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2586 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2587 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2588 let Inst{31-27} = 0b11111;
2589 let Inst{26-23} = 0b0110;
2590 let Inst{22-20} = 0b101;
2591 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2594 def t2SMMLAR: T2FourReg<
2595 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2596 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2597 Requires<[IsThumb2, HasThumb2DSP]> {
2598 let Inst{31-27} = 0b11111;
2599 let Inst{26-23} = 0b0110;
2600 let Inst{22-20} = 0b101;
2601 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2604 def t2SMMLS: T2FourReg<
2605 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2606 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2607 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2608 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2609 let Inst{31-27} = 0b11111;
2610 let Inst{26-23} = 0b0110;
2611 let Inst{22-20} = 0b110;
2612 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2615 def t2SMMLSR:T2FourReg<
2616 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2617 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2618 Requires<[IsThumb2, HasThumb2DSP]> {
2619 let Inst{31-27} = 0b11111;
2620 let Inst{26-23} = 0b0110;
2621 let Inst{22-20} = 0b110;
2622 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2625 multiclass T2I_smul<string opc, PatFrag opnode> {
2626 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2627 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2628 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2629 (sext_inreg rGPR:$Rm, i16)))]>,
2630 Requires<[IsThumb2, HasThumb2DSP]> {
2631 let Inst{31-27} = 0b11111;
2632 let Inst{26-23} = 0b0110;
2633 let Inst{22-20} = 0b001;
2634 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2635 let Inst{7-6} = 0b00;
2636 let Inst{5-4} = 0b00;
2639 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2640 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2641 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2642 (sra rGPR:$Rm, (i32 16))))]>,
2643 Requires<[IsThumb2, HasThumb2DSP]> {
2644 let Inst{31-27} = 0b11111;
2645 let Inst{26-23} = 0b0110;
2646 let Inst{22-20} = 0b001;
2647 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2648 let Inst{7-6} = 0b00;
2649 let Inst{5-4} = 0b01;
2652 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2653 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2654 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2655 (sext_inreg rGPR:$Rm, i16)))]>,
2656 Requires<[IsThumb2, HasThumb2DSP]> {
2657 let Inst{31-27} = 0b11111;
2658 let Inst{26-23} = 0b0110;
2659 let Inst{22-20} = 0b001;
2660 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2661 let Inst{7-6} = 0b00;
2662 let Inst{5-4} = 0b10;
2665 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2666 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2667 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2668 (sra rGPR:$Rm, (i32 16))))]>,
2669 Requires<[IsThumb2, HasThumb2DSP]> {
2670 let Inst{31-27} = 0b11111;
2671 let Inst{26-23} = 0b0110;
2672 let Inst{22-20} = 0b001;
2673 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2674 let Inst{7-6} = 0b00;
2675 let Inst{5-4} = 0b11;
2678 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2679 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2680 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2681 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2682 Requires<[IsThumb2, HasThumb2DSP]> {
2683 let Inst{31-27} = 0b11111;
2684 let Inst{26-23} = 0b0110;
2685 let Inst{22-20} = 0b011;
2686 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2687 let Inst{7-6} = 0b00;
2688 let Inst{5-4} = 0b00;
2691 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2692 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2693 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2694 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2695 Requires<[IsThumb2, HasThumb2DSP]> {
2696 let Inst{31-27} = 0b11111;
2697 let Inst{26-23} = 0b0110;
2698 let Inst{22-20} = 0b011;
2699 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2700 let Inst{7-6} = 0b00;
2701 let Inst{5-4} = 0b01;
2706 multiclass T2I_smla<string opc, PatFrag opnode> {
2708 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2709 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2710 [(set rGPR:$Rd, (add rGPR:$Ra,
2711 (opnode (sext_inreg rGPR:$Rn, i16),
2712 (sext_inreg rGPR:$Rm, i16))))]>,
2713 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2714 let Inst{31-27} = 0b11111;
2715 let Inst{26-23} = 0b0110;
2716 let Inst{22-20} = 0b001;
2717 let Inst{7-6} = 0b00;
2718 let Inst{5-4} = 0b00;
2722 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2723 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2724 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2725 (sra rGPR:$Rm, (i32 16)))))]>,
2726 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2727 let Inst{31-27} = 0b11111;
2728 let Inst{26-23} = 0b0110;
2729 let Inst{22-20} = 0b001;
2730 let Inst{7-6} = 0b00;
2731 let Inst{5-4} = 0b01;
2735 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2736 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2737 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2738 (sext_inreg rGPR:$Rm, i16))))]>,
2739 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2740 let Inst{31-27} = 0b11111;
2741 let Inst{26-23} = 0b0110;
2742 let Inst{22-20} = 0b001;
2743 let Inst{7-6} = 0b00;
2744 let Inst{5-4} = 0b10;
2748 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2749 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2750 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2751 (sra rGPR:$Rm, (i32 16)))))]>,
2752 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2753 let Inst{31-27} = 0b11111;
2754 let Inst{26-23} = 0b0110;
2755 let Inst{22-20} = 0b001;
2756 let Inst{7-6} = 0b00;
2757 let Inst{5-4} = 0b11;
2761 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2762 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2763 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2764 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2765 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2766 let Inst{31-27} = 0b11111;
2767 let Inst{26-23} = 0b0110;
2768 let Inst{22-20} = 0b011;
2769 let Inst{7-6} = 0b00;
2770 let Inst{5-4} = 0b00;
2774 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2775 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2776 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2777 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2778 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2779 let Inst{31-27} = 0b11111;
2780 let Inst{26-23} = 0b0110;
2781 let Inst{22-20} = 0b011;
2782 let Inst{7-6} = 0b00;
2783 let Inst{5-4} = 0b01;
2787 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2788 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2790 // Halfword multiple accumulate long: SMLAL<x><y>
2791 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2792 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2793 [/* For disassembly only; pattern left blank */]>,
2794 Requires<[IsThumb2, HasThumb2DSP]>;
2795 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2796 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2797 [/* For disassembly only; pattern left blank */]>,
2798 Requires<[IsThumb2, HasThumb2DSP]>;
2799 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2800 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2801 [/* For disassembly only; pattern left blank */]>,
2802 Requires<[IsThumb2, HasThumb2DSP]>;
2803 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2804 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2805 [/* For disassembly only; pattern left blank */]>,
2806 Requires<[IsThumb2, HasThumb2DSP]>;
2808 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2809 def t2SMUAD: T2ThreeReg_mac<
2810 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2811 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2812 Requires<[IsThumb2, HasThumb2DSP]> {
2813 let Inst{15-12} = 0b1111;
2815 def t2SMUADX:T2ThreeReg_mac<
2816 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2817 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2818 Requires<[IsThumb2, HasThumb2DSP]> {
2819 let Inst{15-12} = 0b1111;
2821 def t2SMUSD: T2ThreeReg_mac<
2822 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2823 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2824 Requires<[IsThumb2, HasThumb2DSP]> {
2825 let Inst{15-12} = 0b1111;
2827 def t2SMUSDX:T2ThreeReg_mac<
2828 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2829 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2830 Requires<[IsThumb2, HasThumb2DSP]> {
2831 let Inst{15-12} = 0b1111;
2833 def t2SMLAD : T2FourReg_mac<
2834 0, 0b010, 0b0000, (outs rGPR:$Rd),
2835 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2836 "\t$Rd, $Rn, $Rm, $Ra", []>,
2837 Requires<[IsThumb2, HasThumb2DSP]>;
2838 def t2SMLADX : T2FourReg_mac<
2839 0, 0b010, 0b0001, (outs rGPR:$Rd),
2840 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2841 "\t$Rd, $Rn, $Rm, $Ra", []>,
2842 Requires<[IsThumb2, HasThumb2DSP]>;
2843 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2844 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2845 "\t$Rd, $Rn, $Rm, $Ra", []>,
2846 Requires<[IsThumb2, HasThumb2DSP]>;
2847 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2848 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2849 "\t$Rd, $Rn, $Rm, $Ra", []>,
2850 Requires<[IsThumb2, HasThumb2DSP]>;
2851 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2852 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2853 "\t$Ra, $Rd, $Rn, $Rm", []>,
2854 Requires<[IsThumb2, HasThumb2DSP]>;
2855 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2856 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2857 "\t$Ra, $Rd, $Rn, $Rm", []>,
2858 Requires<[IsThumb2, HasThumb2DSP]>;
2859 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2860 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2861 "\t$Ra, $Rd, $Rn, $Rm", []>,
2862 Requires<[IsThumb2, HasThumb2DSP]>;
2863 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2864 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2865 "\t$Ra, $Rd, $Rn, $Rm", []>,
2866 Requires<[IsThumb2, HasThumb2DSP]>;
2868 //===----------------------------------------------------------------------===//
2869 // Division Instructions.
2870 // Signed and unsigned division on v7-M
2872 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2873 "sdiv", "\t$Rd, $Rn, $Rm",
2874 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2875 Requires<[HasDivide, IsThumb2]> {
2876 let Inst{31-27} = 0b11111;
2877 let Inst{26-21} = 0b011100;
2879 let Inst{15-12} = 0b1111;
2880 let Inst{7-4} = 0b1111;
2883 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2884 "udiv", "\t$Rd, $Rn, $Rm",
2885 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2886 Requires<[HasDivide, IsThumb2]> {
2887 let Inst{31-27} = 0b11111;
2888 let Inst{26-21} = 0b011101;
2890 let Inst{15-12} = 0b1111;
2891 let Inst{7-4} = 0b1111;
2894 //===----------------------------------------------------------------------===//
2895 // Misc. Arithmetic Instructions.
2898 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2899 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2900 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2901 let Inst{31-27} = 0b11111;
2902 let Inst{26-22} = 0b01010;
2903 let Inst{21-20} = op1;
2904 let Inst{15-12} = 0b1111;
2905 let Inst{7-6} = 0b10;
2906 let Inst{5-4} = op2;
2910 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2911 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2914 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2915 "rbit", "\t$Rd, $Rm",
2916 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>,
2919 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2920 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2923 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2924 "rev16", ".w\t$Rd, $Rm",
2925 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2928 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2929 "revsh", ".w\t$Rd, $Rm",
2930 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2933 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2934 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2935 (t2REVSH rGPR:$Rm)>;
2937 def t2PKHBT : T2ThreeReg<
2938 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2939 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2940 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2941 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2943 Requires<[HasT2ExtractPack, IsThumb2]>,
2944 Sched<[WriteALUsi, ReadALU]> {
2945 let Inst{31-27} = 0b11101;
2946 let Inst{26-25} = 0b01;
2947 let Inst{24-20} = 0b01100;
2948 let Inst{5} = 0; // BT form
2952 let Inst{14-12} = sh{4-2};
2953 let Inst{7-6} = sh{1-0};
2956 // Alternate cases for PKHBT where identities eliminate some nodes.
2957 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2958 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2959 Requires<[HasT2ExtractPack, IsThumb2]>;
2960 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2961 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2962 Requires<[HasT2ExtractPack, IsThumb2]>;
2964 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2965 // will match the pattern below.
2966 def t2PKHTB : T2ThreeReg<
2967 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2968 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2969 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2970 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2972 Requires<[HasT2ExtractPack, IsThumb2]>,
2973 Sched<[WriteALUsi, ReadALU]> {
2974 let Inst{31-27} = 0b11101;
2975 let Inst{26-25} = 0b01;
2976 let Inst{24-20} = 0b01100;
2977 let Inst{5} = 1; // TB form
2981 let Inst{14-12} = sh{4-2};
2982 let Inst{7-6} = sh{1-0};
2985 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2986 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2987 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
2988 // pkhtb src1, src2, asr (17..31).
2989 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
2990 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
2991 Requires<[HasT2ExtractPack, IsThumb2]>;
2992 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
2993 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2994 Requires<[HasT2ExtractPack, IsThumb2]>;
2995 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2996 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2997 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2998 Requires<[HasT2ExtractPack, IsThumb2]>;
3000 //===----------------------------------------------------------------------===//
3001 // Comparison Instructions...
3003 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
3004 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
3005 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3007 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
3008 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
3009 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
3010 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
3011 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
3012 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
3014 let isCompare = 1, Defs = [CPSR] in {
3016 def t2CMNri : T2OneRegCmpImm<
3017 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
3018 "cmn", ".w\t$Rn, $imm",
3019 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
3020 Sched<[WriteCMP, ReadALU]> {
3021 let Inst{31-27} = 0b11110;
3023 let Inst{24-21} = 0b1000;
3024 let Inst{20} = 1; // The S bit.
3026 let Inst{11-8} = 0b1111; // Rd
3029 def t2CMNzrr : T2TwoRegCmp<
3030 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
3031 "cmn", ".w\t$Rn, $Rm",
3032 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3033 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
3034 let Inst{31-27} = 0b11101;
3035 let Inst{26-25} = 0b01;
3036 let Inst{24-21} = 0b1000;
3037 let Inst{20} = 1; // The S bit.
3038 let Inst{14-12} = 0b000; // imm3
3039 let Inst{11-8} = 0b1111; // Rd
3040 let Inst{7-6} = 0b00; // imm2
3041 let Inst{5-4} = 0b00; // type
3044 def t2CMNzrs : T2OneRegCmpShiftedReg<
3045 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
3046 "cmn", ".w\t$Rn, $ShiftedRm",
3047 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3048 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
3049 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3050 let Inst{31-27} = 0b11101;
3051 let Inst{26-25} = 0b01;
3052 let Inst{24-21} = 0b1000;
3053 let Inst{20} = 1; // The S bit.
3054 let Inst{11-8} = 0b1111; // Rd
3058 // Assembler aliases w/o the ".w" suffix.
3059 // No alias here for 'rr' version as not all instantiations of this multiclass
3060 // want one (CMP in particular, does not).
3061 def : t2InstAlias<"cmn${p} $Rn, $imm",
3062 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
3063 def : t2InstAlias<"cmn${p} $Rn, $shift",
3064 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
3066 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
3067 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
3069 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
3070 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
3072 defm t2TST : T2I_cmp_irs<0b0000, "tst",
3073 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3074 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3075 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
3076 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3077 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3079 // Conditional moves
3080 let neverHasSideEffects = 1 in {
3082 let isCommutable = 1, isSelect = 1 in
3083 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3084 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p),
3086 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
3088 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3090 let isMoveImm = 1 in
3092 : t2PseudoInst<(outs rGPR:$Rd),
3093 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3095 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3097 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3099 let isCodeGenOnly = 1 in {
3100 let isMoveImm = 1 in
3102 : t2PseudoInst<(outs rGPR:$Rd),
3103 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
3105 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3107 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3109 let isMoveImm = 1 in
3111 : t2PseudoInst<(outs rGPR:$Rd),
3112 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3115 (ARMcmov rGPR:$false, t2_so_imm_not:$imm,
3117 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3119 class MOVCCShPseudo<SDPatternOperator opnode, Operand ty>
3120 : t2PseudoInst<(outs rGPR:$Rd),
3121 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p),
3123 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3124 (opnode rGPR:$Rm, (i32 ty:$imm)),
3126 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3128 def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>;
3129 def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>;
3130 def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>;
3131 def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>;
3133 let isMoveImm = 1 in
3135 : t2PseudoInst<(outs rGPR:$dst),
3136 (ins rGPR:$false, i32imm:$src, cmovpred:$p),
3138 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src,
3140 RegConstraint<"$false = $dst">;
3141 } // isCodeGenOnly = 1
3143 } // neverHasSideEffects
3145 //===----------------------------------------------------------------------===//
3146 // Atomic operations intrinsics
3149 // memory barriers protect the atomic sequences
3150 let hasSideEffects = 1 in {
3151 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3152 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3155 let Inst{31-4} = 0xf3bf8f5;
3156 let Inst{3-0} = opt;
3160 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3161 "dsb", "\t$opt", []>, Requires<[HasDB]> {
3163 let Inst{31-4} = 0xf3bf8f4;
3164 let Inst{3-0} = opt;
3167 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3168 "isb", "\t$opt", []>, Requires<[HasDB]> {
3170 let Inst{31-4} = 0xf3bf8f6;
3171 let Inst{3-0} = opt;
3174 class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3175 InstrItinClass itin, string opc, string asm, string cstr,
3176 list<dag> pattern, bits<4> rt2 = 0b1111>
3177 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3178 let Inst{31-27} = 0b11101;
3179 let Inst{26-20} = 0b0001101;
3180 let Inst{11-8} = rt2;
3181 let Inst{7-4} = opcod;
3182 let Inst{3-0} = 0b1111;
3186 let Inst{19-16} = addr;
3187 let Inst{15-12} = Rt;
3189 class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3190 InstrItinClass itin, string opc, string asm, string cstr,
3191 list<dag> pattern, bits<4> rt2 = 0b1111>
3192 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3193 let Inst{31-27} = 0b11101;
3194 let Inst{26-20} = 0b0001100;
3195 let Inst{11-8} = rt2;
3196 let Inst{7-4} = opcod;
3202 let Inst{19-16} = addr;
3203 let Inst{15-12} = Rt;
3206 let mayLoad = 1 in {
3207 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3208 AddrModeNone, 4, NoItinerary,
3209 "ldrexb", "\t$Rt, $addr", "",
3210 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
3211 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3212 AddrModeNone, 4, NoItinerary,
3213 "ldrexh", "\t$Rt, $addr", "",
3214 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
3215 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3216 AddrModeNone, 4, NoItinerary,
3217 "ldrex", "\t$Rt, $addr", "",
3218 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]> {
3221 let Inst{31-27} = 0b11101;
3222 let Inst{26-20} = 0b0000101;
3223 let Inst{19-16} = addr{11-8};
3224 let Inst{15-12} = Rt;
3225 let Inst{11-8} = 0b1111;
3226 let Inst{7-0} = addr{7-0};
3228 let hasExtraDefRegAllocReq = 1 in
3229 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3230 (ins addr_offset_none:$addr),
3231 AddrModeNone, 4, NoItinerary,
3232 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3235 let Inst{11-8} = Rt2;
3237 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3238 AddrModeNone, 4, NoItinerary,
3239 "ldaexb", "\t$Rt, $addr", "",
3240 []>, Requires<[IsThumb, HasV8]>;
3241 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3242 AddrModeNone, 4, NoItinerary,
3243 "ldaexh", "\t$Rt, $addr", "",
3244 []>, Requires<[IsThumb, HasV8]>;
3245 def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
3246 AddrModeNone, 4, NoItinerary,
3247 "ldaex", "\t$Rt, $addr", "",
3248 []>, Requires<[IsThumb, HasV8]> {
3251 let Inst{31-27} = 0b11101;
3252 let Inst{26-20} = 0b0001101;
3253 let Inst{19-16} = addr;
3254 let Inst{15-12} = Rt;
3255 let Inst{11-8} = 0b1111;
3256 let Inst{7-0} = 0b11101111;
3258 let hasExtraDefRegAllocReq = 1 in
3259 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3260 (ins addr_offset_none:$addr),
3261 AddrModeNone, 4, NoItinerary,
3262 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3263 [], {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> {
3265 let Inst{11-8} = Rt2;
3271 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3272 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3273 (ins rGPR:$Rt, addr_offset_none:$addr),
3274 AddrModeNone, 4, NoItinerary,
3275 "strexb", "\t$Rd, $Rt, $addr", "",
3276 [(set rGPR:$Rd, (strex_1 rGPR:$Rt,
3277 addr_offset_none:$addr))]>;
3278 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3279 (ins rGPR:$Rt, addr_offset_none:$addr),
3280 AddrModeNone, 4, NoItinerary,
3281 "strexh", "\t$Rd, $Rt, $addr", "",
3282 [(set rGPR:$Rd, (strex_2 rGPR:$Rt,
3283 addr_offset_none:$addr))]>;
3285 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3286 t2addrmode_imm0_1020s4:$addr),
3287 AddrModeNone, 4, NoItinerary,
3288 "strex", "\t$Rd, $Rt, $addr", "",
3289 [(set rGPR:$Rd, (strex_4 rGPR:$Rt,
3290 t2addrmode_imm0_1020s4:$addr))]> {
3294 let Inst{31-27} = 0b11101;
3295 let Inst{26-20} = 0b0000100;
3296 let Inst{19-16} = addr{11-8};
3297 let Inst{15-12} = Rt;
3298 let Inst{11-8} = Rd;
3299 let Inst{7-0} = addr{7-0};
3301 let hasExtraSrcRegAllocReq = 1 in
3302 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3303 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3304 AddrModeNone, 4, NoItinerary,
3305 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3308 let Inst{11-8} = Rt2;
3310 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3311 (ins rGPR:$Rt, addr_offset_none:$addr),
3312 AddrModeNone, 4, NoItinerary,
3313 "stlexb", "\t$Rd, $Rt, $addr", "",
3314 []>, Requires<[IsThumb, HasV8]>;
3316 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3317 (ins rGPR:$Rt, addr_offset_none:$addr),
3318 AddrModeNone, 4, NoItinerary,
3319 "stlexh", "\t$Rd, $Rt, $addr", "",
3320 []>, Requires<[IsThumb, HasV8]>;
3322 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3323 addr_offset_none:$addr),
3324 AddrModeNone, 4, NoItinerary,
3325 "stlex", "\t$Rd, $Rt, $addr", "",
3326 []>, Requires<[IsThumb, HasV8]> {
3330 let Inst{31-27} = 0b11101;
3331 let Inst{26-20} = 0b0001100;
3332 let Inst{19-16} = addr;
3333 let Inst{15-12} = Rt;
3334 let Inst{11-4} = 0b11111110;
3337 let hasExtraSrcRegAllocReq = 1 in
3338 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3339 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3340 AddrModeNone, 4, NoItinerary,
3341 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3342 {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> {
3344 let Inst{11-8} = Rt2;
3348 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
3349 Requires<[IsThumb2, HasV7]> {
3350 let Inst{31-16} = 0xf3bf;
3351 let Inst{15-14} = 0b10;
3354 let Inst{11-8} = 0b1111;
3355 let Inst{7-4} = 0b0010;
3356 let Inst{3-0} = 0b1111;
3359 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3360 (t2LDREXB addr_offset_none:$addr)>;
3361 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3362 (t2LDREXH addr_offset_none:$addr)>;
3363 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3364 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>;
3365 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3366 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>;
3368 //===----------------------------------------------------------------------===//
3369 // SJLJ Exception handling intrinsics
3370 // eh_sjlj_setjmp() is an instruction sequence to store the return
3371 // address and save #0 in R0 for the non-longjmp case.
3372 // Since by its nature we may be coming from some other function to get
3373 // here, and we're using the stack frame for the containing function to
3374 // save/restore registers, we can't keep anything live in regs across
3375 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3376 // when we get here from a longjmp(). We force everything out of registers
3377 // except for our own input by listing the relevant registers in Defs. By
3378 // doing so, we also cause the prologue/epilogue code to actively preserve
3379 // all of the callee-saved resgisters, which is exactly what we want.
3380 // $val is a scratch register for our use.
3382 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3383 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3384 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3385 usesCustomInserter = 1 in {
3386 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3387 AddrModeNone, 0, NoItinerary, "", "",
3388 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3389 Requires<[IsThumb2, HasVFP2]>;
3393 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3394 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3395 usesCustomInserter = 1 in {
3396 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3397 AddrModeNone, 0, NoItinerary, "", "",
3398 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3399 Requires<[IsThumb2, NoVFP]>;
3403 //===----------------------------------------------------------------------===//
3404 // Control-Flow Instructions
3407 // FIXME: remove when we have a way to marking a MI with these properties.
3408 // FIXME: Should pc be an implicit operand like PICADD, etc?
3409 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3410 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3411 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3412 reglist:$regs, variable_ops),
3413 4, IIC_iLoad_mBr, [],
3414 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3415 RegConstraint<"$Rn = $wb">;
3417 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3418 let isPredicable = 1 in
3419 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3421 [(br bb:$target)]>, Sched<[WriteBr]> {
3422 let Inst{31-27} = 0b11110;
3423 let Inst{15-14} = 0b10;
3427 let Inst{26} = target{23};
3428 let Inst{13} = target{22};
3429 let Inst{11} = target{21};
3430 let Inst{25-16} = target{20-11};
3431 let Inst{10-0} = target{10-0};
3432 let DecoderMethod = "DecodeT2BInstruction";
3433 let AsmMatchConverter = "cvtThumbBranches";
3436 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3437 def t2BR_JT : t2PseudoInst<(outs),
3438 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3440 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>,
3443 // FIXME: Add a non-pc based case that can be predicated.
3444 def t2TBB_JT : t2PseudoInst<(outs),
3445 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3448 def t2TBH_JT : t2PseudoInst<(outs),
3449 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3452 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3453 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3456 let Inst{31-20} = 0b111010001101;
3457 let Inst{19-16} = Rn;
3458 let Inst{15-5} = 0b11110000000;
3459 let Inst{4} = 0; // B form
3462 let DecoderMethod = "DecodeThumbTableBranch";
3465 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3466 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3469 let Inst{31-20} = 0b111010001101;
3470 let Inst{19-16} = Rn;
3471 let Inst{15-5} = 0b11110000000;
3472 let Inst{4} = 1; // H form
3475 let DecoderMethod = "DecodeThumbTableBranch";
3477 } // isNotDuplicable, isIndirectBranch
3479 } // isBranch, isTerminator, isBarrier
3481 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3482 // a two-value operand where a dag node expects ", "two operands. :(
3483 let isBranch = 1, isTerminator = 1 in
3484 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3486 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3487 let Inst{31-27} = 0b11110;
3488 let Inst{15-14} = 0b10;
3492 let Inst{25-22} = p;
3495 let Inst{26} = target{20};
3496 let Inst{11} = target{19};
3497 let Inst{13} = target{18};
3498 let Inst{21-16} = target{17-12};
3499 let Inst{10-0} = target{11-1};
3501 let DecoderMethod = "DecodeThumb2BCCInstruction";
3502 let AsmMatchConverter = "cvtThumbBranches";
3505 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3507 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3510 def tTAILJMPd: tPseudoExpand<(outs),
3511 (ins uncondbrtarget:$dst, pred:$p),
3513 (t2B uncondbrtarget:$dst, pred:$p)>,
3514 Requires<[IsThumb2, IsIOS]>, Sched<[WriteBr]>;
3518 let Defs = [ITSTATE] in
3519 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3520 AddrModeNone, 2, IIC_iALUx,
3521 "it$mask\t$cc", "", []> {
3522 // 16-bit instruction.
3523 let Inst{31-16} = 0x0000;
3524 let Inst{15-8} = 0b10111111;
3529 let Inst{3-0} = mask;
3531 let DecoderMethod = "DecodeIT";
3534 // Branch and Exchange Jazelle -- for disassembly only
3536 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []>,
3539 let Inst{31-27} = 0b11110;
3541 let Inst{25-20} = 0b111100;
3542 let Inst{19-16} = func;
3543 let Inst{15-0} = 0b1000111100000000;
3546 // Compare and branch on zero / non-zero
3547 let isBranch = 1, isTerminator = 1 in {
3548 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3549 "cbz\t$Rn, $target", []>,
3550 T1Misc<{0,0,?,1,?,?,?}>,
3551 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3555 let Inst{9} = target{5};
3556 let Inst{7-3} = target{4-0};
3560 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3561 "cbnz\t$Rn, $target", []>,
3562 T1Misc<{1,0,?,1,?,?,?}>,
3563 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3567 let Inst{9} = target{5};
3568 let Inst{7-3} = target{4-0};
3574 // Change Processor State is a system instruction.
3575 // FIXME: Since the asm parser has currently no clean way to handle optional
3576 // operands, create 3 versions of the same instruction. Once there's a clean
3577 // framework to represent optional operands, change this behavior.
3578 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3579 !strconcat("cps", asm_op), []> {
3585 let Inst{31-11} = 0b111100111010111110000;
3586 let Inst{10-9} = imod;
3588 let Inst{7-5} = iflags;
3589 let Inst{4-0} = mode;
3590 let DecoderMethod = "DecodeT2CPSInstruction";
3594 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3595 "$imod\t$iflags, $mode">;
3596 let mode = 0, M = 0 in
3597 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3598 "$imod.w\t$iflags">;
3599 let imod = 0, iflags = 0, M = 1 in
3600 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3602 def : t2InstAlias<"cps$imod.w $iflags, $mode",
3603 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
3604 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
3606 // A6.3.4 Branches and miscellaneous control
3607 // Table A6-14 Change Processor State, and hint instructions
3608 def t2HINT : T2I<(outs), (ins imm0_4:$imm), NoItinerary, "hint", "\t$imm",[]> {
3610 let Inst{31-3} = 0b11110011101011111000000000000;
3611 let Inst{2-0} = imm;
3614 def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_4:$imm, pred:$p)>;
3615 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3616 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3617 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3618 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3619 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3621 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3623 let Inst{31-20} = 0b111100111010;
3624 let Inst{19-16} = 0b1111;
3625 let Inst{15-8} = 0b10000000;
3626 let Inst{7-4} = 0b1111;
3627 let Inst{3-0} = opt;
3630 // Secure Monitor Call is a system instruction.
3631 // Option = Inst{19-16}
3632 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3633 []>, Requires<[IsThumb2, HasTrustZone]> {
3634 let Inst{31-27} = 0b11110;
3635 let Inst{26-20} = 0b1111111;
3636 let Inst{15-12} = 0b1000;
3639 let Inst{19-16} = opt;
3642 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3643 string opc, string asm, list<dag> pattern>
3644 : T2I<oops, iops, itin, opc, asm, pattern> {
3646 let Inst{31-25} = 0b1110100;
3647 let Inst{24-23} = Op;
3650 let Inst{20-16} = 0b01101;
3651 let Inst{15-5} = 0b11000000000;
3652 let Inst{4-0} = mode{4-0};
3655 // Store Return State is a system instruction.
3656 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3657 "srsdb", "\tsp!, $mode", []>;
3658 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3659 "srsdb","\tsp, $mode", []>;
3660 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3661 "srsia","\tsp!, $mode", []>;
3662 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3663 "srsia","\tsp, $mode", []>;
3666 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3667 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3669 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3670 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3672 // Return From Exception is a system instruction.
3673 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3674 string opc, string asm, list<dag> pattern>
3675 : T2I<oops, iops, itin, opc, asm, pattern> {
3676 let Inst{31-20} = op31_20{11-0};
3679 let Inst{19-16} = Rn;
3680 let Inst{15-0} = 0xc000;
3683 def t2RFEDBW : T2RFE<0b111010000011,
3684 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3685 [/* For disassembly only; pattern left blank */]>;
3686 def t2RFEDB : T2RFE<0b111010000001,
3687 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3688 [/* For disassembly only; pattern left blank */]>;
3689 def t2RFEIAW : T2RFE<0b111010011011,
3690 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3691 [/* For disassembly only; pattern left blank */]>;
3692 def t2RFEIA : T2RFE<0b111010011001,
3693 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3694 [/* For disassembly only; pattern left blank */]>;
3696 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
3697 let Defs = [PC], Uses = [LR] in
3698 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
3699 "subs", "\tpc, lr, $imm", []>, Requires<[IsThumb2]> {
3700 let Inst{31-8} = 0b111100111101111010001111;
3703 let Inst{7-0} = imm;
3706 //===----------------------------------------------------------------------===//
3707 // Non-Instruction Patterns
3710 // 32-bit immediate using movw + movt.
3711 // This is a single pseudo instruction to make it re-materializable.
3712 // FIXME: Remove this when we can do generalized remat.
3713 let isReMaterializable = 1, isMoveImm = 1 in
3714 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3715 [(set rGPR:$dst, (i32 imm:$src))]>,
3716 Requires<[IsThumb, HasV6T2]>;
3718 // Pseudo instruction that combines movw + movt + add pc (if pic).
3719 // It also makes it possible to rematerialize the instructions.
3720 // FIXME: Remove this when we can do generalized remat and when machine licm
3721 // can properly the instructions.
3722 let isReMaterializable = 1 in {
3723 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3725 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3726 Requires<[IsThumb2, UseMovt]>;
3728 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3730 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3731 Requires<[IsThumb2, UseMovt]>;
3734 // ConstantPool, GlobalAddress, and JumpTable
3735 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3736 Requires<[IsThumb2, DontUseMovt]>;
3737 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3738 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3739 Requires<[IsThumb2, UseMovt]>;
3741 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3742 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3744 // Pseudo instruction that combines ldr from constpool and add pc. This should
3745 // be expanded into two instructions late to allow if-conversion and
3747 let canFoldAsLoad = 1, isReMaterializable = 1 in
3748 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3750 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3752 Requires<[IsThumb2]>;
3754 // Pseudo isntruction that combines movs + predicated rsbmi
3755 // to implement integer ABS
3756 let usesCustomInserter = 1, Defs = [CPSR] in {
3757 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3758 NoItinerary, []>, Requires<[IsThumb2]>;
3761 //===----------------------------------------------------------------------===//
3762 // Coprocessor load/store -- for disassembly only
3764 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3765 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3766 let Inst{31-28} = op31_28;
3767 let Inst{27-25} = 0b110;
3770 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3771 def _OFFSET : T2CI<op31_28,
3772 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3773 asm, "\t$cop, $CRd, $addr"> {
3777 let Inst{24} = 1; // P = 1
3778 let Inst{23} = addr{8};
3779 let Inst{22} = Dbit;
3780 let Inst{21} = 0; // W = 0
3781 let Inst{20} = load;
3782 let Inst{19-16} = addr{12-9};
3783 let Inst{15-12} = CRd;
3784 let Inst{11-8} = cop;
3785 let Inst{7-0} = addr{7-0};
3786 let DecoderMethod = "DecodeCopMemInstruction";
3788 def _PRE : T2CI<op31_28,
3789 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3790 asm, "\t$cop, $CRd, $addr!"> {
3794 let Inst{24} = 1; // P = 1
3795 let Inst{23} = addr{8};
3796 let Inst{22} = Dbit;
3797 let Inst{21} = 1; // W = 1
3798 let Inst{20} = load;
3799 let Inst{19-16} = addr{12-9};
3800 let Inst{15-12} = CRd;
3801 let Inst{11-8} = cop;
3802 let Inst{7-0} = addr{7-0};
3803 let DecoderMethod = "DecodeCopMemInstruction";
3805 def _POST: T2CI<op31_28,
3806 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3807 postidx_imm8s4:$offset),
3808 asm, "\t$cop, $CRd, $addr, $offset"> {
3813 let Inst{24} = 0; // P = 0
3814 let Inst{23} = offset{8};
3815 let Inst{22} = Dbit;
3816 let Inst{21} = 1; // W = 1
3817 let Inst{20} = load;
3818 let Inst{19-16} = addr;
3819 let Inst{15-12} = CRd;
3820 let Inst{11-8} = cop;
3821 let Inst{7-0} = offset{7-0};
3822 let DecoderMethod = "DecodeCopMemInstruction";
3824 def _OPTION : T2CI<op31_28, (outs),
3825 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3826 coproc_option_imm:$option),
3827 asm, "\t$cop, $CRd, $addr, $option"> {
3832 let Inst{24} = 0; // P = 0
3833 let Inst{23} = 1; // U = 1
3834 let Inst{22} = Dbit;
3835 let Inst{21} = 0; // W = 0
3836 let Inst{20} = load;
3837 let Inst{19-16} = addr;
3838 let Inst{15-12} = CRd;
3839 let Inst{11-8} = cop;
3840 let Inst{7-0} = option;
3841 let DecoderMethod = "DecodeCopMemInstruction";
3845 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3846 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3847 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3848 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3849 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3850 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3851 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3852 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3855 //===----------------------------------------------------------------------===//
3856 // Move between special register and ARM core register -- for disassembly only
3858 // Move to ARM core register from Special Register
3862 // A/R class can only move from CPSR or SPSR.
3863 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3864 []>, Requires<[IsThumb2,IsARClass]> {
3866 let Inst{31-12} = 0b11110011111011111000;
3867 let Inst{11-8} = Rd;
3868 let Inst{7-0} = 0b0000;
3871 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3873 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3874 []>, Requires<[IsThumb2,IsARClass]> {
3876 let Inst{31-12} = 0b11110011111111111000;
3877 let Inst{11-8} = Rd;
3878 let Inst{7-0} = 0b0000;
3883 // This MRS has a mask field in bits 7-0 and can take more values than
3884 // the A/R class (a full msr_mask).
3885 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3886 "mrs", "\t$Rd, $mask", []>,
3887 Requires<[IsThumb,IsMClass]> {
3890 let Inst{31-12} = 0b11110011111011111000;
3891 let Inst{11-8} = Rd;
3892 let Inst{19-16} = 0b1111;
3893 let Inst{7-0} = mask;
3897 // Move from ARM core register to Special Register
3901 // No need to have both system and application versions, the encodings are the
3902 // same and the assembly parser has no way to distinguish between them. The mask
3903 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3904 // the mask with the fields to be accessed in the special register.
3905 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3906 NoItinerary, "msr", "\t$mask, $Rn", []>,
3907 Requires<[IsThumb2,IsARClass]> {
3910 let Inst{31-21} = 0b11110011100;
3911 let Inst{20} = mask{4}; // R Bit
3912 let Inst{19-16} = Rn;
3913 let Inst{15-12} = 0b1000;
3914 let Inst{11-8} = mask{3-0};
3920 // Move from ARM core register to Special Register
3921 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3922 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3923 Requires<[IsThumb,IsMClass]> {
3926 let Inst{31-21} = 0b11110011100;
3928 let Inst{19-16} = Rn;
3929 let Inst{15-12} = 0b1000;
3930 let Inst{11-0} = SYSm;
3934 //===----------------------------------------------------------------------===//
3935 // Move between coprocessor and ARM core register
3938 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3940 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3942 let Inst{27-24} = 0b1110;
3943 let Inst{20} = direction;
3953 let Inst{15-12} = Rt;
3954 let Inst{11-8} = cop;
3955 let Inst{23-21} = opc1;
3956 let Inst{7-5} = opc2;
3957 let Inst{3-0} = CRm;
3958 let Inst{19-16} = CRn;
3961 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3962 list<dag> pattern = []>
3964 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3965 opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3966 let Inst{27-24} = 0b1100;
3967 let Inst{23-21} = 0b010;
3968 let Inst{20} = direction;
3976 let Inst{15-12} = Rt;
3977 let Inst{19-16} = Rt2;
3978 let Inst{11-8} = cop;
3979 let Inst{7-4} = opc1;
3980 let Inst{3-0} = CRm;
3983 /* from ARM core register to coprocessor */
3984 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3986 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3987 c_imm:$CRm, imm0_7:$opc2),
3988 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3989 imm:$CRm, imm:$opc2)]>;
3990 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
3991 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3992 c_imm:$CRm, 0, pred:$p)>;
3993 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3994 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3995 c_imm:$CRm, imm0_7:$opc2),
3996 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3997 imm:$CRm, imm:$opc2)]>;
3998 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
3999 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4000 c_imm:$CRm, 0, pred:$p)>;
4002 /* from coprocessor to ARM core register */
4003 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
4004 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4005 c_imm:$CRm, imm0_7:$opc2), []>;
4006 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4007 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4008 c_imm:$CRm, 0, pred:$p)>;
4010 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4011 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4012 c_imm:$CRm, imm0_7:$opc2), []>;
4013 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4014 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4015 c_imm:$CRm, 0, pred:$p)>;
4017 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4018 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4020 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4021 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4024 /* from ARM core register to coprocessor */
4025 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
4026 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4028 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
4029 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
4030 GPR:$Rt2, imm:$CRm)]>;
4031 /* from coprocessor to ARM core register */
4032 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
4034 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
4036 //===----------------------------------------------------------------------===//
4037 // Other Coprocessor Instructions.
4040 def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4041 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4042 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4043 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4044 imm:$CRm, imm:$opc2)]> {
4045 let Inst{27-24} = 0b1110;
4054 let Inst{3-0} = CRm;
4056 let Inst{7-5} = opc2;
4057 let Inst{11-8} = cop;
4058 let Inst{15-12} = CRd;
4059 let Inst{19-16} = CRn;
4060 let Inst{23-20} = opc1;
4063 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4064 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4065 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4066 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4067 imm:$CRm, imm:$opc2)]> {
4068 let Inst{27-24} = 0b1110;
4077 let Inst{3-0} = CRm;
4079 let Inst{7-5} = opc2;
4080 let Inst{11-8} = cop;
4081 let Inst{15-12} = CRd;
4082 let Inst{19-16} = CRn;
4083 let Inst{23-20} = opc1;
4088 //===----------------------------------------------------------------------===//
4089 // Non-Instruction Patterns
4092 // SXT/UXT with no rotate
4093 let AddedComplexity = 16 in {
4094 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4095 Requires<[IsThumb2]>;
4096 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4097 Requires<[IsThumb2]>;
4098 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4099 Requires<[HasT2ExtractPack, IsThumb2]>;
4100 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4101 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4102 Requires<[HasT2ExtractPack, IsThumb2]>;
4103 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4104 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4105 Requires<[HasT2ExtractPack, IsThumb2]>;
4108 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4109 Requires<[IsThumb2]>;
4110 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4111 Requires<[IsThumb2]>;
4112 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4113 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4114 Requires<[HasT2ExtractPack, IsThumb2]>;
4115 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4116 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4117 Requires<[HasT2ExtractPack, IsThumb2]>;
4119 // Atomic load/store patterns
4120 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4121 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4122 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4123 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4124 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4125 (t2LDRBs t2addrmode_so_reg:$addr)>;
4126 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4127 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4128 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4129 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4130 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4131 (t2LDRHs t2addrmode_so_reg:$addr)>;
4132 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4133 (t2LDRi12 t2addrmode_imm12:$addr)>;
4134 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4135 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4136 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4137 (t2LDRs t2addrmode_so_reg:$addr)>;
4138 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4139 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4140 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4141 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4142 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4143 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4144 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4145 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4146 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4147 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4148 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4149 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4150 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4151 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4152 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4153 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4154 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4155 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4158 //===----------------------------------------------------------------------===//
4159 // Assembler aliases
4162 // Aliases for ADC without the ".w" optional width specifier.
4163 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4164 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4165 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4166 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4167 pred:$p, cc_out:$s)>;
4169 // Aliases for SBC without the ".w" optional width specifier.
4170 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4171 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4172 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4173 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4174 pred:$p, cc_out:$s)>;
4176 // Aliases for ADD without the ".w" optional width specifier.
4177 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4178 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4180 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4181 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4182 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4183 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4184 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4185 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4186 pred:$p, cc_out:$s)>;
4187 // ... and with the destination and source register combined.
4188 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4189 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4190 def : t2InstAlias<"add${p} $Rdn, $imm",
4191 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4192 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4193 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4194 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4195 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4196 pred:$p, cc_out:$s)>;
4198 // add w/ negative immediates is just a sub.
4199 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4200 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4202 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4203 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4204 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4205 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4207 def : t2InstAlias<"add${p} $Rdn, $imm",
4208 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4210 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4211 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4213 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4214 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4215 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4216 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4218 def : t2InstAlias<"addw${p} $Rdn, $imm",
4219 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4222 // Aliases for SUB without the ".w" optional width specifier.
4223 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4224 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4225 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4226 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4227 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4228 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4229 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4230 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4231 pred:$p, cc_out:$s)>;
4232 // ... and with the destination and source register combined.
4233 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4234 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4235 def : t2InstAlias<"sub${p} $Rdn, $imm",
4236 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4237 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4238 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4239 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4240 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4241 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4242 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4243 pred:$p, cc_out:$s)>;
4245 // Alias for compares without the ".w" optional width specifier.
4246 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4247 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4248 def : t2InstAlias<"teq${p} $Rn, $Rm",
4249 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4250 def : t2InstAlias<"tst${p} $Rn, $Rm",
4251 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4254 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
4255 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
4256 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
4258 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4260 def : t2InstAlias<"ldr${p} $Rt, $addr",
4261 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4262 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4263 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4264 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4265 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4266 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4267 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4268 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4269 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4271 def : t2InstAlias<"ldr${p} $Rt, $addr",
4272 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4273 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4274 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4275 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4276 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4277 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4278 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4279 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4280 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4282 def : t2InstAlias<"ldr${p} $Rt, $addr",
4283 (t2LDRpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4284 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4285 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4286 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4287 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4288 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4289 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4290 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4291 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4293 // Alias for MVN with(out) the ".w" optional width specifier.
4294 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4295 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4296 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4297 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4298 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4299 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4301 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4302 // shift amount is zero (i.e., unspecified).
4303 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4304 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4305 Requires<[HasT2ExtractPack, IsThumb2]>;
4306 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4307 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4308 Requires<[HasT2ExtractPack, IsThumb2]>;
4310 // PUSH/POP aliases for STM/LDM
4311 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4312 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4313 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4314 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4316 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4317 def : t2InstAlias<"stm${p} $Rn, $regs",
4318 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4319 def : t2InstAlias<"stm${p} $Rn!, $regs",
4320 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4322 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4323 def : t2InstAlias<"ldm${p} $Rn, $regs",
4324 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4325 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4326 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4328 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4329 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4330 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4331 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4332 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4334 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4335 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4336 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4337 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4338 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4340 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4341 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4342 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4343 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4346 // Alias for RSB without the ".w" optional width specifier, and with optional
4347 // implied destination register.
4348 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4349 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4350 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4351 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4352 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4353 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4354 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4355 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4358 // SSAT/USAT optional shift operand.
4359 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4360 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4361 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4362 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4364 // STM w/o the .w suffix.
4365 def : t2InstAlias<"stm${p} $Rn, $regs",
4366 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4368 // Alias for STR, STRB, and STRH without the ".w" optional
4370 def : t2InstAlias<"str${p} $Rt, $addr",
4371 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4372 def : t2InstAlias<"strb${p} $Rt, $addr",
4373 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4374 def : t2InstAlias<"strh${p} $Rt, $addr",
4375 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4377 def : t2InstAlias<"str${p} $Rt, $addr",
4378 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4379 def : t2InstAlias<"strb${p} $Rt, $addr",
4380 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4381 def : t2InstAlias<"strh${p} $Rt, $addr",
4382 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4384 // Extend instruction optional rotate operand.
4385 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4386 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4387 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4388 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4389 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4390 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4392 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4393 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4394 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4395 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4396 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4397 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4398 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4399 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4400 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4401 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4403 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4404 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4405 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4406 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4407 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4408 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4409 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4410 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4411 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4412 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4413 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4414 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4416 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4417 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4418 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4419 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4421 // Extend instruction w/o the ".w" optional width specifier.
4422 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4423 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4424 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4425 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4426 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4427 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4429 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4430 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4431 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4432 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4433 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4434 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4437 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4439 def : t2InstAlias<"mov${p} $Rd, $imm",
4440 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4441 def : t2InstAlias<"mvn${p} $Rd, $imm",
4442 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4443 // Same for AND <--> BIC
4444 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4445 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4446 pred:$p, cc_out:$s)>;
4447 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4448 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4449 pred:$p, cc_out:$s)>;
4450 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4451 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4452 pred:$p, cc_out:$s)>;
4453 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4454 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4455 pred:$p, cc_out:$s)>;
4456 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4457 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4458 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4459 pred:$p, cc_out:$s)>;
4460 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4461 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4462 pred:$p, cc_out:$s)>;
4463 // Same for CMP <--> CMN via t2_so_imm_neg
4464 def : t2InstAlias<"cmp${p} $Rd, $imm",
4465 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4466 def : t2InstAlias<"cmn${p} $Rd, $imm",
4467 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4470 // Wide 'mul' encoding can be specified with only two operands.
4471 def : t2InstAlias<"mul${p} $Rn, $Rm",
4472 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4474 // "neg" is and alias for "rsb rd, rn, #0"
4475 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4476 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4478 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4479 // these, unfortunately.
4480 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4481 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4482 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4483 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4485 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4486 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4487 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4488 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4490 // ADR w/o the .w suffix
4491 def : t2InstAlias<"adr${p} $Rd, $addr",
4492 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4494 // LDR(literal) w/ alternate [pc, #imm] syntax.
4495 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4496 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4497 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4498 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4499 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4500 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4501 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4502 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4503 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4504 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4505 // Version w/ the .w suffix.
4506 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4507 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;
4508 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4509 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4510 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4511 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4512 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4513 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4514 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4515 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4517 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4518 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
4520 // PLD/PLDW/PLI with alternate literal form.
4521 def : t2InstAlias<"pld${p} $addr",
4522 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
4523 def : InstAlias<"pli${p} $addr",
4524 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p)>,
4525 Requires<[IsThumb2,HasV7]>;