1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // Shifted operands. No register controlled shifts for Thumb2.
32 // Note: We do not support rrx shifted operands yet.
33 def t2_so_reg : Operand<i32>, // reg imm
34 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
36 let EncoderMethod = "getT2SORegOpValue";
37 let PrintMethod = "printT2SOOperand";
38 let DecoderMethod = "DecodeSORegImmOperand";
39 let ParserMatchClass = ShiftedImmAsmOperand;
40 let MIOperandInfo = (ops rGPR, i32imm);
43 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
44 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
48 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
49 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
50 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
53 // t2_so_imm - Match a 32-bit immediate operand, which is an
54 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
55 // immediate splatted into multiple bytes of the word.
56 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
57 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
58 return ARM_AM::getT2SOImmVal(Imm) != -1;
60 let ParserMatchClass = t2_so_imm_asmoperand;
61 let EncoderMethod = "getT2SOImmOpValue";
62 let DecoderMethod = "DecodeT2SOImm";
65 // t2_so_imm_not - Match an immediate that is a complement
67 def t2_so_imm_not : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
70 }], t2_so_imm_not_XFORM>;
72 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
73 def t2_so_imm_neg : Operand<i32>,
75 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
76 }], t2_so_imm_neg_XFORM>;
78 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
79 def imm0_4095 : Operand<i32>,
81 return Imm >= 0 && Imm < 4096;
84 def imm0_4095_neg : PatLeaf<(i32 imm), [{
85 return (uint32_t)(-N->getZExtValue()) < 4096;
88 def imm0_255_neg : PatLeaf<(i32 imm), [{
89 return (uint32_t)(-N->getZExtValue()) < 255;
92 def imm0_255_not : PatLeaf<(i32 imm), [{
93 return (uint32_t)(~N->getZExtValue()) < 255;
96 def lo5AllOne : PatLeaf<(i32 imm), [{
97 // Returns true if all low 5-bits are 1.
98 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
101 // Define Thumb2 specific addressing modes.
103 // t2addrmode_imm12 := reg + imm12
104 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
105 def t2addrmode_imm12 : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
107 let PrintMethod = "printAddrModeImm12Operand";
108 let EncoderMethod = "getAddrModeImm12OpValue";
109 let DecoderMethod = "DecodeT2AddrModeImm12";
110 let ParserMatchClass = t2addrmode_imm12_asmoperand;
111 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
114 // t2ldrlabel := imm12
115 def t2ldrlabel : Operand<i32> {
116 let EncoderMethod = "getAddrModeImm12OpValue";
120 // ADR instruction labels.
121 def t2adrlabel : Operand<i32> {
122 let EncoderMethod = "getT2AdrLabelOpValue";
126 // t2addrmode_posimm8 := reg + imm8
127 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
128 def t2addrmode_posimm8 : Operand<i32> {
129 let PrintMethod = "printT2AddrModeImm8Operand";
130 let EncoderMethod = "getT2AddrModeImm8OpValue";
131 let DecoderMethod = "DecodeT2AddrModeImm8";
132 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
133 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
136 // t2addrmode_negimm8 := reg - imm8
137 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
138 def t2addrmode_negimm8 : Operand<i32>,
139 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
140 let PrintMethod = "printT2AddrModeImm8Operand";
141 let EncoderMethod = "getT2AddrModeImm8OpValue";
142 let DecoderMethod = "DecodeT2AddrModeImm8";
143 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
144 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
147 // t2addrmode_imm8 := reg +/- imm8
148 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
149 def t2addrmode_imm8 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
151 let PrintMethod = "printT2AddrModeImm8Operand";
152 let EncoderMethod = "getT2AddrModeImm8OpValue";
153 let DecoderMethod = "DecodeT2AddrModeImm8";
154 let ParserMatchClass = MemImm8OffsetAsmOperand;
155 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
158 def t2am_imm8_offset : Operand<i32>,
159 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
160 [], [SDNPWantRoot]> {
161 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
162 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
163 let DecoderMethod = "DecodeT2Imm8";
166 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
167 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
168 def t2addrmode_imm8s4 : Operand<i32> {
169 let PrintMethod = "printT2AddrModeImm8s4Operand";
170 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
171 let DecoderMethod = "DecodeT2AddrModeImm8s4";
172 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
173 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
176 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
177 def t2am_imm8s4_offset : Operand<i32> {
178 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
179 let EncoderMethod = "getT2Imm8s4OpValue";
180 let DecoderMethod = "DecodeT2Imm8S4";
183 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
184 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
185 let Name = "MemImm0_1020s4Offset";
187 def t2addrmode_imm0_1020s4 : Operand<i32> {
188 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
189 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
190 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
191 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
192 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
195 // t2addrmode_so_reg := reg + (reg << imm2)
196 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
197 def t2addrmode_so_reg : Operand<i32>,
198 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
199 let PrintMethod = "printT2AddrModeSoRegOperand";
200 let EncoderMethod = "getT2AddrModeSORegOpValue";
201 let DecoderMethod = "DecodeT2AddrModeSOReg";
202 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
203 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
206 //===----------------------------------------------------------------------===//
207 // Multiclass helpers...
211 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
212 string opc, string asm, list<dag> pattern>
213 : T2I<oops, iops, itin, opc, asm, pattern> {
218 let Inst{26} = imm{11};
219 let Inst{14-12} = imm{10-8};
220 let Inst{7-0} = imm{7-0};
224 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
225 string opc, string asm, list<dag> pattern>
226 : T2sI<oops, iops, itin, opc, asm, pattern> {
232 let Inst{26} = imm{11};
233 let Inst{14-12} = imm{10-8};
234 let Inst{7-0} = imm{7-0};
237 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
238 string opc, string asm, list<dag> pattern>
239 : T2I<oops, iops, itin, opc, asm, pattern> {
243 let Inst{19-16} = Rn;
244 let Inst{26} = imm{11};
245 let Inst{14-12} = imm{10-8};
246 let Inst{7-0} = imm{7-0};
250 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
251 string opc, string asm, list<dag> pattern>
252 : T2I<oops, iops, itin, opc, asm, pattern> {
257 let Inst{3-0} = ShiftedRm{3-0};
258 let Inst{5-4} = ShiftedRm{6-5};
259 let Inst{14-12} = ShiftedRm{11-9};
260 let Inst{7-6} = ShiftedRm{8-7};
263 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
264 string opc, string asm, list<dag> pattern>
265 : T2sI<oops, iops, itin, opc, asm, pattern> {
270 let Inst{3-0} = ShiftedRm{3-0};
271 let Inst{5-4} = ShiftedRm{6-5};
272 let Inst{14-12} = ShiftedRm{11-9};
273 let Inst{7-6} = ShiftedRm{8-7};
276 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
277 string opc, string asm, list<dag> pattern>
278 : T2I<oops, iops, itin, opc, asm, pattern> {
282 let Inst{19-16} = Rn;
283 let Inst{3-0} = ShiftedRm{3-0};
284 let Inst{5-4} = ShiftedRm{6-5};
285 let Inst{14-12} = ShiftedRm{11-9};
286 let Inst{7-6} = ShiftedRm{8-7};
289 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
290 string opc, string asm, list<dag> pattern>
291 : T2I<oops, iops, itin, opc, asm, pattern> {
299 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
300 string opc, string asm, list<dag> pattern>
301 : T2sI<oops, iops, itin, opc, asm, pattern> {
309 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
310 string opc, string asm, list<dag> pattern>
311 : T2I<oops, iops, itin, opc, asm, pattern> {
315 let Inst{19-16} = Rn;
320 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
321 string opc, string asm, list<dag> pattern>
322 : T2I<oops, iops, itin, opc, asm, pattern> {
328 let Inst{19-16} = Rn;
329 let Inst{26} = imm{11};
330 let Inst{14-12} = imm{10-8};
331 let Inst{7-0} = imm{7-0};
334 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
335 string opc, string asm, list<dag> pattern>
336 : T2sI<oops, iops, itin, opc, asm, pattern> {
342 let Inst{19-16} = Rn;
343 let Inst{26} = imm{11};
344 let Inst{14-12} = imm{10-8};
345 let Inst{7-0} = imm{7-0};
348 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
349 string opc, string asm, list<dag> pattern>
350 : T2I<oops, iops, itin, opc, asm, pattern> {
357 let Inst{14-12} = imm{4-2};
358 let Inst{7-6} = imm{1-0};
361 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
362 string opc, string asm, list<dag> pattern>
363 : T2sI<oops, iops, itin, opc, asm, pattern> {
370 let Inst{14-12} = imm{4-2};
371 let Inst{7-6} = imm{1-0};
374 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
375 string opc, string asm, list<dag> pattern>
376 : T2I<oops, iops, itin, opc, asm, pattern> {
382 let Inst{19-16} = Rn;
386 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
387 string opc, string asm, list<dag> pattern>
388 : T2sI<oops, iops, itin, opc, asm, pattern> {
394 let Inst{19-16} = Rn;
398 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
399 string opc, string asm, list<dag> pattern>
400 : T2I<oops, iops, itin, opc, asm, pattern> {
406 let Inst{19-16} = Rn;
407 let Inst{3-0} = ShiftedRm{3-0};
408 let Inst{5-4} = ShiftedRm{6-5};
409 let Inst{14-12} = ShiftedRm{11-9};
410 let Inst{7-6} = ShiftedRm{8-7};
413 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
414 string opc, string asm, list<dag> pattern>
415 : T2sI<oops, iops, itin, opc, asm, pattern> {
421 let Inst{19-16} = Rn;
422 let Inst{3-0} = ShiftedRm{3-0};
423 let Inst{5-4} = ShiftedRm{6-5};
424 let Inst{14-12} = ShiftedRm{11-9};
425 let Inst{7-6} = ShiftedRm{8-7};
428 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
429 string opc, string asm, list<dag> pattern>
430 : T2I<oops, iops, itin, opc, asm, pattern> {
436 let Inst{19-16} = Rn;
437 let Inst{15-12} = Ra;
442 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
443 dag oops, dag iops, InstrItinClass itin,
444 string opc, string asm, list<dag> pattern>
445 : T2I<oops, iops, itin, opc, asm, pattern> {
451 let Inst{31-23} = 0b111110111;
452 let Inst{22-20} = opc22_20;
453 let Inst{19-16} = Rn;
454 let Inst{15-12} = RdLo;
455 let Inst{11-8} = RdHi;
456 let Inst{7-4} = opc7_4;
461 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
462 /// unary operation that produces a value. These are predicable and can be
463 /// changed to modify CPSR.
464 multiclass T2I_un_irs<bits<4> opcod, string opc,
465 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
466 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
468 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
470 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
471 let isAsCheapAsAMove = Cheap;
472 let isReMaterializable = ReMat;
473 let Inst{31-27} = 0b11110;
475 let Inst{24-21} = opcod;
476 let Inst{19-16} = 0b1111; // Rn
480 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
482 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
483 let Inst{31-27} = 0b11101;
484 let Inst{26-25} = 0b01;
485 let Inst{24-21} = opcod;
486 let Inst{19-16} = 0b1111; // Rn
487 let Inst{14-12} = 0b000; // imm3
488 let Inst{7-6} = 0b00; // imm2
489 let Inst{5-4} = 0b00; // type
492 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
493 opc, ".w\t$Rd, $ShiftedRm",
494 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
495 let Inst{31-27} = 0b11101;
496 let Inst{26-25} = 0b01;
497 let Inst{24-21} = opcod;
498 let Inst{19-16} = 0b1111; // Rn
502 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
503 /// binary operation that produces a value. These are predicable and can be
504 /// changed to modify CPSR.
505 multiclass T2I_bin_irs<bits<4> opcod, string opc,
506 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
507 PatFrag opnode, string baseOpc, bit Commutable = 0,
510 def ri : T2sTwoRegImm<
511 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
512 opc, "\t$Rd, $Rn, $imm",
513 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
514 let Inst{31-27} = 0b11110;
516 let Inst{24-21} = opcod;
520 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
521 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
522 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
523 let isCommutable = Commutable;
524 let Inst{31-27} = 0b11101;
525 let Inst{26-25} = 0b01;
526 let Inst{24-21} = opcod;
527 let Inst{14-12} = 0b000; // imm3
528 let Inst{7-6} = 0b00; // imm2
529 let Inst{5-4} = 0b00; // type
532 def rs : T2sTwoRegShiftedReg<
533 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
534 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
535 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
536 let Inst{31-27} = 0b11101;
537 let Inst{26-25} = 0b01;
538 let Inst{24-21} = opcod;
540 // Assembly aliases for optional destination operand when it's the same
541 // as the source operand.
542 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
543 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
544 t2_so_imm:$imm, pred:$p,
546 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
547 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
550 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
551 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
552 t2_so_reg:$shift, pred:$p,
556 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
557 // the ".w" suffix to indicate that they are wide.
558 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
559 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
560 PatFrag opnode, string baseOpc, bit Commutable = 0> :
561 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
562 // Assembler aliases w/o the ".w" suffix.
563 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
564 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
567 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
568 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
569 t2_so_reg:$shift, pred:$p,
572 // and with the optional destination operand, too.
573 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
574 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
577 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
578 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
579 t2_so_reg:$shift, pred:$p,
583 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
584 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
585 /// it is equivalent to the T2I_bin_irs counterpart.
586 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
588 def ri : T2sTwoRegImm<
589 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
590 opc, ".w\t$Rd, $Rn, $imm",
591 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
592 let Inst{31-27} = 0b11110;
594 let Inst{24-21} = opcod;
598 def rr : T2sThreeReg<
599 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
600 opc, "\t$Rd, $Rn, $Rm",
601 [/* For disassembly only; pattern left blank */]> {
602 let Inst{31-27} = 0b11101;
603 let Inst{26-25} = 0b01;
604 let Inst{24-21} = opcod;
605 let Inst{14-12} = 0b000; // imm3
606 let Inst{7-6} = 0b00; // imm2
607 let Inst{5-4} = 0b00; // type
610 def rs : T2sTwoRegShiftedReg<
611 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
612 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
613 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
614 let Inst{31-27} = 0b11101;
615 let Inst{26-25} = 0b01;
616 let Inst{24-21} = opcod;
620 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
621 /// instruction modifies the CPSR register.
622 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
623 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
624 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
625 PatFrag opnode, bit Commutable = 0> {
627 def ri : T2sTwoRegImm<
628 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
629 opc, ".w\t$Rd, $Rn, $imm",
630 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
631 let Inst{31-27} = 0b11110;
633 let Inst{24-21} = opcod;
637 def rr : T2sThreeReg<
638 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
639 opc, ".w\t$Rd, $Rn, $Rm",
640 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
641 let isCommutable = Commutable;
642 let Inst{31-27} = 0b11101;
643 let Inst{26-25} = 0b01;
644 let Inst{24-21} = opcod;
645 let Inst{14-12} = 0b000; // imm3
646 let Inst{7-6} = 0b00; // imm2
647 let Inst{5-4} = 0b00; // type
650 def rs : T2sTwoRegShiftedReg<
651 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
652 opc, ".w\t$Rd, $Rn, $ShiftedRm",
653 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
654 let Inst{31-27} = 0b11101;
655 let Inst{26-25} = 0b01;
656 let Inst{24-21} = opcod;
661 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
662 /// patterns for a binary operation that produces a value.
663 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
664 bit Commutable = 0> {
666 // The register-immediate version is re-materializable. This is useful
667 // in particular for taking the address of a local.
668 let isReMaterializable = 1 in {
669 def ri : T2sTwoRegImm<
670 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
671 opc, ".w\t$Rd, $Rn, $imm",
672 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
673 let Inst{31-27} = 0b11110;
676 let Inst{23-21} = op23_21;
682 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
683 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
684 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
688 let Inst{31-27} = 0b11110;
689 let Inst{26} = imm{11};
690 let Inst{25-24} = 0b10;
691 let Inst{23-21} = op23_21;
692 let Inst{20} = 0; // The S bit.
693 let Inst{19-16} = Rn;
695 let Inst{14-12} = imm{10-8};
697 let Inst{7-0} = imm{7-0};
700 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
701 opc, ".w\t$Rd, $Rn, $Rm",
702 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
703 let isCommutable = Commutable;
704 let Inst{31-27} = 0b11101;
705 let Inst{26-25} = 0b01;
707 let Inst{23-21} = op23_21;
708 let Inst{14-12} = 0b000; // imm3
709 let Inst{7-6} = 0b00; // imm2
710 let Inst{5-4} = 0b00; // type
713 def rs : T2sTwoRegShiftedReg<
714 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
715 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
716 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
717 let Inst{31-27} = 0b11101;
718 let Inst{26-25} = 0b01;
720 let Inst{23-21} = op23_21;
724 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
725 /// for a binary operation that produces a value and use the carry
726 /// bit. It's not predicable.
727 let Defs = [CPSR], Uses = [CPSR] in {
728 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
729 bit Commutable = 0> {
731 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
732 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
733 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
734 Requires<[IsThumb2]> {
735 let Inst{31-27} = 0b11110;
737 let Inst{24-21} = opcod;
741 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
742 opc, ".w\t$Rd, $Rn, $Rm",
743 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
744 Requires<[IsThumb2]> {
745 let isCommutable = Commutable;
746 let Inst{31-27} = 0b11101;
747 let Inst{26-25} = 0b01;
748 let Inst{24-21} = opcod;
749 let Inst{14-12} = 0b000; // imm3
750 let Inst{7-6} = 0b00; // imm2
751 let Inst{5-4} = 0b00; // type
754 def rs : T2sTwoRegShiftedReg<
755 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
756 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
757 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
758 Requires<[IsThumb2]> {
759 let Inst{31-27} = 0b11101;
760 let Inst{26-25} = 0b01;
761 let Inst{24-21} = opcod;
766 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
767 /// version is not needed since this is only for codegen.
768 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
769 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
771 def ri : T2sTwoRegImm<
772 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
773 opc, ".w\t$Rd, $Rn, $imm",
774 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
775 let Inst{31-27} = 0b11110;
777 let Inst{24-21} = opcod;
781 def rs : T2sTwoRegShiftedReg<
782 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
783 IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
784 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
785 let Inst{31-27} = 0b11101;
786 let Inst{26-25} = 0b01;
787 let Inst{24-21} = opcod;
792 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
793 // rotate operation that produces a value.
794 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
797 def ri : T2sTwoRegShiftImm<
798 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
799 opc, ".w\t$Rd, $Rm, $imm",
800 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
801 let Inst{31-27} = 0b11101;
802 let Inst{26-21} = 0b010010;
803 let Inst{19-16} = 0b1111; // Rn
804 let Inst{5-4} = opcod;
807 def rr : T2sThreeReg<
808 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
809 opc, ".w\t$Rd, $Rn, $Rm",
810 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
811 let Inst{31-27} = 0b11111;
812 let Inst{26-23} = 0b0100;
813 let Inst{22-21} = opcod;
814 let Inst{15-12} = 0b1111;
815 let Inst{7-4} = 0b0000;
818 // Optional destination register
819 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
820 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
823 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
824 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
828 // Assembler aliases w/o the ".w" suffix.
829 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
830 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
833 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
834 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
838 // and with the optional destination operand, too.
839 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
840 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
843 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
844 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
849 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
850 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
851 /// a explicit result, only implicitly set CPSR.
852 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
853 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
854 PatFrag opnode, string baseOpc> {
855 let isCompare = 1, Defs = [CPSR] in {
857 def ri : T2OneRegCmpImm<
858 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
859 opc, ".w\t$Rn, $imm",
860 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
861 let Inst{31-27} = 0b11110;
863 let Inst{24-21} = opcod;
864 let Inst{20} = 1; // The S bit.
866 let Inst{11-8} = 0b1111; // Rd
869 def rr : T2TwoRegCmp<
870 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
872 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
873 let Inst{31-27} = 0b11101;
874 let Inst{26-25} = 0b01;
875 let Inst{24-21} = opcod;
876 let Inst{20} = 1; // The S bit.
877 let Inst{14-12} = 0b000; // imm3
878 let Inst{11-8} = 0b1111; // Rd
879 let Inst{7-6} = 0b00; // imm2
880 let Inst{5-4} = 0b00; // type
883 def rs : T2OneRegCmpShiftedReg<
884 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
885 opc, ".w\t$Rn, $ShiftedRm",
886 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
887 let Inst{31-27} = 0b11101;
888 let Inst{26-25} = 0b01;
889 let Inst{24-21} = opcod;
890 let Inst{20} = 1; // The S bit.
891 let Inst{11-8} = 0b1111; // Rd
895 // Assembler aliases w/o the ".w" suffix.
896 // No alias here for 'rr' version as not all instantiations of this
897 // multiclass want one (CMP in particular, does not).
898 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
899 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
900 t2_so_imm:$imm, pred:$p)>;
901 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
902 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
907 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
908 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
909 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
911 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
912 opc, ".w\t$Rt, $addr",
913 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
916 let Inst{31-25} = 0b1111100;
917 let Inst{24} = signed;
919 let Inst{22-21} = opcod;
920 let Inst{20} = 1; // load
921 let Inst{19-16} = addr{16-13}; // Rn
922 let Inst{15-12} = Rt;
923 let Inst{11-0} = addr{11-0}; // imm
925 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
927 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
930 let Inst{31-27} = 0b11111;
931 let Inst{26-25} = 0b00;
932 let Inst{24} = signed;
934 let Inst{22-21} = opcod;
935 let Inst{20} = 1; // load
936 let Inst{19-16} = addr{12-9}; // Rn
937 let Inst{15-12} = Rt;
939 // Offset: index==TRUE, wback==FALSE
940 let Inst{10} = 1; // The P bit.
941 let Inst{9} = addr{8}; // U
942 let Inst{8} = 0; // The W bit.
943 let Inst{7-0} = addr{7-0}; // imm
945 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
946 opc, ".w\t$Rt, $addr",
947 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
948 let Inst{31-27} = 0b11111;
949 let Inst{26-25} = 0b00;
950 let Inst{24} = signed;
952 let Inst{22-21} = opcod;
953 let Inst{20} = 1; // load
954 let Inst{11-6} = 0b000000;
957 let Inst{15-12} = Rt;
960 let Inst{19-16} = addr{9-6}; // Rn
961 let Inst{3-0} = addr{5-2}; // Rm
962 let Inst{5-4} = addr{1-0}; // imm
964 let DecoderMethod = "DecodeT2LoadShift";
967 // FIXME: Is the pci variant actually needed?
968 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
969 opc, ".w\t$Rt, $addr",
970 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
971 let isReMaterializable = 1;
972 let Inst{31-27} = 0b11111;
973 let Inst{26-25} = 0b00;
974 let Inst{24} = signed;
975 let Inst{23} = ?; // add = (U == '1')
976 let Inst{22-21} = opcod;
977 let Inst{20} = 1; // load
978 let Inst{19-16} = 0b1111; // Rn
981 let Inst{15-12} = Rt{3-0};
982 let Inst{11-0} = addr{11-0};
986 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
987 multiclass T2I_st<bits<2> opcod, string opc,
988 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
990 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
991 opc, ".w\t$Rt, $addr",
992 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
993 let Inst{31-27} = 0b11111;
994 let Inst{26-23} = 0b0001;
995 let Inst{22-21} = opcod;
996 let Inst{20} = 0; // !load
999 let Inst{15-12} = Rt;
1002 let addr{12} = 1; // add = TRUE
1003 let Inst{19-16} = addr{16-13}; // Rn
1004 let Inst{23} = addr{12}; // U
1005 let Inst{11-0} = addr{11-0}; // imm
1007 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1008 opc, "\t$Rt, $addr",
1009 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1010 let Inst{31-27} = 0b11111;
1011 let Inst{26-23} = 0b0000;
1012 let Inst{22-21} = opcod;
1013 let Inst{20} = 0; // !load
1015 // Offset: index==TRUE, wback==FALSE
1016 let Inst{10} = 1; // The P bit.
1017 let Inst{8} = 0; // The W bit.
1020 let Inst{15-12} = Rt;
1023 let Inst{19-16} = addr{12-9}; // Rn
1024 let Inst{9} = addr{8}; // U
1025 let Inst{7-0} = addr{7-0}; // imm
1027 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1028 opc, ".w\t$Rt, $addr",
1029 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1030 let Inst{31-27} = 0b11111;
1031 let Inst{26-23} = 0b0000;
1032 let Inst{22-21} = opcod;
1033 let Inst{20} = 0; // !load
1034 let Inst{11-6} = 0b000000;
1037 let Inst{15-12} = Rt;
1040 let Inst{19-16} = addr{9-6}; // Rn
1041 let Inst{3-0} = addr{5-2}; // Rm
1042 let Inst{5-4} = addr{1-0}; // imm
1046 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1047 /// register and one whose operand is a register rotated by 8/16/24.
1048 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1049 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1050 opc, ".w\t$Rd, $Rm$rot",
1051 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1052 Requires<[IsThumb2]> {
1053 let Inst{31-27} = 0b11111;
1054 let Inst{26-23} = 0b0100;
1055 let Inst{22-20} = opcod;
1056 let Inst{19-16} = 0b1111; // Rn
1057 let Inst{15-12} = 0b1111;
1061 let Inst{5-4} = rot{1-0}; // rotate
1064 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1065 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1066 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1067 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1068 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1069 Requires<[HasT2ExtractPack, IsThumb2]> {
1071 let Inst{31-27} = 0b11111;
1072 let Inst{26-23} = 0b0100;
1073 let Inst{22-20} = opcod;
1074 let Inst{19-16} = 0b1111; // Rn
1075 let Inst{15-12} = 0b1111;
1077 let Inst{5-4} = rot;
1080 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1082 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1083 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1084 opc, "\t$Rd, $Rm$rot", []>,
1085 Requires<[IsThumb2, HasT2ExtractPack]> {
1087 let Inst{31-27} = 0b11111;
1088 let Inst{26-23} = 0b0100;
1089 let Inst{22-20} = opcod;
1090 let Inst{19-16} = 0b1111; // Rn
1091 let Inst{15-12} = 0b1111;
1093 let Inst{5-4} = rot;
1096 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1097 /// register and one whose operand is a register rotated by 8/16/24.
1098 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1099 : T2ThreeReg<(outs rGPR:$Rd),
1100 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1101 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1102 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1103 Requires<[HasT2ExtractPack, IsThumb2]> {
1105 let Inst{31-27} = 0b11111;
1106 let Inst{26-23} = 0b0100;
1107 let Inst{22-20} = opcod;
1108 let Inst{15-12} = 0b1111;
1110 let Inst{5-4} = rot;
1113 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1114 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1115 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1117 let Inst{31-27} = 0b11111;
1118 let Inst{26-23} = 0b0100;
1119 let Inst{22-20} = opcod;
1120 let Inst{15-12} = 0b1111;
1122 let Inst{5-4} = rot;
1125 //===----------------------------------------------------------------------===//
1127 //===----------------------------------------------------------------------===//
1129 //===----------------------------------------------------------------------===//
1130 // Miscellaneous Instructions.
1133 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1134 string asm, list<dag> pattern>
1135 : T2XI<oops, iops, itin, asm, pattern> {
1139 let Inst{11-8} = Rd;
1140 let Inst{26} = label{11};
1141 let Inst{14-12} = label{10-8};
1142 let Inst{7-0} = label{7-0};
1145 // LEApcrel - Load a pc-relative address into a register without offending the
1147 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1148 (ins t2adrlabel:$addr, pred:$p),
1149 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1150 let Inst{31-27} = 0b11110;
1151 let Inst{25-24} = 0b10;
1152 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1155 let Inst{19-16} = 0b1111; // Rn
1160 let Inst{11-8} = Rd;
1161 let Inst{23} = addr{12};
1162 let Inst{21} = addr{12};
1163 let Inst{26} = addr{11};
1164 let Inst{14-12} = addr{10-8};
1165 let Inst{7-0} = addr{7-0};
1167 let DecoderMethod = "DecodeT2Adr";
1170 let neverHasSideEffects = 1, isReMaterializable = 1 in
1171 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1173 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1174 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1179 //===----------------------------------------------------------------------===//
1180 // Load / store Instructions.
1184 let canFoldAsLoad = 1, isReMaterializable = 1 in
1185 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1186 UnOpFrag<(load node:$Src)>>;
1188 // Loads with zero extension
1189 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1190 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1191 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1192 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1194 // Loads with sign extension
1195 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1196 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1197 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1198 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1200 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1202 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1203 (ins t2addrmode_imm8s4:$addr),
1204 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1205 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1207 // zextload i1 -> zextload i8
1208 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1209 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1210 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1211 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1212 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1213 (t2LDRBs t2addrmode_so_reg:$addr)>;
1214 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1215 (t2LDRBpci tconstpool:$addr)>;
1217 // extload -> zextload
1218 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1220 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1221 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1222 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1223 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1224 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1225 (t2LDRBs t2addrmode_so_reg:$addr)>;
1226 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1227 (t2LDRBpci tconstpool:$addr)>;
1229 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1230 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1231 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1232 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1233 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1234 (t2LDRBs t2addrmode_so_reg:$addr)>;
1235 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1236 (t2LDRBpci tconstpool:$addr)>;
1238 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1239 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1240 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1241 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1242 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1243 (t2LDRHs t2addrmode_so_reg:$addr)>;
1244 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1245 (t2LDRHpci tconstpool:$addr)>;
1247 // FIXME: The destination register of the loads and stores can't be PC, but
1248 // can be SP. We need another regclass (similar to rGPR) to represent
1249 // that. Not a pressing issue since these are selected manually,
1254 let mayLoad = 1, neverHasSideEffects = 1 in {
1255 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1256 (ins t2addrmode_imm8:$addr),
1257 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1258 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1260 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1263 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1264 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1265 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1266 "ldr", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1268 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1269 (ins t2addrmode_imm8:$addr),
1270 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1271 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1273 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1275 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1276 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1277 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1278 "ldrb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1280 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1281 (ins t2addrmode_imm8:$addr),
1282 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1283 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1285 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1287 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1288 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1289 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1290 "ldrh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1292 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1293 (ins t2addrmode_imm8:$addr),
1294 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1295 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1297 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1299 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1300 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1301 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1302 "ldrsb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1304 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1305 (ins t2addrmode_imm8:$addr),
1306 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1307 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1309 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1311 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1312 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1313 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1314 "ldrsh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1315 } // mayLoad = 1, neverHasSideEffects = 1
1317 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1318 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1319 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1320 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1321 "\t$Rt, $addr", []> {
1324 let Inst{31-27} = 0b11111;
1325 let Inst{26-25} = 0b00;
1326 let Inst{24} = signed;
1328 let Inst{22-21} = type;
1329 let Inst{20} = 1; // load
1330 let Inst{19-16} = addr{12-9};
1331 let Inst{15-12} = Rt;
1333 let Inst{10-8} = 0b110; // PUW.
1334 let Inst{7-0} = addr{7-0};
1337 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1338 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1339 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1340 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1341 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1344 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1345 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1346 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1347 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1348 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1349 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1352 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1353 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1354 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1355 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1358 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1359 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1360 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1361 "str", "\t$Rt, [$Rn, $addr]!",
1362 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1363 [(set GPRnopc:$Rn_wb,
1364 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1366 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1367 (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1368 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1369 "str", "\t$Rt, $Rn, $offset",
1370 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1371 [(set GPRnopc:$Rn_wb,
1372 (post_store rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
1374 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1375 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1376 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1377 "strh", "\t$Rt, [$Rn, $addr]!",
1378 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1379 [(set GPRnopc:$Rn_wb,
1380 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1382 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1383 (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1384 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1385 "strh", "\t$Rt, $Rn, $offset",
1386 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1387 [(set GPRnopc:$Rn_wb,
1388 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
1390 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1391 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1392 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1393 "strb", "\t$Rt, [$Rn, $addr]!",
1394 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1395 [(set GPRnopc:$Rn_wb,
1396 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1398 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1399 (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1400 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1401 "strb", "\t$Rt, $Rn, $offset",
1402 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1403 [(set GPRnopc:$Rn_wb,
1404 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
1406 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1408 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1409 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1410 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1411 "\t$Rt, $addr", []> {
1412 let Inst{31-27} = 0b11111;
1413 let Inst{26-25} = 0b00;
1414 let Inst{24} = 0; // not signed
1416 let Inst{22-21} = type;
1417 let Inst{20} = 0; // store
1419 let Inst{10-8} = 0b110; // PUW
1423 let Inst{15-12} = Rt;
1424 let Inst{19-16} = addr{12-9};
1425 let Inst{7-0} = addr{7-0};
1428 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1429 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1430 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1432 // ldrd / strd pre / post variants
1433 // For disassembly only.
1435 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1436 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1437 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1438 let AsmMatchConverter = "cvtT2LdrdPre";
1439 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1442 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1443 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1444 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr, $imm",
1445 "$addr.base = $wb", []>;
1447 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1448 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1449 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1450 "$addr.base = $wb", []> {
1451 let AsmMatchConverter = "cvtT2StrdPre";
1452 let DecoderMethod = "DecodeT2STRDPreInstruction";
1455 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1456 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1457 t2am_imm8s4_offset:$imm),
1458 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr, $imm",
1459 "$addr.base = $wb", []>;
1461 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1462 // data/instruction access. These are for disassembly only.
1463 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1464 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1465 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1467 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1469 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1470 let Inst{31-25} = 0b1111100;
1471 let Inst{24} = instr;
1473 let Inst{21} = write;
1475 let Inst{15-12} = 0b1111;
1478 let addr{12} = 1; // add = TRUE
1479 let Inst{19-16} = addr{16-13}; // Rn
1480 let Inst{23} = addr{12}; // U
1481 let Inst{11-0} = addr{11-0}; // imm12
1484 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1486 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1487 let Inst{31-25} = 0b1111100;
1488 let Inst{24} = instr;
1489 let Inst{23} = 0; // U = 0
1491 let Inst{21} = write;
1493 let Inst{15-12} = 0b1111;
1494 let Inst{11-8} = 0b1100;
1497 let Inst{19-16} = addr{12-9}; // Rn
1498 let Inst{7-0} = addr{7-0}; // imm8
1501 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1503 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1504 let Inst{31-25} = 0b1111100;
1505 let Inst{24} = instr;
1506 let Inst{23} = 0; // add = TRUE for T1
1508 let Inst{21} = write;
1510 let Inst{15-12} = 0b1111;
1511 let Inst{11-6} = 0000000;
1514 let Inst{19-16} = addr{9-6}; // Rn
1515 let Inst{3-0} = addr{5-2}; // Rm
1516 let Inst{5-4} = addr{1-0}; // imm2
1518 let DecoderMethod = "DecodeT2LoadShift";
1522 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1523 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1524 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1526 //===----------------------------------------------------------------------===//
1527 // Load / store multiple Instructions.
1530 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1531 InstrItinClass itin_upd, bit L_bit> {
1533 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1534 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1538 let Inst{31-27} = 0b11101;
1539 let Inst{26-25} = 0b00;
1540 let Inst{24-23} = 0b01; // Increment After
1542 let Inst{21} = 0; // No writeback
1543 let Inst{20} = L_bit;
1544 let Inst{19-16} = Rn;
1545 let Inst{15-0} = regs;
1548 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1549 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1553 let Inst{31-27} = 0b11101;
1554 let Inst{26-25} = 0b00;
1555 let Inst{24-23} = 0b01; // Increment After
1557 let Inst{21} = 1; // Writeback
1558 let Inst{20} = L_bit;
1559 let Inst{19-16} = Rn;
1560 let Inst{15-0} = regs;
1563 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1564 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1568 let Inst{31-27} = 0b11101;
1569 let Inst{26-25} = 0b00;
1570 let Inst{24-23} = 0b10; // Decrement Before
1572 let Inst{21} = 0; // No writeback
1573 let Inst{20} = L_bit;
1574 let Inst{19-16} = Rn;
1575 let Inst{15-0} = regs;
1578 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1579 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1583 let Inst{31-27} = 0b11101;
1584 let Inst{26-25} = 0b00;
1585 let Inst{24-23} = 0b10; // Decrement Before
1587 let Inst{21} = 1; // Writeback
1588 let Inst{20} = L_bit;
1589 let Inst{19-16} = Rn;
1590 let Inst{15-0} = regs;
1594 let neverHasSideEffects = 1 in {
1596 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1597 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1599 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1600 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1602 } // neverHasSideEffects
1605 //===----------------------------------------------------------------------===//
1606 // Move Instructions.
1609 let neverHasSideEffects = 1 in
1610 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1611 "mov", ".w\t$Rd, $Rm", []> {
1612 let Inst{31-27} = 0b11101;
1613 let Inst{26-25} = 0b01;
1614 let Inst{24-21} = 0b0010;
1615 let Inst{19-16} = 0b1111; // Rn
1616 let Inst{14-12} = 0b000;
1617 let Inst{7-4} = 0b0000;
1619 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1621 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1624 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1625 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1626 AddedComplexity = 1 in
1627 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1628 "mov", ".w\t$Rd, $imm",
1629 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1630 let Inst{31-27} = 0b11110;
1632 let Inst{24-21} = 0b0010;
1633 let Inst{19-16} = 0b1111; // Rn
1637 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1638 // Use aliases to get that to play nice here.
1639 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1641 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1644 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1645 pred:$p, zero_reg)>;
1646 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1647 pred:$p, zero_reg)>;
1649 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1650 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1651 "movw", "\t$Rd, $imm",
1652 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1653 let Inst{31-27} = 0b11110;
1655 let Inst{24-21} = 0b0010;
1656 let Inst{20} = 0; // The S bit.
1662 let Inst{11-8} = Rd;
1663 let Inst{19-16} = imm{15-12};
1664 let Inst{26} = imm{11};
1665 let Inst{14-12} = imm{10-8};
1666 let Inst{7-0} = imm{7-0};
1669 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1670 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1672 let Constraints = "$src = $Rd" in {
1673 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1674 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1675 "movt", "\t$Rd, $imm",
1677 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1678 let Inst{31-27} = 0b11110;
1680 let Inst{24-21} = 0b0110;
1681 let Inst{20} = 0; // The S bit.
1687 let Inst{11-8} = Rd;
1688 let Inst{19-16} = imm{15-12};
1689 let Inst{26} = imm{11};
1690 let Inst{14-12} = imm{10-8};
1691 let Inst{7-0} = imm{7-0};
1694 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1695 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1698 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1700 //===----------------------------------------------------------------------===//
1701 // Extend Instructions.
1706 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1707 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1708 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1709 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1710 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1712 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1713 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1714 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1715 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1716 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1718 // TODO: SXT(A){B|H}16
1722 let AddedComplexity = 16 in {
1723 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1724 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1725 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1726 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1727 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1728 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1730 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1731 // The transformation should probably be done as a combiner action
1732 // instead so we can include a check for masking back in the upper
1733 // eight bits of the source into the lower eight bits of the result.
1734 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1735 // (t2UXTB16 rGPR:$Src, 3)>,
1736 // Requires<[HasT2ExtractPack, IsThumb2]>;
1737 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1738 (t2UXTB16 rGPR:$Src, 1)>,
1739 Requires<[HasT2ExtractPack, IsThumb2]>;
1741 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1742 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1743 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1744 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1745 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1748 //===----------------------------------------------------------------------===//
1749 // Arithmetic Instructions.
1752 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1753 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1754 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1755 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1757 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1758 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1759 // CPSR and the implicit def of CPSR is not needed.
1760 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1761 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1762 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1763 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1764 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1765 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1767 let hasPostISelHook = 1 in {
1768 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1769 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1770 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1771 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1775 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1776 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1778 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1779 // CPSR and the implicit def of CPSR is not needed.
1780 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1781 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1783 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1784 // The assume-no-carry-in form uses the negation of the input since add/sub
1785 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1786 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1788 // The AddedComplexity preferences the first variant over the others since
1789 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1790 let AddedComplexity = 1 in
1791 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1792 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1793 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1794 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1795 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1796 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1797 let AddedComplexity = 1 in
1798 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1799 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1800 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1801 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1802 // The with-carry-in form matches bitwise not instead of the negation.
1803 // Effectively, the inverse interpretation of the carry flag already accounts
1804 // for part of the negation.
1805 let AddedComplexity = 1 in
1806 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1807 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1808 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1809 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1811 // Select Bytes -- for disassembly only
1813 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1814 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1815 Requires<[IsThumb2, HasThumb2DSP]> {
1816 let Inst{31-27} = 0b11111;
1817 let Inst{26-24} = 0b010;
1819 let Inst{22-20} = 0b010;
1820 let Inst{15-12} = 0b1111;
1822 let Inst{6-4} = 0b000;
1825 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1826 // And Miscellaneous operations -- for disassembly only
1827 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1828 list<dag> pat = [/* For disassembly only; pattern left blank */],
1829 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1830 string asm = "\t$Rd, $Rn, $Rm">
1831 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1832 Requires<[IsThumb2, HasThumb2DSP]> {
1833 let Inst{31-27} = 0b11111;
1834 let Inst{26-23} = 0b0101;
1835 let Inst{22-20} = op22_20;
1836 let Inst{15-12} = 0b1111;
1837 let Inst{7-4} = op7_4;
1843 let Inst{11-8} = Rd;
1844 let Inst{19-16} = Rn;
1848 // Saturating add/subtract -- for disassembly only
1850 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1851 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1852 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1853 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1854 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1855 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1856 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1857 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1858 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1859 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1860 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1861 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1862 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1863 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1864 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1865 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1866 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1867 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1868 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1869 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1870 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1871 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1873 // Signed/Unsigned add/subtract -- for disassembly only
1875 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1876 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1877 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1878 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1879 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1880 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1881 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1882 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1883 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1884 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1885 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1886 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1888 // Signed/Unsigned halving add/subtract -- for disassembly only
1890 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1891 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1892 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1893 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1894 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1895 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1896 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1897 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1898 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1899 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1900 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1901 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1903 // Helper class for disassembly only
1904 // A6.3.16 & A6.3.17
1905 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1906 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1907 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1908 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1909 let Inst{31-27} = 0b11111;
1910 let Inst{26-24} = 0b011;
1911 let Inst{23} = long;
1912 let Inst{22-20} = op22_20;
1913 let Inst{7-4} = op7_4;
1916 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1917 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1918 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1919 let Inst{31-27} = 0b11111;
1920 let Inst{26-24} = 0b011;
1921 let Inst{23} = long;
1922 let Inst{22-20} = op22_20;
1923 let Inst{7-4} = op7_4;
1926 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1928 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1929 (ins rGPR:$Rn, rGPR:$Rm),
1930 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1931 Requires<[IsThumb2, HasThumb2DSP]> {
1932 let Inst{15-12} = 0b1111;
1934 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1935 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1936 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1937 Requires<[IsThumb2, HasThumb2DSP]>;
1939 // Signed/Unsigned saturate -- for disassembly only
1941 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1942 string opc, string asm, list<dag> pattern>
1943 : T2I<oops, iops, itin, opc, asm, pattern> {
1949 let Inst{11-8} = Rd;
1950 let Inst{19-16} = Rn;
1951 let Inst{4-0} = sat_imm;
1952 let Inst{21} = sh{5};
1953 let Inst{14-12} = sh{4-2};
1954 let Inst{7-6} = sh{1-0};
1958 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1959 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1960 [/* For disassembly only; pattern left blank */]> {
1961 let Inst{31-27} = 0b11110;
1962 let Inst{25-22} = 0b1100;
1967 def t2SSAT16: T2SatI<
1968 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
1969 "ssat16", "\t$Rd, $sat_imm, $Rn",
1970 [/* For disassembly only; pattern left blank */]>,
1971 Requires<[IsThumb2, HasThumb2DSP]> {
1972 let Inst{31-27} = 0b11110;
1973 let Inst{25-22} = 0b1100;
1976 let Inst{21} = 1; // sh = '1'
1977 let Inst{14-12} = 0b000; // imm3 = '000'
1978 let Inst{7-6} = 0b00; // imm2 = '00'
1982 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1983 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1984 [/* For disassembly only; pattern left blank */]> {
1985 let Inst{31-27} = 0b11110;
1986 let Inst{25-22} = 0b1110;
1991 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn),
1993 "usat16", "\t$Rd, $sat_imm, $Rn",
1994 [/* For disassembly only; pattern left blank */]>,
1995 Requires<[IsThumb2, HasThumb2DSP]> {
1996 let Inst{31-27} = 0b11110;
1997 let Inst{25-22} = 0b1110;
2000 let Inst{21} = 1; // sh = '1'
2001 let Inst{14-12} = 0b000; // imm3 = '000'
2002 let Inst{7-6} = 0b00; // imm2 = '00'
2005 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2006 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2008 //===----------------------------------------------------------------------===//
2009 // Shift and rotate Instructions.
2012 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2013 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2014 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2015 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2016 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2017 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2018 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2019 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2021 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2022 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2023 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2025 let Uses = [CPSR] in {
2026 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2027 "rrx", "\t$Rd, $Rm",
2028 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2029 let Inst{31-27} = 0b11101;
2030 let Inst{26-25} = 0b01;
2031 let Inst{24-21} = 0b0010;
2032 let Inst{19-16} = 0b1111; // Rn
2033 let Inst{14-12} = 0b000;
2034 let Inst{7-4} = 0b0011;
2038 let isCodeGenOnly = 1, Defs = [CPSR] in {
2039 def t2MOVsrl_flag : T2TwoRegShiftImm<
2040 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2041 "lsrs", ".w\t$Rd, $Rm, #1",
2042 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2043 let Inst{31-27} = 0b11101;
2044 let Inst{26-25} = 0b01;
2045 let Inst{24-21} = 0b0010;
2046 let Inst{20} = 1; // The S bit.
2047 let Inst{19-16} = 0b1111; // Rn
2048 let Inst{5-4} = 0b01; // Shift type.
2049 // Shift amount = Inst{14-12:7-6} = 1.
2050 let Inst{14-12} = 0b000;
2051 let Inst{7-6} = 0b01;
2053 def t2MOVsra_flag : T2TwoRegShiftImm<
2054 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2055 "asrs", ".w\t$Rd, $Rm, #1",
2056 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2057 let Inst{31-27} = 0b11101;
2058 let Inst{26-25} = 0b01;
2059 let Inst{24-21} = 0b0010;
2060 let Inst{20} = 1; // The S bit.
2061 let Inst{19-16} = 0b1111; // Rn
2062 let Inst{5-4} = 0b10; // Shift type.
2063 // Shift amount = Inst{14-12:7-6} = 1.
2064 let Inst{14-12} = 0b000;
2065 let Inst{7-6} = 0b01;
2069 //===----------------------------------------------------------------------===//
2070 // Bitwise Instructions.
2073 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2074 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2075 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2076 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2077 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2078 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2079 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2080 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2081 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2083 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2084 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2085 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2088 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2089 string opc, string asm, list<dag> pattern>
2090 : T2I<oops, iops, itin, opc, asm, pattern> {
2095 let Inst{11-8} = Rd;
2096 let Inst{4-0} = msb{4-0};
2097 let Inst{14-12} = lsb{4-2};
2098 let Inst{7-6} = lsb{1-0};
2101 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2102 string opc, string asm, list<dag> pattern>
2103 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2106 let Inst{19-16} = Rn;
2109 let Constraints = "$src = $Rd" in
2110 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2111 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2112 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2113 let Inst{31-27} = 0b11110;
2114 let Inst{26} = 0; // should be 0.
2116 let Inst{24-20} = 0b10110;
2117 let Inst{19-16} = 0b1111; // Rn
2119 let Inst{5} = 0; // should be 0.
2122 let msb{4-0} = imm{9-5};
2123 let lsb{4-0} = imm{4-0};
2126 def t2SBFX: T2TwoRegBitFI<
2127 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2128 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2129 let Inst{31-27} = 0b11110;
2131 let Inst{24-20} = 0b10100;
2135 def t2UBFX: T2TwoRegBitFI<
2136 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2137 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2138 let Inst{31-27} = 0b11110;
2140 let Inst{24-20} = 0b11100;
2144 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2145 let Constraints = "$src = $Rd" in {
2146 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2147 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2148 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2149 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2150 bf_inv_mask_imm:$imm))]> {
2151 let Inst{31-27} = 0b11110;
2152 let Inst{26} = 0; // should be 0.
2154 let Inst{24-20} = 0b10110;
2156 let Inst{5} = 0; // should be 0.
2159 let msb{4-0} = imm{9-5};
2160 let lsb{4-0} = imm{4-0};
2163 // GNU as only supports this form of bfi (w/ 4 arguments)
2164 let isAsmParserOnly = 1 in
2165 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2166 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2168 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2170 let Inst{31-27} = 0b11110;
2171 let Inst{26} = 0; // should be 0.
2173 let Inst{24-20} = 0b10110;
2175 let Inst{5} = 0; // should be 0.
2179 let msb{4-0} = width; // Custom encoder => lsb+width-1
2180 let lsb{4-0} = lsbit;
2184 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2185 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2186 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2189 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2190 let AddedComplexity = 1 in
2191 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2192 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2193 UnOpFrag<(not node:$Src)>, 1, 1>;
2196 let AddedComplexity = 1 in
2197 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2198 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2200 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2201 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2202 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2203 Requires<[IsThumb2]>;
2205 def : T2Pat<(t2_so_imm_not:$src),
2206 (t2MVNi t2_so_imm_not:$src)>;
2208 //===----------------------------------------------------------------------===//
2209 // Multiply Instructions.
2211 let isCommutable = 1 in
2212 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2213 "mul", "\t$Rd, $Rn, $Rm",
2214 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2215 let Inst{31-27} = 0b11111;
2216 let Inst{26-23} = 0b0110;
2217 let Inst{22-20} = 0b000;
2218 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2219 let Inst{7-4} = 0b0000; // Multiply
2222 def t2MLA: T2FourReg<
2223 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2224 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2225 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2226 let Inst{31-27} = 0b11111;
2227 let Inst{26-23} = 0b0110;
2228 let Inst{22-20} = 0b000;
2229 let Inst{7-4} = 0b0000; // Multiply
2232 def t2MLS: T2FourReg<
2233 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2234 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2235 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2236 let Inst{31-27} = 0b11111;
2237 let Inst{26-23} = 0b0110;
2238 let Inst{22-20} = 0b000;
2239 let Inst{7-4} = 0b0001; // Multiply and Subtract
2242 // Extra precision multiplies with low / high results
2243 let neverHasSideEffects = 1 in {
2244 let isCommutable = 1 in {
2245 def t2SMULL : T2MulLong<0b000, 0b0000,
2246 (outs rGPR:$RdLo, rGPR:$RdHi),
2247 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2248 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2250 def t2UMULL : T2MulLong<0b010, 0b0000,
2251 (outs rGPR:$RdLo, rGPR:$RdHi),
2252 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2253 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2256 // Multiply + accumulate
2257 def t2SMLAL : T2MulLong<0b100, 0b0000,
2258 (outs rGPR:$RdLo, rGPR:$RdHi),
2259 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2260 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2262 def t2UMLAL : T2MulLong<0b110, 0b0000,
2263 (outs rGPR:$RdLo, rGPR:$RdHi),
2264 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2265 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2267 def t2UMAAL : T2MulLong<0b110, 0b0110,
2268 (outs rGPR:$RdLo, rGPR:$RdHi),
2269 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2270 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2271 Requires<[IsThumb2, HasThumb2DSP]>;
2272 } // neverHasSideEffects
2274 // Rounding variants of the below included for disassembly only
2276 // Most significant word multiply
2277 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2278 "smmul", "\t$Rd, $Rn, $Rm",
2279 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2280 Requires<[IsThumb2, HasThumb2DSP]> {
2281 let Inst{31-27} = 0b11111;
2282 let Inst{26-23} = 0b0110;
2283 let Inst{22-20} = 0b101;
2284 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2285 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2288 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2289 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2290 Requires<[IsThumb2, HasThumb2DSP]> {
2291 let Inst{31-27} = 0b11111;
2292 let Inst{26-23} = 0b0110;
2293 let Inst{22-20} = 0b101;
2294 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2295 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2298 def t2SMMLA : T2FourReg<
2299 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2300 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2301 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2302 Requires<[IsThumb2, HasThumb2DSP]> {
2303 let Inst{31-27} = 0b11111;
2304 let Inst{26-23} = 0b0110;
2305 let Inst{22-20} = 0b101;
2306 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2309 def t2SMMLAR: T2FourReg<
2310 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2311 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2312 Requires<[IsThumb2, HasThumb2DSP]> {
2313 let Inst{31-27} = 0b11111;
2314 let Inst{26-23} = 0b0110;
2315 let Inst{22-20} = 0b101;
2316 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2319 def t2SMMLS: T2FourReg<
2320 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2321 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2322 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2323 Requires<[IsThumb2, HasThumb2DSP]> {
2324 let Inst{31-27} = 0b11111;
2325 let Inst{26-23} = 0b0110;
2326 let Inst{22-20} = 0b110;
2327 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2330 def t2SMMLSR:T2FourReg<
2331 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2332 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2333 Requires<[IsThumb2, HasThumb2DSP]> {
2334 let Inst{31-27} = 0b11111;
2335 let Inst{26-23} = 0b0110;
2336 let Inst{22-20} = 0b110;
2337 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2340 multiclass T2I_smul<string opc, PatFrag opnode> {
2341 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2342 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2343 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2344 (sext_inreg rGPR:$Rm, i16)))]>,
2345 Requires<[IsThumb2, HasThumb2DSP]> {
2346 let Inst{31-27} = 0b11111;
2347 let Inst{26-23} = 0b0110;
2348 let Inst{22-20} = 0b001;
2349 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2350 let Inst{7-6} = 0b00;
2351 let Inst{5-4} = 0b00;
2354 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2355 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2356 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2357 (sra rGPR:$Rm, (i32 16))))]>,
2358 Requires<[IsThumb2, HasThumb2DSP]> {
2359 let Inst{31-27} = 0b11111;
2360 let Inst{26-23} = 0b0110;
2361 let Inst{22-20} = 0b001;
2362 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2363 let Inst{7-6} = 0b00;
2364 let Inst{5-4} = 0b01;
2367 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2368 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2369 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2370 (sext_inreg rGPR:$Rm, i16)))]>,
2371 Requires<[IsThumb2, HasThumb2DSP]> {
2372 let Inst{31-27} = 0b11111;
2373 let Inst{26-23} = 0b0110;
2374 let Inst{22-20} = 0b001;
2375 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2376 let Inst{7-6} = 0b00;
2377 let Inst{5-4} = 0b10;
2380 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2381 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2382 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2383 (sra rGPR:$Rm, (i32 16))))]>,
2384 Requires<[IsThumb2, HasThumb2DSP]> {
2385 let Inst{31-27} = 0b11111;
2386 let Inst{26-23} = 0b0110;
2387 let Inst{22-20} = 0b001;
2388 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2389 let Inst{7-6} = 0b00;
2390 let Inst{5-4} = 0b11;
2393 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2394 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2395 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2396 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2397 Requires<[IsThumb2, HasThumb2DSP]> {
2398 let Inst{31-27} = 0b11111;
2399 let Inst{26-23} = 0b0110;
2400 let Inst{22-20} = 0b011;
2401 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2402 let Inst{7-6} = 0b00;
2403 let Inst{5-4} = 0b00;
2406 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2407 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2408 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2409 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2410 Requires<[IsThumb2, HasThumb2DSP]> {
2411 let Inst{31-27} = 0b11111;
2412 let Inst{26-23} = 0b0110;
2413 let Inst{22-20} = 0b011;
2414 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2415 let Inst{7-6} = 0b00;
2416 let Inst{5-4} = 0b01;
2421 multiclass T2I_smla<string opc, PatFrag opnode> {
2423 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2424 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2425 [(set rGPR:$Rd, (add rGPR:$Ra,
2426 (opnode (sext_inreg rGPR:$Rn, i16),
2427 (sext_inreg rGPR:$Rm, i16))))]>,
2428 Requires<[IsThumb2, HasThumb2DSP]> {
2429 let Inst{31-27} = 0b11111;
2430 let Inst{26-23} = 0b0110;
2431 let Inst{22-20} = 0b001;
2432 let Inst{7-6} = 0b00;
2433 let Inst{5-4} = 0b00;
2437 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2438 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2439 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2440 (sra rGPR:$Rm, (i32 16)))))]>,
2441 Requires<[IsThumb2, HasThumb2DSP]> {
2442 let Inst{31-27} = 0b11111;
2443 let Inst{26-23} = 0b0110;
2444 let Inst{22-20} = 0b001;
2445 let Inst{7-6} = 0b00;
2446 let Inst{5-4} = 0b01;
2450 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2451 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2452 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2453 (sext_inreg rGPR:$Rm, i16))))]>,
2454 Requires<[IsThumb2, HasThumb2DSP]> {
2455 let Inst{31-27} = 0b11111;
2456 let Inst{26-23} = 0b0110;
2457 let Inst{22-20} = 0b001;
2458 let Inst{7-6} = 0b00;
2459 let Inst{5-4} = 0b10;
2463 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2464 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2465 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2466 (sra rGPR:$Rm, (i32 16)))))]>,
2467 Requires<[IsThumb2, HasThumb2DSP]> {
2468 let Inst{31-27} = 0b11111;
2469 let Inst{26-23} = 0b0110;
2470 let Inst{22-20} = 0b001;
2471 let Inst{7-6} = 0b00;
2472 let Inst{5-4} = 0b11;
2476 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2477 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2478 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2479 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2480 Requires<[IsThumb2, HasThumb2DSP]> {
2481 let Inst{31-27} = 0b11111;
2482 let Inst{26-23} = 0b0110;
2483 let Inst{22-20} = 0b011;
2484 let Inst{7-6} = 0b00;
2485 let Inst{5-4} = 0b00;
2489 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2490 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2491 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2492 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2493 Requires<[IsThumb2, HasThumb2DSP]> {
2494 let Inst{31-27} = 0b11111;
2495 let Inst{26-23} = 0b0110;
2496 let Inst{22-20} = 0b011;
2497 let Inst{7-6} = 0b00;
2498 let Inst{5-4} = 0b01;
2502 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2503 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2505 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2506 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2507 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2508 [/* For disassembly only; pattern left blank */]>,
2509 Requires<[IsThumb2, HasThumb2DSP]>;
2510 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2511 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2512 [/* For disassembly only; pattern left blank */]>,
2513 Requires<[IsThumb2, HasThumb2DSP]>;
2514 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2515 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2516 [/* For disassembly only; pattern left blank */]>,
2517 Requires<[IsThumb2, HasThumb2DSP]>;
2518 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2519 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2520 [/* For disassembly only; pattern left blank */]>,
2521 Requires<[IsThumb2, HasThumb2DSP]>;
2523 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2524 // These are for disassembly only.
2526 def t2SMUAD: T2ThreeReg_mac<
2527 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2528 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2529 Requires<[IsThumb2, HasThumb2DSP]> {
2530 let Inst{15-12} = 0b1111;
2532 def t2SMUADX:T2ThreeReg_mac<
2533 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2534 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2535 Requires<[IsThumb2, HasThumb2DSP]> {
2536 let Inst{15-12} = 0b1111;
2538 def t2SMUSD: T2ThreeReg_mac<
2539 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2540 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2541 Requires<[IsThumb2, HasThumb2DSP]> {
2542 let Inst{15-12} = 0b1111;
2544 def t2SMUSDX:T2ThreeReg_mac<
2545 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2546 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2547 Requires<[IsThumb2, HasThumb2DSP]> {
2548 let Inst{15-12} = 0b1111;
2550 def t2SMLAD : T2FourReg_mac<
2551 0, 0b010, 0b0000, (outs rGPR:$Rd),
2552 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2553 "\t$Rd, $Rn, $Rm, $Ra", []>,
2554 Requires<[IsThumb2, HasThumb2DSP]>;
2555 def t2SMLADX : T2FourReg_mac<
2556 0, 0b010, 0b0001, (outs rGPR:$Rd),
2557 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2558 "\t$Rd, $Rn, $Rm, $Ra", []>,
2559 Requires<[IsThumb2, HasThumb2DSP]>;
2560 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2561 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2562 "\t$Rd, $Rn, $Rm, $Ra", []>,
2563 Requires<[IsThumb2, HasThumb2DSP]>;
2564 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2565 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2566 "\t$Rd, $Rn, $Rm, $Ra", []>,
2567 Requires<[IsThumb2, HasThumb2DSP]>;
2568 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2569 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2570 "\t$Ra, $Rd, $Rm, $Rn", []>,
2571 Requires<[IsThumb2, HasThumb2DSP]>;
2572 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2573 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2574 "\t$Ra, $Rd, $Rm, $Rn", []>,
2575 Requires<[IsThumb2, HasThumb2DSP]>;
2576 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2577 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2578 "\t$Ra, $Rd, $Rm, $Rn", []>,
2579 Requires<[IsThumb2, HasThumb2DSP]>;
2580 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2581 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2582 "\t$Ra, $Rd, $Rm, $Rn", []>,
2583 Requires<[IsThumb2, HasThumb2DSP]>;
2585 //===----------------------------------------------------------------------===//
2586 // Division Instructions.
2587 // Signed and unsigned division on v7-M
2589 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2590 "sdiv", "\t$Rd, $Rn, $Rm",
2591 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2592 Requires<[HasDivide, IsThumb2]> {
2593 let Inst{31-27} = 0b11111;
2594 let Inst{26-21} = 0b011100;
2596 let Inst{15-12} = 0b1111;
2597 let Inst{7-4} = 0b1111;
2600 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2601 "udiv", "\t$Rd, $Rn, $Rm",
2602 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2603 Requires<[HasDivide, IsThumb2]> {
2604 let Inst{31-27} = 0b11111;
2605 let Inst{26-21} = 0b011101;
2607 let Inst{15-12} = 0b1111;
2608 let Inst{7-4} = 0b1111;
2611 //===----------------------------------------------------------------------===//
2612 // Misc. Arithmetic Instructions.
2615 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2616 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2617 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2618 let Inst{31-27} = 0b11111;
2619 let Inst{26-22} = 0b01010;
2620 let Inst{21-20} = op1;
2621 let Inst{15-12} = 0b1111;
2622 let Inst{7-6} = 0b10;
2623 let Inst{5-4} = op2;
2627 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2628 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2630 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2631 "rbit", "\t$Rd, $Rm",
2632 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2634 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2635 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2637 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2638 "rev16", ".w\t$Rd, $Rm",
2639 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2641 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2642 "revsh", ".w\t$Rd, $Rm",
2643 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2645 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2646 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2647 (t2REVSH rGPR:$Rm)>;
2649 def t2PKHBT : T2ThreeReg<
2650 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2651 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
2652 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2653 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2655 Requires<[HasT2ExtractPack, IsThumb2]> {
2656 let Inst{31-27} = 0b11101;
2657 let Inst{26-25} = 0b01;
2658 let Inst{24-20} = 0b01100;
2659 let Inst{5} = 0; // BT form
2663 let Inst{14-12} = sh{4-2};
2664 let Inst{7-6} = sh{1-0};
2667 // Alternate cases for PKHBT where identities eliminate some nodes.
2668 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2669 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2670 Requires<[HasT2ExtractPack, IsThumb2]>;
2671 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2672 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2673 Requires<[HasT2ExtractPack, IsThumb2]>;
2675 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2676 // will match the pattern below.
2677 def t2PKHTB : T2ThreeReg<
2678 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2679 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
2680 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2681 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2683 Requires<[HasT2ExtractPack, IsThumb2]> {
2684 let Inst{31-27} = 0b11101;
2685 let Inst{26-25} = 0b01;
2686 let Inst{24-20} = 0b01100;
2687 let Inst{5} = 1; // TB form
2691 let Inst{14-12} = sh{4-2};
2692 let Inst{7-6} = sh{1-0};
2695 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2696 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2697 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2698 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2699 Requires<[HasT2ExtractPack, IsThumb2]>;
2700 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2701 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2702 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2703 Requires<[HasT2ExtractPack, IsThumb2]>;
2705 //===----------------------------------------------------------------------===//
2706 // Comparison Instructions...
2708 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2709 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2710 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2712 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2713 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2714 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2715 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2716 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2717 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2719 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2720 // Compare-to-zero still works out, just not the relationals
2721 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2722 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2723 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2724 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2725 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2728 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2729 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2731 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2732 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2734 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2735 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2736 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2738 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2739 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2740 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2743 // Conditional moves
2744 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2745 // a two-value operand where a dag node expects two operands. :(
2746 let neverHasSideEffects = 1 in {
2747 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2748 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2750 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2751 RegConstraint<"$false = $Rd">;
2753 let isMoveImm = 1 in
2754 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2755 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2757 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2758 RegConstraint<"$false = $Rd">;
2760 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2761 let isCodeGenOnly = 1 in {
2762 let isMoveImm = 1 in
2763 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2765 "movw", "\t$Rd, $imm", []>,
2766 RegConstraint<"$false = $Rd"> {
2767 let Inst{31-27} = 0b11110;
2769 let Inst{24-21} = 0b0010;
2770 let Inst{20} = 0; // The S bit.
2776 let Inst{11-8} = Rd;
2777 let Inst{19-16} = imm{15-12};
2778 let Inst{26} = imm{11};
2779 let Inst{14-12} = imm{10-8};
2780 let Inst{7-0} = imm{7-0};
2783 let isMoveImm = 1 in
2784 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2785 (ins rGPR:$false, i32imm:$src, pred:$p),
2786 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2788 let isMoveImm = 1 in
2789 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2790 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2791 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2792 imm:$cc, CCR:$ccr))*/]>,
2793 RegConstraint<"$false = $Rd"> {
2794 let Inst{31-27} = 0b11110;
2796 let Inst{24-21} = 0b0011;
2797 let Inst{20} = 0; // The S bit.
2798 let Inst{19-16} = 0b1111; // Rn
2802 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2803 string opc, string asm, list<dag> pattern>
2804 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2805 let Inst{31-27} = 0b11101;
2806 let Inst{26-25} = 0b01;
2807 let Inst{24-21} = 0b0010;
2808 let Inst{20} = 0; // The S bit.
2809 let Inst{19-16} = 0b1111; // Rn
2810 let Inst{5-4} = opcod; // Shift type.
2812 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2813 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2814 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2815 RegConstraint<"$false = $Rd">;
2816 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2817 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2818 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2819 RegConstraint<"$false = $Rd">;
2820 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2821 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2822 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2823 RegConstraint<"$false = $Rd">;
2824 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2825 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2826 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2827 RegConstraint<"$false = $Rd">;
2828 } // isCodeGenOnly = 1
2829 } // neverHasSideEffects
2831 //===----------------------------------------------------------------------===//
2832 // Atomic operations intrinsics
2835 // memory barriers protect the atomic sequences
2836 let hasSideEffects = 1 in {
2837 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2838 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2839 Requires<[IsThumb, HasDB]> {
2841 let Inst{31-4} = 0xf3bf8f5;
2842 let Inst{3-0} = opt;
2846 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2847 "dsb", "\t$opt", []>,
2848 Requires<[IsThumb, HasDB]> {
2850 let Inst{31-4} = 0xf3bf8f4;
2851 let Inst{3-0} = opt;
2854 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2856 []>, Requires<[IsThumb2, HasDB]> {
2858 let Inst{31-4} = 0xf3bf8f6;
2859 let Inst{3-0} = opt;
2862 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2863 InstrItinClass itin, string opc, string asm, string cstr,
2864 list<dag> pattern, bits<4> rt2 = 0b1111>
2865 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2866 let Inst{31-27} = 0b11101;
2867 let Inst{26-20} = 0b0001101;
2868 let Inst{11-8} = rt2;
2869 let Inst{7-6} = 0b01;
2870 let Inst{5-4} = opcod;
2871 let Inst{3-0} = 0b1111;
2875 let Inst{19-16} = addr;
2876 let Inst{15-12} = Rt;
2878 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2879 InstrItinClass itin, string opc, string asm, string cstr,
2880 list<dag> pattern, bits<4> rt2 = 0b1111>
2881 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2882 let Inst{31-27} = 0b11101;
2883 let Inst{26-20} = 0b0001100;
2884 let Inst{11-8} = rt2;
2885 let Inst{7-6} = 0b01;
2886 let Inst{5-4} = opcod;
2892 let Inst{19-16} = addr;
2893 let Inst{15-12} = Rt;
2896 let mayLoad = 1 in {
2897 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2898 AddrModeNone, 4, NoItinerary,
2899 "ldrexb", "\t$Rt, $addr", "", []>;
2900 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2901 AddrModeNone, 4, NoItinerary,
2902 "ldrexh", "\t$Rt, $addr", "", []>;
2903 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
2904 AddrModeNone, 4, NoItinerary,
2905 "ldrex", "\t$Rt, $addr", "", []> {
2908 let Inst{31-27} = 0b11101;
2909 let Inst{26-20} = 0b0000101;
2910 let Inst{19-16} = addr{11-8};
2911 let Inst{15-12} = Rt;
2912 let Inst{11-8} = 0b1111;
2913 let Inst{7-0} = addr{7-0};
2915 let hasExtraDefRegAllocReq = 1 in
2916 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2917 (ins addr_offset_none:$addr),
2918 AddrModeNone, 4, NoItinerary,
2919 "ldrexd", "\t$Rt, $Rt2, $addr", "",
2922 let Inst{11-8} = Rt2;
2926 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2927 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2928 (ins rGPR:$Rt, addr_offset_none:$addr),
2929 AddrModeNone, 4, NoItinerary,
2930 "strexb", "\t$Rd, $Rt, $addr", "", []>;
2931 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2932 (ins rGPR:$Rt, addr_offset_none:$addr),
2933 AddrModeNone, 4, NoItinerary,
2934 "strexh", "\t$Rd, $Rt, $addr", "", []>;
2935 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
2936 t2addrmode_imm0_1020s4:$addr),
2937 AddrModeNone, 4, NoItinerary,
2938 "strex", "\t$Rd, $Rt, $addr", "",
2943 let Inst{31-27} = 0b11101;
2944 let Inst{26-20} = 0b0000100;
2945 let Inst{19-16} = addr{11-8};
2946 let Inst{15-12} = Rt;
2947 let Inst{11-8} = Rd;
2948 let Inst{7-0} = addr{7-0};
2952 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2953 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2954 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
2955 AddrModeNone, 4, NoItinerary,
2956 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2959 let Inst{11-8} = Rt2;
2962 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
2963 Requires<[IsThumb2, HasV7]> {
2964 let Inst{31-16} = 0xf3bf;
2965 let Inst{15-14} = 0b10;
2968 let Inst{11-8} = 0b1111;
2969 let Inst{7-4} = 0b0010;
2970 let Inst{3-0} = 0b1111;
2973 //===----------------------------------------------------------------------===//
2974 // SJLJ Exception handling intrinsics
2975 // eh_sjlj_setjmp() is an instruction sequence to store the return
2976 // address and save #0 in R0 for the non-longjmp case.
2977 // Since by its nature we may be coming from some other function to get
2978 // here, and we're using the stack frame for the containing function to
2979 // save/restore registers, we can't keep anything live in regs across
2980 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2981 // when we get here from a longjmp(). We force everything out of registers
2982 // except for our own input by listing the relevant registers in Defs. By
2983 // doing so, we also cause the prologue/epilogue code to actively preserve
2984 // all of the callee-saved resgisters, which is exactly what we want.
2985 // $val is a scratch register for our use.
2987 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
2988 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2989 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2990 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2991 AddrModeNone, 0, NoItinerary, "", "",
2992 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2993 Requires<[IsThumb2, HasVFP2]>;
2997 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
2998 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2999 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3000 AddrModeNone, 0, NoItinerary, "", "",
3001 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3002 Requires<[IsThumb2, NoVFP]>;
3006 //===----------------------------------------------------------------------===//
3007 // Control-Flow Instructions
3010 // FIXME: remove when we have a way to marking a MI with these properties.
3011 // FIXME: Should pc be an implicit operand like PICADD, etc?
3012 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3013 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3014 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3015 reglist:$regs, variable_ops),
3016 4, IIC_iLoad_mBr, [],
3017 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3018 RegConstraint<"$Rn = $wb">;
3020 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3021 let isPredicable = 1 in
3022 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3024 [(br bb:$target)]> {
3025 let Inst{31-27} = 0b11110;
3026 let Inst{15-14} = 0b10;
3030 let Inst{26} = target{19};
3031 let Inst{11} = target{18};
3032 let Inst{13} = target{17};
3033 let Inst{21-16} = target{16-11};
3034 let Inst{10-0} = target{10-0};
3037 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3038 def t2BR_JT : t2PseudoInst<(outs),
3039 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3041 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3043 // FIXME: Add a non-pc based case that can be predicated.
3044 def t2TBB_JT : t2PseudoInst<(outs),
3045 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3048 def t2TBH_JT : t2PseudoInst<(outs),
3049 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3052 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3053 "tbb", "\t[$Rn, $Rm]", []> {
3056 let Inst{31-20} = 0b111010001101;
3057 let Inst{19-16} = Rn;
3058 let Inst{15-5} = 0b11110000000;
3059 let Inst{4} = 0; // B form
3063 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3064 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3067 let Inst{31-20} = 0b111010001101;
3068 let Inst{19-16} = Rn;
3069 let Inst{15-5} = 0b11110000000;
3070 let Inst{4} = 1; // H form
3073 } // isNotDuplicable, isIndirectBranch
3075 } // isBranch, isTerminator, isBarrier
3077 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3078 // a two-value operand where a dag node expects ", "two operands. :(
3079 let isBranch = 1, isTerminator = 1 in
3080 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3082 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3083 let Inst{31-27} = 0b11110;
3084 let Inst{15-14} = 0b10;
3088 let Inst{25-22} = p;
3091 let Inst{26} = target{20};
3092 let Inst{11} = target{19};
3093 let Inst{13} = target{18};
3094 let Inst{21-16} = target{17-12};
3095 let Inst{10-0} = target{11-1};
3097 let DecoderMethod = "DecodeThumb2BCCInstruction";
3100 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3102 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3104 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3106 def tTAILJMPd: tPseudoExpand<(outs),
3107 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3109 (t2B uncondbrtarget:$dst, pred:$p)>,
3110 Requires<[IsThumb2, IsDarwin]>;
3114 let Defs = [ITSTATE] in
3115 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3116 AddrModeNone, 2, IIC_iALUx,
3117 "it$mask\t$cc", "", []> {
3118 // 16-bit instruction.
3119 let Inst{31-16} = 0x0000;
3120 let Inst{15-8} = 0b10111111;
3125 let Inst{3-0} = mask;
3127 let DecoderMethod = "DecodeIT";
3130 // Branch and Exchange Jazelle -- for disassembly only
3132 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3134 let Inst{31-27} = 0b11110;
3136 let Inst{25-20} = 0b111100;
3137 let Inst{19-16} = func;
3138 let Inst{15-0} = 0b1000111100000000;
3141 // Compare and branch on zero / non-zero
3142 let isBranch = 1, isTerminator = 1 in {
3143 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3144 "cbz\t$Rn, $target", []>,
3145 T1Misc<{0,0,?,1,?,?,?}>,
3146 Requires<[IsThumb2]> {
3150 let Inst{9} = target{5};
3151 let Inst{7-3} = target{4-0};
3155 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3156 "cbnz\t$Rn, $target", []>,
3157 T1Misc<{1,0,?,1,?,?,?}>,
3158 Requires<[IsThumb2]> {
3162 let Inst{9} = target{5};
3163 let Inst{7-3} = target{4-0};
3169 // Change Processor State is a system instruction -- for disassembly and
3171 // FIXME: Since the asm parser has currently no clean way to handle optional
3172 // operands, create 3 versions of the same instruction. Once there's a clean
3173 // framework to represent optional operands, change this behavior.
3174 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3175 !strconcat("cps", asm_op),
3176 [/* For disassembly only; pattern left blank */]> {
3182 let Inst{31-27} = 0b11110;
3184 let Inst{25-20} = 0b111010;
3185 let Inst{19-16} = 0b1111;
3186 let Inst{15-14} = 0b10;
3188 let Inst{10-9} = imod;
3190 let Inst{7-5} = iflags;
3191 let Inst{4-0} = mode;
3192 let DecoderMethod = "DecodeT2CPSInstruction";
3196 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3197 "$imod.w\t$iflags, $mode">;
3198 let mode = 0, M = 0 in
3199 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3200 "$imod.w\t$iflags">;
3201 let imod = 0, iflags = 0, M = 1 in
3202 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3204 // A6.3.4 Branches and miscellaneous control
3205 // Table A6-14 Change Processor State, and hint instructions
3206 // Helper class for disassembly only.
3207 class T2I_hint<bits<8> op7_0, string opc, string asm>
3208 : T2I<(outs), (ins), NoItinerary, opc, asm,
3209 [/* For disassembly only; pattern left blank */]> {
3210 let Inst{31-20} = 0xf3a;
3211 let Inst{19-16} = 0b1111;
3212 let Inst{15-14} = 0b10;
3214 let Inst{10-8} = 0b000;
3215 let Inst{7-0} = op7_0;
3218 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3219 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3220 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3221 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3222 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3224 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3226 let Inst{31-20} = 0b111100111010;
3227 let Inst{19-16} = 0b1111;
3228 let Inst{15-8} = 0b10000000;
3229 let Inst{7-4} = 0b1111;
3230 let Inst{3-0} = opt;
3233 // Secure Monitor Call is a system instruction -- for disassembly only
3234 // Option = Inst{19-16}
3235 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3236 [/* For disassembly only; pattern left blank */]> {
3237 let Inst{31-27} = 0b11110;
3238 let Inst{26-20} = 0b1111111;
3239 let Inst{15-12} = 0b1000;
3242 let Inst{19-16} = opt;
3245 class T2SRS<bits<12> op31_20,
3246 dag oops, dag iops, InstrItinClass itin,
3247 string opc, string asm, list<dag> pattern>
3248 : T2I<oops, iops, itin, opc, asm, pattern> {
3249 let Inst{31-20} = op31_20{11-0};
3252 let Inst{4-0} = mode{4-0};
3255 // Store Return State is a system instruction -- for disassembly only
3256 def t2SRSDBW : T2SRS<0b111010000010,
3257 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3258 [/* For disassembly only; pattern left blank */]>;
3259 def t2SRSDB : T2SRS<0b111010000000,
3260 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3261 [/* For disassembly only; pattern left blank */]>;
3262 def t2SRSIAW : T2SRS<0b111010011010,
3263 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3264 [/* For disassembly only; pattern left blank */]>;
3265 def t2SRSIA : T2SRS<0b111010011000,
3266 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3267 [/* For disassembly only; pattern left blank */]>;
3269 // Return From Exception is a system instruction -- for disassembly only
3271 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3272 string opc, string asm, list<dag> pattern>
3273 : T2I<oops, iops, itin, opc, asm, pattern> {
3274 let Inst{31-20} = op31_20{11-0};
3277 let Inst{19-16} = Rn;
3278 let Inst{15-0} = 0xc000;
3281 def t2RFEDBW : T2RFE<0b111010000011,
3282 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3283 [/* For disassembly only; pattern left blank */]>;
3284 def t2RFEDB : T2RFE<0b111010000001,
3285 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3286 [/* For disassembly only; pattern left blank */]>;
3287 def t2RFEIAW : T2RFE<0b111010011011,
3288 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3289 [/* For disassembly only; pattern left blank */]>;
3290 def t2RFEIA : T2RFE<0b111010011001,
3291 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3292 [/* For disassembly only; pattern left blank */]>;
3294 //===----------------------------------------------------------------------===//
3295 // Non-Instruction Patterns
3298 // 32-bit immediate using movw + movt.
3299 // This is a single pseudo instruction to make it re-materializable.
3300 // FIXME: Remove this when we can do generalized remat.
3301 let isReMaterializable = 1, isMoveImm = 1 in
3302 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3303 [(set rGPR:$dst, (i32 imm:$src))]>,
3304 Requires<[IsThumb, HasV6T2]>;
3306 // Pseudo instruction that combines movw + movt + add pc (if pic).
3307 // It also makes it possible to rematerialize the instructions.
3308 // FIXME: Remove this when we can do generalized remat and when machine licm
3309 // can properly the instructions.
3310 let isReMaterializable = 1 in {
3311 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3313 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3314 Requires<[IsThumb2, UseMovt]>;
3316 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3318 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3319 Requires<[IsThumb2, UseMovt]>;
3322 // ConstantPool, GlobalAddress, and JumpTable
3323 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3324 Requires<[IsThumb2, DontUseMovt]>;
3325 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3326 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3327 Requires<[IsThumb2, UseMovt]>;
3329 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3330 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3332 // Pseudo instruction that combines ldr from constpool and add pc. This should
3333 // be expanded into two instructions late to allow if-conversion and
3335 let canFoldAsLoad = 1, isReMaterializable = 1 in
3336 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3338 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3340 Requires<[IsThumb2]>;
3341 //===----------------------------------------------------------------------===//
3342 // Coprocessor load/store -- for disassembly only
3344 class T2CI<dag oops, dag iops, string opc, string asm>
3345 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3346 let Inst{27-25} = 0b110;
3349 multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
3350 def _OFFSET : T2CI<(outs),
3351 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3352 opc, "\tp$cop, cr$CRd, $addr"> {
3353 let Inst{31-28} = op31_28;
3354 let Inst{24} = 1; // P = 1
3355 let Inst{21} = 0; // W = 0
3356 let Inst{22} = 0; // D = 0
3357 let Inst{20} = load;
3358 let DecoderMethod = "DecodeCopMemInstruction";
3361 def _PRE : T2CI<(outs),
3362 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3363 opc, "\tp$cop, cr$CRd, $addr!"> {
3364 let Inst{31-28} = op31_28;
3365 let Inst{24} = 1; // P = 1
3366 let Inst{21} = 1; // W = 1
3367 let Inst{22} = 0; // D = 0
3368 let Inst{20} = load;
3369 let DecoderMethod = "DecodeCopMemInstruction";
3372 def _POST : T2CI<(outs),
3373 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3374 opc, "\tp$cop, cr$CRd, $addr"> {
3375 let Inst{31-28} = op31_28;
3376 let Inst{24} = 0; // P = 0
3377 let Inst{21} = 1; // W = 1
3378 let Inst{22} = 0; // D = 0
3379 let Inst{20} = load;
3380 let DecoderMethod = "DecodeCopMemInstruction";
3383 def _OPTION : T2CI<(outs),
3384 (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3385 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3386 let Inst{31-28} = op31_28;
3387 let Inst{24} = 0; // P = 0
3388 let Inst{23} = 1; // U = 1
3389 let Inst{21} = 0; // W = 0
3390 let Inst{22} = 0; // D = 0
3391 let Inst{20} = load;
3392 let DecoderMethod = "DecodeCopMemInstruction";
3395 def L_OFFSET : T2CI<(outs),
3396 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3397 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3398 let Inst{31-28} = op31_28;
3399 let Inst{24} = 1; // P = 1
3400 let Inst{21} = 0; // W = 0
3401 let Inst{22} = 1; // D = 1
3402 let Inst{20} = load;
3403 let DecoderMethod = "DecodeCopMemInstruction";
3406 def L_PRE : T2CI<(outs),
3407 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3408 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3409 let Inst{31-28} = op31_28;
3410 let Inst{24} = 1; // P = 1
3411 let Inst{21} = 1; // W = 1
3412 let Inst{22} = 1; // D = 1
3413 let Inst{20} = load;
3414 let DecoderMethod = "DecodeCopMemInstruction";
3417 def L_POST : T2CI<(outs),
3418 (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
3419 postidx_imm8s4:$offset),
3420 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
3421 let Inst{31-28} = op31_28;
3422 let Inst{24} = 0; // P = 0
3423 let Inst{21} = 1; // W = 1
3424 let Inst{22} = 1; // D = 1
3425 let Inst{20} = load;
3426 let DecoderMethod = "DecodeCopMemInstruction";
3429 def L_OPTION : T2CI<(outs),
3430 (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3431 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3432 let Inst{31-28} = op31_28;
3433 let Inst{24} = 0; // P = 0
3434 let Inst{23} = 1; // U = 1
3435 let Inst{21} = 0; // W = 0
3436 let Inst{22} = 1; // D = 1
3437 let Inst{20} = load;
3438 let DecoderMethod = "DecodeCopMemInstruction";
3442 defm t2LDC : T2LdStCop<0b1111, 1, "ldc">;
3443 defm t2STC : T2LdStCop<0b1111, 0, "stc">;
3446 //===----------------------------------------------------------------------===//
3447 // Move between special register and ARM core register -- for disassembly only
3450 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3451 dag oops, dag iops, InstrItinClass itin,
3452 string opc, string asm, list<dag> pattern>
3453 : T2I<oops, iops, itin, opc, asm, pattern> {
3454 let Inst{31-20} = op31_20{11-0};
3455 let Inst{15-14} = op15_14{1-0};
3457 let Inst{12} = op12{0};
3461 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3462 dag oops, dag iops, InstrItinClass itin,
3463 string opc, string asm, list<dag> pattern>
3464 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3466 let Inst{11-8} = Rd;
3467 let Inst{19-16} = 0b1111;
3470 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3471 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3472 [/* For disassembly only; pattern left blank */]>;
3473 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3474 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3475 [/* For disassembly only; pattern left blank */]>;
3477 // Move from ARM core register to Special Register
3479 // No need to have both system and application versions, the encodings are the
3480 // same and the assembly parser has no way to distinguish between them. The mask
3481 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3482 // the mask with the fields to be accessed in the special register.
3483 def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3484 0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3485 NoItinerary, "msr", "\t$mask, $Rn",
3486 [/* For disassembly only; pattern left blank */]> {
3489 let Inst{19-16} = Rn;
3490 let Inst{20} = mask{4}; // R Bit
3491 let Inst{11-8} = mask{3-0};
3494 //===----------------------------------------------------------------------===//
3495 // Move between coprocessor and ARM core register
3498 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3500 : T2Cop<Op, oops, iops,
3501 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3503 let Inst{27-24} = 0b1110;
3504 let Inst{20} = direction;
3514 let Inst{15-12} = Rt;
3515 let Inst{11-8} = cop;
3516 let Inst{23-21} = opc1;
3517 let Inst{7-5} = opc2;
3518 let Inst{3-0} = CRm;
3519 let Inst{19-16} = CRn;
3522 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3523 list<dag> pattern = []>
3525 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3526 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3527 let Inst{27-24} = 0b1100;
3528 let Inst{23-21} = 0b010;
3529 let Inst{20} = direction;
3537 let Inst{15-12} = Rt;
3538 let Inst{19-16} = Rt2;
3539 let Inst{11-8} = cop;
3540 let Inst{7-4} = opc1;
3541 let Inst{3-0} = CRm;
3544 /* from ARM core register to coprocessor */
3545 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3547 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3548 c_imm:$CRm, imm0_7:$opc2),
3549 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3550 imm:$CRm, imm:$opc2)]>;
3551 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3552 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3553 c_imm:$CRm, imm0_7:$opc2),
3554 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3555 imm:$CRm, imm:$opc2)]>;
3557 /* from coprocessor to ARM core register */
3558 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3559 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3560 c_imm:$CRm, imm0_7:$opc2), []>;
3562 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3563 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3564 c_imm:$CRm, imm0_7:$opc2), []>;
3566 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3567 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3569 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3570 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3573 /* from ARM core register to coprocessor */
3574 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3575 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3577 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3578 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3579 GPR:$Rt2, imm:$CRm)]>;
3580 /* from coprocessor to ARM core register */
3581 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3583 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3585 //===----------------------------------------------------------------------===//
3586 // Other Coprocessor Instructions.
3589 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3590 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3591 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3592 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3593 imm:$CRm, imm:$opc2)]> {
3594 let Inst{27-24} = 0b1110;
3603 let Inst{3-0} = CRm;
3605 let Inst{7-5} = opc2;
3606 let Inst{11-8} = cop;
3607 let Inst{15-12} = CRd;
3608 let Inst{19-16} = CRn;
3609 let Inst{23-20} = opc1;
3612 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3613 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3614 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3615 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3616 imm:$CRm, imm:$opc2)]> {
3617 let Inst{27-24} = 0b1110;
3626 let Inst{3-0} = CRm;
3628 let Inst{7-5} = opc2;
3629 let Inst{11-8} = cop;
3630 let Inst{15-12} = CRd;
3631 let Inst{19-16} = CRn;
3632 let Inst{23-20} = opc1;
3637 //===----------------------------------------------------------------------===//
3638 // Non-Instruction Patterns
3641 // SXT/UXT with no rotate
3642 let AddedComplexity = 16 in {
3643 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3644 Requires<[IsThumb2]>;
3645 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3646 Requires<[IsThumb2]>;
3647 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3648 Requires<[HasT2ExtractPack, IsThumb2]>;
3649 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3650 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3651 Requires<[HasT2ExtractPack, IsThumb2]>;
3652 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3653 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3654 Requires<[HasT2ExtractPack, IsThumb2]>;
3657 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3658 Requires<[IsThumb2]>;
3659 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3660 Requires<[IsThumb2]>;
3661 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3662 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3663 Requires<[HasT2ExtractPack, IsThumb2]>;
3664 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3665 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3666 Requires<[HasT2ExtractPack, IsThumb2]>;
3668 // Atomic load/store patterns
3669 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3670 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3671 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3672 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3673 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3674 (t2LDRBs t2addrmode_so_reg:$addr)>;
3675 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3676 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3677 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3678 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3679 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3680 (t2LDRHs t2addrmode_so_reg:$addr)>;
3681 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3682 (t2LDRi12 t2addrmode_imm12:$addr)>;
3683 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3684 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3685 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3686 (t2LDRs t2addrmode_so_reg:$addr)>;
3687 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3688 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3689 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3690 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3691 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3692 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3693 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3694 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3695 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3696 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3697 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3698 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3699 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3700 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3701 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3702 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3703 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3704 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3707 //===----------------------------------------------------------------------===//
3708 // Assembler aliases
3711 // Aliases for ADC without the ".w" optional width specifier.
3712 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3713 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3714 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3715 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3716 pred:$p, cc_out:$s)>;
3718 // Aliases for SBC without the ".w" optional width specifier.
3719 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3720 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3721 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3722 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3723 pred:$p, cc_out:$s)>;
3725 // Aliases for ADD without the ".w" optional width specifier.
3726 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3727 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3728 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3729 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3730 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3731 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3732 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3733 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3734 pred:$p, cc_out:$s)>;
3736 // Alias for compares without the ".w" optional width specifier.
3737 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3738 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3739 def : t2InstAlias<"teq${p} $Rn, $Rm",
3740 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3741 def : t2InstAlias<"tst${p} $Rn, $Rm",
3742 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3745 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3746 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3747 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3749 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3751 def : t2InstAlias<"ldr${p} $Rt, $addr",
3752 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3753 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3754 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3755 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3756 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3757 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3758 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3759 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3760 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3762 def : t2InstAlias<"ldr${p} $Rt, $addr",
3763 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3764 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3765 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3766 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3767 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3768 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3769 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3770 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3771 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;