1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
19 let PrintMethod = "printT2SOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
24 // described for t2_so_imm def below.
25 def t2_so_imm_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(
27 ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
30 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
31 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
32 return CurDAG->getTargetConstant(
33 ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
36 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
37 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(
39 ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
42 // t2_so_imm - Match a 32-bit immediate operand, which is an
43 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
44 // immediate splatted into multiple bytes of the word. t2_so_imm values are
45 // represented in the imm field in the same 12-bit form that they are encoded
46 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
47 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
48 def t2_so_imm : Operand<i32>,
50 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
51 }], t2_so_imm_XFORM> {
52 let PrintMethod = "printT2SOImmOperand";
55 // t2_so_imm_not - Match an immediate that is a complement
57 def t2_so_imm_not : Operand<i32>,
59 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60 }], t2_so_imm_not_XFORM> {
61 let PrintMethod = "printT2SOImmOperand";
64 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65 def t2_so_imm_neg : Operand<i32>,
67 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
68 }], t2_so_imm_neg_XFORM> {
69 let PrintMethod = "printT2SOImmOperand";
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
88 def imm0_65535 : PatLeaf<(i32 imm), [{
89 return (uint32_t)N->getZExtValue() < 65536;
92 /// Split a 32-bit immediate into two 16 bit parts.
93 def t2_lo16 : SDNodeXForm<imm, [{
94 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
98 def t2_hi16 : SDNodeXForm<imm, [{
99 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
102 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
103 // Returns true if all low 16-bits are 0.
104 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
108 // Define Thumb2 specific addressing modes.
110 // t2addrmode_imm12 := reg + imm12
111 def t2addrmode_imm12 : Operand<i32>,
112 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
113 let PrintMethod = "printT2AddrModeImm12Operand";
114 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
117 // t2addrmode_imm8 := reg - imm8
118 def t2addrmode_imm8 : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
120 let PrintMethod = "printT2AddrModeImm8Operand";
121 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
124 def t2am_imm8_offset : Operand<i32>,
125 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
126 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
129 // t2addrmode_imm8s4 := reg + (imm8 << 2)
130 def t2addrmode_imm8s4 : Operand<i32>,
131 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
132 let PrintMethod = "printT2AddrModeImm8Operand";
133 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
136 // t2addrmode_so_reg := reg + reg << imm2
137 def t2addrmode_so_reg : Operand<i32>,
138 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
139 let PrintMethod = "printT2AddrModeSoRegOperand";
140 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
144 //===----------------------------------------------------------------------===//
145 // Multiclass helpers...
148 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
149 /// unary operation that produces a value. These are predicable and can be
150 /// changed to modify CPSR.
151 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
153 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
155 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
156 let isAsCheapAsAMove = Cheap;
157 let isReMaterializable = ReMat;
160 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
162 [(set GPR:$dst, (opnode GPR:$src))]>;
164 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
166 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
169 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
170 // binary operation that produces a value. These are predicable and can be
171 /// changed to modify CPSR.
172 multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
174 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
175 opc, " $dst, $lhs, $rhs",
176 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
178 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
179 opc, " $dst, $lhs, $rhs",
180 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
181 let isCommutable = Commutable;
184 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
185 opc, " $dst, $lhs, $rhs",
186 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
189 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
190 /// reversed. It doesn't define the 'rr' form since it's handled by its
191 /// T2I_bin_irs counterpart.
192 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
194 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
195 opc, " $dst, $rhs, $lhs",
196 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
198 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
199 opc, " $dst, $rhs, $lhs",
200 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
203 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
204 /// instruction modifies the CPSR register.
205 let Defs = [CPSR] in {
206 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
208 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
209 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
210 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
212 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
213 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
214 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
215 let isCommutable = Commutable;
218 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
219 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
220 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
224 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
225 /// patterns for a binary operation that produces a value.
226 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
228 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
229 opc, " $dst, $lhs, $rhs",
230 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
232 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
233 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
234 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
236 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
237 opc, " $dst, $lhs, $rhs",
238 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
239 let isCommutable = Commutable;
242 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
243 opc, " $dst, $lhs, $rhs",
244 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
247 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
248 /// binary operation that produces a value and use and define the carry bit.
249 /// It's not predicable.
250 let Uses = [CPSR] in {
251 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
253 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
254 opc, " $dst, $lhs, $rhs",
255 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
256 Requires<[IsThumb2, CarryDefIsUnused]>;
258 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
259 opc, " $dst, $lhs, $rhs",
260 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
261 Requires<[IsThumb2, CarryDefIsUnused]> {
262 let isCommutable = Commutable;
265 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
266 opc, " $dst, $lhs, $rhs",
267 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
268 Requires<[IsThumb2, CarryDefIsUnused]>;
269 // Carry setting variants
271 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
272 !strconcat(opc, "s $dst, $lhs, $rhs"),
273 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
274 Requires<[IsThumb2, CarryDefIsUsed]> {
278 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
279 !strconcat(opc, "s $dst, $lhs, $rhs"),
280 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
281 Requires<[IsThumb2, CarryDefIsUsed]> {
283 let isCommutable = Commutable;
286 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
287 !strconcat(opc, "s $dst, $lhs, $rhs"),
288 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
289 Requires<[IsThumb2, CarryDefIsUsed]> {
295 /// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
296 /// reversed. It doesn't define the 'rr' form since it's handled by its
297 /// T2I_adde_sube_irs counterpart.
298 let Defs = [CPSR], Uses = [CPSR] in {
299 multiclass T2I_rsc_is<string opc, PatFrag opnode> {
301 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
302 opc, " $dst, $rhs, $lhs",
303 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
304 Requires<[IsThumb2, CarryDefIsUnused]>;
306 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
307 opc, " $dst, $rhs, $lhs",
308 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
309 Requires<[IsThumb2, CarryDefIsUnused]>;
311 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
312 !strconcat(opc, "s $dst, $rhs, $lhs"),
313 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
314 Requires<[IsThumb2, CarryDefIsUsed]> {
318 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
319 !strconcat(opc, "s $dst, $rhs, $lhs"),
320 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
321 Requires<[IsThumb2, CarryDefIsUsed]> {
327 /// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
328 /// reversed. It doesn't define the 'rr' form since it's handled by its
329 /// T2I_bin_s_irs counterpart.
330 let Defs = [CPSR] in {
331 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
333 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
334 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
335 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
337 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
338 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
339 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
343 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
344 // rotate operation that produces a value.
345 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
347 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
348 opc, " $dst, $lhs, $rhs",
349 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
351 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
352 opc, " $dst, $lhs, $rhs",
353 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
356 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
357 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
358 /// a explicit result, only implicitly set CPSR.
359 let Uses = [CPSR] in {
360 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
362 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
364 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
366 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
368 [(opnode GPR:$lhs, GPR:$rhs)]>;
370 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
372 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
376 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
377 multiclass T2I_ld<string opc, PatFrag opnode> {
378 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
380 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
381 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
383 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
384 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
386 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
387 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
389 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
392 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
393 multiclass T2I_st<string opc, PatFrag opnode> {
394 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
396 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
397 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
399 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
400 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
402 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
405 /// T2I_picld - Defines the PIC load pattern.
406 class T2I_picld<string opc, PatFrag opnode> :
407 T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
408 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
409 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
411 /// T2I_picst - Defines the PIC store pattern.
412 class T2I_picst<string opc, PatFrag opnode> :
413 T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
414 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
415 [(opnode GPR:$src, addrmodepc:$addr)]>;
418 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
419 /// register and one whose operand is a register rotated by 8/16/24.
420 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
421 def r : T2I<(outs GPR:$dst), (ins GPR:$Src),
423 [(set GPR:$dst, (opnode GPR:$Src))]>;
424 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
425 opc, " $dst, $Src, ror $rot",
426 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
429 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
430 /// register and one whose operand is a register rotated by 8/16/24.
431 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
432 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
433 opc, " $dst, $LHS, $RHS",
434 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
435 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
436 opc, " $dst, $LHS, $RHS, ror $rot",
437 [(set GPR:$dst, (opnode GPR:$LHS,
438 (rotr GPR:$RHS, rot_imm:$rot)))]>;
441 //===----------------------------------------------------------------------===//
443 //===----------------------------------------------------------------------===//
445 //===----------------------------------------------------------------------===//
446 // Miscellaneous Instructions.
449 let isNotDuplicable = 1 in
450 def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
451 "$cp:\n\tadd $dst, pc",
452 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
455 // LEApcrel - Load a pc-relative address into a register without offending the
457 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
458 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
459 "${:private}PCRELL${:uid}+8))\n"),
460 !strconcat("${:private}PCRELL${:uid}:\n\t",
461 "add$p $dst, pc, #PCRELV${:uid}")),
464 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
465 (ins i32imm:$label, i32imm:$id, pred:$p),
466 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
467 "${:private}PCRELL${:uid}+8))\n"),
468 !strconcat("${:private}PCRELL${:uid}:\n\t",
469 "add$p $dst, pc, #PCRELV${:uid}")),
472 // ADD rd, sp, #so_imm
473 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
474 "add $dst, $sp, $imm",
477 // ADD rd, sp, #imm12
478 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
479 "addw $dst, $sp, $imm",
482 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
483 "addw $dst, $sp, $rhs",
487 //===----------------------------------------------------------------------===//
488 // Load / store Instructions.
492 let canFoldAsLoad = 1 in
493 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
495 // Loads with zero extension
496 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
497 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
499 // Loads with sign extension
500 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
501 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
505 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
506 "ldrd", " $dst, $addr", []>;
507 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
508 "ldrd", " $dst, $addr", []>;
511 // zextload i1 -> zextload i8
512 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
513 (t2LDRBi12 t2addrmode_imm12:$addr)>;
514 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
515 (t2LDRBi8 t2addrmode_imm8:$addr)>;
516 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
517 (t2LDRBs t2addrmode_so_reg:$addr)>;
518 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
519 (t2LDRBpci tconstpool:$addr)>;
521 // extload -> zextload
522 // FIXME: Reduce the number of patterns by legalizing extload to zextload
524 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
525 (t2LDRBi12 t2addrmode_imm12:$addr)>;
526 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
527 (t2LDRBi8 t2addrmode_imm8:$addr)>;
528 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
529 (t2LDRBs t2addrmode_so_reg:$addr)>;
530 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
531 (t2LDRBpci tconstpool:$addr)>;
533 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
534 (t2LDRBi12 t2addrmode_imm12:$addr)>;
535 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
536 (t2LDRBi8 t2addrmode_imm8:$addr)>;
537 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
538 (t2LDRBs t2addrmode_so_reg:$addr)>;
539 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
540 (t2LDRBpci tconstpool:$addr)>;
542 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
543 (t2LDRHi12 t2addrmode_imm12:$addr)>;
544 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
545 (t2LDRHi8 t2addrmode_imm8:$addr)>;
546 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
547 (t2LDRHs t2addrmode_so_reg:$addr)>;
548 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
549 (t2LDRHpci tconstpool:$addr)>;
553 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
554 (ins t2addrmode_imm8:$addr),
555 AddrModeT2_i8, IndexModePre,
556 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
559 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
560 (ins GPR:$base, t2am_imm8_offset:$offset),
561 AddrModeT2_i8, IndexModePost,
562 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
565 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
566 (ins t2addrmode_imm8:$addr),
567 AddrModeT2_i8, IndexModePre,
568 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
570 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
571 (ins GPR:$base, t2am_imm8_offset:$offset),
572 AddrModeT2_i8, IndexModePost,
573 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
576 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
577 (ins t2addrmode_imm8:$addr),
578 AddrModeT2_i8, IndexModePre,
579 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
581 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
582 (ins GPR:$base, t2am_imm8_offset:$offset),
583 AddrModeT2_i8, IndexModePost,
584 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
587 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
588 (ins t2addrmode_imm8:$addr),
589 AddrModeT2_i8, IndexModePre,
590 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
592 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
593 (ins GPR:$base, t2am_imm8_offset:$offset),
594 AddrModeT2_i8, IndexModePost,
595 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
598 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
599 (ins t2addrmode_imm8:$addr),
600 AddrModeT2_i8, IndexModePre,
601 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
603 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
604 (ins GPR:$base, t2am_imm8_offset:$offset),
605 AddrModeT2_i8, IndexModePost,
606 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
611 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
612 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
613 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
617 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
618 "strd", " $src, $addr", []>;
621 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
622 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
623 AddrModeT2_i8, IndexModePre,
624 "str", " $src, [$base, $offset]!", "$base = $base_wb",
626 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
628 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
629 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
630 AddrModeT2_i8, IndexModePost,
631 "str", " $src, [$base], $offset", "$base = $base_wb",
633 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
635 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
636 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
637 AddrModeT2_i8, IndexModePre,
638 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
640 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
642 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
643 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
644 AddrModeT2_i8, IndexModePost,
645 "strh", " $src, [$base], $offset", "$base = $base_wb",
647 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
649 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
650 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
651 AddrModeT2_i8, IndexModePre,
652 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
654 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
656 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
657 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
658 AddrModeT2_i8, IndexModePost,
659 "strb", " $src, [$base], $offset", "$base = $base_wb",
661 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
664 // Address computation and loads and stores in PIC mode.
665 let isNotDuplicable = 1, AddedComplexity = 10 in {
666 let canFoldAsLoad = 1 in
667 def t2PICLDR : T2I_picld<"ldr", UnOpFrag<(load node:$Src)>>;
669 def t2PICLDRH : T2I_picld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
670 def t2PICLDRB : T2I_picld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
671 def t2PICLDRSH : T2I_picld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
672 def t2PICLDRSB : T2I_picld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
674 def t2PICSTR : T2I_picst<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
675 def t2PICSTRH : T2I_picst<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
676 def t2PICSTRB : T2I_picst<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
677 } // isNotDuplicable = 1, AddedComplexity = 10
680 //===----------------------------------------------------------------------===//
681 // Load / store multiple Instructions.
685 def t2LDM : T2XI<(outs),
686 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
687 "ldm${p}${addr:submode} $addr, $dst1", []>;
690 def t2STM : T2XI<(outs),
691 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
692 "stm${p}${addr:submode} $addr, $src1", []>;
694 //===----------------------------------------------------------------------===//
695 // Move Instructions.
698 let neverHasSideEffects = 1 in
699 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
700 "mov", " $dst, $src", []>;
702 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
703 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
704 "mov", " $dst, $src",
705 [(set GPR:$dst, t2_so_imm:$src)]>;
707 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
708 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
709 "movw", " $dst, $src",
710 [(set GPR:$dst, imm0_65535:$src)]>;
712 // FIXME: Also available in ARM mode.
713 let Constraints = "$src = $dst" in
714 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
715 "movt", " $dst, $imm",
717 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
719 //===----------------------------------------------------------------------===//
720 // Extend Instructions.
725 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
726 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
728 defm t2SXTAB : T2I_bin_rrot<"sxtab",
729 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
730 defm t2SXTAH : T2I_bin_rrot<"sxtah",
731 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
733 // TODO: SXT(A){B|H}16
737 let AddedComplexity = 16 in {
738 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
739 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
740 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
742 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
743 (t2UXTB16r_rot GPR:$Src, 24)>;
744 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
745 (t2UXTB16r_rot GPR:$Src, 8)>;
747 defm t2UXTAB : T2I_bin_rrot<"uxtab",
748 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
749 defm t2UXTAH : T2I_bin_rrot<"uxtah",
750 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
753 //===----------------------------------------------------------------------===//
754 // Arithmetic Instructions.
757 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
758 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
760 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
761 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
762 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
764 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
765 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
768 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
769 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
770 defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
772 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
773 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
774 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
775 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
776 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
779 //===----------------------------------------------------------------------===//
780 // Shift and rotate Instructions.
783 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
784 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
785 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
786 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
788 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
789 "mov", " $dst, $src, rrx",
790 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
792 //===----------------------------------------------------------------------===//
793 // Bitwise Instructions.
796 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
797 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
798 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
800 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
802 let Constraints = "$src = $dst" in
803 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
804 "bfc", " $dst, $imm",
805 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
807 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
809 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
811 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
812 let AddedComplexity = 1 in
813 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
816 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
817 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
819 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
820 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
822 def : T2Pat<(t2_so_imm_not:$src),
823 (t2MVNi t2_so_imm_not:$src)>;
825 //===----------------------------------------------------------------------===//
826 // Multiply Instructions.
828 let isCommutable = 1 in
829 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
830 "mul", " $dst, $a, $b",
831 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
833 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
834 "mla", " $dst, $a, $b, $c",
835 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
837 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
838 "mls", " $dst, $a, $b, $c",
839 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
841 // Extra precision multiplies with low / high results
842 let neverHasSideEffects = 1 in {
843 let isCommutable = 1 in {
844 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
845 "smull", " $ldst, $hdst, $a, $b", []>;
847 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
848 "umull", " $ldst, $hdst, $a, $b", []>;
851 // Multiply + accumulate
852 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
853 "smlal", " $ldst, $hdst, $a, $b", []>;
855 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
856 "umlal", " $ldst, $hdst, $a, $b", []>;
858 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
859 "umaal", " $ldst, $hdst, $a, $b", []>;
860 } // neverHasSideEffects
862 // Most significant word multiply
863 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
864 "smmul", " $dst, $a, $b",
865 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
867 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
868 "smmla", " $dst, $a, $b, $c",
869 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
872 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
873 "smmls", " $dst, $a, $b, $c",
874 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
876 multiclass T2I_smul<string opc, PatFrag opnode> {
877 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
878 !strconcat(opc, "bb"), " $dst, $a, $b",
879 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
880 (sext_inreg GPR:$b, i16)))]>;
882 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
883 !strconcat(opc, "bt"), " $dst, $a, $b",
884 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
885 (sra GPR:$b, (i32 16))))]>;
887 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
888 !strconcat(opc, "tb"), " $dst, $a, $b",
889 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
890 (sext_inreg GPR:$b, i16)))]>;
892 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
893 !strconcat(opc, "tt"), " $dst, $a, $b",
894 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
895 (sra GPR:$b, (i32 16))))]>;
897 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
898 !strconcat(opc, "wb"), " $dst, $a, $b",
899 [(set GPR:$dst, (sra (opnode GPR:$a,
900 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
902 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
903 !strconcat(opc, "wt"), " $dst, $a, $b",
904 [(set GPR:$dst, (sra (opnode GPR:$a,
905 (sra GPR:$b, (i32 16))), (i32 16)))]>;
909 multiclass T2I_smla<string opc, PatFrag opnode> {
910 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
911 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
912 [(set GPR:$dst, (add GPR:$acc,
913 (opnode (sext_inreg GPR:$a, i16),
914 (sext_inreg GPR:$b, i16))))]>;
916 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
917 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
918 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
919 (sra GPR:$b, (i32 16)))))]>;
921 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
922 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
923 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
924 (sext_inreg GPR:$b, i16))))]>;
926 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
927 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
928 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
929 (sra GPR:$b, (i32 16)))))]>;
931 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
932 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
933 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
934 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
936 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
937 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
938 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
939 (sra GPR:$b, (i32 16))), (i32 16))))]>;
942 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
943 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
945 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
946 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
949 //===----------------------------------------------------------------------===//
950 // Misc. Arithmetic Instructions.
953 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
954 "clz", " $dst, $src",
955 [(set GPR:$dst, (ctlz GPR:$src))]>;
957 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
958 "rev", " $dst, $src",
959 [(set GPR:$dst, (bswap GPR:$src))]>;
961 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
962 "rev16", " $dst, $src",
964 (or (and (srl GPR:$src, (i32 8)), 0xFF),
965 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
966 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
967 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
969 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
970 "revsh", " $dst, $src",
973 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
974 (shl GPR:$src, (i32 8))), i16))]>;
976 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
977 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
978 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
979 (and (shl GPR:$src2, (i32 imm:$shamt)),
982 // Alternate cases for PKHBT where identities eliminate some nodes.
983 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
984 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
985 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
986 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
988 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
989 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
990 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
991 (and (sra GPR:$src2, imm16_31:$shamt),
994 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
995 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
996 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
997 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
998 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
999 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1000 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1002 //===----------------------------------------------------------------------===//
1003 // Comparison Instructions...
1006 defm t2CMP : T2I_cmp_is<"cmp",
1007 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1008 defm t2CMPz : T2I_cmp_is<"cmp",
1009 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1011 defm t2CMN : T2I_cmp_is<"cmn",
1012 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1013 defm t2CMNz : T2I_cmp_is<"cmn",
1014 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1016 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1017 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1019 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1020 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1022 defm t2TST : T2I_cmp_is<"tst",
1023 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1024 defm t2TEQ : T2I_cmp_is<"teq",
1025 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1027 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1028 // Short range conditional branch. Looks awesome for loops. Need to figure
1029 // out how to use this one.
1032 // Conditional moves
1033 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1034 // a two-value operand where a dag node expects two operands. :(
1035 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
1036 "mov", " $dst, $true",
1037 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1038 RegConstraint<"$false = $dst">;
1040 def t2MOVCCs : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_reg:$true),
1041 "mov", " $dst, $true",
1042 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1043 RegConstraint<"$false = $dst">;
1045 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1046 "mov", " $dst, $true",
1047 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1048 RegConstraint<"$false = $dst">;
1050 //===----------------------------------------------------------------------===//
1051 // Control-Flow Instructions
1054 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1055 let isPredicable = 1 in
1056 def t2B : T2XI<(outs), (ins brtarget:$target),
1060 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1061 def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1062 "mov pc, $target \n$jt",
1063 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1067 (ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id),
1068 "ldr pc, $target \n$jt",
1069 [(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt,
1074 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1075 "add pc, $target, $idx \n$jt",
1076 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>;
1077 } // isNotDuplicate, isIndirectBranch
1078 } // isBranch, isTerminator, isBarrier
1080 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1081 // a two-value operand where a dag node expects two operands. :(
1082 let isBranch = 1, isTerminator = 1 in
1083 def t2Bcc : T2I<(outs), (ins brtarget:$target),
1085 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1087 //===----------------------------------------------------------------------===//
1088 // Non-Instruction Patterns
1091 // ConstantPool, GlobalAddress, and JumpTable
1092 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1093 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1094 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1095 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1097 // Large immediate handling.
1099 def : T2Pat<(i32 imm:$src),
1100 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;