1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // Shifted operands. No register controlled shifts for Thumb2.
32 // Note: We do not support rrx shifted operands yet.
33 def t2_so_reg : Operand<i32>, // reg imm
34 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
36 let EncoderMethod = "getT2SORegOpValue";
37 let PrintMethod = "printT2SOOperand";
38 let DecoderMethod = "DecodeSORegImmOperand";
39 let ParserMatchClass = ShiftedImmAsmOperand;
40 let MIOperandInfo = (ops rGPR, i32imm);
43 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
44 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
48 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
49 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
50 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
53 // t2_so_imm - Match a 32-bit immediate operand, which is an
54 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
55 // immediate splatted into multiple bytes of the word.
56 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
57 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
58 return ARM_AM::getT2SOImmVal(Imm) != -1;
60 let ParserMatchClass = t2_so_imm_asmoperand;
61 let EncoderMethod = "getT2SOImmOpValue";
62 let DecoderMethod = "DecodeT2SOImm";
65 // t2_so_imm_not - Match an immediate that is a complement
67 def t2_so_imm_not : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
70 }], t2_so_imm_not_XFORM>;
72 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
73 def t2_so_imm_neg : Operand<i32>,
75 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
76 }], t2_so_imm_neg_XFORM>;
78 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
79 def imm0_4095 : Operand<i32>,
81 return Imm >= 0 && Imm < 4096;
84 def imm0_4095_neg : PatLeaf<(i32 imm), [{
85 return (uint32_t)(-N->getZExtValue()) < 4096;
88 def imm0_255_neg : PatLeaf<(i32 imm), [{
89 return (uint32_t)(-N->getZExtValue()) < 255;
92 def imm0_255_not : PatLeaf<(i32 imm), [{
93 return (uint32_t)(~N->getZExtValue()) < 255;
96 def lo5AllOne : PatLeaf<(i32 imm), [{
97 // Returns true if all low 5-bits are 1.
98 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
101 // Define Thumb2 specific addressing modes.
103 // t2addrmode_imm12 := reg + imm12
104 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
105 def t2addrmode_imm12 : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
107 let PrintMethod = "printAddrModeImm12Operand";
108 let EncoderMethod = "getAddrModeImm12OpValue";
109 let DecoderMethod = "DecodeT2AddrModeImm12";
110 let ParserMatchClass = t2addrmode_imm12_asmoperand;
111 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
114 // t2ldrlabel := imm12
115 def t2ldrlabel : Operand<i32> {
116 let EncoderMethod = "getAddrModeImm12OpValue";
120 // ADR instruction labels.
121 def t2adrlabel : Operand<i32> {
122 let EncoderMethod = "getT2AdrLabelOpValue";
126 // t2addrmode_posimm8 := reg + imm8
127 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
128 def t2addrmode_posimm8 : Operand<i32> {
129 let PrintMethod = "printT2AddrModeImm8Operand";
130 let EncoderMethod = "getT2AddrModeImm8OpValue";
131 let DecoderMethod = "DecodeT2AddrModeImm8";
132 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
133 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
136 // t2addrmode_negimm8 := reg - imm8
137 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
138 def t2addrmode_negimm8 : Operand<i32>,
139 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
140 let PrintMethod = "printT2AddrModeImm8Operand";
141 let EncoderMethod = "getT2AddrModeImm8OpValue";
142 let DecoderMethod = "DecodeT2AddrModeImm8";
143 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
144 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
147 // t2addrmode_imm8 := reg +/- imm8
148 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
149 def t2addrmode_imm8 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
151 let PrintMethod = "printT2AddrModeImm8Operand";
152 let EncoderMethod = "getT2AddrModeImm8OpValue";
153 let DecoderMethod = "DecodeT2AddrModeImm8";
154 let ParserMatchClass = MemImm8OffsetAsmOperand;
155 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
158 def t2am_imm8_offset : Operand<i32>,
159 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
160 [], [SDNPWantRoot]> {
161 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
162 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
163 let DecoderMethod = "DecodeT2Imm8";
166 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
167 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
168 def t2addrmode_imm8s4 : Operand<i32> {
169 let PrintMethod = "printT2AddrModeImm8s4Operand";
170 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
171 let DecoderMethod = "DecodeT2AddrModeImm8s4";
172 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
173 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
176 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
177 def t2am_imm8s4_offset : Operand<i32> {
178 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
179 let EncoderMethod = "getT2Imm8s4OpValue";
180 let DecoderMethod = "DecodeT2Imm8S4";
183 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
184 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
185 let Name = "MemImm0_1020s4Offset";
187 def t2addrmode_imm0_1020s4 : Operand<i32> {
188 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
189 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
190 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
191 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
192 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
195 // t2addrmode_so_reg := reg + (reg << imm2)
196 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
197 def t2addrmode_so_reg : Operand<i32>,
198 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
199 let PrintMethod = "printT2AddrModeSoRegOperand";
200 let EncoderMethod = "getT2AddrModeSORegOpValue";
201 let DecoderMethod = "DecodeT2AddrModeSOReg";
202 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
203 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
206 // Addresses for the TBB/TBH instructions.
207 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
208 def addrmode_tbb : Operand<i32> {
209 let PrintMethod = "printAddrModeTBB";
210 let ParserMatchClass = addrmode_tbb_asmoperand;
211 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
213 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
214 def addrmode_tbh : Operand<i32> {
215 let PrintMethod = "printAddrModeTBH";
216 let ParserMatchClass = addrmode_tbh_asmoperand;
217 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
220 //===----------------------------------------------------------------------===//
221 // Multiclass helpers...
225 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
226 string opc, string asm, list<dag> pattern>
227 : T2I<oops, iops, itin, opc, asm, pattern> {
232 let Inst{26} = imm{11};
233 let Inst{14-12} = imm{10-8};
234 let Inst{7-0} = imm{7-0};
238 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
239 string opc, string asm, list<dag> pattern>
240 : T2sI<oops, iops, itin, opc, asm, pattern> {
246 let Inst{26} = imm{11};
247 let Inst{14-12} = imm{10-8};
248 let Inst{7-0} = imm{7-0};
251 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
252 string opc, string asm, list<dag> pattern>
253 : T2I<oops, iops, itin, opc, asm, pattern> {
257 let Inst{19-16} = Rn;
258 let Inst{26} = imm{11};
259 let Inst{14-12} = imm{10-8};
260 let Inst{7-0} = imm{7-0};
264 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
265 string opc, string asm, list<dag> pattern>
266 : T2I<oops, iops, itin, opc, asm, pattern> {
271 let Inst{3-0} = ShiftedRm{3-0};
272 let Inst{5-4} = ShiftedRm{6-5};
273 let Inst{14-12} = ShiftedRm{11-9};
274 let Inst{7-6} = ShiftedRm{8-7};
277 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
278 string opc, string asm, list<dag> pattern>
279 : T2sI<oops, iops, itin, opc, asm, pattern> {
284 let Inst{3-0} = ShiftedRm{3-0};
285 let Inst{5-4} = ShiftedRm{6-5};
286 let Inst{14-12} = ShiftedRm{11-9};
287 let Inst{7-6} = ShiftedRm{8-7};
290 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
291 string opc, string asm, list<dag> pattern>
292 : T2I<oops, iops, itin, opc, asm, pattern> {
296 let Inst{19-16} = Rn;
297 let Inst{3-0} = ShiftedRm{3-0};
298 let Inst{5-4} = ShiftedRm{6-5};
299 let Inst{14-12} = ShiftedRm{11-9};
300 let Inst{7-6} = ShiftedRm{8-7};
303 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
304 string opc, string asm, list<dag> pattern>
305 : T2I<oops, iops, itin, opc, asm, pattern> {
313 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
314 string opc, string asm, list<dag> pattern>
315 : T2sI<oops, iops, itin, opc, asm, pattern> {
323 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
324 string opc, string asm, list<dag> pattern>
325 : T2I<oops, iops, itin, opc, asm, pattern> {
329 let Inst{19-16} = Rn;
334 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
335 string opc, string asm, list<dag> pattern>
336 : T2I<oops, iops, itin, opc, asm, pattern> {
342 let Inst{19-16} = Rn;
343 let Inst{26} = imm{11};
344 let Inst{14-12} = imm{10-8};
345 let Inst{7-0} = imm{7-0};
348 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
349 string opc, string asm, list<dag> pattern>
350 : T2sI<oops, iops, itin, opc, asm, pattern> {
356 let Inst{19-16} = Rn;
357 let Inst{26} = imm{11};
358 let Inst{14-12} = imm{10-8};
359 let Inst{7-0} = imm{7-0};
362 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
363 string opc, string asm, list<dag> pattern>
364 : T2I<oops, iops, itin, opc, asm, pattern> {
371 let Inst{14-12} = imm{4-2};
372 let Inst{7-6} = imm{1-0};
375 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
376 string opc, string asm, list<dag> pattern>
377 : T2sI<oops, iops, itin, opc, asm, pattern> {
384 let Inst{14-12} = imm{4-2};
385 let Inst{7-6} = imm{1-0};
388 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
389 string opc, string asm, list<dag> pattern>
390 : T2I<oops, iops, itin, opc, asm, pattern> {
396 let Inst{19-16} = Rn;
400 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
401 string opc, string asm, list<dag> pattern>
402 : T2sI<oops, iops, itin, opc, asm, pattern> {
408 let Inst{19-16} = Rn;
412 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
413 string opc, string asm, list<dag> pattern>
414 : T2I<oops, iops, itin, opc, asm, pattern> {
420 let Inst{19-16} = Rn;
421 let Inst{3-0} = ShiftedRm{3-0};
422 let Inst{5-4} = ShiftedRm{6-5};
423 let Inst{14-12} = ShiftedRm{11-9};
424 let Inst{7-6} = ShiftedRm{8-7};
427 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
428 string opc, string asm, list<dag> pattern>
429 : T2sI<oops, iops, itin, opc, asm, pattern> {
435 let Inst{19-16} = Rn;
436 let Inst{3-0} = ShiftedRm{3-0};
437 let Inst{5-4} = ShiftedRm{6-5};
438 let Inst{14-12} = ShiftedRm{11-9};
439 let Inst{7-6} = ShiftedRm{8-7};
442 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
443 string opc, string asm, list<dag> pattern>
444 : T2I<oops, iops, itin, opc, asm, pattern> {
450 let Inst{19-16} = Rn;
451 let Inst{15-12} = Ra;
456 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
457 dag oops, dag iops, InstrItinClass itin,
458 string opc, string asm, list<dag> pattern>
459 : T2I<oops, iops, itin, opc, asm, pattern> {
465 let Inst{31-23} = 0b111110111;
466 let Inst{22-20} = opc22_20;
467 let Inst{19-16} = Rn;
468 let Inst{15-12} = RdLo;
469 let Inst{11-8} = RdHi;
470 let Inst{7-4} = opc7_4;
475 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
476 /// binary operation that produces a value. These are predicable and can be
477 /// changed to modify CPSR.
478 multiclass T2I_bin_irs<bits<4> opcod, string opc,
479 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
480 PatFrag opnode, string baseOpc, bit Commutable = 0,
483 def ri : T2sTwoRegImm<
484 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
485 opc, "\t$Rd, $Rn, $imm",
486 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
487 let Inst{31-27} = 0b11110;
489 let Inst{24-21} = opcod;
493 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
494 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
495 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
496 let isCommutable = Commutable;
497 let Inst{31-27} = 0b11101;
498 let Inst{26-25} = 0b01;
499 let Inst{24-21} = opcod;
500 let Inst{14-12} = 0b000; // imm3
501 let Inst{7-6} = 0b00; // imm2
502 let Inst{5-4} = 0b00; // type
505 def rs : T2sTwoRegShiftedReg<
506 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
507 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
508 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
509 let Inst{31-27} = 0b11101;
510 let Inst{26-25} = 0b01;
511 let Inst{24-21} = opcod;
513 // Assembly aliases for optional destination operand when it's the same
514 // as the source operand.
515 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
516 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
517 t2_so_imm:$imm, pred:$p,
519 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
520 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
523 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
524 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
525 t2_so_reg:$shift, pred:$p,
529 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
530 // the ".w" suffix to indicate that they are wide.
531 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
532 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
533 PatFrag opnode, string baseOpc, bit Commutable = 0> :
534 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
535 // Assembler aliases w/o the ".w" suffix.
536 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
537 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
540 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
541 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
542 t2_so_reg:$shift, pred:$p,
545 // and with the optional destination operand, too.
546 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
547 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
550 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
551 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
552 t2_so_reg:$shift, pred:$p,
556 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
557 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
558 /// it is equivalent to the T2I_bin_irs counterpart.
559 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
561 def ri : T2sTwoRegImm<
562 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
563 opc, ".w\t$Rd, $Rn, $imm",
564 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
565 let Inst{31-27} = 0b11110;
567 let Inst{24-21} = opcod;
571 def rr : T2sThreeReg<
572 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
573 opc, "\t$Rd, $Rn, $Rm",
574 [/* For disassembly only; pattern left blank */]> {
575 let Inst{31-27} = 0b11101;
576 let Inst{26-25} = 0b01;
577 let Inst{24-21} = opcod;
578 let Inst{14-12} = 0b000; // imm3
579 let Inst{7-6} = 0b00; // imm2
580 let Inst{5-4} = 0b00; // type
583 def rs : T2sTwoRegShiftedReg<
584 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
585 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
586 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
587 let Inst{31-27} = 0b11101;
588 let Inst{26-25} = 0b01;
589 let Inst{24-21} = opcod;
593 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
594 /// instruction modifies the CPSR register.
596 /// These opcodes will be converted to the real non-S opcodes by
597 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
598 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
599 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
600 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
601 PatFrag opnode, bit Commutable = 0> {
603 def ri : T2sTwoRegImm<
604 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
605 opc, ".w\t$Rd, $Rn, $imm",
606 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]>;
608 def rr : T2sThreeReg<
609 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
610 opc, ".w\t$Rd, $Rn, $Rm",
611 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]>;
613 def rs : T2sTwoRegShiftedReg<
614 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
615 opc, ".w\t$Rd, $Rn, $ShiftedRm",
616 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]>;
620 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
621 /// patterns for a binary operation that produces a value.
622 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
623 bit Commutable = 0> {
625 // The register-immediate version is re-materializable. This is useful
626 // in particular for taking the address of a local.
627 let isReMaterializable = 1 in {
628 def ri : T2sTwoRegImm<
629 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
630 opc, ".w\t$Rd, $Rn, $imm",
631 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
632 let Inst{31-27} = 0b11110;
635 let Inst{23-21} = op23_21;
641 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
642 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
643 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
647 let Inst{31-27} = 0b11110;
648 let Inst{26} = imm{11};
649 let Inst{25-24} = 0b10;
650 let Inst{23-21} = op23_21;
651 let Inst{20} = 0; // The S bit.
652 let Inst{19-16} = Rn;
654 let Inst{14-12} = imm{10-8};
656 let Inst{7-0} = imm{7-0};
659 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
660 opc, ".w\t$Rd, $Rn, $Rm",
661 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
662 let isCommutable = Commutable;
663 let Inst{31-27} = 0b11101;
664 let Inst{26-25} = 0b01;
666 let Inst{23-21} = op23_21;
667 let Inst{14-12} = 0b000; // imm3
668 let Inst{7-6} = 0b00; // imm2
669 let Inst{5-4} = 0b00; // type
672 def rs : T2sTwoRegShiftedReg<
673 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
674 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
675 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
676 let Inst{31-27} = 0b11101;
677 let Inst{26-25} = 0b01;
679 let Inst{23-21} = op23_21;
683 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
684 /// for a binary operation that produces a value and use the carry
685 /// bit. It's not predicable.
686 let Defs = [CPSR], Uses = [CPSR] in {
687 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
688 bit Commutable = 0> {
690 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
691 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
692 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
693 Requires<[IsThumb2]> {
694 let Inst{31-27} = 0b11110;
696 let Inst{24-21} = opcod;
700 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
701 opc, ".w\t$Rd, $Rn, $Rm",
702 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
703 Requires<[IsThumb2]> {
704 let isCommutable = Commutable;
705 let Inst{31-27} = 0b11101;
706 let Inst{26-25} = 0b01;
707 let Inst{24-21} = opcod;
708 let Inst{14-12} = 0b000; // imm3
709 let Inst{7-6} = 0b00; // imm2
710 let Inst{5-4} = 0b00; // type
713 def rs : T2sTwoRegShiftedReg<
714 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
715 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
716 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
717 Requires<[IsThumb2]> {
718 let Inst{31-27} = 0b11101;
719 let Inst{26-25} = 0b01;
720 let Inst{24-21} = opcod;
725 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
726 /// version is not needed since this is only for codegen.
728 /// These opcodes will be converted to the real non-S opcodes by
729 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
730 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
731 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
733 def ri : T2sTwoRegImm<
734 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
735 opc, ".w\t$Rd, $Rn, $imm",
736 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]>;
738 def rs : T2sTwoRegShiftedReg<
739 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
740 IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
741 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>;
745 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
746 // rotate operation that produces a value.
747 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
750 def ri : T2sTwoRegShiftImm<
751 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
752 opc, ".w\t$Rd, $Rm, $imm",
753 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
754 let Inst{31-27} = 0b11101;
755 let Inst{26-21} = 0b010010;
756 let Inst{19-16} = 0b1111; // Rn
757 let Inst{5-4} = opcod;
760 def rr : T2sThreeReg<
761 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
762 opc, ".w\t$Rd, $Rn, $Rm",
763 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
764 let Inst{31-27} = 0b11111;
765 let Inst{26-23} = 0b0100;
766 let Inst{22-21} = opcod;
767 let Inst{15-12} = 0b1111;
768 let Inst{7-4} = 0b0000;
771 // Optional destination register
772 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
773 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
776 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
777 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
781 // Assembler aliases w/o the ".w" suffix.
782 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
783 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
786 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
787 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
791 // and with the optional destination operand, too.
792 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
793 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
796 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
797 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
802 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
803 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
804 /// a explicit result, only implicitly set CPSR.
805 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
806 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
807 PatFrag opnode, string baseOpc> {
808 let isCompare = 1, Defs = [CPSR] in {
810 def ri : T2OneRegCmpImm<
811 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
812 opc, ".w\t$Rn, $imm",
813 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
814 let Inst{31-27} = 0b11110;
816 let Inst{24-21} = opcod;
817 let Inst{20} = 1; // The S bit.
819 let Inst{11-8} = 0b1111; // Rd
822 def rr : T2TwoRegCmp<
823 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
825 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
826 let Inst{31-27} = 0b11101;
827 let Inst{26-25} = 0b01;
828 let Inst{24-21} = opcod;
829 let Inst{20} = 1; // The S bit.
830 let Inst{14-12} = 0b000; // imm3
831 let Inst{11-8} = 0b1111; // Rd
832 let Inst{7-6} = 0b00; // imm2
833 let Inst{5-4} = 0b00; // type
836 def rs : T2OneRegCmpShiftedReg<
837 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
838 opc, ".w\t$Rn, $ShiftedRm",
839 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
840 let Inst{31-27} = 0b11101;
841 let Inst{26-25} = 0b01;
842 let Inst{24-21} = opcod;
843 let Inst{20} = 1; // The S bit.
844 let Inst{11-8} = 0b1111; // Rd
848 // Assembler aliases w/o the ".w" suffix.
849 // No alias here for 'rr' version as not all instantiations of this
850 // multiclass want one (CMP in particular, does not).
851 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
852 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
853 t2_so_imm:$imm, pred:$p)>;
854 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
855 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
860 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
861 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
862 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
864 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
865 opc, ".w\t$Rt, $addr",
866 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
869 let Inst{31-25} = 0b1111100;
870 let Inst{24} = signed;
872 let Inst{22-21} = opcod;
873 let Inst{20} = 1; // load
874 let Inst{19-16} = addr{16-13}; // Rn
875 let Inst{15-12} = Rt;
876 let Inst{11-0} = addr{11-0}; // imm
878 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
880 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
883 let Inst{31-27} = 0b11111;
884 let Inst{26-25} = 0b00;
885 let Inst{24} = signed;
887 let Inst{22-21} = opcod;
888 let Inst{20} = 1; // load
889 let Inst{19-16} = addr{12-9}; // Rn
890 let Inst{15-12} = Rt;
892 // Offset: index==TRUE, wback==FALSE
893 let Inst{10} = 1; // The P bit.
894 let Inst{9} = addr{8}; // U
895 let Inst{8} = 0; // The W bit.
896 let Inst{7-0} = addr{7-0}; // imm
898 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
899 opc, ".w\t$Rt, $addr",
900 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
901 let Inst{31-27} = 0b11111;
902 let Inst{26-25} = 0b00;
903 let Inst{24} = signed;
905 let Inst{22-21} = opcod;
906 let Inst{20} = 1; // load
907 let Inst{11-6} = 0b000000;
910 let Inst{15-12} = Rt;
913 let Inst{19-16} = addr{9-6}; // Rn
914 let Inst{3-0} = addr{5-2}; // Rm
915 let Inst{5-4} = addr{1-0}; // imm
917 let DecoderMethod = "DecodeT2LoadShift";
920 // FIXME: Is the pci variant actually needed?
921 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
922 opc, ".w\t$Rt, $addr",
923 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
924 let isReMaterializable = 1;
925 let Inst{31-27} = 0b11111;
926 let Inst{26-25} = 0b00;
927 let Inst{24} = signed;
928 let Inst{23} = ?; // add = (U == '1')
929 let Inst{22-21} = opcod;
930 let Inst{20} = 1; // load
931 let Inst{19-16} = 0b1111; // Rn
934 let Inst{15-12} = Rt{3-0};
935 let Inst{11-0} = addr{11-0};
939 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
940 multiclass T2I_st<bits<2> opcod, string opc,
941 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
943 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
944 opc, ".w\t$Rt, $addr",
945 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
946 let Inst{31-27} = 0b11111;
947 let Inst{26-23} = 0b0001;
948 let Inst{22-21} = opcod;
949 let Inst{20} = 0; // !load
952 let Inst{15-12} = Rt;
955 let addr{12} = 1; // add = TRUE
956 let Inst{19-16} = addr{16-13}; // Rn
957 let Inst{23} = addr{12}; // U
958 let Inst{11-0} = addr{11-0}; // imm
960 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
962 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
963 let Inst{31-27} = 0b11111;
964 let Inst{26-23} = 0b0000;
965 let Inst{22-21} = opcod;
966 let Inst{20} = 0; // !load
968 // Offset: index==TRUE, wback==FALSE
969 let Inst{10} = 1; // The P bit.
970 let Inst{8} = 0; // The W bit.
973 let Inst{15-12} = Rt;
976 let Inst{19-16} = addr{12-9}; // Rn
977 let Inst{9} = addr{8}; // U
978 let Inst{7-0} = addr{7-0}; // imm
980 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
981 opc, ".w\t$Rt, $addr",
982 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
983 let Inst{31-27} = 0b11111;
984 let Inst{26-23} = 0b0000;
985 let Inst{22-21} = opcod;
986 let Inst{20} = 0; // !load
987 let Inst{11-6} = 0b000000;
990 let Inst{15-12} = Rt;
993 let Inst{19-16} = addr{9-6}; // Rn
994 let Inst{3-0} = addr{5-2}; // Rm
995 let Inst{5-4} = addr{1-0}; // imm
999 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1000 /// register and one whose operand is a register rotated by 8/16/24.
1001 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1002 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1003 opc, ".w\t$Rd, $Rm$rot",
1004 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1005 Requires<[IsThumb2]> {
1006 let Inst{31-27} = 0b11111;
1007 let Inst{26-23} = 0b0100;
1008 let Inst{22-20} = opcod;
1009 let Inst{19-16} = 0b1111; // Rn
1010 let Inst{15-12} = 0b1111;
1014 let Inst{5-4} = rot{1-0}; // rotate
1017 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1018 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1019 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1020 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1021 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1022 Requires<[HasT2ExtractPack, IsThumb2]> {
1024 let Inst{31-27} = 0b11111;
1025 let Inst{26-23} = 0b0100;
1026 let Inst{22-20} = opcod;
1027 let Inst{19-16} = 0b1111; // Rn
1028 let Inst{15-12} = 0b1111;
1030 let Inst{5-4} = rot;
1033 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1035 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1036 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1037 opc, "\t$Rd, $Rm$rot", []>,
1038 Requires<[IsThumb2, HasT2ExtractPack]> {
1040 let Inst{31-27} = 0b11111;
1041 let Inst{26-23} = 0b0100;
1042 let Inst{22-20} = opcod;
1043 let Inst{19-16} = 0b1111; // Rn
1044 let Inst{15-12} = 0b1111;
1046 let Inst{5-4} = rot;
1049 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1050 /// register and one whose operand is a register rotated by 8/16/24.
1051 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1052 : T2ThreeReg<(outs rGPR:$Rd),
1053 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1054 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1055 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1056 Requires<[HasT2ExtractPack, IsThumb2]> {
1058 let Inst{31-27} = 0b11111;
1059 let Inst{26-23} = 0b0100;
1060 let Inst{22-20} = opcod;
1061 let Inst{15-12} = 0b1111;
1063 let Inst{5-4} = rot;
1066 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1067 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1068 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1070 let Inst{31-27} = 0b11111;
1071 let Inst{26-23} = 0b0100;
1072 let Inst{22-20} = opcod;
1073 let Inst{15-12} = 0b1111;
1075 let Inst{5-4} = rot;
1078 //===----------------------------------------------------------------------===//
1080 //===----------------------------------------------------------------------===//
1082 //===----------------------------------------------------------------------===//
1083 // Miscellaneous Instructions.
1086 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1087 string asm, list<dag> pattern>
1088 : T2XI<oops, iops, itin, asm, pattern> {
1092 let Inst{11-8} = Rd;
1093 let Inst{26} = label{11};
1094 let Inst{14-12} = label{10-8};
1095 let Inst{7-0} = label{7-0};
1098 // LEApcrel - Load a pc-relative address into a register without offending the
1100 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1101 (ins t2adrlabel:$addr, pred:$p),
1102 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1103 let Inst{31-27} = 0b11110;
1104 let Inst{25-24} = 0b10;
1105 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1108 let Inst{19-16} = 0b1111; // Rn
1113 let Inst{11-8} = Rd;
1114 let Inst{23} = addr{12};
1115 let Inst{21} = addr{12};
1116 let Inst{26} = addr{11};
1117 let Inst{14-12} = addr{10-8};
1118 let Inst{7-0} = addr{7-0};
1120 let DecoderMethod = "DecodeT2Adr";
1123 let neverHasSideEffects = 1, isReMaterializable = 1 in
1124 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1126 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1127 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1132 //===----------------------------------------------------------------------===//
1133 // Load / store Instructions.
1137 let canFoldAsLoad = 1, isReMaterializable = 1 in
1138 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1139 UnOpFrag<(load node:$Src)>>;
1141 // Loads with zero extension
1142 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1143 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1144 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1145 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1147 // Loads with sign extension
1148 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1149 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1150 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1151 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1153 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1155 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1156 (ins t2addrmode_imm8s4:$addr),
1157 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1158 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1160 // zextload i1 -> zextload i8
1161 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1162 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1163 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1164 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1165 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1166 (t2LDRBs t2addrmode_so_reg:$addr)>;
1167 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1168 (t2LDRBpci tconstpool:$addr)>;
1170 // extload -> zextload
1171 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1173 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1174 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1175 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1176 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1177 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1178 (t2LDRBs t2addrmode_so_reg:$addr)>;
1179 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1180 (t2LDRBpci tconstpool:$addr)>;
1182 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1183 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1184 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1185 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1186 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1187 (t2LDRBs t2addrmode_so_reg:$addr)>;
1188 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1189 (t2LDRBpci tconstpool:$addr)>;
1191 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1192 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1193 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1194 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1195 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1196 (t2LDRHs t2addrmode_so_reg:$addr)>;
1197 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1198 (t2LDRHpci tconstpool:$addr)>;
1200 // FIXME: The destination register of the loads and stores can't be PC, but
1201 // can be SP. We need another regclass (similar to rGPR) to represent
1202 // that. Not a pressing issue since these are selected manually,
1207 let mayLoad = 1, neverHasSideEffects = 1 in {
1208 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1209 (ins t2addrmode_imm8:$addr),
1210 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1211 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1213 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1216 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1217 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1218 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1219 "ldr", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1221 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1222 (ins t2addrmode_imm8:$addr),
1223 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1224 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1226 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1228 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1229 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1230 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1231 "ldrb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1233 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1234 (ins t2addrmode_imm8:$addr),
1235 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1236 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1238 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1240 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1241 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1242 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1243 "ldrh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1245 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1246 (ins t2addrmode_imm8:$addr),
1247 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1248 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1250 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1252 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1253 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1254 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1255 "ldrsb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1257 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1258 (ins t2addrmode_imm8:$addr),
1259 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1260 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1262 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1264 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1265 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1266 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1267 "ldrsh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1268 } // mayLoad = 1, neverHasSideEffects = 1
1270 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1271 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1272 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1273 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1274 "\t$Rt, $addr", []> {
1277 let Inst{31-27} = 0b11111;
1278 let Inst{26-25} = 0b00;
1279 let Inst{24} = signed;
1281 let Inst{22-21} = type;
1282 let Inst{20} = 1; // load
1283 let Inst{19-16} = addr{12-9};
1284 let Inst{15-12} = Rt;
1286 let Inst{10-8} = 0b110; // PUW.
1287 let Inst{7-0} = addr{7-0};
1290 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1291 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1292 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1293 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1294 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1297 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1298 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1299 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1300 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1301 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1302 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1305 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1306 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1307 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1308 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1311 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1312 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1313 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1314 "str", "\t$Rt, $addr!",
1315 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1316 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1318 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1319 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1320 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1321 "strh", "\t$Rt, $addr!",
1322 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1323 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1326 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1327 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1328 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1329 "strb", "\t$Rt, $addr!",
1330 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1331 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1334 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1335 (ins rGPR:$Rt, addr_offset_none:$Rn,
1336 t2am_imm8_offset:$offset),
1337 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1338 "str", "\t$Rt, $Rn, $offset",
1339 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1340 [(set GPRnopc:$Rn_wb,
1341 (post_store rGPR:$Rt, addr_offset_none:$Rn,
1342 t2am_imm8_offset:$offset))]>;
1344 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1345 (ins rGPR:$Rt, addr_offset_none:$Rn,
1346 t2am_imm8_offset:$offset),
1347 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1348 "strh", "\t$Rt, $Rn, $offset",
1349 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1350 [(set GPRnopc:$Rn_wb,
1351 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1352 t2am_imm8_offset:$offset))]>;
1354 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1355 (ins rGPR:$Rt, addr_offset_none:$Rn,
1356 t2am_imm8_offset:$offset),
1357 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1358 "strb", "\t$Rt, $Rn, $offset",
1359 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1360 [(set GPRnopc:$Rn_wb,
1361 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1362 t2am_imm8_offset:$offset))]>;
1364 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1365 // put the patterns on the instruction definitions directly as ISel wants
1366 // the address base and offset to be separate operands, not a single
1367 // complex operand like we represent the instructions themselves. The
1368 // pseudos map between the two.
1369 let usesCustomInserter = 1,
1370 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1371 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1372 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1374 [(set GPRnopc:$Rn_wb,
1375 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1376 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1377 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1379 [(set GPRnopc:$Rn_wb,
1380 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1381 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1382 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1384 [(set GPRnopc:$Rn_wb,
1385 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1389 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1391 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1392 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1393 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1394 "\t$Rt, $addr", []> {
1395 let Inst{31-27} = 0b11111;
1396 let Inst{26-25} = 0b00;
1397 let Inst{24} = 0; // not signed
1399 let Inst{22-21} = type;
1400 let Inst{20} = 0; // store
1402 let Inst{10-8} = 0b110; // PUW
1406 let Inst{15-12} = Rt;
1407 let Inst{19-16} = addr{12-9};
1408 let Inst{7-0} = addr{7-0};
1411 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1412 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1413 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1415 // ldrd / strd pre / post variants
1416 // For disassembly only.
1418 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1419 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1420 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1421 let AsmMatchConverter = "cvtT2LdrdPre";
1422 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1425 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1426 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1427 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1428 "$addr.base = $wb", []>;
1430 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1431 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1432 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1433 "$addr.base = $wb", []> {
1434 let AsmMatchConverter = "cvtT2StrdPre";
1435 let DecoderMethod = "DecodeT2STRDPreInstruction";
1438 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1439 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1440 t2am_imm8s4_offset:$imm),
1441 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1442 "$addr.base = $wb", []>;
1444 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1445 // data/instruction access. These are for disassembly only.
1446 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1447 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1448 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1450 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1452 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1453 let Inst{31-25} = 0b1111100;
1454 let Inst{24} = instr;
1456 let Inst{21} = write;
1458 let Inst{15-12} = 0b1111;
1461 let addr{12} = 1; // add = TRUE
1462 let Inst{19-16} = addr{16-13}; // Rn
1463 let Inst{23} = addr{12}; // U
1464 let Inst{11-0} = addr{11-0}; // imm12
1467 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1469 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1470 let Inst{31-25} = 0b1111100;
1471 let Inst{24} = instr;
1472 let Inst{23} = 0; // U = 0
1474 let Inst{21} = write;
1476 let Inst{15-12} = 0b1111;
1477 let Inst{11-8} = 0b1100;
1480 let Inst{19-16} = addr{12-9}; // Rn
1481 let Inst{7-0} = addr{7-0}; // imm8
1484 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1486 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1487 let Inst{31-25} = 0b1111100;
1488 let Inst{24} = instr;
1489 let Inst{23} = 0; // add = TRUE for T1
1491 let Inst{21} = write;
1493 let Inst{15-12} = 0b1111;
1494 let Inst{11-6} = 0000000;
1497 let Inst{19-16} = addr{9-6}; // Rn
1498 let Inst{3-0} = addr{5-2}; // Rm
1499 let Inst{5-4} = addr{1-0}; // imm2
1501 let DecoderMethod = "DecodeT2LoadShift";
1505 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1506 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1507 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1509 //===----------------------------------------------------------------------===//
1510 // Load / store multiple Instructions.
1513 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1514 InstrItinClass itin_upd, bit L_bit> {
1516 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1517 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1521 let Inst{31-27} = 0b11101;
1522 let Inst{26-25} = 0b00;
1523 let Inst{24-23} = 0b01; // Increment After
1525 let Inst{21} = 0; // No writeback
1526 let Inst{20} = L_bit;
1527 let Inst{19-16} = Rn;
1529 let Inst{14-0} = regs{14-0};
1532 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1533 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1537 let Inst{31-27} = 0b11101;
1538 let Inst{26-25} = 0b00;
1539 let Inst{24-23} = 0b01; // Increment After
1541 let Inst{21} = 1; // Writeback
1542 let Inst{20} = L_bit;
1543 let Inst{19-16} = Rn;
1545 let Inst{14-0} = regs{14-0};
1548 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1549 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1553 let Inst{31-27} = 0b11101;
1554 let Inst{26-25} = 0b00;
1555 let Inst{24-23} = 0b10; // Decrement Before
1557 let Inst{21} = 0; // No writeback
1558 let Inst{20} = L_bit;
1559 let Inst{19-16} = Rn;
1561 let Inst{14-0} = regs{14-0};
1564 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1565 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1569 let Inst{31-27} = 0b11101;
1570 let Inst{26-25} = 0b00;
1571 let Inst{24-23} = 0b10; // Decrement Before
1573 let Inst{21} = 1; // Writeback
1574 let Inst{20} = L_bit;
1575 let Inst{19-16} = Rn;
1577 let Inst{14-0} = regs{14-0};
1581 let neverHasSideEffects = 1 in {
1583 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1584 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1586 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1587 InstrItinClass itin_upd, bit L_bit> {
1589 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1590 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1594 let Inst{31-27} = 0b11101;
1595 let Inst{26-25} = 0b00;
1596 let Inst{24-23} = 0b01; // Increment After
1598 let Inst{21} = 0; // No writeback
1599 let Inst{20} = L_bit;
1600 let Inst{19-16} = Rn;
1602 let Inst{14} = regs{14};
1604 let Inst{12-0} = regs{12-0};
1607 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1608 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1612 let Inst{31-27} = 0b11101;
1613 let Inst{26-25} = 0b00;
1614 let Inst{24-23} = 0b01; // Increment After
1616 let Inst{21} = 1; // Writeback
1617 let Inst{20} = L_bit;
1618 let Inst{19-16} = Rn;
1620 let Inst{14} = regs{14};
1622 let Inst{12-0} = regs{12-0};
1625 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1626 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1630 let Inst{31-27} = 0b11101;
1631 let Inst{26-25} = 0b00;
1632 let Inst{24-23} = 0b10; // Decrement Before
1634 let Inst{21} = 0; // No writeback
1635 let Inst{20} = L_bit;
1636 let Inst{19-16} = Rn;
1638 let Inst{14} = regs{14};
1640 let Inst{12-0} = regs{12-0};
1643 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1644 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1648 let Inst{31-27} = 0b11101;
1649 let Inst{26-25} = 0b00;
1650 let Inst{24-23} = 0b10; // Decrement Before
1652 let Inst{21} = 1; // Writeback
1653 let Inst{20} = L_bit;
1654 let Inst{19-16} = Rn;
1656 let Inst{14} = regs{14};
1658 let Inst{12-0} = regs{12-0};
1663 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1664 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1666 } // neverHasSideEffects
1669 //===----------------------------------------------------------------------===//
1670 // Move Instructions.
1673 let neverHasSideEffects = 1 in
1674 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1675 "mov", ".w\t$Rd, $Rm", []> {
1676 let Inst{31-27} = 0b11101;
1677 let Inst{26-25} = 0b01;
1678 let Inst{24-21} = 0b0010;
1679 let Inst{19-16} = 0b1111; // Rn
1680 let Inst{14-12} = 0b000;
1681 let Inst{7-4} = 0b0000;
1683 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1685 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1688 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1689 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1690 AddedComplexity = 1 in
1691 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1692 "mov", ".w\t$Rd, $imm",
1693 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1694 let Inst{31-27} = 0b11110;
1696 let Inst{24-21} = 0b0010;
1697 let Inst{19-16} = 0b1111; // Rn
1701 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1702 // Use aliases to get that to play nice here.
1703 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1705 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1708 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1709 pred:$p, zero_reg)>;
1710 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1711 pred:$p, zero_reg)>;
1713 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1714 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1715 "movw", "\t$Rd, $imm",
1716 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1717 let Inst{31-27} = 0b11110;
1719 let Inst{24-21} = 0b0010;
1720 let Inst{20} = 0; // The S bit.
1726 let Inst{11-8} = Rd;
1727 let Inst{19-16} = imm{15-12};
1728 let Inst{26} = imm{11};
1729 let Inst{14-12} = imm{10-8};
1730 let Inst{7-0} = imm{7-0};
1733 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1734 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1736 let Constraints = "$src = $Rd" in {
1737 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1738 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1739 "movt", "\t$Rd, $imm",
1741 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1742 let Inst{31-27} = 0b11110;
1744 let Inst{24-21} = 0b0110;
1745 let Inst{20} = 0; // The S bit.
1751 let Inst{11-8} = Rd;
1752 let Inst{19-16} = imm{15-12};
1753 let Inst{26} = imm{11};
1754 let Inst{14-12} = imm{10-8};
1755 let Inst{7-0} = imm{7-0};
1758 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1759 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1762 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1764 //===----------------------------------------------------------------------===//
1765 // Extend Instructions.
1770 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1771 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1772 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1773 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1774 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1776 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1777 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1778 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1779 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1780 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1784 let AddedComplexity = 16 in {
1785 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1786 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1787 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1788 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1789 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1790 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1792 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1793 // The transformation should probably be done as a combiner action
1794 // instead so we can include a check for masking back in the upper
1795 // eight bits of the source into the lower eight bits of the result.
1796 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1797 // (t2UXTB16 rGPR:$Src, 3)>,
1798 // Requires<[HasT2ExtractPack, IsThumb2]>;
1799 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1800 (t2UXTB16 rGPR:$Src, 1)>,
1801 Requires<[HasT2ExtractPack, IsThumb2]>;
1803 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1804 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1805 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1806 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1807 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1810 //===----------------------------------------------------------------------===//
1811 // Arithmetic Instructions.
1814 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1815 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1816 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1817 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1819 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1821 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1822 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1823 // AdjustInstrPostInstrSelection where we determine whether or not to
1824 // set the "s" bit based on CPSR liveness.
1826 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1827 // support for an optional CPSR definition that corresponds to the DAG
1828 // node's second value. We can then eliminate the implicit def of CPSR.
1829 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1830 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1831 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1832 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1833 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1834 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1836 let hasPostISelHook = 1 in {
1837 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1838 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1839 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1840 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1844 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1845 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1847 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1848 // CPSR and the implicit def of CPSR is not needed.
1849 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1850 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1852 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1853 // The assume-no-carry-in form uses the negation of the input since add/sub
1854 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1855 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1857 // The AddedComplexity preferences the first variant over the others since
1858 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1859 let AddedComplexity = 1 in
1860 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1861 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1862 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1863 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1864 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1865 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1866 let AddedComplexity = 1 in
1867 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1868 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1869 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1870 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1871 // The with-carry-in form matches bitwise not instead of the negation.
1872 // Effectively, the inverse interpretation of the carry flag already accounts
1873 // for part of the negation.
1874 let AddedComplexity = 1 in
1875 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1876 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1877 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1878 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1880 // Select Bytes -- for disassembly only
1882 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1883 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1884 Requires<[IsThumb2, HasThumb2DSP]> {
1885 let Inst{31-27} = 0b11111;
1886 let Inst{26-24} = 0b010;
1888 let Inst{22-20} = 0b010;
1889 let Inst{15-12} = 0b1111;
1891 let Inst{6-4} = 0b000;
1894 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1895 // And Miscellaneous operations -- for disassembly only
1896 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1897 list<dag> pat = [/* For disassembly only; pattern left blank */],
1898 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1899 string asm = "\t$Rd, $Rn, $Rm">
1900 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1901 Requires<[IsThumb2, HasThumb2DSP]> {
1902 let Inst{31-27} = 0b11111;
1903 let Inst{26-23} = 0b0101;
1904 let Inst{22-20} = op22_20;
1905 let Inst{15-12} = 0b1111;
1906 let Inst{7-4} = op7_4;
1912 let Inst{11-8} = Rd;
1913 let Inst{19-16} = Rn;
1917 // Saturating add/subtract -- for disassembly only
1919 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1920 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1921 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1922 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1923 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1924 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1925 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1926 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1927 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1928 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1929 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1930 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1931 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1932 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1933 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1934 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1935 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1936 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1937 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1938 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1939 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1940 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1942 // Signed/Unsigned add/subtract -- for disassembly only
1944 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1945 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1946 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1947 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1948 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1949 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1950 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1951 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1952 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1953 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1954 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1955 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1957 // Signed/Unsigned halving add/subtract -- for disassembly only
1959 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1960 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1961 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1962 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1963 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1964 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1965 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1966 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1967 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1968 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1969 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1970 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1972 // Helper class for disassembly only
1973 // A6.3.16 & A6.3.17
1974 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1975 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1976 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1977 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1978 let Inst{31-27} = 0b11111;
1979 let Inst{26-24} = 0b011;
1980 let Inst{23} = long;
1981 let Inst{22-20} = op22_20;
1982 let Inst{7-4} = op7_4;
1985 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1986 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1987 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1988 let Inst{31-27} = 0b11111;
1989 let Inst{26-24} = 0b011;
1990 let Inst{23} = long;
1991 let Inst{22-20} = op22_20;
1992 let Inst{7-4} = op7_4;
1995 // Unsigned Sum of Absolute Differences [and Accumulate].
1996 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1997 (ins rGPR:$Rn, rGPR:$Rm),
1998 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1999 Requires<[IsThumb2, HasThumb2DSP]> {
2000 let Inst{15-12} = 0b1111;
2002 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2003 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2004 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2005 Requires<[IsThumb2, HasThumb2DSP]>;
2007 // Signed/Unsigned saturate.
2008 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2009 string opc, string asm, list<dag> pattern>
2010 : T2I<oops, iops, itin, opc, asm, pattern> {
2016 let Inst{11-8} = Rd;
2017 let Inst{19-16} = Rn;
2018 let Inst{4-0} = sat_imm;
2019 let Inst{21} = sh{5};
2020 let Inst{14-12} = sh{4-2};
2021 let Inst{7-6} = sh{1-0};
2025 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2026 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2027 let Inst{31-27} = 0b11110;
2028 let Inst{25-22} = 0b1100;
2034 def t2SSAT16: T2SatI<
2035 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2036 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2037 Requires<[IsThumb2, HasThumb2DSP]> {
2038 let Inst{31-27} = 0b11110;
2039 let Inst{25-22} = 0b1100;
2042 let Inst{21} = 1; // sh = '1'
2043 let Inst{14-12} = 0b000; // imm3 = '000'
2044 let Inst{7-6} = 0b00; // imm2 = '00'
2045 let Inst{5-4} = 0b00;
2049 (outs rGPR:$Rd), (ins imm0_31:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2050 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2051 let Inst{31-27} = 0b11110;
2052 let Inst{25-22} = 0b1110;
2057 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2059 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2060 Requires<[IsThumb2, HasThumb2DSP]> {
2061 let Inst{31-27} = 0b11110;
2062 let Inst{25-22} = 0b1110;
2065 let Inst{21} = 1; // sh = '1'
2066 let Inst{14-12} = 0b000; // imm3 = '000'
2067 let Inst{7-6} = 0b00; // imm2 = '00'
2070 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2071 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2073 //===----------------------------------------------------------------------===//
2074 // Shift and rotate Instructions.
2077 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2078 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2079 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2080 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2081 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2082 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2083 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2084 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2086 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2087 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2088 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2090 let Uses = [CPSR] in {
2091 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2092 "rrx", "\t$Rd, $Rm",
2093 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2094 let Inst{31-27} = 0b11101;
2095 let Inst{26-25} = 0b01;
2096 let Inst{24-21} = 0b0010;
2097 let Inst{19-16} = 0b1111; // Rn
2098 let Inst{14-12} = 0b000;
2099 let Inst{7-4} = 0b0011;
2103 let isCodeGenOnly = 1, Defs = [CPSR] in {
2104 def t2MOVsrl_flag : T2TwoRegShiftImm<
2105 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2106 "lsrs", ".w\t$Rd, $Rm, #1",
2107 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2108 let Inst{31-27} = 0b11101;
2109 let Inst{26-25} = 0b01;
2110 let Inst{24-21} = 0b0010;
2111 let Inst{20} = 1; // The S bit.
2112 let Inst{19-16} = 0b1111; // Rn
2113 let Inst{5-4} = 0b01; // Shift type.
2114 // Shift amount = Inst{14-12:7-6} = 1.
2115 let Inst{14-12} = 0b000;
2116 let Inst{7-6} = 0b01;
2118 def t2MOVsra_flag : T2TwoRegShiftImm<
2119 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2120 "asrs", ".w\t$Rd, $Rm, #1",
2121 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2122 let Inst{31-27} = 0b11101;
2123 let Inst{26-25} = 0b01;
2124 let Inst{24-21} = 0b0010;
2125 let Inst{20} = 1; // The S bit.
2126 let Inst{19-16} = 0b1111; // Rn
2127 let Inst{5-4} = 0b10; // Shift type.
2128 // Shift amount = Inst{14-12:7-6} = 1.
2129 let Inst{14-12} = 0b000;
2130 let Inst{7-6} = 0b01;
2134 //===----------------------------------------------------------------------===//
2135 // Bitwise Instructions.
2138 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2139 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2140 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2141 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2142 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2143 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2144 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2145 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2146 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2148 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2149 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2150 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2153 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2154 string opc, string asm, list<dag> pattern>
2155 : T2I<oops, iops, itin, opc, asm, pattern> {
2160 let Inst{11-8} = Rd;
2161 let Inst{4-0} = msb{4-0};
2162 let Inst{14-12} = lsb{4-2};
2163 let Inst{7-6} = lsb{1-0};
2166 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2167 string opc, string asm, list<dag> pattern>
2168 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2171 let Inst{19-16} = Rn;
2174 let Constraints = "$src = $Rd" in
2175 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2176 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2177 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2178 let Inst{31-27} = 0b11110;
2179 let Inst{26} = 0; // should be 0.
2181 let Inst{24-20} = 0b10110;
2182 let Inst{19-16} = 0b1111; // Rn
2184 let Inst{5} = 0; // should be 0.
2187 let msb{4-0} = imm{9-5};
2188 let lsb{4-0} = imm{4-0};
2191 def t2SBFX: T2TwoRegBitFI<
2192 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2193 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2194 let Inst{31-27} = 0b11110;
2196 let Inst{24-20} = 0b10100;
2200 def t2UBFX: T2TwoRegBitFI<
2201 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2202 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2203 let Inst{31-27} = 0b11110;
2205 let Inst{24-20} = 0b11100;
2209 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2210 let Constraints = "$src = $Rd" in {
2211 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2212 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2213 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2214 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2215 bf_inv_mask_imm:$imm))]> {
2216 let Inst{31-27} = 0b11110;
2217 let Inst{26} = 0; // should be 0.
2219 let Inst{24-20} = 0b10110;
2221 let Inst{5} = 0; // should be 0.
2224 let msb{4-0} = imm{9-5};
2225 let lsb{4-0} = imm{4-0};
2229 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2230 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2231 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2234 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2235 /// unary operation that produces a value. These are predicable and can be
2236 /// changed to modify CPSR.
2237 multiclass T2I_un_irs<bits<4> opcod, string opc,
2238 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2239 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2241 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2243 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2244 let isAsCheapAsAMove = Cheap;
2245 let isReMaterializable = ReMat;
2246 let Inst{31-27} = 0b11110;
2248 let Inst{24-21} = opcod;
2249 let Inst{19-16} = 0b1111; // Rn
2253 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2254 opc, ".w\t$Rd, $Rm",
2255 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2256 let Inst{31-27} = 0b11101;
2257 let Inst{26-25} = 0b01;
2258 let Inst{24-21} = opcod;
2259 let Inst{19-16} = 0b1111; // Rn
2260 let Inst{14-12} = 0b000; // imm3
2261 let Inst{7-6} = 0b00; // imm2
2262 let Inst{5-4} = 0b00; // type
2265 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2266 opc, ".w\t$Rd, $ShiftedRm",
2267 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2268 let Inst{31-27} = 0b11101;
2269 let Inst{26-25} = 0b01;
2270 let Inst{24-21} = opcod;
2271 let Inst{19-16} = 0b1111; // Rn
2275 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2276 let AddedComplexity = 1 in
2277 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2278 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2279 UnOpFrag<(not node:$Src)>, 1, 1>;
2281 let AddedComplexity = 1 in
2282 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2283 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2285 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2286 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2287 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2288 Requires<[IsThumb2]>;
2290 def : T2Pat<(t2_so_imm_not:$src),
2291 (t2MVNi t2_so_imm_not:$src)>;
2293 //===----------------------------------------------------------------------===//
2294 // Multiply Instructions.
2296 let isCommutable = 1 in
2297 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2298 "mul", "\t$Rd, $Rn, $Rm",
2299 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2300 let Inst{31-27} = 0b11111;
2301 let Inst{26-23} = 0b0110;
2302 let Inst{22-20} = 0b000;
2303 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2304 let Inst{7-4} = 0b0000; // Multiply
2307 def t2MLA: T2FourReg<
2308 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2309 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2310 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2311 let Inst{31-27} = 0b11111;
2312 let Inst{26-23} = 0b0110;
2313 let Inst{22-20} = 0b000;
2314 let Inst{7-4} = 0b0000; // Multiply
2317 def t2MLS: T2FourReg<
2318 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2319 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2320 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2321 let Inst{31-27} = 0b11111;
2322 let Inst{26-23} = 0b0110;
2323 let Inst{22-20} = 0b000;
2324 let Inst{7-4} = 0b0001; // Multiply and Subtract
2327 // Extra precision multiplies with low / high results
2328 let neverHasSideEffects = 1 in {
2329 let isCommutable = 1 in {
2330 def t2SMULL : T2MulLong<0b000, 0b0000,
2331 (outs rGPR:$RdLo, rGPR:$RdHi),
2332 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2333 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2335 def t2UMULL : T2MulLong<0b010, 0b0000,
2336 (outs rGPR:$RdLo, rGPR:$RdHi),
2337 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2338 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2341 // Multiply + accumulate
2342 def t2SMLAL : T2MulLong<0b100, 0b0000,
2343 (outs rGPR:$RdLo, rGPR:$RdHi),
2344 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2345 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2347 def t2UMLAL : T2MulLong<0b110, 0b0000,
2348 (outs rGPR:$RdLo, rGPR:$RdHi),
2349 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2350 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2352 def t2UMAAL : T2MulLong<0b110, 0b0110,
2353 (outs rGPR:$RdLo, rGPR:$RdHi),
2354 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2355 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2356 Requires<[IsThumb2, HasThumb2DSP]>;
2357 } // neverHasSideEffects
2359 // Rounding variants of the below included for disassembly only
2361 // Most significant word multiply
2362 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2363 "smmul", "\t$Rd, $Rn, $Rm",
2364 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2365 Requires<[IsThumb2, HasThumb2DSP]> {
2366 let Inst{31-27} = 0b11111;
2367 let Inst{26-23} = 0b0110;
2368 let Inst{22-20} = 0b101;
2369 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2370 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2373 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2374 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2375 Requires<[IsThumb2, HasThumb2DSP]> {
2376 let Inst{31-27} = 0b11111;
2377 let Inst{26-23} = 0b0110;
2378 let Inst{22-20} = 0b101;
2379 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2380 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2383 def t2SMMLA : T2FourReg<
2384 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2385 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2386 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2387 Requires<[IsThumb2, HasThumb2DSP]> {
2388 let Inst{31-27} = 0b11111;
2389 let Inst{26-23} = 0b0110;
2390 let Inst{22-20} = 0b101;
2391 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2394 def t2SMMLAR: T2FourReg<
2395 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2396 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2397 Requires<[IsThumb2, HasThumb2DSP]> {
2398 let Inst{31-27} = 0b11111;
2399 let Inst{26-23} = 0b0110;
2400 let Inst{22-20} = 0b101;
2401 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2404 def t2SMMLS: T2FourReg<
2405 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2406 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2407 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2408 Requires<[IsThumb2, HasThumb2DSP]> {
2409 let Inst{31-27} = 0b11111;
2410 let Inst{26-23} = 0b0110;
2411 let Inst{22-20} = 0b110;
2412 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2415 def t2SMMLSR:T2FourReg<
2416 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2417 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2418 Requires<[IsThumb2, HasThumb2DSP]> {
2419 let Inst{31-27} = 0b11111;
2420 let Inst{26-23} = 0b0110;
2421 let Inst{22-20} = 0b110;
2422 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2425 multiclass T2I_smul<string opc, PatFrag opnode> {
2426 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2427 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2428 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2429 (sext_inreg rGPR:$Rm, i16)))]>,
2430 Requires<[IsThumb2, HasThumb2DSP]> {
2431 let Inst{31-27} = 0b11111;
2432 let Inst{26-23} = 0b0110;
2433 let Inst{22-20} = 0b001;
2434 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2435 let Inst{7-6} = 0b00;
2436 let Inst{5-4} = 0b00;
2439 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2440 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2441 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2442 (sra rGPR:$Rm, (i32 16))))]>,
2443 Requires<[IsThumb2, HasThumb2DSP]> {
2444 let Inst{31-27} = 0b11111;
2445 let Inst{26-23} = 0b0110;
2446 let Inst{22-20} = 0b001;
2447 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2448 let Inst{7-6} = 0b00;
2449 let Inst{5-4} = 0b01;
2452 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2453 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2454 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2455 (sext_inreg rGPR:$Rm, i16)))]>,
2456 Requires<[IsThumb2, HasThumb2DSP]> {
2457 let Inst{31-27} = 0b11111;
2458 let Inst{26-23} = 0b0110;
2459 let Inst{22-20} = 0b001;
2460 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2461 let Inst{7-6} = 0b00;
2462 let Inst{5-4} = 0b10;
2465 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2466 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2467 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2468 (sra rGPR:$Rm, (i32 16))))]>,
2469 Requires<[IsThumb2, HasThumb2DSP]> {
2470 let Inst{31-27} = 0b11111;
2471 let Inst{26-23} = 0b0110;
2472 let Inst{22-20} = 0b001;
2473 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2474 let Inst{7-6} = 0b00;
2475 let Inst{5-4} = 0b11;
2478 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2479 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2480 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2481 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2482 Requires<[IsThumb2, HasThumb2DSP]> {
2483 let Inst{31-27} = 0b11111;
2484 let Inst{26-23} = 0b0110;
2485 let Inst{22-20} = 0b011;
2486 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2487 let Inst{7-6} = 0b00;
2488 let Inst{5-4} = 0b00;
2491 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2492 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2493 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2494 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2495 Requires<[IsThumb2, HasThumb2DSP]> {
2496 let Inst{31-27} = 0b11111;
2497 let Inst{26-23} = 0b0110;
2498 let Inst{22-20} = 0b011;
2499 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2500 let Inst{7-6} = 0b00;
2501 let Inst{5-4} = 0b01;
2506 multiclass T2I_smla<string opc, PatFrag opnode> {
2508 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2509 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2510 [(set rGPR:$Rd, (add rGPR:$Ra,
2511 (opnode (sext_inreg rGPR:$Rn, i16),
2512 (sext_inreg rGPR:$Rm, i16))))]>,
2513 Requires<[IsThumb2, HasThumb2DSP]> {
2514 let Inst{31-27} = 0b11111;
2515 let Inst{26-23} = 0b0110;
2516 let Inst{22-20} = 0b001;
2517 let Inst{7-6} = 0b00;
2518 let Inst{5-4} = 0b00;
2522 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2523 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2524 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2525 (sra rGPR:$Rm, (i32 16)))))]>,
2526 Requires<[IsThumb2, HasThumb2DSP]> {
2527 let Inst{31-27} = 0b11111;
2528 let Inst{26-23} = 0b0110;
2529 let Inst{22-20} = 0b001;
2530 let Inst{7-6} = 0b00;
2531 let Inst{5-4} = 0b01;
2535 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2536 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2537 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2538 (sext_inreg rGPR:$Rm, i16))))]>,
2539 Requires<[IsThumb2, HasThumb2DSP]> {
2540 let Inst{31-27} = 0b11111;
2541 let Inst{26-23} = 0b0110;
2542 let Inst{22-20} = 0b001;
2543 let Inst{7-6} = 0b00;
2544 let Inst{5-4} = 0b10;
2548 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2549 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2550 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2551 (sra rGPR:$Rm, (i32 16)))))]>,
2552 Requires<[IsThumb2, HasThumb2DSP]> {
2553 let Inst{31-27} = 0b11111;
2554 let Inst{26-23} = 0b0110;
2555 let Inst{22-20} = 0b001;
2556 let Inst{7-6} = 0b00;
2557 let Inst{5-4} = 0b11;
2561 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2562 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2563 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2564 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2565 Requires<[IsThumb2, HasThumb2DSP]> {
2566 let Inst{31-27} = 0b11111;
2567 let Inst{26-23} = 0b0110;
2568 let Inst{22-20} = 0b011;
2569 let Inst{7-6} = 0b00;
2570 let Inst{5-4} = 0b00;
2574 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2575 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2576 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2577 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2578 Requires<[IsThumb2, HasThumb2DSP]> {
2579 let Inst{31-27} = 0b11111;
2580 let Inst{26-23} = 0b0110;
2581 let Inst{22-20} = 0b011;
2582 let Inst{7-6} = 0b00;
2583 let Inst{5-4} = 0b01;
2587 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2588 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2590 // Halfword multiple accumulate long: SMLAL<x><y>
2591 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2592 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2593 [/* For disassembly only; pattern left blank */]>,
2594 Requires<[IsThumb2, HasThumb2DSP]>;
2595 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2596 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2597 [/* For disassembly only; pattern left blank */]>,
2598 Requires<[IsThumb2, HasThumb2DSP]>;
2599 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2600 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2601 [/* For disassembly only; pattern left blank */]>,
2602 Requires<[IsThumb2, HasThumb2DSP]>;
2603 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2604 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2605 [/* For disassembly only; pattern left blank */]>,
2606 Requires<[IsThumb2, HasThumb2DSP]>;
2608 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2609 def t2SMUAD: T2ThreeReg_mac<
2610 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2611 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2612 Requires<[IsThumb2, HasThumb2DSP]> {
2613 let Inst{15-12} = 0b1111;
2615 def t2SMUADX:T2ThreeReg_mac<
2616 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2617 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2618 Requires<[IsThumb2, HasThumb2DSP]> {
2619 let Inst{15-12} = 0b1111;
2621 def t2SMUSD: T2ThreeReg_mac<
2622 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2623 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2624 Requires<[IsThumb2, HasThumb2DSP]> {
2625 let Inst{15-12} = 0b1111;
2627 def t2SMUSDX:T2ThreeReg_mac<
2628 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2629 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2630 Requires<[IsThumb2, HasThumb2DSP]> {
2631 let Inst{15-12} = 0b1111;
2633 def t2SMLAD : T2FourReg_mac<
2634 0, 0b010, 0b0000, (outs rGPR:$Rd),
2635 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2636 "\t$Rd, $Rn, $Rm, $Ra", []>,
2637 Requires<[IsThumb2, HasThumb2DSP]>;
2638 def t2SMLADX : T2FourReg_mac<
2639 0, 0b010, 0b0001, (outs rGPR:$Rd),
2640 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2641 "\t$Rd, $Rn, $Rm, $Ra", []>,
2642 Requires<[IsThumb2, HasThumb2DSP]>;
2643 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2644 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2645 "\t$Rd, $Rn, $Rm, $Ra", []>,
2646 Requires<[IsThumb2, HasThumb2DSP]>;
2647 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2648 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2649 "\t$Rd, $Rn, $Rm, $Ra", []>,
2650 Requires<[IsThumb2, HasThumb2DSP]>;
2651 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2652 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2653 "\t$Ra, $Rd, $Rn, $Rm", []>,
2654 Requires<[IsThumb2, HasThumb2DSP]>;
2655 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2656 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2657 "\t$Ra, $Rd, $Rn, $Rm", []>,
2658 Requires<[IsThumb2, HasThumb2DSP]>;
2659 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2660 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2661 "\t$Ra, $Rd, $Rn, $Rm", []>,
2662 Requires<[IsThumb2, HasThumb2DSP]>;
2663 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2664 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2665 "\t$Ra, $Rd, $Rn, $Rm", []>,
2666 Requires<[IsThumb2, HasThumb2DSP]>;
2668 //===----------------------------------------------------------------------===//
2669 // Division Instructions.
2670 // Signed and unsigned division on v7-M
2672 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2673 "sdiv", "\t$Rd, $Rn, $Rm",
2674 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2675 Requires<[HasDivide, IsThumb2]> {
2676 let Inst{31-27} = 0b11111;
2677 let Inst{26-21} = 0b011100;
2679 let Inst{15-12} = 0b1111;
2680 let Inst{7-4} = 0b1111;
2683 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2684 "udiv", "\t$Rd, $Rn, $Rm",
2685 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2686 Requires<[HasDivide, IsThumb2]> {
2687 let Inst{31-27} = 0b11111;
2688 let Inst{26-21} = 0b011101;
2690 let Inst{15-12} = 0b1111;
2691 let Inst{7-4} = 0b1111;
2694 //===----------------------------------------------------------------------===//
2695 // Misc. Arithmetic Instructions.
2698 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2699 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2700 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2701 let Inst{31-27} = 0b11111;
2702 let Inst{26-22} = 0b01010;
2703 let Inst{21-20} = op1;
2704 let Inst{15-12} = 0b1111;
2705 let Inst{7-6} = 0b10;
2706 let Inst{5-4} = op2;
2710 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2711 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2713 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2714 "rbit", "\t$Rd, $Rm",
2715 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2717 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2718 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2720 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2721 "rev16", ".w\t$Rd, $Rm",
2722 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2724 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2725 "revsh", ".w\t$Rd, $Rm",
2726 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2728 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2729 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2730 (t2REVSH rGPR:$Rm)>;
2732 def t2PKHBT : T2ThreeReg<
2733 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2734 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2735 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2736 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2738 Requires<[HasT2ExtractPack, IsThumb2]> {
2739 let Inst{31-27} = 0b11101;
2740 let Inst{26-25} = 0b01;
2741 let Inst{24-20} = 0b01100;
2742 let Inst{5} = 0; // BT form
2746 let Inst{14-12} = sh{4-2};
2747 let Inst{7-6} = sh{1-0};
2750 // Alternate cases for PKHBT where identities eliminate some nodes.
2751 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2752 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2753 Requires<[HasT2ExtractPack, IsThumb2]>;
2754 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2755 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2756 Requires<[HasT2ExtractPack, IsThumb2]>;
2758 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2759 // will match the pattern below.
2760 def t2PKHTB : T2ThreeReg<
2761 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2762 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2763 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2764 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2766 Requires<[HasT2ExtractPack, IsThumb2]> {
2767 let Inst{31-27} = 0b11101;
2768 let Inst{26-25} = 0b01;
2769 let Inst{24-20} = 0b01100;
2770 let Inst{5} = 1; // TB form
2774 let Inst{14-12} = sh{4-2};
2775 let Inst{7-6} = sh{1-0};
2778 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2779 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2780 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2781 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2782 Requires<[HasT2ExtractPack, IsThumb2]>;
2783 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2784 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2785 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2786 Requires<[HasT2ExtractPack, IsThumb2]>;
2788 //===----------------------------------------------------------------------===//
2789 // Comparison Instructions...
2791 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2792 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2793 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2795 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2796 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2797 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2798 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2799 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2800 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2802 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2803 // Compare-to-zero still works out, just not the relationals
2804 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2805 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2806 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2807 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2808 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2811 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2812 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2814 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2815 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2817 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2818 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2819 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2821 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2822 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2823 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2826 // Conditional moves
2827 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2828 // a two-value operand where a dag node expects two operands. :(
2829 let neverHasSideEffects = 1 in {
2830 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2831 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2833 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2834 RegConstraint<"$false = $Rd">;
2836 let isMoveImm = 1 in
2837 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2838 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2840 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2841 RegConstraint<"$false = $Rd">;
2843 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2844 let isCodeGenOnly = 1 in {
2845 let isMoveImm = 1 in
2846 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2848 "movw", "\t$Rd, $imm", []>,
2849 RegConstraint<"$false = $Rd"> {
2850 let Inst{31-27} = 0b11110;
2852 let Inst{24-21} = 0b0010;
2853 let Inst{20} = 0; // The S bit.
2859 let Inst{11-8} = Rd;
2860 let Inst{19-16} = imm{15-12};
2861 let Inst{26} = imm{11};
2862 let Inst{14-12} = imm{10-8};
2863 let Inst{7-0} = imm{7-0};
2866 let isMoveImm = 1 in
2867 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2868 (ins rGPR:$false, i32imm:$src, pred:$p),
2869 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2871 let isMoveImm = 1 in
2872 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2873 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2874 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2875 imm:$cc, CCR:$ccr))*/]>,
2876 RegConstraint<"$false = $Rd"> {
2877 let Inst{31-27} = 0b11110;
2879 let Inst{24-21} = 0b0011;
2880 let Inst{20} = 0; // The S bit.
2881 let Inst{19-16} = 0b1111; // Rn
2885 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2886 string opc, string asm, list<dag> pattern>
2887 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2888 let Inst{31-27} = 0b11101;
2889 let Inst{26-25} = 0b01;
2890 let Inst{24-21} = 0b0010;
2891 let Inst{20} = 0; // The S bit.
2892 let Inst{19-16} = 0b1111; // Rn
2893 let Inst{5-4} = opcod; // Shift type.
2895 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2896 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2897 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2898 RegConstraint<"$false = $Rd">;
2899 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2900 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2901 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2902 RegConstraint<"$false = $Rd">;
2903 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2904 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2905 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2906 RegConstraint<"$false = $Rd">;
2907 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2908 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2909 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2910 RegConstraint<"$false = $Rd">;
2911 } // isCodeGenOnly = 1
2912 } // neverHasSideEffects
2914 //===----------------------------------------------------------------------===//
2915 // Atomic operations intrinsics
2918 // memory barriers protect the atomic sequences
2919 let hasSideEffects = 1 in {
2920 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2921 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2922 Requires<[IsThumb, HasDB]> {
2924 let Inst{31-4} = 0xf3bf8f5;
2925 let Inst{3-0} = opt;
2929 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2930 "dsb", "\t$opt", []>,
2931 Requires<[IsThumb, HasDB]> {
2933 let Inst{31-4} = 0xf3bf8f4;
2934 let Inst{3-0} = opt;
2937 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2939 []>, Requires<[IsThumb2, HasDB]> {
2941 let Inst{31-4} = 0xf3bf8f6;
2942 let Inst{3-0} = opt;
2945 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2946 InstrItinClass itin, string opc, string asm, string cstr,
2947 list<dag> pattern, bits<4> rt2 = 0b1111>
2948 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2949 let Inst{31-27} = 0b11101;
2950 let Inst{26-20} = 0b0001101;
2951 let Inst{11-8} = rt2;
2952 let Inst{7-6} = 0b01;
2953 let Inst{5-4} = opcod;
2954 let Inst{3-0} = 0b1111;
2958 let Inst{19-16} = addr;
2959 let Inst{15-12} = Rt;
2961 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2962 InstrItinClass itin, string opc, string asm, string cstr,
2963 list<dag> pattern, bits<4> rt2 = 0b1111>
2964 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2965 let Inst{31-27} = 0b11101;
2966 let Inst{26-20} = 0b0001100;
2967 let Inst{11-8} = rt2;
2968 let Inst{7-6} = 0b01;
2969 let Inst{5-4} = opcod;
2975 let Inst{19-16} = addr;
2976 let Inst{15-12} = Rt;
2979 let mayLoad = 1 in {
2980 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2981 AddrModeNone, 4, NoItinerary,
2982 "ldrexb", "\t$Rt, $addr", "", []>;
2983 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2984 AddrModeNone, 4, NoItinerary,
2985 "ldrexh", "\t$Rt, $addr", "", []>;
2986 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
2987 AddrModeNone, 4, NoItinerary,
2988 "ldrex", "\t$Rt, $addr", "", []> {
2991 let Inst{31-27} = 0b11101;
2992 let Inst{26-20} = 0b0000101;
2993 let Inst{19-16} = addr{11-8};
2994 let Inst{15-12} = Rt;
2995 let Inst{11-8} = 0b1111;
2996 let Inst{7-0} = addr{7-0};
2998 let hasExtraDefRegAllocReq = 1 in
2999 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3000 (ins addr_offset_none:$addr),
3001 AddrModeNone, 4, NoItinerary,
3002 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3005 let Inst{11-8} = Rt2;
3009 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3010 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3011 (ins rGPR:$Rt, addr_offset_none:$addr),
3012 AddrModeNone, 4, NoItinerary,
3013 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3014 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3015 (ins rGPR:$Rt, addr_offset_none:$addr),
3016 AddrModeNone, 4, NoItinerary,
3017 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3018 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3019 t2addrmode_imm0_1020s4:$addr),
3020 AddrModeNone, 4, NoItinerary,
3021 "strex", "\t$Rd, $Rt, $addr", "",
3026 let Inst{31-27} = 0b11101;
3027 let Inst{26-20} = 0b0000100;
3028 let Inst{19-16} = addr{11-8};
3029 let Inst{15-12} = Rt;
3030 let Inst{11-8} = Rd;
3031 let Inst{7-0} = addr{7-0};
3035 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3036 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3037 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3038 AddrModeNone, 4, NoItinerary,
3039 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3042 let Inst{11-8} = Rt2;
3045 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3046 Requires<[IsThumb2, HasV7]> {
3047 let Inst{31-16} = 0xf3bf;
3048 let Inst{15-14} = 0b10;
3051 let Inst{11-8} = 0b1111;
3052 let Inst{7-4} = 0b0010;
3053 let Inst{3-0} = 0b1111;
3056 //===----------------------------------------------------------------------===//
3057 // SJLJ Exception handling intrinsics
3058 // eh_sjlj_setjmp() is an instruction sequence to store the return
3059 // address and save #0 in R0 for the non-longjmp case.
3060 // Since by its nature we may be coming from some other function to get
3061 // here, and we're using the stack frame for the containing function to
3062 // save/restore registers, we can't keep anything live in regs across
3063 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3064 // when we get here from a longjmp(). We force everything out of registers
3065 // except for our own input by listing the relevant registers in Defs. By
3066 // doing so, we also cause the prologue/epilogue code to actively preserve
3067 // all of the callee-saved resgisters, which is exactly what we want.
3068 // $val is a scratch register for our use.
3070 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3071 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
3072 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3073 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3074 AddrModeNone, 0, NoItinerary, "", "",
3075 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3076 Requires<[IsThumb2, HasVFP2]>;
3080 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3081 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3082 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3083 AddrModeNone, 0, NoItinerary, "", "",
3084 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3085 Requires<[IsThumb2, NoVFP]>;
3089 //===----------------------------------------------------------------------===//
3090 // Control-Flow Instructions
3093 // FIXME: remove when we have a way to marking a MI with these properties.
3094 // FIXME: Should pc be an implicit operand like PICADD, etc?
3095 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3096 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3097 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3098 reglist:$regs, variable_ops),
3099 4, IIC_iLoad_mBr, [],
3100 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3101 RegConstraint<"$Rn = $wb">;
3103 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3104 let isPredicable = 1 in
3105 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3107 [(br bb:$target)]> {
3108 let Inst{31-27} = 0b11110;
3109 let Inst{15-14} = 0b10;
3113 let Inst{26} = target{19};
3114 let Inst{11} = target{18};
3115 let Inst{13} = target{17};
3116 let Inst{21-16} = target{16-11};
3117 let Inst{10-0} = target{10-0};
3120 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3121 def t2BR_JT : t2PseudoInst<(outs),
3122 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3124 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3126 // FIXME: Add a non-pc based case that can be predicated.
3127 def t2TBB_JT : t2PseudoInst<(outs),
3128 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3130 def t2TBH_JT : t2PseudoInst<(outs),
3131 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3133 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3134 "tbb", "\t$addr", []> {
3137 let Inst{31-20} = 0b111010001101;
3138 let Inst{19-16} = Rn;
3139 let Inst{15-5} = 0b11110000000;
3140 let Inst{4} = 0; // B form
3143 let DecoderMethod = "DecodeThumbTableBranch";
3146 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3147 "tbh", "\t$addr", []> {
3150 let Inst{31-20} = 0b111010001101;
3151 let Inst{19-16} = Rn;
3152 let Inst{15-5} = 0b11110000000;
3153 let Inst{4} = 1; // H form
3156 let DecoderMethod = "DecodeThumbTableBranch";
3158 } // isNotDuplicable, isIndirectBranch
3160 } // isBranch, isTerminator, isBarrier
3162 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3163 // a two-value operand where a dag node expects ", "two operands. :(
3164 let isBranch = 1, isTerminator = 1 in
3165 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3167 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3168 let Inst{31-27} = 0b11110;
3169 let Inst{15-14} = 0b10;
3173 let Inst{25-22} = p;
3176 let Inst{26} = target{20};
3177 let Inst{11} = target{19};
3178 let Inst{13} = target{18};
3179 let Inst{21-16} = target{17-12};
3180 let Inst{10-0} = target{11-1};
3182 let DecoderMethod = "DecodeThumb2BCCInstruction";
3185 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3187 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3189 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3191 def tTAILJMPd: tPseudoExpand<(outs),
3192 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3194 (t2B uncondbrtarget:$dst, pred:$p)>,
3195 Requires<[IsThumb2, IsDarwin]>;
3199 let Defs = [ITSTATE] in
3200 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3201 AddrModeNone, 2, IIC_iALUx,
3202 "it$mask\t$cc", "", []> {
3203 // 16-bit instruction.
3204 let Inst{31-16} = 0x0000;
3205 let Inst{15-8} = 0b10111111;
3210 let Inst{3-0} = mask;
3212 let DecoderMethod = "DecodeIT";
3215 // Branch and Exchange Jazelle -- for disassembly only
3217 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3219 let Inst{31-27} = 0b11110;
3221 let Inst{25-20} = 0b111100;
3222 let Inst{19-16} = func;
3223 let Inst{15-0} = 0b1000111100000000;
3226 // Compare and branch on zero / non-zero
3227 let isBranch = 1, isTerminator = 1 in {
3228 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3229 "cbz\t$Rn, $target", []>,
3230 T1Misc<{0,0,?,1,?,?,?}>,
3231 Requires<[IsThumb2]> {
3235 let Inst{9} = target{5};
3236 let Inst{7-3} = target{4-0};
3240 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3241 "cbnz\t$Rn, $target", []>,
3242 T1Misc<{1,0,?,1,?,?,?}>,
3243 Requires<[IsThumb2]> {
3247 let Inst{9} = target{5};
3248 let Inst{7-3} = target{4-0};
3254 // Change Processor State is a system instruction.
3255 // FIXME: Since the asm parser has currently no clean way to handle optional
3256 // operands, create 3 versions of the same instruction. Once there's a clean
3257 // framework to represent optional operands, change this behavior.
3258 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3259 !strconcat("cps", asm_op), []> {
3265 let Inst{31-27} = 0b11110;
3267 let Inst{25-20} = 0b111010;
3268 let Inst{19-16} = 0b1111;
3269 let Inst{15-14} = 0b10;
3271 let Inst{10-9} = imod;
3273 let Inst{7-5} = iflags;
3274 let Inst{4-0} = mode;
3275 let DecoderMethod = "DecodeT2CPSInstruction";
3279 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3280 "$imod.w\t$iflags, $mode">;
3281 let mode = 0, M = 0 in
3282 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3283 "$imod.w\t$iflags">;
3284 let imod = 0, iflags = 0, M = 1 in
3285 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3287 // A6.3.4 Branches and miscellaneous control
3288 // Table A6-14 Change Processor State, and hint instructions
3289 class T2I_hint<bits<8> op7_0, string opc, string asm>
3290 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3291 let Inst{31-20} = 0xf3a;
3292 let Inst{19-16} = 0b1111;
3293 let Inst{15-14} = 0b10;
3295 let Inst{10-8} = 0b000;
3296 let Inst{7-0} = op7_0;
3299 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3300 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3301 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3302 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3303 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3305 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3307 let Inst{31-20} = 0b111100111010;
3308 let Inst{19-16} = 0b1111;
3309 let Inst{15-8} = 0b10000000;
3310 let Inst{7-4} = 0b1111;
3311 let Inst{3-0} = opt;
3314 // Secure Monitor Call is a system instruction.
3315 // Option = Inst{19-16}
3316 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3317 let Inst{31-27} = 0b11110;
3318 let Inst{26-20} = 0b1111111;
3319 let Inst{15-12} = 0b1000;
3322 let Inst{19-16} = opt;
3325 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3326 string opc, string asm, list<dag> pattern>
3327 : T2I<oops, iops, itin, opc, asm, pattern> {
3329 let Inst{31-25} = 0b1110100;
3330 let Inst{24-23} = Op;
3333 let Inst{20-16} = 0b01101;
3334 let Inst{15-5} = 0b11000000000;
3335 let Inst{4-0} = mode{4-0};
3338 // Store Return State is a system instruction.
3339 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3340 "srsdb", "\tsp!, $mode", []>;
3341 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3342 "srsdb","\tsp, $mode", []>;
3343 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3344 "srsia","\tsp!, $mode", []>;
3345 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3346 "srsia","\tsp, $mode", []>;
3348 // Return From Exception is a system instruction.
3349 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3350 string opc, string asm, list<dag> pattern>
3351 : T2I<oops, iops, itin, opc, asm, pattern> {
3352 let Inst{31-20} = op31_20{11-0};
3355 let Inst{19-16} = Rn;
3356 let Inst{15-0} = 0xc000;
3359 def t2RFEDBW : T2RFE<0b111010000011,
3360 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3361 [/* For disassembly only; pattern left blank */]>;
3362 def t2RFEDB : T2RFE<0b111010000001,
3363 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3364 [/* For disassembly only; pattern left blank */]>;
3365 def t2RFEIAW : T2RFE<0b111010011011,
3366 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3367 [/* For disassembly only; pattern left blank */]>;
3368 def t2RFEIA : T2RFE<0b111010011001,
3369 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3370 [/* For disassembly only; pattern left blank */]>;
3372 //===----------------------------------------------------------------------===//
3373 // Non-Instruction Patterns
3376 // 32-bit immediate using movw + movt.
3377 // This is a single pseudo instruction to make it re-materializable.
3378 // FIXME: Remove this when we can do generalized remat.
3379 let isReMaterializable = 1, isMoveImm = 1 in
3380 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3381 [(set rGPR:$dst, (i32 imm:$src))]>,
3382 Requires<[IsThumb, HasV6T2]>;
3384 // Pseudo instruction that combines movw + movt + add pc (if pic).
3385 // It also makes it possible to rematerialize the instructions.
3386 // FIXME: Remove this when we can do generalized remat and when machine licm
3387 // can properly the instructions.
3388 let isReMaterializable = 1 in {
3389 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3391 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3392 Requires<[IsThumb2, UseMovt]>;
3394 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3396 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3397 Requires<[IsThumb2, UseMovt]>;
3400 // ConstantPool, GlobalAddress, and JumpTable
3401 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3402 Requires<[IsThumb2, DontUseMovt]>;
3403 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3404 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3405 Requires<[IsThumb2, UseMovt]>;
3407 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3408 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3410 // Pseudo instruction that combines ldr from constpool and add pc. This should
3411 // be expanded into two instructions late to allow if-conversion and
3413 let canFoldAsLoad = 1, isReMaterializable = 1 in
3414 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3416 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3418 Requires<[IsThumb2]>;
3419 //===----------------------------------------------------------------------===//
3420 // Coprocessor load/store -- for disassembly only
3422 class T2CI<dag oops, dag iops, string opc, string asm>
3423 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3424 let Inst{27-25} = 0b110;
3427 multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
3428 def _OFFSET : T2CI<(outs),
3429 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3430 opc, "\tp$cop, cr$CRd, $addr"> {
3431 let Inst{31-28} = op31_28;
3432 let Inst{24} = 1; // P = 1
3433 let Inst{21} = 0; // W = 0
3434 let Inst{22} = 0; // D = 0
3435 let Inst{20} = load;
3436 let DecoderMethod = "DecodeCopMemInstruction";
3439 def _PRE : T2CI<(outs),
3440 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3441 opc, "\tp$cop, cr$CRd, $addr!"> {
3442 let Inst{31-28} = op31_28;
3443 let Inst{24} = 1; // P = 1
3444 let Inst{21} = 1; // W = 1
3445 let Inst{22} = 0; // D = 0
3446 let Inst{20} = load;
3447 let DecoderMethod = "DecodeCopMemInstruction";
3450 def _POST : T2CI<(outs),
3451 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3452 opc, "\tp$cop, cr$CRd, $addr"> {
3453 let Inst{31-28} = op31_28;
3454 let Inst{24} = 0; // P = 0
3455 let Inst{21} = 1; // W = 1
3456 let Inst{22} = 0; // D = 0
3457 let Inst{20} = load;
3458 let DecoderMethod = "DecodeCopMemInstruction";
3461 def _OPTION : T2CI<(outs),
3462 (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3463 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3464 let Inst{31-28} = op31_28;
3465 let Inst{24} = 0; // P = 0
3466 let Inst{23} = 1; // U = 1
3467 let Inst{21} = 0; // W = 0
3468 let Inst{22} = 0; // D = 0
3469 let Inst{20} = load;
3470 let DecoderMethod = "DecodeCopMemInstruction";
3473 def L_OFFSET : T2CI<(outs),
3474 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3475 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3476 let Inst{31-28} = op31_28;
3477 let Inst{24} = 1; // P = 1
3478 let Inst{21} = 0; // W = 0
3479 let Inst{22} = 1; // D = 1
3480 let Inst{20} = load;
3481 let DecoderMethod = "DecodeCopMemInstruction";
3484 def L_PRE : T2CI<(outs),
3485 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3486 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3487 let Inst{31-28} = op31_28;
3488 let Inst{24} = 1; // P = 1
3489 let Inst{21} = 1; // W = 1
3490 let Inst{22} = 1; // D = 1
3491 let Inst{20} = load;
3492 let DecoderMethod = "DecodeCopMemInstruction";
3495 def L_POST : T2CI<(outs),
3496 (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
3497 postidx_imm8s4:$offset),
3498 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
3499 let Inst{31-28} = op31_28;
3500 let Inst{24} = 0; // P = 0
3501 let Inst{21} = 1; // W = 1
3502 let Inst{22} = 1; // D = 1
3503 let Inst{20} = load;
3504 let DecoderMethod = "DecodeCopMemInstruction";
3507 def L_OPTION : T2CI<(outs),
3508 (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3509 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3510 let Inst{31-28} = op31_28;
3511 let Inst{24} = 0; // P = 0
3512 let Inst{23} = 1; // U = 1
3513 let Inst{21} = 0; // W = 0
3514 let Inst{22} = 1; // D = 1
3515 let Inst{20} = load;
3516 let DecoderMethod = "DecodeCopMemInstruction";
3520 defm t2LDC : T2LdStCop<0b1111, 1, "ldc">;
3521 defm t2STC : T2LdStCop<0b1111, 0, "stc">;
3524 //===----------------------------------------------------------------------===//
3525 // Move between special register and ARM core register -- for disassembly only
3527 // Move to ARM core register from Special Register
3528 def t2MRS : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> {
3530 let Inst{31-12} = 0b11110011111011111000;
3531 let Inst{11-8} = Rd;
3532 let Inst{7-0} = 0b0000;
3535 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS GPR:$Rd, pred:$p)>;
3537 def t2MRSsys:T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> {
3539 let Inst{31-12} = 0b11110011111111111000;
3540 let Inst{11-8} = Rd;
3541 let Inst{7-0} = 0b0000;
3544 // Move from ARM core register to Special Register
3546 // No need to have both system and application versions, the encodings are the
3547 // same and the assembly parser has no way to distinguish between them. The mask
3548 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3549 // the mask with the fields to be accessed in the special register.
3550 def t2MSR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3551 NoItinerary, "msr", "\t$mask, $Rn", []> {
3554 let Inst{31-21} = 0b11110011100;
3555 let Inst{20} = mask{4}; // R Bit
3556 let Inst{19-16} = Rn;
3557 let Inst{15-12} = 0b1000;
3558 let Inst{11-8} = mask{3-0};
3562 //===----------------------------------------------------------------------===//
3563 // Move between coprocessor and ARM core register
3566 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3568 : T2Cop<Op, oops, iops,
3569 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3571 let Inst{27-24} = 0b1110;
3572 let Inst{20} = direction;
3582 let Inst{15-12} = Rt;
3583 let Inst{11-8} = cop;
3584 let Inst{23-21} = opc1;
3585 let Inst{7-5} = opc2;
3586 let Inst{3-0} = CRm;
3587 let Inst{19-16} = CRn;
3590 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3591 list<dag> pattern = []>
3593 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3594 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3595 let Inst{27-24} = 0b1100;
3596 let Inst{23-21} = 0b010;
3597 let Inst{20} = direction;
3605 let Inst{15-12} = Rt;
3606 let Inst{19-16} = Rt2;
3607 let Inst{11-8} = cop;
3608 let Inst{7-4} = opc1;
3609 let Inst{3-0} = CRm;
3612 /* from ARM core register to coprocessor */
3613 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3615 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3616 c_imm:$CRm, imm0_7:$opc2),
3617 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3618 imm:$CRm, imm:$opc2)]>;
3619 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3620 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3621 c_imm:$CRm, imm0_7:$opc2),
3622 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3623 imm:$CRm, imm:$opc2)]>;
3625 /* from coprocessor to ARM core register */
3626 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3627 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3628 c_imm:$CRm, imm0_7:$opc2), []>;
3630 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3631 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3632 c_imm:$CRm, imm0_7:$opc2), []>;
3634 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3635 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3637 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3638 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3641 /* from ARM core register to coprocessor */
3642 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3643 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3645 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3646 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3647 GPR:$Rt2, imm:$CRm)]>;
3648 /* from coprocessor to ARM core register */
3649 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3651 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3653 //===----------------------------------------------------------------------===//
3654 // Other Coprocessor Instructions.
3657 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3658 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3659 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3660 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3661 imm:$CRm, imm:$opc2)]> {
3662 let Inst{27-24} = 0b1110;
3671 let Inst{3-0} = CRm;
3673 let Inst{7-5} = opc2;
3674 let Inst{11-8} = cop;
3675 let Inst{15-12} = CRd;
3676 let Inst{19-16} = CRn;
3677 let Inst{23-20} = opc1;
3680 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3681 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3682 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3683 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3684 imm:$CRm, imm:$opc2)]> {
3685 let Inst{27-24} = 0b1110;
3694 let Inst{3-0} = CRm;
3696 let Inst{7-5} = opc2;
3697 let Inst{11-8} = cop;
3698 let Inst{15-12} = CRd;
3699 let Inst{19-16} = CRn;
3700 let Inst{23-20} = opc1;
3705 //===----------------------------------------------------------------------===//
3706 // Non-Instruction Patterns
3709 // SXT/UXT with no rotate
3710 let AddedComplexity = 16 in {
3711 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3712 Requires<[IsThumb2]>;
3713 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3714 Requires<[IsThumb2]>;
3715 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3716 Requires<[HasT2ExtractPack, IsThumb2]>;
3717 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3718 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3719 Requires<[HasT2ExtractPack, IsThumb2]>;
3720 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3721 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3722 Requires<[HasT2ExtractPack, IsThumb2]>;
3725 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3726 Requires<[IsThumb2]>;
3727 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3728 Requires<[IsThumb2]>;
3729 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3730 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3731 Requires<[HasT2ExtractPack, IsThumb2]>;
3732 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3733 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3734 Requires<[HasT2ExtractPack, IsThumb2]>;
3736 // Atomic load/store patterns
3737 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3738 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3739 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3740 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3741 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3742 (t2LDRBs t2addrmode_so_reg:$addr)>;
3743 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3744 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3745 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3746 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3747 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3748 (t2LDRHs t2addrmode_so_reg:$addr)>;
3749 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3750 (t2LDRi12 t2addrmode_imm12:$addr)>;
3751 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3752 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3753 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3754 (t2LDRs t2addrmode_so_reg:$addr)>;
3755 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3756 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3757 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3758 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3759 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3760 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3761 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3762 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3763 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3764 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3765 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3766 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3767 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3768 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3769 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3770 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3771 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3772 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3775 //===----------------------------------------------------------------------===//
3776 // Assembler aliases
3779 // Aliases for ADC without the ".w" optional width specifier.
3780 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3781 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3782 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3783 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3784 pred:$p, cc_out:$s)>;
3786 // Aliases for SBC without the ".w" optional width specifier.
3787 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3788 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3789 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3790 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3791 pred:$p, cc_out:$s)>;
3793 // Aliases for ADD without the ".w" optional width specifier.
3794 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3795 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3796 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3797 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3798 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3799 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3800 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3801 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3802 pred:$p, cc_out:$s)>;
3804 // Aliases for SUB without the ".w" optional width specifier.
3805 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3806 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3807 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3808 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3809 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3810 (t2SUBrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3811 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3812 (t2SUBrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3813 pred:$p, cc_out:$s)>;
3815 // Alias for compares without the ".w" optional width specifier.
3816 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3817 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3818 def : t2InstAlias<"teq${p} $Rn, $Rm",
3819 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3820 def : t2InstAlias<"tst${p} $Rn, $Rm",
3821 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3824 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3825 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3826 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3828 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3830 def : t2InstAlias<"ldr${p} $Rt, $addr",
3831 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3832 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3833 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3834 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3835 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3836 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3837 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3838 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3839 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3841 def : t2InstAlias<"ldr${p} $Rt, $addr",
3842 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3843 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3844 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3845 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3846 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3847 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3848 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3849 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3850 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3852 // Alias for MVN without the ".w" optional width specifier.
3853 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
3854 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
3855 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
3856 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
3858 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
3859 // shift amount is zero (i.e., unspecified).
3860 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
3861 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3862 Requires<[HasT2ExtractPack, IsThumb2]>;
3863 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
3864 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3865 Requires<[HasT2ExtractPack, IsThumb2]>;
3867 // PUSH/POP aliases for STM/LDM
3868 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3869 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3870 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3871 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3873 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
3874 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3875 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3876 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3879 // Alias for RSB without the ".w" optional width specifier, and with optional
3880 // implied destination register.
3881 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
3882 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3883 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
3884 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3885 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
3886 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3887 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
3888 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
3891 // SSAT/USAT optional shift operand.
3892 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
3893 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3894 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
3895 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3897 // STM w/o the .w suffix.
3898 def : t2InstAlias<"stm${p} $Rn, $regs",
3899 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
3901 // Alias for STR, STRB, and STRH without the ".w" optional
3903 def : t2InstAlias<"str${p} $Rt, $addr",
3904 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3905 def : t2InstAlias<"strb${p} $Rt, $addr",
3906 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3907 def : t2InstAlias<"strh${p} $Rt, $addr",
3908 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3910 def : t2InstAlias<"str${p} $Rt, $addr",
3911 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3912 def : t2InstAlias<"strb${p} $Rt, $addr",
3913 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3914 def : t2InstAlias<"strh${p} $Rt, $addr",
3915 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3917 // Extend instruction optional rotate operand.
3918 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
3919 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3920 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
3921 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3922 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
3923 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3924 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
3925 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3926 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
3927 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3928 def : t2InstAlias<"sxth${p} $Rd, $Rm",
3929 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3931 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
3932 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3933 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
3934 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3935 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
3936 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3937 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
3938 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3939 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
3940 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3941 def : t2InstAlias<"uxth${p} $Rd, $Rm",
3942 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3944 // Extend instruction w/o the ".w" optional width specifier.
3945 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
3946 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3947 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
3948 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3949 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
3950 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3952 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
3953 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3954 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
3955 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3956 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
3957 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;