1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // Shifted operands. No register controlled shifts for Thumb2.
32 // Note: We do not support rrx shifted operands yet.
33 def t2_so_reg : Operand<i32>, // reg imm
34 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
36 let EncoderMethod = "getT2SORegOpValue";
37 let PrintMethod = "printT2SOOperand";
38 let DecoderMethod = "DecodeSORegImmOperand";
39 let ParserMatchClass = ShiftedImmAsmOperand;
40 let MIOperandInfo = (ops rGPR, i32imm);
43 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
44 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
48 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
49 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
50 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
53 // t2_so_imm - Match a 32-bit immediate operand, which is an
54 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
55 // immediate splatted into multiple bytes of the word.
56 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
57 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
58 return ARM_AM::getT2SOImmVal(Imm) != -1;
60 let ParserMatchClass = t2_so_imm_asmoperand;
61 let EncoderMethod = "getT2SOImmOpValue";
62 let DecoderMethod = "DecodeT2SOImm";
65 // t2_so_imm_not - Match an immediate that is a complement
67 def t2_so_imm_not : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
70 }], t2_so_imm_not_XFORM>;
72 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
73 def t2_so_imm_neg : Operand<i32>,
75 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
76 }], t2_so_imm_neg_XFORM>;
78 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
79 def imm0_4095 : Operand<i32>,
81 return Imm >= 0 && Imm < 4096;
84 def imm0_4095_neg : PatLeaf<(i32 imm), [{
85 return (uint32_t)(-N->getZExtValue()) < 4096;
88 def imm0_255_neg : PatLeaf<(i32 imm), [{
89 return (uint32_t)(-N->getZExtValue()) < 255;
92 def imm0_255_not : PatLeaf<(i32 imm), [{
93 return (uint32_t)(~N->getZExtValue()) < 255;
96 def lo5AllOne : PatLeaf<(i32 imm), [{
97 // Returns true if all low 5-bits are 1.
98 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
101 // Define Thumb2 specific addressing modes.
103 // t2addrmode_imm12 := reg + imm12
104 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
105 def t2addrmode_imm12 : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
107 let PrintMethod = "printAddrModeImm12Operand";
108 let EncoderMethod = "getAddrModeImm12OpValue";
109 let DecoderMethod = "DecodeT2AddrModeImm12";
110 let ParserMatchClass = t2addrmode_imm12_asmoperand;
111 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
114 // t2ldrlabel := imm12
115 def t2ldrlabel : Operand<i32> {
116 let EncoderMethod = "getAddrModeImm12OpValue";
120 // ADR instruction labels.
121 def t2adrlabel : Operand<i32> {
122 let EncoderMethod = "getT2AdrLabelOpValue";
126 // t2addrmode_posimm8 := reg + imm8
127 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
128 def t2addrmode_posimm8 : Operand<i32> {
129 let PrintMethod = "printT2AddrModeImm8Operand";
130 let EncoderMethod = "getT2AddrModeImm8OpValue";
131 let DecoderMethod = "DecodeT2AddrModeImm8";
132 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
133 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
136 // t2addrmode_negimm8 := reg - imm8
137 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
138 def t2addrmode_negimm8 : Operand<i32>,
139 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
140 let PrintMethod = "printT2AddrModeImm8Operand";
141 let EncoderMethod = "getT2AddrModeImm8OpValue";
142 let DecoderMethod = "DecodeT2AddrModeImm8";
143 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
144 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
147 // t2addrmode_imm8 := reg +/- imm8
148 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
149 def t2addrmode_imm8 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
151 let PrintMethod = "printT2AddrModeImm8Operand";
152 let EncoderMethod = "getT2AddrModeImm8OpValue";
153 let DecoderMethod = "DecodeT2AddrModeImm8";
154 let ParserMatchClass = MemImm8OffsetAsmOperand;
155 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
158 def t2am_imm8_offset : Operand<i32>,
159 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
160 [], [SDNPWantRoot]> {
161 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
162 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
163 let DecoderMethod = "DecodeT2Imm8";
166 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
167 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
168 def t2addrmode_imm8s4 : Operand<i32> {
169 let PrintMethod = "printT2AddrModeImm8s4Operand";
170 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
171 let DecoderMethod = "DecodeT2AddrModeImm8s4";
172 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
173 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
176 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
177 def t2am_imm8s4_offset : Operand<i32> {
178 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
179 let EncoderMethod = "getT2Imm8s4OpValue";
180 let DecoderMethod = "DecodeT2Imm8S4";
183 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
184 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
185 let Name = "MemImm0_1020s4Offset";
187 def t2addrmode_imm0_1020s4 : Operand<i32> {
188 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
189 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
190 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
191 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
192 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
195 // t2addrmode_so_reg := reg + (reg << imm2)
196 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
197 def t2addrmode_so_reg : Operand<i32>,
198 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
199 let PrintMethod = "printT2AddrModeSoRegOperand";
200 let EncoderMethod = "getT2AddrModeSORegOpValue";
201 let DecoderMethod = "DecodeT2AddrModeSOReg";
202 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
203 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
206 //===----------------------------------------------------------------------===//
207 // Multiclass helpers...
211 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
212 string opc, string asm, list<dag> pattern>
213 : T2I<oops, iops, itin, opc, asm, pattern> {
218 let Inst{26} = imm{11};
219 let Inst{14-12} = imm{10-8};
220 let Inst{7-0} = imm{7-0};
224 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
225 string opc, string asm, list<dag> pattern>
226 : T2sI<oops, iops, itin, opc, asm, pattern> {
232 let Inst{26} = imm{11};
233 let Inst{14-12} = imm{10-8};
234 let Inst{7-0} = imm{7-0};
237 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
238 string opc, string asm, list<dag> pattern>
239 : T2I<oops, iops, itin, opc, asm, pattern> {
243 let Inst{19-16} = Rn;
244 let Inst{26} = imm{11};
245 let Inst{14-12} = imm{10-8};
246 let Inst{7-0} = imm{7-0};
250 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
251 string opc, string asm, list<dag> pattern>
252 : T2I<oops, iops, itin, opc, asm, pattern> {
257 let Inst{3-0} = ShiftedRm{3-0};
258 let Inst{5-4} = ShiftedRm{6-5};
259 let Inst{14-12} = ShiftedRm{11-9};
260 let Inst{7-6} = ShiftedRm{8-7};
263 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
264 string opc, string asm, list<dag> pattern>
265 : T2sI<oops, iops, itin, opc, asm, pattern> {
270 let Inst{3-0} = ShiftedRm{3-0};
271 let Inst{5-4} = ShiftedRm{6-5};
272 let Inst{14-12} = ShiftedRm{11-9};
273 let Inst{7-6} = ShiftedRm{8-7};
276 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
277 string opc, string asm, list<dag> pattern>
278 : T2I<oops, iops, itin, opc, asm, pattern> {
282 let Inst{19-16} = Rn;
283 let Inst{3-0} = ShiftedRm{3-0};
284 let Inst{5-4} = ShiftedRm{6-5};
285 let Inst{14-12} = ShiftedRm{11-9};
286 let Inst{7-6} = ShiftedRm{8-7};
289 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
290 string opc, string asm, list<dag> pattern>
291 : T2I<oops, iops, itin, opc, asm, pattern> {
299 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
300 string opc, string asm, list<dag> pattern>
301 : T2sI<oops, iops, itin, opc, asm, pattern> {
309 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
310 string opc, string asm, list<dag> pattern>
311 : T2I<oops, iops, itin, opc, asm, pattern> {
315 let Inst{19-16} = Rn;
320 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
321 string opc, string asm, list<dag> pattern>
322 : T2I<oops, iops, itin, opc, asm, pattern> {
328 let Inst{19-16} = Rn;
329 let Inst{26} = imm{11};
330 let Inst{14-12} = imm{10-8};
331 let Inst{7-0} = imm{7-0};
334 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
335 string opc, string asm, list<dag> pattern>
336 : T2sI<oops, iops, itin, opc, asm, pattern> {
342 let Inst{19-16} = Rn;
343 let Inst{26} = imm{11};
344 let Inst{14-12} = imm{10-8};
345 let Inst{7-0} = imm{7-0};
348 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
349 string opc, string asm, list<dag> pattern>
350 : T2I<oops, iops, itin, opc, asm, pattern> {
357 let Inst{14-12} = imm{4-2};
358 let Inst{7-6} = imm{1-0};
361 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
362 string opc, string asm, list<dag> pattern>
363 : T2sI<oops, iops, itin, opc, asm, pattern> {
370 let Inst{14-12} = imm{4-2};
371 let Inst{7-6} = imm{1-0};
374 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
375 string opc, string asm, list<dag> pattern>
376 : T2I<oops, iops, itin, opc, asm, pattern> {
382 let Inst{19-16} = Rn;
386 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
387 string opc, string asm, list<dag> pattern>
388 : T2sI<oops, iops, itin, opc, asm, pattern> {
394 let Inst{19-16} = Rn;
398 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
399 string opc, string asm, list<dag> pattern>
400 : T2I<oops, iops, itin, opc, asm, pattern> {
406 let Inst{19-16} = Rn;
407 let Inst{3-0} = ShiftedRm{3-0};
408 let Inst{5-4} = ShiftedRm{6-5};
409 let Inst{14-12} = ShiftedRm{11-9};
410 let Inst{7-6} = ShiftedRm{8-7};
413 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
414 string opc, string asm, list<dag> pattern>
415 : T2sI<oops, iops, itin, opc, asm, pattern> {
421 let Inst{19-16} = Rn;
422 let Inst{3-0} = ShiftedRm{3-0};
423 let Inst{5-4} = ShiftedRm{6-5};
424 let Inst{14-12} = ShiftedRm{11-9};
425 let Inst{7-6} = ShiftedRm{8-7};
428 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
429 string opc, string asm, list<dag> pattern>
430 : T2I<oops, iops, itin, opc, asm, pattern> {
436 let Inst{19-16} = Rn;
437 let Inst{15-12} = Ra;
442 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
443 dag oops, dag iops, InstrItinClass itin,
444 string opc, string asm, list<dag> pattern>
445 : T2I<oops, iops, itin, opc, asm, pattern> {
451 let Inst{31-23} = 0b111110111;
452 let Inst{22-20} = opc22_20;
453 let Inst{19-16} = Rn;
454 let Inst{15-12} = RdLo;
455 let Inst{11-8} = RdHi;
456 let Inst{7-4} = opc7_4;
461 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
462 /// binary operation that produces a value. These are predicable and can be
463 /// changed to modify CPSR.
464 multiclass T2I_bin_irs<bits<4> opcod, string opc,
465 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
466 PatFrag opnode, string baseOpc, bit Commutable = 0,
469 def ri : T2sTwoRegImm<
470 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
471 opc, "\t$Rd, $Rn, $imm",
472 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
473 let Inst{31-27} = 0b11110;
475 let Inst{24-21} = opcod;
479 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
480 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
481 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
482 let isCommutable = Commutable;
483 let Inst{31-27} = 0b11101;
484 let Inst{26-25} = 0b01;
485 let Inst{24-21} = opcod;
486 let Inst{14-12} = 0b000; // imm3
487 let Inst{7-6} = 0b00; // imm2
488 let Inst{5-4} = 0b00; // type
491 def rs : T2sTwoRegShiftedReg<
492 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
493 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
494 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
495 let Inst{31-27} = 0b11101;
496 let Inst{26-25} = 0b01;
497 let Inst{24-21} = opcod;
499 // Assembly aliases for optional destination operand when it's the same
500 // as the source operand.
501 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
502 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
503 t2_so_imm:$imm, pred:$p,
505 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
506 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
509 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
510 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
511 t2_so_reg:$shift, pred:$p,
515 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
516 // the ".w" suffix to indicate that they are wide.
517 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
518 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
519 PatFrag opnode, string baseOpc, bit Commutable = 0> :
520 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
521 // Assembler aliases w/o the ".w" suffix.
522 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
523 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
526 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
527 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
528 t2_so_reg:$shift, pred:$p,
531 // and with the optional destination operand, too.
532 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
533 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
536 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
537 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
538 t2_so_reg:$shift, pred:$p,
542 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
543 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
544 /// it is equivalent to the T2I_bin_irs counterpart.
545 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
547 def ri : T2sTwoRegImm<
548 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
549 opc, ".w\t$Rd, $Rn, $imm",
550 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
551 let Inst{31-27} = 0b11110;
553 let Inst{24-21} = opcod;
557 def rr : T2sThreeReg<
558 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
559 opc, "\t$Rd, $Rn, $Rm",
560 [/* For disassembly only; pattern left blank */]> {
561 let Inst{31-27} = 0b11101;
562 let Inst{26-25} = 0b01;
563 let Inst{24-21} = opcod;
564 let Inst{14-12} = 0b000; // imm3
565 let Inst{7-6} = 0b00; // imm2
566 let Inst{5-4} = 0b00; // type
569 def rs : T2sTwoRegShiftedReg<
570 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
571 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
572 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
573 let Inst{31-27} = 0b11101;
574 let Inst{26-25} = 0b01;
575 let Inst{24-21} = opcod;
579 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
580 /// instruction modifies the CPSR register.
581 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
582 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
583 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
584 PatFrag opnode, bit Commutable = 0> {
586 def ri : T2sTwoRegImm<
587 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
588 opc, ".w\t$Rd, $Rn, $imm",
589 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
590 let Inst{31-27} = 0b11110;
592 let Inst{24-21} = opcod;
596 def rr : T2sThreeReg<
597 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
598 opc, ".w\t$Rd, $Rn, $Rm",
599 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
600 let isCommutable = Commutable;
601 let Inst{31-27} = 0b11101;
602 let Inst{26-25} = 0b01;
603 let Inst{24-21} = opcod;
604 let Inst{14-12} = 0b000; // imm3
605 let Inst{7-6} = 0b00; // imm2
606 let Inst{5-4} = 0b00; // type
609 def rs : T2sTwoRegShiftedReg<
610 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
611 opc, ".w\t$Rd, $Rn, $ShiftedRm",
612 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
613 let Inst{31-27} = 0b11101;
614 let Inst{26-25} = 0b01;
615 let Inst{24-21} = opcod;
620 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
621 /// patterns for a binary operation that produces a value.
622 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
623 bit Commutable = 0> {
625 // The register-immediate version is re-materializable. This is useful
626 // in particular for taking the address of a local.
627 let isReMaterializable = 1 in {
628 def ri : T2sTwoRegImm<
629 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
630 opc, ".w\t$Rd, $Rn, $imm",
631 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
632 let Inst{31-27} = 0b11110;
635 let Inst{23-21} = op23_21;
641 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
642 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
643 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
647 let Inst{31-27} = 0b11110;
648 let Inst{26} = imm{11};
649 let Inst{25-24} = 0b10;
650 let Inst{23-21} = op23_21;
651 let Inst{20} = 0; // The S bit.
652 let Inst{19-16} = Rn;
654 let Inst{14-12} = imm{10-8};
656 let Inst{7-0} = imm{7-0};
659 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
660 opc, ".w\t$Rd, $Rn, $Rm",
661 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
662 let isCommutable = Commutable;
663 let Inst{31-27} = 0b11101;
664 let Inst{26-25} = 0b01;
666 let Inst{23-21} = op23_21;
667 let Inst{14-12} = 0b000; // imm3
668 let Inst{7-6} = 0b00; // imm2
669 let Inst{5-4} = 0b00; // type
672 def rs : T2sTwoRegShiftedReg<
673 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
674 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
675 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
676 let Inst{31-27} = 0b11101;
677 let Inst{26-25} = 0b01;
679 let Inst{23-21} = op23_21;
683 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
684 /// for a binary operation that produces a value and use the carry
685 /// bit. It's not predicable.
686 let Defs = [CPSR], Uses = [CPSR] in {
687 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
688 bit Commutable = 0> {
690 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
691 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
692 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
693 Requires<[IsThumb2]> {
694 let Inst{31-27} = 0b11110;
696 let Inst{24-21} = opcod;
700 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
701 opc, ".w\t$Rd, $Rn, $Rm",
702 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
703 Requires<[IsThumb2]> {
704 let isCommutable = Commutable;
705 let Inst{31-27} = 0b11101;
706 let Inst{26-25} = 0b01;
707 let Inst{24-21} = opcod;
708 let Inst{14-12} = 0b000; // imm3
709 let Inst{7-6} = 0b00; // imm2
710 let Inst{5-4} = 0b00; // type
713 def rs : T2sTwoRegShiftedReg<
714 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
715 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
716 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
717 Requires<[IsThumb2]> {
718 let Inst{31-27} = 0b11101;
719 let Inst{26-25} = 0b01;
720 let Inst{24-21} = opcod;
725 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
726 /// version is not needed since this is only for codegen.
727 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
728 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
730 def ri : T2sTwoRegImm<
731 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
732 opc, ".w\t$Rd, $Rn, $imm",
733 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
734 let Inst{31-27} = 0b11110;
736 let Inst{24-21} = opcod;
740 def rs : T2sTwoRegShiftedReg<
741 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
742 IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
743 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
744 let Inst{31-27} = 0b11101;
745 let Inst{26-25} = 0b01;
746 let Inst{24-21} = opcod;
751 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
752 // rotate operation that produces a value.
753 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
756 def ri : T2sTwoRegShiftImm<
757 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
758 opc, ".w\t$Rd, $Rm, $imm",
759 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
760 let Inst{31-27} = 0b11101;
761 let Inst{26-21} = 0b010010;
762 let Inst{19-16} = 0b1111; // Rn
763 let Inst{5-4} = opcod;
766 def rr : T2sThreeReg<
767 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
768 opc, ".w\t$Rd, $Rn, $Rm",
769 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
770 let Inst{31-27} = 0b11111;
771 let Inst{26-23} = 0b0100;
772 let Inst{22-21} = opcod;
773 let Inst{15-12} = 0b1111;
774 let Inst{7-4} = 0b0000;
777 // Optional destination register
778 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
779 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
782 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
783 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
787 // Assembler aliases w/o the ".w" suffix.
788 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
789 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
792 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
793 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
797 // and with the optional destination operand, too.
798 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
799 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
802 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
803 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
808 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
809 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
810 /// a explicit result, only implicitly set CPSR.
811 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
812 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
813 PatFrag opnode, string baseOpc> {
814 let isCompare = 1, Defs = [CPSR] in {
816 def ri : T2OneRegCmpImm<
817 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
818 opc, ".w\t$Rn, $imm",
819 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
820 let Inst{31-27} = 0b11110;
822 let Inst{24-21} = opcod;
823 let Inst{20} = 1; // The S bit.
825 let Inst{11-8} = 0b1111; // Rd
828 def rr : T2TwoRegCmp<
829 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
831 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
832 let Inst{31-27} = 0b11101;
833 let Inst{26-25} = 0b01;
834 let Inst{24-21} = opcod;
835 let Inst{20} = 1; // The S bit.
836 let Inst{14-12} = 0b000; // imm3
837 let Inst{11-8} = 0b1111; // Rd
838 let Inst{7-6} = 0b00; // imm2
839 let Inst{5-4} = 0b00; // type
842 def rs : T2OneRegCmpShiftedReg<
843 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
844 opc, ".w\t$Rn, $ShiftedRm",
845 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
846 let Inst{31-27} = 0b11101;
847 let Inst{26-25} = 0b01;
848 let Inst{24-21} = opcod;
849 let Inst{20} = 1; // The S bit.
850 let Inst{11-8} = 0b1111; // Rd
854 // Assembler aliases w/o the ".w" suffix.
855 // No alias here for 'rr' version as not all instantiations of this
856 // multiclass want one (CMP in particular, does not).
857 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
858 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
859 t2_so_imm:$imm, pred:$p)>;
860 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
861 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
866 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
867 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
868 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
870 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
871 opc, ".w\t$Rt, $addr",
872 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
875 let Inst{31-25} = 0b1111100;
876 let Inst{24} = signed;
878 let Inst{22-21} = opcod;
879 let Inst{20} = 1; // load
880 let Inst{19-16} = addr{16-13}; // Rn
881 let Inst{15-12} = Rt;
882 let Inst{11-0} = addr{11-0}; // imm
884 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
886 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
889 let Inst{31-27} = 0b11111;
890 let Inst{26-25} = 0b00;
891 let Inst{24} = signed;
893 let Inst{22-21} = opcod;
894 let Inst{20} = 1; // load
895 let Inst{19-16} = addr{12-9}; // Rn
896 let Inst{15-12} = Rt;
898 // Offset: index==TRUE, wback==FALSE
899 let Inst{10} = 1; // The P bit.
900 let Inst{9} = addr{8}; // U
901 let Inst{8} = 0; // The W bit.
902 let Inst{7-0} = addr{7-0}; // imm
904 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
905 opc, ".w\t$Rt, $addr",
906 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
907 let Inst{31-27} = 0b11111;
908 let Inst{26-25} = 0b00;
909 let Inst{24} = signed;
911 let Inst{22-21} = opcod;
912 let Inst{20} = 1; // load
913 let Inst{11-6} = 0b000000;
916 let Inst{15-12} = Rt;
919 let Inst{19-16} = addr{9-6}; // Rn
920 let Inst{3-0} = addr{5-2}; // Rm
921 let Inst{5-4} = addr{1-0}; // imm
923 let DecoderMethod = "DecodeT2LoadShift";
926 // FIXME: Is the pci variant actually needed?
927 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
928 opc, ".w\t$Rt, $addr",
929 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
930 let isReMaterializable = 1;
931 let Inst{31-27} = 0b11111;
932 let Inst{26-25} = 0b00;
933 let Inst{24} = signed;
934 let Inst{23} = ?; // add = (U == '1')
935 let Inst{22-21} = opcod;
936 let Inst{20} = 1; // load
937 let Inst{19-16} = 0b1111; // Rn
940 let Inst{15-12} = Rt{3-0};
941 let Inst{11-0} = addr{11-0};
945 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
946 multiclass T2I_st<bits<2> opcod, string opc,
947 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
949 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
950 opc, ".w\t$Rt, $addr",
951 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
952 let Inst{31-27} = 0b11111;
953 let Inst{26-23} = 0b0001;
954 let Inst{22-21} = opcod;
955 let Inst{20} = 0; // !load
958 let Inst{15-12} = Rt;
961 let addr{12} = 1; // add = TRUE
962 let Inst{19-16} = addr{16-13}; // Rn
963 let Inst{23} = addr{12}; // U
964 let Inst{11-0} = addr{11-0}; // imm
966 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
968 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
969 let Inst{31-27} = 0b11111;
970 let Inst{26-23} = 0b0000;
971 let Inst{22-21} = opcod;
972 let Inst{20} = 0; // !load
974 // Offset: index==TRUE, wback==FALSE
975 let Inst{10} = 1; // The P bit.
976 let Inst{8} = 0; // The W bit.
979 let Inst{15-12} = Rt;
982 let Inst{19-16} = addr{12-9}; // Rn
983 let Inst{9} = addr{8}; // U
984 let Inst{7-0} = addr{7-0}; // imm
986 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
987 opc, ".w\t$Rt, $addr",
988 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
989 let Inst{31-27} = 0b11111;
990 let Inst{26-23} = 0b0000;
991 let Inst{22-21} = opcod;
992 let Inst{20} = 0; // !load
993 let Inst{11-6} = 0b000000;
996 let Inst{15-12} = Rt;
999 let Inst{19-16} = addr{9-6}; // Rn
1000 let Inst{3-0} = addr{5-2}; // Rm
1001 let Inst{5-4} = addr{1-0}; // imm
1005 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1006 /// register and one whose operand is a register rotated by 8/16/24.
1007 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1008 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1009 opc, ".w\t$Rd, $Rm$rot",
1010 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1011 Requires<[IsThumb2]> {
1012 let Inst{31-27} = 0b11111;
1013 let Inst{26-23} = 0b0100;
1014 let Inst{22-20} = opcod;
1015 let Inst{19-16} = 0b1111; // Rn
1016 let Inst{15-12} = 0b1111;
1020 let Inst{5-4} = rot{1-0}; // rotate
1023 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1024 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1025 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1026 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1027 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1028 Requires<[HasT2ExtractPack, IsThumb2]> {
1030 let Inst{31-27} = 0b11111;
1031 let Inst{26-23} = 0b0100;
1032 let Inst{22-20} = opcod;
1033 let Inst{19-16} = 0b1111; // Rn
1034 let Inst{15-12} = 0b1111;
1036 let Inst{5-4} = rot;
1039 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1041 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1042 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1043 opc, "\t$Rd, $Rm$rot", []>,
1044 Requires<[IsThumb2, HasT2ExtractPack]> {
1046 let Inst{31-27} = 0b11111;
1047 let Inst{26-23} = 0b0100;
1048 let Inst{22-20} = opcod;
1049 let Inst{19-16} = 0b1111; // Rn
1050 let Inst{15-12} = 0b1111;
1052 let Inst{5-4} = rot;
1055 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1056 /// register and one whose operand is a register rotated by 8/16/24.
1057 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1058 : T2ThreeReg<(outs rGPR:$Rd),
1059 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1060 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1061 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1062 Requires<[HasT2ExtractPack, IsThumb2]> {
1064 let Inst{31-27} = 0b11111;
1065 let Inst{26-23} = 0b0100;
1066 let Inst{22-20} = opcod;
1067 let Inst{15-12} = 0b1111;
1069 let Inst{5-4} = rot;
1072 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1073 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1074 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1076 let Inst{31-27} = 0b11111;
1077 let Inst{26-23} = 0b0100;
1078 let Inst{22-20} = opcod;
1079 let Inst{15-12} = 0b1111;
1081 let Inst{5-4} = rot;
1084 //===----------------------------------------------------------------------===//
1086 //===----------------------------------------------------------------------===//
1088 //===----------------------------------------------------------------------===//
1089 // Miscellaneous Instructions.
1092 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1093 string asm, list<dag> pattern>
1094 : T2XI<oops, iops, itin, asm, pattern> {
1098 let Inst{11-8} = Rd;
1099 let Inst{26} = label{11};
1100 let Inst{14-12} = label{10-8};
1101 let Inst{7-0} = label{7-0};
1104 // LEApcrel - Load a pc-relative address into a register without offending the
1106 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1107 (ins t2adrlabel:$addr, pred:$p),
1108 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1109 let Inst{31-27} = 0b11110;
1110 let Inst{25-24} = 0b10;
1111 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1114 let Inst{19-16} = 0b1111; // Rn
1119 let Inst{11-8} = Rd;
1120 let Inst{23} = addr{12};
1121 let Inst{21} = addr{12};
1122 let Inst{26} = addr{11};
1123 let Inst{14-12} = addr{10-8};
1124 let Inst{7-0} = addr{7-0};
1126 let DecoderMethod = "DecodeT2Adr";
1129 let neverHasSideEffects = 1, isReMaterializable = 1 in
1130 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1132 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1133 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1138 //===----------------------------------------------------------------------===//
1139 // Load / store Instructions.
1143 let canFoldAsLoad = 1, isReMaterializable = 1 in
1144 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1145 UnOpFrag<(load node:$Src)>>;
1147 // Loads with zero extension
1148 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1149 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1150 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1151 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1153 // Loads with sign extension
1154 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1155 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1156 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1157 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1159 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1161 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1162 (ins t2addrmode_imm8s4:$addr),
1163 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1164 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1166 // zextload i1 -> zextload i8
1167 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1168 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1169 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1170 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1171 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1172 (t2LDRBs t2addrmode_so_reg:$addr)>;
1173 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1174 (t2LDRBpci tconstpool:$addr)>;
1176 // extload -> zextload
1177 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1179 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1180 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1181 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1182 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1183 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1184 (t2LDRBs t2addrmode_so_reg:$addr)>;
1185 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1186 (t2LDRBpci tconstpool:$addr)>;
1188 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1189 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1190 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1191 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1192 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1193 (t2LDRBs t2addrmode_so_reg:$addr)>;
1194 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1195 (t2LDRBpci tconstpool:$addr)>;
1197 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1198 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1199 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1200 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1201 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1202 (t2LDRHs t2addrmode_so_reg:$addr)>;
1203 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1204 (t2LDRHpci tconstpool:$addr)>;
1206 // FIXME: The destination register of the loads and stores can't be PC, but
1207 // can be SP. We need another regclass (similar to rGPR) to represent
1208 // that. Not a pressing issue since these are selected manually,
1213 let mayLoad = 1, neverHasSideEffects = 1 in {
1214 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1215 (ins t2addrmode_imm8:$addr),
1216 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1217 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1219 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1222 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1223 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1224 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1225 "ldr", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1227 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1228 (ins t2addrmode_imm8:$addr),
1229 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1230 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1232 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1234 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1235 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1236 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1237 "ldrb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1239 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1240 (ins t2addrmode_imm8:$addr),
1241 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1242 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1244 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1246 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1247 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1248 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1249 "ldrh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1251 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1252 (ins t2addrmode_imm8:$addr),
1253 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1254 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1256 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1258 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1259 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1260 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1261 "ldrsb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1263 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1264 (ins t2addrmode_imm8:$addr),
1265 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1266 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1268 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1270 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1271 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1272 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1273 "ldrsh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1274 } // mayLoad = 1, neverHasSideEffects = 1
1276 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1277 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1278 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1279 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1280 "\t$Rt, $addr", []> {
1283 let Inst{31-27} = 0b11111;
1284 let Inst{26-25} = 0b00;
1285 let Inst{24} = signed;
1287 let Inst{22-21} = type;
1288 let Inst{20} = 1; // load
1289 let Inst{19-16} = addr{12-9};
1290 let Inst{15-12} = Rt;
1292 let Inst{10-8} = 0b110; // PUW.
1293 let Inst{7-0} = addr{7-0};
1296 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1297 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1298 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1299 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1300 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1303 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1304 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1305 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1306 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1307 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1308 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1311 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1312 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1313 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1314 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1317 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1318 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1319 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1320 "str", "\t$Rt, [$Rn, $addr]!",
1321 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1322 [(set GPRnopc:$Rn_wb,
1323 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1325 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1326 (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1327 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1328 "str", "\t$Rt, $Rn, $offset",
1329 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1330 [(set GPRnopc:$Rn_wb,
1331 (post_store rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
1333 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1334 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1335 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1336 "strh", "\t$Rt, [$Rn, $addr]!",
1337 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1338 [(set GPRnopc:$Rn_wb,
1339 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1341 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1342 (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1343 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1344 "strh", "\t$Rt, $Rn, $offset",
1345 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1346 [(set GPRnopc:$Rn_wb,
1347 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
1349 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1350 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1351 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1352 "strb", "\t$Rt, [$Rn, $addr]!",
1353 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1354 [(set GPRnopc:$Rn_wb,
1355 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1357 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1358 (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1359 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1360 "strb", "\t$Rt, $Rn, $offset",
1361 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1362 [(set GPRnopc:$Rn_wb,
1363 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
1365 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1367 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1368 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1369 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1370 "\t$Rt, $addr", []> {
1371 let Inst{31-27} = 0b11111;
1372 let Inst{26-25} = 0b00;
1373 let Inst{24} = 0; // not signed
1375 let Inst{22-21} = type;
1376 let Inst{20} = 0; // store
1378 let Inst{10-8} = 0b110; // PUW
1382 let Inst{15-12} = Rt;
1383 let Inst{19-16} = addr{12-9};
1384 let Inst{7-0} = addr{7-0};
1387 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1388 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1389 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1391 // ldrd / strd pre / post variants
1392 // For disassembly only.
1394 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1395 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1396 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1397 let AsmMatchConverter = "cvtT2LdrdPre";
1398 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1401 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1402 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1403 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1404 "$addr.base = $wb", []>;
1406 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1407 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1408 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1409 "$addr.base = $wb", []> {
1410 let AsmMatchConverter = "cvtT2StrdPre";
1411 let DecoderMethod = "DecodeT2STRDPreInstruction";
1414 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1415 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1416 t2am_imm8s4_offset:$imm),
1417 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1418 "$addr.base = $wb", []>;
1420 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1421 // data/instruction access. These are for disassembly only.
1422 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1423 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1424 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1426 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1428 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1429 let Inst{31-25} = 0b1111100;
1430 let Inst{24} = instr;
1432 let Inst{21} = write;
1434 let Inst{15-12} = 0b1111;
1437 let addr{12} = 1; // add = TRUE
1438 let Inst{19-16} = addr{16-13}; // Rn
1439 let Inst{23} = addr{12}; // U
1440 let Inst{11-0} = addr{11-0}; // imm12
1443 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1445 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1446 let Inst{31-25} = 0b1111100;
1447 let Inst{24} = instr;
1448 let Inst{23} = 0; // U = 0
1450 let Inst{21} = write;
1452 let Inst{15-12} = 0b1111;
1453 let Inst{11-8} = 0b1100;
1456 let Inst{19-16} = addr{12-9}; // Rn
1457 let Inst{7-0} = addr{7-0}; // imm8
1460 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1462 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1463 let Inst{31-25} = 0b1111100;
1464 let Inst{24} = instr;
1465 let Inst{23} = 0; // add = TRUE for T1
1467 let Inst{21} = write;
1469 let Inst{15-12} = 0b1111;
1470 let Inst{11-6} = 0000000;
1473 let Inst{19-16} = addr{9-6}; // Rn
1474 let Inst{3-0} = addr{5-2}; // Rm
1475 let Inst{5-4} = addr{1-0}; // imm2
1477 let DecoderMethod = "DecodeT2LoadShift";
1481 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1482 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1483 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1485 //===----------------------------------------------------------------------===//
1486 // Load / store multiple Instructions.
1489 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1490 InstrItinClass itin_upd, bit L_bit> {
1492 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1493 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1497 let Inst{31-27} = 0b11101;
1498 let Inst{26-25} = 0b00;
1499 let Inst{24-23} = 0b01; // Increment After
1501 let Inst{21} = 0; // No writeback
1502 let Inst{20} = L_bit;
1503 let Inst{19-16} = Rn;
1505 let Inst{14-0} = regs{14-0};
1508 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1509 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1513 let Inst{31-27} = 0b11101;
1514 let Inst{26-25} = 0b00;
1515 let Inst{24-23} = 0b01; // Increment After
1517 let Inst{21} = 1; // Writeback
1518 let Inst{20} = L_bit;
1519 let Inst{19-16} = Rn;
1521 let Inst{14-0} = regs{14-0};
1524 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1525 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1529 let Inst{31-27} = 0b11101;
1530 let Inst{26-25} = 0b00;
1531 let Inst{24-23} = 0b10; // Decrement Before
1533 let Inst{21} = 0; // No writeback
1534 let Inst{20} = L_bit;
1535 let Inst{19-16} = Rn;
1537 let Inst{14-0} = regs{14-0};
1540 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1541 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1545 let Inst{31-27} = 0b11101;
1546 let Inst{26-25} = 0b00;
1547 let Inst{24-23} = 0b10; // Decrement Before
1549 let Inst{21} = 1; // Writeback
1550 let Inst{20} = L_bit;
1551 let Inst{19-16} = Rn;
1553 let Inst{14-0} = regs{14-0};
1557 let neverHasSideEffects = 1 in {
1559 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1560 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1562 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1563 InstrItinClass itin_upd, bit L_bit> {
1565 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1566 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1570 let Inst{31-27} = 0b11101;
1571 let Inst{26-25} = 0b00;
1572 let Inst{24-23} = 0b01; // Increment After
1574 let Inst{21} = 0; // No writeback
1575 let Inst{20} = L_bit;
1576 let Inst{19-16} = Rn;
1578 let Inst{14} = regs{14};
1580 let Inst{12-0} = regs{12-0};
1583 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1584 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1588 let Inst{31-27} = 0b11101;
1589 let Inst{26-25} = 0b00;
1590 let Inst{24-23} = 0b01; // Increment After
1592 let Inst{21} = 1; // Writeback
1593 let Inst{20} = L_bit;
1594 let Inst{19-16} = Rn;
1596 let Inst{14} = regs{14};
1598 let Inst{12-0} = regs{12-0};
1601 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1602 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1606 let Inst{31-27} = 0b11101;
1607 let Inst{26-25} = 0b00;
1608 let Inst{24-23} = 0b10; // Decrement Before
1610 let Inst{21} = 0; // No writeback
1611 let Inst{20} = L_bit;
1612 let Inst{19-16} = Rn;
1614 let Inst{14} = regs{14};
1616 let Inst{12-0} = regs{12-0};
1619 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1620 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1624 let Inst{31-27} = 0b11101;
1625 let Inst{26-25} = 0b00;
1626 let Inst{24-23} = 0b10; // Decrement Before
1628 let Inst{21} = 1; // Writeback
1629 let Inst{20} = L_bit;
1630 let Inst{19-16} = Rn;
1632 let Inst{14} = regs{14};
1634 let Inst{12-0} = regs{12-0};
1639 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1640 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1642 } // neverHasSideEffects
1645 //===----------------------------------------------------------------------===//
1646 // Move Instructions.
1649 let neverHasSideEffects = 1 in
1650 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1651 "mov", ".w\t$Rd, $Rm", []> {
1652 let Inst{31-27} = 0b11101;
1653 let Inst{26-25} = 0b01;
1654 let Inst{24-21} = 0b0010;
1655 let Inst{19-16} = 0b1111; // Rn
1656 let Inst{14-12} = 0b000;
1657 let Inst{7-4} = 0b0000;
1659 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1661 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1664 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1665 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1666 AddedComplexity = 1 in
1667 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1668 "mov", ".w\t$Rd, $imm",
1669 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1670 let Inst{31-27} = 0b11110;
1672 let Inst{24-21} = 0b0010;
1673 let Inst{19-16} = 0b1111; // Rn
1677 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1678 // Use aliases to get that to play nice here.
1679 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1681 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1684 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1685 pred:$p, zero_reg)>;
1686 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1687 pred:$p, zero_reg)>;
1689 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1690 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1691 "movw", "\t$Rd, $imm",
1692 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1693 let Inst{31-27} = 0b11110;
1695 let Inst{24-21} = 0b0010;
1696 let Inst{20} = 0; // The S bit.
1702 let Inst{11-8} = Rd;
1703 let Inst{19-16} = imm{15-12};
1704 let Inst{26} = imm{11};
1705 let Inst{14-12} = imm{10-8};
1706 let Inst{7-0} = imm{7-0};
1709 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1710 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1712 let Constraints = "$src = $Rd" in {
1713 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1714 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1715 "movt", "\t$Rd, $imm",
1717 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1718 let Inst{31-27} = 0b11110;
1720 let Inst{24-21} = 0b0110;
1721 let Inst{20} = 0; // The S bit.
1727 let Inst{11-8} = Rd;
1728 let Inst{19-16} = imm{15-12};
1729 let Inst{26} = imm{11};
1730 let Inst{14-12} = imm{10-8};
1731 let Inst{7-0} = imm{7-0};
1734 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1735 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1738 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1740 //===----------------------------------------------------------------------===//
1741 // Extend Instructions.
1746 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1747 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1748 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1749 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1750 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1752 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1753 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1754 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1755 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1756 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1758 // TODO: SXT(A){B|H}16
1762 let AddedComplexity = 16 in {
1763 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1764 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1765 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1766 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1767 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1768 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1770 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1771 // The transformation should probably be done as a combiner action
1772 // instead so we can include a check for masking back in the upper
1773 // eight bits of the source into the lower eight bits of the result.
1774 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1775 // (t2UXTB16 rGPR:$Src, 3)>,
1776 // Requires<[HasT2ExtractPack, IsThumb2]>;
1777 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1778 (t2UXTB16 rGPR:$Src, 1)>,
1779 Requires<[HasT2ExtractPack, IsThumb2]>;
1781 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1782 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1783 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1784 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1785 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1788 //===----------------------------------------------------------------------===//
1789 // Arithmetic Instructions.
1792 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1793 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1794 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1795 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1797 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1798 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1799 // CPSR and the implicit def of CPSR is not needed.
1800 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1801 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1802 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1803 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1804 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1805 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1807 let hasPostISelHook = 1 in {
1808 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1809 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1810 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1811 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1815 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1816 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1818 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1819 // CPSR and the implicit def of CPSR is not needed.
1820 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1821 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1823 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1824 // The assume-no-carry-in form uses the negation of the input since add/sub
1825 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1826 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1828 // The AddedComplexity preferences the first variant over the others since
1829 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1830 let AddedComplexity = 1 in
1831 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1832 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1833 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1834 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1835 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1836 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1837 let AddedComplexity = 1 in
1838 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1839 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1840 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1841 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1842 // The with-carry-in form matches bitwise not instead of the negation.
1843 // Effectively, the inverse interpretation of the carry flag already accounts
1844 // for part of the negation.
1845 let AddedComplexity = 1 in
1846 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1847 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1848 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1849 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1851 // Select Bytes -- for disassembly only
1853 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1854 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1855 Requires<[IsThumb2, HasThumb2DSP]> {
1856 let Inst{31-27} = 0b11111;
1857 let Inst{26-24} = 0b010;
1859 let Inst{22-20} = 0b010;
1860 let Inst{15-12} = 0b1111;
1862 let Inst{6-4} = 0b000;
1865 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1866 // And Miscellaneous operations -- for disassembly only
1867 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1868 list<dag> pat = [/* For disassembly only; pattern left blank */],
1869 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1870 string asm = "\t$Rd, $Rn, $Rm">
1871 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1872 Requires<[IsThumb2, HasThumb2DSP]> {
1873 let Inst{31-27} = 0b11111;
1874 let Inst{26-23} = 0b0101;
1875 let Inst{22-20} = op22_20;
1876 let Inst{15-12} = 0b1111;
1877 let Inst{7-4} = op7_4;
1883 let Inst{11-8} = Rd;
1884 let Inst{19-16} = Rn;
1888 // Saturating add/subtract -- for disassembly only
1890 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1891 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1892 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1893 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1894 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1895 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1896 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1897 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1898 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1899 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1900 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1901 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1902 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1903 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1904 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1905 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1906 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1907 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1908 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1909 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1910 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1911 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1913 // Signed/Unsigned add/subtract -- for disassembly only
1915 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1916 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1917 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1918 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1919 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1920 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1921 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1922 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1923 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1924 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1925 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1926 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1928 // Signed/Unsigned halving add/subtract -- for disassembly only
1930 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1931 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1932 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1933 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1934 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1935 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1936 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1937 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1938 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1939 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1940 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1941 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1943 // Helper class for disassembly only
1944 // A6.3.16 & A6.3.17
1945 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1946 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1947 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1948 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1949 let Inst{31-27} = 0b11111;
1950 let Inst{26-24} = 0b011;
1951 let Inst{23} = long;
1952 let Inst{22-20} = op22_20;
1953 let Inst{7-4} = op7_4;
1956 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1957 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1958 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1959 let Inst{31-27} = 0b11111;
1960 let Inst{26-24} = 0b011;
1961 let Inst{23} = long;
1962 let Inst{22-20} = op22_20;
1963 let Inst{7-4} = op7_4;
1966 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1968 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1969 (ins rGPR:$Rn, rGPR:$Rm),
1970 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1971 Requires<[IsThumb2, HasThumb2DSP]> {
1972 let Inst{15-12} = 0b1111;
1974 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1975 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1976 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1977 Requires<[IsThumb2, HasThumb2DSP]>;
1979 // Signed/Unsigned saturate -- for disassembly only
1981 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1982 string opc, string asm, list<dag> pattern>
1983 : T2I<oops, iops, itin, opc, asm, pattern> {
1989 let Inst{11-8} = Rd;
1990 let Inst{19-16} = Rn;
1991 let Inst{4-0} = sat_imm;
1992 let Inst{21} = sh{5};
1993 let Inst{14-12} = sh{4-2};
1994 let Inst{7-6} = sh{1-0};
1998 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1999 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
2000 [/* For disassembly only; pattern left blank */]> {
2001 let Inst{31-27} = 0b11110;
2002 let Inst{25-22} = 0b1100;
2007 def t2SSAT16: T2SatI<
2008 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2009 "ssat16", "\t$Rd, $sat_imm, $Rn",
2010 [/* For disassembly only; pattern left blank */]>,
2011 Requires<[IsThumb2, HasThumb2DSP]> {
2012 let Inst{31-27} = 0b11110;
2013 let Inst{25-22} = 0b1100;
2016 let Inst{21} = 1; // sh = '1'
2017 let Inst{14-12} = 0b000; // imm3 = '000'
2018 let Inst{7-6} = 0b00; // imm2 = '00'
2022 (outs rGPR:$Rd), (ins imm0_31:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2023 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
2024 [/* For disassembly only; pattern left blank */]> {
2025 let Inst{31-27} = 0b11110;
2026 let Inst{25-22} = 0b1110;
2031 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2033 "usat16", "\t$Rd, $sat_imm, $Rn",
2034 [/* For disassembly only; pattern left blank */]>,
2035 Requires<[IsThumb2, HasThumb2DSP]> {
2036 let Inst{31-27} = 0b11110;
2037 let Inst{25-22} = 0b1110;
2040 let Inst{21} = 1; // sh = '1'
2041 let Inst{14-12} = 0b000; // imm3 = '000'
2042 let Inst{7-6} = 0b00; // imm2 = '00'
2045 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2046 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2048 //===----------------------------------------------------------------------===//
2049 // Shift and rotate Instructions.
2052 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2053 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2054 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2055 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2056 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2057 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2058 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2059 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2061 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2062 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2063 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2065 let Uses = [CPSR] in {
2066 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2067 "rrx", "\t$Rd, $Rm",
2068 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2069 let Inst{31-27} = 0b11101;
2070 let Inst{26-25} = 0b01;
2071 let Inst{24-21} = 0b0010;
2072 let Inst{19-16} = 0b1111; // Rn
2073 let Inst{14-12} = 0b000;
2074 let Inst{7-4} = 0b0011;
2078 let isCodeGenOnly = 1, Defs = [CPSR] in {
2079 def t2MOVsrl_flag : T2TwoRegShiftImm<
2080 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2081 "lsrs", ".w\t$Rd, $Rm, #1",
2082 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2083 let Inst{31-27} = 0b11101;
2084 let Inst{26-25} = 0b01;
2085 let Inst{24-21} = 0b0010;
2086 let Inst{20} = 1; // The S bit.
2087 let Inst{19-16} = 0b1111; // Rn
2088 let Inst{5-4} = 0b01; // Shift type.
2089 // Shift amount = Inst{14-12:7-6} = 1.
2090 let Inst{14-12} = 0b000;
2091 let Inst{7-6} = 0b01;
2093 def t2MOVsra_flag : T2TwoRegShiftImm<
2094 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2095 "asrs", ".w\t$Rd, $Rm, #1",
2096 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2097 let Inst{31-27} = 0b11101;
2098 let Inst{26-25} = 0b01;
2099 let Inst{24-21} = 0b0010;
2100 let Inst{20} = 1; // The S bit.
2101 let Inst{19-16} = 0b1111; // Rn
2102 let Inst{5-4} = 0b10; // Shift type.
2103 // Shift amount = Inst{14-12:7-6} = 1.
2104 let Inst{14-12} = 0b000;
2105 let Inst{7-6} = 0b01;
2109 //===----------------------------------------------------------------------===//
2110 // Bitwise Instructions.
2113 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2114 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2115 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2116 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2117 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2118 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2119 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2120 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2121 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2123 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2124 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2125 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2128 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2129 string opc, string asm, list<dag> pattern>
2130 : T2I<oops, iops, itin, opc, asm, pattern> {
2135 let Inst{11-8} = Rd;
2136 let Inst{4-0} = msb{4-0};
2137 let Inst{14-12} = lsb{4-2};
2138 let Inst{7-6} = lsb{1-0};
2141 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2142 string opc, string asm, list<dag> pattern>
2143 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2146 let Inst{19-16} = Rn;
2149 let Constraints = "$src = $Rd" in
2150 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2151 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2152 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2153 let Inst{31-27} = 0b11110;
2154 let Inst{26} = 0; // should be 0.
2156 let Inst{24-20} = 0b10110;
2157 let Inst{19-16} = 0b1111; // Rn
2159 let Inst{5} = 0; // should be 0.
2162 let msb{4-0} = imm{9-5};
2163 let lsb{4-0} = imm{4-0};
2166 def t2SBFX: T2TwoRegBitFI<
2167 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2168 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2169 let Inst{31-27} = 0b11110;
2171 let Inst{24-20} = 0b10100;
2175 def t2UBFX: T2TwoRegBitFI<
2176 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2177 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2178 let Inst{31-27} = 0b11110;
2180 let Inst{24-20} = 0b11100;
2184 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2185 let Constraints = "$src = $Rd" in {
2186 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2187 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2188 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2189 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2190 bf_inv_mask_imm:$imm))]> {
2191 let Inst{31-27} = 0b11110;
2192 let Inst{26} = 0; // should be 0.
2194 let Inst{24-20} = 0b10110;
2196 let Inst{5} = 0; // should be 0.
2199 let msb{4-0} = imm{9-5};
2200 let lsb{4-0} = imm{4-0};
2204 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2205 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2206 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2209 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2210 /// unary operation that produces a value. These are predicable and can be
2211 /// changed to modify CPSR.
2212 multiclass T2I_un_irs<bits<4> opcod, string opc,
2213 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2214 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2216 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2218 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2219 let isAsCheapAsAMove = Cheap;
2220 let isReMaterializable = ReMat;
2221 let Inst{31-27} = 0b11110;
2223 let Inst{24-21} = opcod;
2224 let Inst{19-16} = 0b1111; // Rn
2228 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2229 opc, ".w\t$Rd, $Rm",
2230 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2231 let Inst{31-27} = 0b11101;
2232 let Inst{26-25} = 0b01;
2233 let Inst{24-21} = opcod;
2234 let Inst{19-16} = 0b1111; // Rn
2235 let Inst{14-12} = 0b000; // imm3
2236 let Inst{7-6} = 0b00; // imm2
2237 let Inst{5-4} = 0b00; // type
2240 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2241 opc, ".w\t$Rd, $ShiftedRm",
2242 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2243 let Inst{31-27} = 0b11101;
2244 let Inst{26-25} = 0b01;
2245 let Inst{24-21} = opcod;
2246 let Inst{19-16} = 0b1111; // Rn
2250 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2251 let AddedComplexity = 1 in
2252 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2253 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2254 UnOpFrag<(not node:$Src)>, 1, 1>;
2256 let AddedComplexity = 1 in
2257 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2258 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2260 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2261 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2262 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2263 Requires<[IsThumb2]>;
2265 def : T2Pat<(t2_so_imm_not:$src),
2266 (t2MVNi t2_so_imm_not:$src)>;
2268 //===----------------------------------------------------------------------===//
2269 // Multiply Instructions.
2271 let isCommutable = 1 in
2272 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2273 "mul", "\t$Rd, $Rn, $Rm",
2274 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2275 let Inst{31-27} = 0b11111;
2276 let Inst{26-23} = 0b0110;
2277 let Inst{22-20} = 0b000;
2278 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2279 let Inst{7-4} = 0b0000; // Multiply
2282 def t2MLA: T2FourReg<
2283 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2284 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2285 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2286 let Inst{31-27} = 0b11111;
2287 let Inst{26-23} = 0b0110;
2288 let Inst{22-20} = 0b000;
2289 let Inst{7-4} = 0b0000; // Multiply
2292 def t2MLS: T2FourReg<
2293 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2294 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2295 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2296 let Inst{31-27} = 0b11111;
2297 let Inst{26-23} = 0b0110;
2298 let Inst{22-20} = 0b000;
2299 let Inst{7-4} = 0b0001; // Multiply and Subtract
2302 // Extra precision multiplies with low / high results
2303 let neverHasSideEffects = 1 in {
2304 let isCommutable = 1 in {
2305 def t2SMULL : T2MulLong<0b000, 0b0000,
2306 (outs rGPR:$RdLo, rGPR:$RdHi),
2307 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2308 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2310 def t2UMULL : T2MulLong<0b010, 0b0000,
2311 (outs rGPR:$RdLo, rGPR:$RdHi),
2312 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2313 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2316 // Multiply + accumulate
2317 def t2SMLAL : T2MulLong<0b100, 0b0000,
2318 (outs rGPR:$RdLo, rGPR:$RdHi),
2319 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2320 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2322 def t2UMLAL : T2MulLong<0b110, 0b0000,
2323 (outs rGPR:$RdLo, rGPR:$RdHi),
2324 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2325 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2327 def t2UMAAL : T2MulLong<0b110, 0b0110,
2328 (outs rGPR:$RdLo, rGPR:$RdHi),
2329 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2330 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2331 Requires<[IsThumb2, HasThumb2DSP]>;
2332 } // neverHasSideEffects
2334 // Rounding variants of the below included for disassembly only
2336 // Most significant word multiply
2337 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2338 "smmul", "\t$Rd, $Rn, $Rm",
2339 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2340 Requires<[IsThumb2, HasThumb2DSP]> {
2341 let Inst{31-27} = 0b11111;
2342 let Inst{26-23} = 0b0110;
2343 let Inst{22-20} = 0b101;
2344 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2345 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2348 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2349 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2350 Requires<[IsThumb2, HasThumb2DSP]> {
2351 let Inst{31-27} = 0b11111;
2352 let Inst{26-23} = 0b0110;
2353 let Inst{22-20} = 0b101;
2354 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2355 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2358 def t2SMMLA : T2FourReg<
2359 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2360 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2361 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2362 Requires<[IsThumb2, HasThumb2DSP]> {
2363 let Inst{31-27} = 0b11111;
2364 let Inst{26-23} = 0b0110;
2365 let Inst{22-20} = 0b101;
2366 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2369 def t2SMMLAR: T2FourReg<
2370 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2371 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2372 Requires<[IsThumb2, HasThumb2DSP]> {
2373 let Inst{31-27} = 0b11111;
2374 let Inst{26-23} = 0b0110;
2375 let Inst{22-20} = 0b101;
2376 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2379 def t2SMMLS: T2FourReg<
2380 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2381 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2382 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2383 Requires<[IsThumb2, HasThumb2DSP]> {
2384 let Inst{31-27} = 0b11111;
2385 let Inst{26-23} = 0b0110;
2386 let Inst{22-20} = 0b110;
2387 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2390 def t2SMMLSR:T2FourReg<
2391 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2392 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2393 Requires<[IsThumb2, HasThumb2DSP]> {
2394 let Inst{31-27} = 0b11111;
2395 let Inst{26-23} = 0b0110;
2396 let Inst{22-20} = 0b110;
2397 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2400 multiclass T2I_smul<string opc, PatFrag opnode> {
2401 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2402 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2403 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2404 (sext_inreg rGPR:$Rm, i16)))]>,
2405 Requires<[IsThumb2, HasThumb2DSP]> {
2406 let Inst{31-27} = 0b11111;
2407 let Inst{26-23} = 0b0110;
2408 let Inst{22-20} = 0b001;
2409 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2410 let Inst{7-6} = 0b00;
2411 let Inst{5-4} = 0b00;
2414 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2415 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2416 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2417 (sra rGPR:$Rm, (i32 16))))]>,
2418 Requires<[IsThumb2, HasThumb2DSP]> {
2419 let Inst{31-27} = 0b11111;
2420 let Inst{26-23} = 0b0110;
2421 let Inst{22-20} = 0b001;
2422 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2423 let Inst{7-6} = 0b00;
2424 let Inst{5-4} = 0b01;
2427 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2428 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2429 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2430 (sext_inreg rGPR:$Rm, i16)))]>,
2431 Requires<[IsThumb2, HasThumb2DSP]> {
2432 let Inst{31-27} = 0b11111;
2433 let Inst{26-23} = 0b0110;
2434 let Inst{22-20} = 0b001;
2435 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2436 let Inst{7-6} = 0b00;
2437 let Inst{5-4} = 0b10;
2440 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2441 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2442 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2443 (sra rGPR:$Rm, (i32 16))))]>,
2444 Requires<[IsThumb2, HasThumb2DSP]> {
2445 let Inst{31-27} = 0b11111;
2446 let Inst{26-23} = 0b0110;
2447 let Inst{22-20} = 0b001;
2448 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2449 let Inst{7-6} = 0b00;
2450 let Inst{5-4} = 0b11;
2453 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2454 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2455 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2456 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2457 Requires<[IsThumb2, HasThumb2DSP]> {
2458 let Inst{31-27} = 0b11111;
2459 let Inst{26-23} = 0b0110;
2460 let Inst{22-20} = 0b011;
2461 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2462 let Inst{7-6} = 0b00;
2463 let Inst{5-4} = 0b00;
2466 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2467 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2468 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2469 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2470 Requires<[IsThumb2, HasThumb2DSP]> {
2471 let Inst{31-27} = 0b11111;
2472 let Inst{26-23} = 0b0110;
2473 let Inst{22-20} = 0b011;
2474 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2475 let Inst{7-6} = 0b00;
2476 let Inst{5-4} = 0b01;
2481 multiclass T2I_smla<string opc, PatFrag opnode> {
2483 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2484 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2485 [(set rGPR:$Rd, (add rGPR:$Ra,
2486 (opnode (sext_inreg rGPR:$Rn, i16),
2487 (sext_inreg rGPR:$Rm, i16))))]>,
2488 Requires<[IsThumb2, HasThumb2DSP]> {
2489 let Inst{31-27} = 0b11111;
2490 let Inst{26-23} = 0b0110;
2491 let Inst{22-20} = 0b001;
2492 let Inst{7-6} = 0b00;
2493 let Inst{5-4} = 0b00;
2497 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2498 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2499 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2500 (sra rGPR:$Rm, (i32 16)))))]>,
2501 Requires<[IsThumb2, HasThumb2DSP]> {
2502 let Inst{31-27} = 0b11111;
2503 let Inst{26-23} = 0b0110;
2504 let Inst{22-20} = 0b001;
2505 let Inst{7-6} = 0b00;
2506 let Inst{5-4} = 0b01;
2510 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2511 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2512 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2513 (sext_inreg rGPR:$Rm, i16))))]>,
2514 Requires<[IsThumb2, HasThumb2DSP]> {
2515 let Inst{31-27} = 0b11111;
2516 let Inst{26-23} = 0b0110;
2517 let Inst{22-20} = 0b001;
2518 let Inst{7-6} = 0b00;
2519 let Inst{5-4} = 0b10;
2523 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2524 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2525 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2526 (sra rGPR:$Rm, (i32 16)))))]>,
2527 Requires<[IsThumb2, HasThumb2DSP]> {
2528 let Inst{31-27} = 0b11111;
2529 let Inst{26-23} = 0b0110;
2530 let Inst{22-20} = 0b001;
2531 let Inst{7-6} = 0b00;
2532 let Inst{5-4} = 0b11;
2536 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2537 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2538 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2539 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2540 Requires<[IsThumb2, HasThumb2DSP]> {
2541 let Inst{31-27} = 0b11111;
2542 let Inst{26-23} = 0b0110;
2543 let Inst{22-20} = 0b011;
2544 let Inst{7-6} = 0b00;
2545 let Inst{5-4} = 0b00;
2549 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2550 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2551 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2552 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2553 Requires<[IsThumb2, HasThumb2DSP]> {
2554 let Inst{31-27} = 0b11111;
2555 let Inst{26-23} = 0b0110;
2556 let Inst{22-20} = 0b011;
2557 let Inst{7-6} = 0b00;
2558 let Inst{5-4} = 0b01;
2562 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2563 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2565 // Halfword multiple accumulate long: SMLAL<x><y>
2566 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2567 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2568 [/* For disassembly only; pattern left blank */]>,
2569 Requires<[IsThumb2, HasThumb2DSP]>;
2570 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2571 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2572 [/* For disassembly only; pattern left blank */]>,
2573 Requires<[IsThumb2, HasThumb2DSP]>;
2574 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2575 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2576 [/* For disassembly only; pattern left blank */]>,
2577 Requires<[IsThumb2, HasThumb2DSP]>;
2578 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2579 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2580 [/* For disassembly only; pattern left blank */]>,
2581 Requires<[IsThumb2, HasThumb2DSP]>;
2583 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2584 def t2SMUAD: T2ThreeReg_mac<
2585 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2586 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2587 Requires<[IsThumb2, HasThumb2DSP]> {
2588 let Inst{15-12} = 0b1111;
2590 def t2SMUADX:T2ThreeReg_mac<
2591 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2592 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2593 Requires<[IsThumb2, HasThumb2DSP]> {
2594 let Inst{15-12} = 0b1111;
2596 def t2SMUSD: T2ThreeReg_mac<
2597 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2598 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2599 Requires<[IsThumb2, HasThumb2DSP]> {
2600 let Inst{15-12} = 0b1111;
2602 def t2SMUSDX:T2ThreeReg_mac<
2603 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2604 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2605 Requires<[IsThumb2, HasThumb2DSP]> {
2606 let Inst{15-12} = 0b1111;
2608 def t2SMLAD : T2FourReg_mac<
2609 0, 0b010, 0b0000, (outs rGPR:$Rd),
2610 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2611 "\t$Rd, $Rn, $Rm, $Ra", []>,
2612 Requires<[IsThumb2, HasThumb2DSP]>;
2613 def t2SMLADX : T2FourReg_mac<
2614 0, 0b010, 0b0001, (outs rGPR:$Rd),
2615 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2616 "\t$Rd, $Rn, $Rm, $Ra", []>,
2617 Requires<[IsThumb2, HasThumb2DSP]>;
2618 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2619 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2620 "\t$Rd, $Rn, $Rm, $Ra", []>,
2621 Requires<[IsThumb2, HasThumb2DSP]>;
2622 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2623 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2624 "\t$Rd, $Rn, $Rm, $Ra", []>,
2625 Requires<[IsThumb2, HasThumb2DSP]>;
2626 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2627 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2628 "\t$Ra, $Rd, $Rn, $Rm", []>,
2629 Requires<[IsThumb2, HasThumb2DSP]>;
2630 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2631 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2632 "\t$Ra, $Rd, $Rn, $Rm", []>,
2633 Requires<[IsThumb2, HasThumb2DSP]>;
2634 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2635 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2636 "\t$Ra, $Rd, $Rn, $Rm", []>,
2637 Requires<[IsThumb2, HasThumb2DSP]>;
2638 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2639 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2640 "\t$Ra, $Rd, $Rn, $Rm", []>,
2641 Requires<[IsThumb2, HasThumb2DSP]>;
2643 //===----------------------------------------------------------------------===//
2644 // Division Instructions.
2645 // Signed and unsigned division on v7-M
2647 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2648 "sdiv", "\t$Rd, $Rn, $Rm",
2649 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2650 Requires<[HasDivide, IsThumb2]> {
2651 let Inst{31-27} = 0b11111;
2652 let Inst{26-21} = 0b011100;
2654 let Inst{15-12} = 0b1111;
2655 let Inst{7-4} = 0b1111;
2658 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2659 "udiv", "\t$Rd, $Rn, $Rm",
2660 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2661 Requires<[HasDivide, IsThumb2]> {
2662 let Inst{31-27} = 0b11111;
2663 let Inst{26-21} = 0b011101;
2665 let Inst{15-12} = 0b1111;
2666 let Inst{7-4} = 0b1111;
2669 //===----------------------------------------------------------------------===//
2670 // Misc. Arithmetic Instructions.
2673 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2674 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2675 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2676 let Inst{31-27} = 0b11111;
2677 let Inst{26-22} = 0b01010;
2678 let Inst{21-20} = op1;
2679 let Inst{15-12} = 0b1111;
2680 let Inst{7-6} = 0b10;
2681 let Inst{5-4} = op2;
2685 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2686 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2688 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2689 "rbit", "\t$Rd, $Rm",
2690 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2692 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2693 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2695 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2696 "rev16", ".w\t$Rd, $Rm",
2697 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2699 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2700 "revsh", ".w\t$Rd, $Rm",
2701 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2703 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2704 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2705 (t2REVSH rGPR:$Rm)>;
2707 def t2PKHBT : T2ThreeReg<
2708 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2709 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2710 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2711 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2713 Requires<[HasT2ExtractPack, IsThumb2]> {
2714 let Inst{31-27} = 0b11101;
2715 let Inst{26-25} = 0b01;
2716 let Inst{24-20} = 0b01100;
2717 let Inst{5} = 0; // BT form
2721 let Inst{14-12} = sh{4-2};
2722 let Inst{7-6} = sh{1-0};
2725 // Alternate cases for PKHBT where identities eliminate some nodes.
2726 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2727 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2728 Requires<[HasT2ExtractPack, IsThumb2]>;
2729 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2730 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2731 Requires<[HasT2ExtractPack, IsThumb2]>;
2733 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2734 // will match the pattern below.
2735 def t2PKHTB : T2ThreeReg<
2736 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2737 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2738 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2739 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2741 Requires<[HasT2ExtractPack, IsThumb2]> {
2742 let Inst{31-27} = 0b11101;
2743 let Inst{26-25} = 0b01;
2744 let Inst{24-20} = 0b01100;
2745 let Inst{5} = 1; // TB form
2749 let Inst{14-12} = sh{4-2};
2750 let Inst{7-6} = sh{1-0};
2753 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2754 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2755 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2756 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2757 Requires<[HasT2ExtractPack, IsThumb2]>;
2758 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2759 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2760 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2761 Requires<[HasT2ExtractPack, IsThumb2]>;
2763 //===----------------------------------------------------------------------===//
2764 // Comparison Instructions...
2766 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2767 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2768 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2770 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2771 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2772 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2773 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2774 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2775 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2777 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2778 // Compare-to-zero still works out, just not the relationals
2779 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2780 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2781 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2782 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2783 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2786 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2787 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2789 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2790 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2792 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2793 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2794 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2796 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2797 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2798 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2801 // Conditional moves
2802 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2803 // a two-value operand where a dag node expects two operands. :(
2804 let neverHasSideEffects = 1 in {
2805 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2806 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2808 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2809 RegConstraint<"$false = $Rd">;
2811 let isMoveImm = 1 in
2812 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2813 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2815 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2816 RegConstraint<"$false = $Rd">;
2818 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2819 let isCodeGenOnly = 1 in {
2820 let isMoveImm = 1 in
2821 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2823 "movw", "\t$Rd, $imm", []>,
2824 RegConstraint<"$false = $Rd"> {
2825 let Inst{31-27} = 0b11110;
2827 let Inst{24-21} = 0b0010;
2828 let Inst{20} = 0; // The S bit.
2834 let Inst{11-8} = Rd;
2835 let Inst{19-16} = imm{15-12};
2836 let Inst{26} = imm{11};
2837 let Inst{14-12} = imm{10-8};
2838 let Inst{7-0} = imm{7-0};
2841 let isMoveImm = 1 in
2842 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2843 (ins rGPR:$false, i32imm:$src, pred:$p),
2844 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2846 let isMoveImm = 1 in
2847 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2848 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2849 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2850 imm:$cc, CCR:$ccr))*/]>,
2851 RegConstraint<"$false = $Rd"> {
2852 let Inst{31-27} = 0b11110;
2854 let Inst{24-21} = 0b0011;
2855 let Inst{20} = 0; // The S bit.
2856 let Inst{19-16} = 0b1111; // Rn
2860 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2861 string opc, string asm, list<dag> pattern>
2862 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2863 let Inst{31-27} = 0b11101;
2864 let Inst{26-25} = 0b01;
2865 let Inst{24-21} = 0b0010;
2866 let Inst{20} = 0; // The S bit.
2867 let Inst{19-16} = 0b1111; // Rn
2868 let Inst{5-4} = opcod; // Shift type.
2870 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2871 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2872 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2873 RegConstraint<"$false = $Rd">;
2874 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2875 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2876 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2877 RegConstraint<"$false = $Rd">;
2878 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2879 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2880 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2881 RegConstraint<"$false = $Rd">;
2882 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2883 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2884 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2885 RegConstraint<"$false = $Rd">;
2886 } // isCodeGenOnly = 1
2887 } // neverHasSideEffects
2889 //===----------------------------------------------------------------------===//
2890 // Atomic operations intrinsics
2893 // memory barriers protect the atomic sequences
2894 let hasSideEffects = 1 in {
2895 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2896 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2897 Requires<[IsThumb, HasDB]> {
2899 let Inst{31-4} = 0xf3bf8f5;
2900 let Inst{3-0} = opt;
2904 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2905 "dsb", "\t$opt", []>,
2906 Requires<[IsThumb, HasDB]> {
2908 let Inst{31-4} = 0xf3bf8f4;
2909 let Inst{3-0} = opt;
2912 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2914 []>, Requires<[IsThumb2, HasDB]> {
2916 let Inst{31-4} = 0xf3bf8f6;
2917 let Inst{3-0} = opt;
2920 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2921 InstrItinClass itin, string opc, string asm, string cstr,
2922 list<dag> pattern, bits<4> rt2 = 0b1111>
2923 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2924 let Inst{31-27} = 0b11101;
2925 let Inst{26-20} = 0b0001101;
2926 let Inst{11-8} = rt2;
2927 let Inst{7-6} = 0b01;
2928 let Inst{5-4} = opcod;
2929 let Inst{3-0} = 0b1111;
2933 let Inst{19-16} = addr;
2934 let Inst{15-12} = Rt;
2936 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2937 InstrItinClass itin, string opc, string asm, string cstr,
2938 list<dag> pattern, bits<4> rt2 = 0b1111>
2939 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2940 let Inst{31-27} = 0b11101;
2941 let Inst{26-20} = 0b0001100;
2942 let Inst{11-8} = rt2;
2943 let Inst{7-6} = 0b01;
2944 let Inst{5-4} = opcod;
2950 let Inst{19-16} = addr;
2951 let Inst{15-12} = Rt;
2954 let mayLoad = 1 in {
2955 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2956 AddrModeNone, 4, NoItinerary,
2957 "ldrexb", "\t$Rt, $addr", "", []>;
2958 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2959 AddrModeNone, 4, NoItinerary,
2960 "ldrexh", "\t$Rt, $addr", "", []>;
2961 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
2962 AddrModeNone, 4, NoItinerary,
2963 "ldrex", "\t$Rt, $addr", "", []> {
2966 let Inst{31-27} = 0b11101;
2967 let Inst{26-20} = 0b0000101;
2968 let Inst{19-16} = addr{11-8};
2969 let Inst{15-12} = Rt;
2970 let Inst{11-8} = 0b1111;
2971 let Inst{7-0} = addr{7-0};
2973 let hasExtraDefRegAllocReq = 1 in
2974 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2975 (ins addr_offset_none:$addr),
2976 AddrModeNone, 4, NoItinerary,
2977 "ldrexd", "\t$Rt, $Rt2, $addr", "",
2980 let Inst{11-8} = Rt2;
2984 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2985 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2986 (ins rGPR:$Rt, addr_offset_none:$addr),
2987 AddrModeNone, 4, NoItinerary,
2988 "strexb", "\t$Rd, $Rt, $addr", "", []>;
2989 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2990 (ins rGPR:$Rt, addr_offset_none:$addr),
2991 AddrModeNone, 4, NoItinerary,
2992 "strexh", "\t$Rd, $Rt, $addr", "", []>;
2993 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
2994 t2addrmode_imm0_1020s4:$addr),
2995 AddrModeNone, 4, NoItinerary,
2996 "strex", "\t$Rd, $Rt, $addr", "",
3001 let Inst{31-27} = 0b11101;
3002 let Inst{26-20} = 0b0000100;
3003 let Inst{19-16} = addr{11-8};
3004 let Inst{15-12} = Rt;
3005 let Inst{11-8} = Rd;
3006 let Inst{7-0} = addr{7-0};
3010 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3011 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3012 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3013 AddrModeNone, 4, NoItinerary,
3014 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3017 let Inst{11-8} = Rt2;
3020 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3021 Requires<[IsThumb2, HasV7]> {
3022 let Inst{31-16} = 0xf3bf;
3023 let Inst{15-14} = 0b10;
3026 let Inst{11-8} = 0b1111;
3027 let Inst{7-4} = 0b0010;
3028 let Inst{3-0} = 0b1111;
3031 //===----------------------------------------------------------------------===//
3032 // SJLJ Exception handling intrinsics
3033 // eh_sjlj_setjmp() is an instruction sequence to store the return
3034 // address and save #0 in R0 for the non-longjmp case.
3035 // Since by its nature we may be coming from some other function to get
3036 // here, and we're using the stack frame for the containing function to
3037 // save/restore registers, we can't keep anything live in regs across
3038 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3039 // when we get here from a longjmp(). We force everything out of registers
3040 // except for our own input by listing the relevant registers in Defs. By
3041 // doing so, we also cause the prologue/epilogue code to actively preserve
3042 // all of the callee-saved resgisters, which is exactly what we want.
3043 // $val is a scratch register for our use.
3045 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3046 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
3047 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3048 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3049 AddrModeNone, 0, NoItinerary, "", "",
3050 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3051 Requires<[IsThumb2, HasVFP2]>;
3055 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3056 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3057 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3058 AddrModeNone, 0, NoItinerary, "", "",
3059 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3060 Requires<[IsThumb2, NoVFP]>;
3064 //===----------------------------------------------------------------------===//
3065 // Control-Flow Instructions
3068 // FIXME: remove when we have a way to marking a MI with these properties.
3069 // FIXME: Should pc be an implicit operand like PICADD, etc?
3070 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3071 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3072 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3073 reglist:$regs, variable_ops),
3074 4, IIC_iLoad_mBr, [],
3075 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3076 RegConstraint<"$Rn = $wb">;
3078 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3079 let isPredicable = 1 in
3080 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3082 [(br bb:$target)]> {
3083 let Inst{31-27} = 0b11110;
3084 let Inst{15-14} = 0b10;
3088 let Inst{26} = target{19};
3089 let Inst{11} = target{18};
3090 let Inst{13} = target{17};
3091 let Inst{21-16} = target{16-11};
3092 let Inst{10-0} = target{10-0};
3095 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3096 def t2BR_JT : t2PseudoInst<(outs),
3097 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3099 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3101 // FIXME: Add a non-pc based case that can be predicated.
3102 def t2TBB_JT : t2PseudoInst<(outs),
3103 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3106 def t2TBH_JT : t2PseudoInst<(outs),
3107 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3110 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3111 "tbb", "\t[$Rn, $Rm]", []> {
3114 let Inst{31-20} = 0b111010001101;
3115 let Inst{19-16} = Rn;
3116 let Inst{15-5} = 0b11110000000;
3117 let Inst{4} = 0; // B form
3121 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3122 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3125 let Inst{31-20} = 0b111010001101;
3126 let Inst{19-16} = Rn;
3127 let Inst{15-5} = 0b11110000000;
3128 let Inst{4} = 1; // H form
3131 } // isNotDuplicable, isIndirectBranch
3133 } // isBranch, isTerminator, isBarrier
3135 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3136 // a two-value operand where a dag node expects ", "two operands. :(
3137 let isBranch = 1, isTerminator = 1 in
3138 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3140 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3141 let Inst{31-27} = 0b11110;
3142 let Inst{15-14} = 0b10;
3146 let Inst{25-22} = p;
3149 let Inst{26} = target{20};
3150 let Inst{11} = target{19};
3151 let Inst{13} = target{18};
3152 let Inst{21-16} = target{17-12};
3153 let Inst{10-0} = target{11-1};
3155 let DecoderMethod = "DecodeThumb2BCCInstruction";
3158 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3160 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3162 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3164 def tTAILJMPd: tPseudoExpand<(outs),
3165 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3167 (t2B uncondbrtarget:$dst, pred:$p)>,
3168 Requires<[IsThumb2, IsDarwin]>;
3172 let Defs = [ITSTATE] in
3173 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3174 AddrModeNone, 2, IIC_iALUx,
3175 "it$mask\t$cc", "", []> {
3176 // 16-bit instruction.
3177 let Inst{31-16} = 0x0000;
3178 let Inst{15-8} = 0b10111111;
3183 let Inst{3-0} = mask;
3185 let DecoderMethod = "DecodeIT";
3188 // Branch and Exchange Jazelle -- for disassembly only
3190 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3192 let Inst{31-27} = 0b11110;
3194 let Inst{25-20} = 0b111100;
3195 let Inst{19-16} = func;
3196 let Inst{15-0} = 0b1000111100000000;
3199 // Compare and branch on zero / non-zero
3200 let isBranch = 1, isTerminator = 1 in {
3201 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3202 "cbz\t$Rn, $target", []>,
3203 T1Misc<{0,0,?,1,?,?,?}>,
3204 Requires<[IsThumb2]> {
3208 let Inst{9} = target{5};
3209 let Inst{7-3} = target{4-0};
3213 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3214 "cbnz\t$Rn, $target", []>,
3215 T1Misc<{1,0,?,1,?,?,?}>,
3216 Requires<[IsThumb2]> {
3220 let Inst{9} = target{5};
3221 let Inst{7-3} = target{4-0};
3227 // Change Processor State is a system instruction -- for disassembly and
3229 // FIXME: Since the asm parser has currently no clean way to handle optional
3230 // operands, create 3 versions of the same instruction. Once there's a clean
3231 // framework to represent optional operands, change this behavior.
3232 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3233 !strconcat("cps", asm_op),
3234 [/* For disassembly only; pattern left blank */]> {
3240 let Inst{31-27} = 0b11110;
3242 let Inst{25-20} = 0b111010;
3243 let Inst{19-16} = 0b1111;
3244 let Inst{15-14} = 0b10;
3246 let Inst{10-9} = imod;
3248 let Inst{7-5} = iflags;
3249 let Inst{4-0} = mode;
3250 let DecoderMethod = "DecodeT2CPSInstruction";
3254 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3255 "$imod.w\t$iflags, $mode">;
3256 let mode = 0, M = 0 in
3257 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3258 "$imod.w\t$iflags">;
3259 let imod = 0, iflags = 0, M = 1 in
3260 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3262 // A6.3.4 Branches and miscellaneous control
3263 // Table A6-14 Change Processor State, and hint instructions
3264 // Helper class for disassembly only.
3265 class T2I_hint<bits<8> op7_0, string opc, string asm>
3266 : T2I<(outs), (ins), NoItinerary, opc, asm,
3267 [/* For disassembly only; pattern left blank */]> {
3268 let Inst{31-20} = 0xf3a;
3269 let Inst{19-16} = 0b1111;
3270 let Inst{15-14} = 0b10;
3272 let Inst{10-8} = 0b000;
3273 let Inst{7-0} = op7_0;
3276 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3277 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3278 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3279 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3280 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3282 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3284 let Inst{31-20} = 0b111100111010;
3285 let Inst{19-16} = 0b1111;
3286 let Inst{15-8} = 0b10000000;
3287 let Inst{7-4} = 0b1111;
3288 let Inst{3-0} = opt;
3291 // Secure Monitor Call is a system instruction -- for disassembly only
3292 // Option = Inst{19-16}
3293 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3294 [/* For disassembly only; pattern left blank */]> {
3295 let Inst{31-27} = 0b11110;
3296 let Inst{26-20} = 0b1111111;
3297 let Inst{15-12} = 0b1000;
3300 let Inst{19-16} = opt;
3303 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3304 string opc, string asm, list<dag> pattern>
3305 : T2I<oops, iops, itin, opc, asm, pattern> {
3307 let Inst{31-25} = 0b1110100;
3308 let Inst{24-23} = Op;
3311 let Inst{20-16} = 0b01101;
3312 let Inst{15-5} = 0b11000000000;
3313 let Inst{4-0} = mode{4-0};
3316 // Store Return State is a system instruction.
3317 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3318 "srsdb", "\tsp!, $mode", []>;
3319 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3320 "srsdb","\tsp, $mode", []>;
3321 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3322 "srsia","\tsp!, $mode", []>;
3323 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3324 "srsia","\tsp, $mode", []>;
3326 // Return From Exception is a system instruction.
3327 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3328 string opc, string asm, list<dag> pattern>
3329 : T2I<oops, iops, itin, opc, asm, pattern> {
3330 let Inst{31-20} = op31_20{11-0};
3333 let Inst{19-16} = Rn;
3334 let Inst{15-0} = 0xc000;
3337 def t2RFEDBW : T2RFE<0b111010000011,
3338 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3339 [/* For disassembly only; pattern left blank */]>;
3340 def t2RFEDB : T2RFE<0b111010000001,
3341 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3342 [/* For disassembly only; pattern left blank */]>;
3343 def t2RFEIAW : T2RFE<0b111010011011,
3344 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3345 [/* For disassembly only; pattern left blank */]>;
3346 def t2RFEIA : T2RFE<0b111010011001,
3347 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3348 [/* For disassembly only; pattern left blank */]>;
3350 //===----------------------------------------------------------------------===//
3351 // Non-Instruction Patterns
3354 // 32-bit immediate using movw + movt.
3355 // This is a single pseudo instruction to make it re-materializable.
3356 // FIXME: Remove this when we can do generalized remat.
3357 let isReMaterializable = 1, isMoveImm = 1 in
3358 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3359 [(set rGPR:$dst, (i32 imm:$src))]>,
3360 Requires<[IsThumb, HasV6T2]>;
3362 // Pseudo instruction that combines movw + movt + add pc (if pic).
3363 // It also makes it possible to rematerialize the instructions.
3364 // FIXME: Remove this when we can do generalized remat and when machine licm
3365 // can properly the instructions.
3366 let isReMaterializable = 1 in {
3367 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3369 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3370 Requires<[IsThumb2, UseMovt]>;
3372 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3374 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3375 Requires<[IsThumb2, UseMovt]>;
3378 // ConstantPool, GlobalAddress, and JumpTable
3379 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3380 Requires<[IsThumb2, DontUseMovt]>;
3381 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3382 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3383 Requires<[IsThumb2, UseMovt]>;
3385 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3386 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3388 // Pseudo instruction that combines ldr from constpool and add pc. This should
3389 // be expanded into two instructions late to allow if-conversion and
3391 let canFoldAsLoad = 1, isReMaterializable = 1 in
3392 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3394 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3396 Requires<[IsThumb2]>;
3397 //===----------------------------------------------------------------------===//
3398 // Coprocessor load/store -- for disassembly only
3400 class T2CI<dag oops, dag iops, string opc, string asm>
3401 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3402 let Inst{27-25} = 0b110;
3405 multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
3406 def _OFFSET : T2CI<(outs),
3407 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3408 opc, "\tp$cop, cr$CRd, $addr"> {
3409 let Inst{31-28} = op31_28;
3410 let Inst{24} = 1; // P = 1
3411 let Inst{21} = 0; // W = 0
3412 let Inst{22} = 0; // D = 0
3413 let Inst{20} = load;
3414 let DecoderMethod = "DecodeCopMemInstruction";
3417 def _PRE : T2CI<(outs),
3418 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3419 opc, "\tp$cop, cr$CRd, $addr!"> {
3420 let Inst{31-28} = op31_28;
3421 let Inst{24} = 1; // P = 1
3422 let Inst{21} = 1; // W = 1
3423 let Inst{22} = 0; // D = 0
3424 let Inst{20} = load;
3425 let DecoderMethod = "DecodeCopMemInstruction";
3428 def _POST : T2CI<(outs),
3429 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3430 opc, "\tp$cop, cr$CRd, $addr"> {
3431 let Inst{31-28} = op31_28;
3432 let Inst{24} = 0; // P = 0
3433 let Inst{21} = 1; // W = 1
3434 let Inst{22} = 0; // D = 0
3435 let Inst{20} = load;
3436 let DecoderMethod = "DecodeCopMemInstruction";
3439 def _OPTION : T2CI<(outs),
3440 (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3441 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3442 let Inst{31-28} = op31_28;
3443 let Inst{24} = 0; // P = 0
3444 let Inst{23} = 1; // U = 1
3445 let Inst{21} = 0; // W = 0
3446 let Inst{22} = 0; // D = 0
3447 let Inst{20} = load;
3448 let DecoderMethod = "DecodeCopMemInstruction";
3451 def L_OFFSET : T2CI<(outs),
3452 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3453 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3454 let Inst{31-28} = op31_28;
3455 let Inst{24} = 1; // P = 1
3456 let Inst{21} = 0; // W = 0
3457 let Inst{22} = 1; // D = 1
3458 let Inst{20} = load;
3459 let DecoderMethod = "DecodeCopMemInstruction";
3462 def L_PRE : T2CI<(outs),
3463 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3464 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3465 let Inst{31-28} = op31_28;
3466 let Inst{24} = 1; // P = 1
3467 let Inst{21} = 1; // W = 1
3468 let Inst{22} = 1; // D = 1
3469 let Inst{20} = load;
3470 let DecoderMethod = "DecodeCopMemInstruction";
3473 def L_POST : T2CI<(outs),
3474 (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
3475 postidx_imm8s4:$offset),
3476 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
3477 let Inst{31-28} = op31_28;
3478 let Inst{24} = 0; // P = 0
3479 let Inst{21} = 1; // W = 1
3480 let Inst{22} = 1; // D = 1
3481 let Inst{20} = load;
3482 let DecoderMethod = "DecodeCopMemInstruction";
3485 def L_OPTION : T2CI<(outs),
3486 (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3487 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3488 let Inst{31-28} = op31_28;
3489 let Inst{24} = 0; // P = 0
3490 let Inst{23} = 1; // U = 1
3491 let Inst{21} = 0; // W = 0
3492 let Inst{22} = 1; // D = 1
3493 let Inst{20} = load;
3494 let DecoderMethod = "DecodeCopMemInstruction";
3498 defm t2LDC : T2LdStCop<0b1111, 1, "ldc">;
3499 defm t2STC : T2LdStCop<0b1111, 0, "stc">;
3502 //===----------------------------------------------------------------------===//
3503 // Move between special register and ARM core register -- for disassembly only
3505 // Move to ARM core register from Special Register
3506 def t2MRS : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> {
3508 let Inst{31-12} = 0b11110011111011111000;
3509 let Inst{11-8} = Rd;
3510 let Inst{7-0} = 0b0000;
3513 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS GPR:$Rd, pred:$p)>;
3515 def t2MRSsys:T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> {
3517 let Inst{31-12} = 0b11110011111111111000;
3518 let Inst{11-8} = Rd;
3519 let Inst{7-0} = 0b0000;
3522 // Move from ARM core register to Special Register
3524 // No need to have both system and application versions, the encodings are the
3525 // same and the assembly parser has no way to distinguish between them. The mask
3526 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3527 // the mask with the fields to be accessed in the special register.
3528 def t2MSR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3529 NoItinerary, "msr", "\t$mask, $Rn", []> {
3532 let Inst{31-21} = 0b11110011100;
3533 let Inst{20} = mask{4}; // R Bit
3534 let Inst{19-16} = Rn;
3535 let Inst{15-12} = 0b1000;
3536 let Inst{11-8} = mask{3-0};
3540 //===----------------------------------------------------------------------===//
3541 // Move between coprocessor and ARM core register
3544 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3546 : T2Cop<Op, oops, iops,
3547 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3549 let Inst{27-24} = 0b1110;
3550 let Inst{20} = direction;
3560 let Inst{15-12} = Rt;
3561 let Inst{11-8} = cop;
3562 let Inst{23-21} = opc1;
3563 let Inst{7-5} = opc2;
3564 let Inst{3-0} = CRm;
3565 let Inst{19-16} = CRn;
3568 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3569 list<dag> pattern = []>
3571 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3572 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3573 let Inst{27-24} = 0b1100;
3574 let Inst{23-21} = 0b010;
3575 let Inst{20} = direction;
3583 let Inst{15-12} = Rt;
3584 let Inst{19-16} = Rt2;
3585 let Inst{11-8} = cop;
3586 let Inst{7-4} = opc1;
3587 let Inst{3-0} = CRm;
3590 /* from ARM core register to coprocessor */
3591 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3593 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3594 c_imm:$CRm, imm0_7:$opc2),
3595 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3596 imm:$CRm, imm:$opc2)]>;
3597 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3598 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3599 c_imm:$CRm, imm0_7:$opc2),
3600 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3601 imm:$CRm, imm:$opc2)]>;
3603 /* from coprocessor to ARM core register */
3604 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3605 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3606 c_imm:$CRm, imm0_7:$opc2), []>;
3608 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3609 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3610 c_imm:$CRm, imm0_7:$opc2), []>;
3612 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3613 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3615 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3616 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3619 /* from ARM core register to coprocessor */
3620 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3621 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3623 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3624 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3625 GPR:$Rt2, imm:$CRm)]>;
3626 /* from coprocessor to ARM core register */
3627 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3629 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3631 //===----------------------------------------------------------------------===//
3632 // Other Coprocessor Instructions.
3635 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3636 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3637 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3638 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3639 imm:$CRm, imm:$opc2)]> {
3640 let Inst{27-24} = 0b1110;
3649 let Inst{3-0} = CRm;
3651 let Inst{7-5} = opc2;
3652 let Inst{11-8} = cop;
3653 let Inst{15-12} = CRd;
3654 let Inst{19-16} = CRn;
3655 let Inst{23-20} = opc1;
3658 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3659 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3660 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3661 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3662 imm:$CRm, imm:$opc2)]> {
3663 let Inst{27-24} = 0b1110;
3672 let Inst{3-0} = CRm;
3674 let Inst{7-5} = opc2;
3675 let Inst{11-8} = cop;
3676 let Inst{15-12} = CRd;
3677 let Inst{19-16} = CRn;
3678 let Inst{23-20} = opc1;
3683 //===----------------------------------------------------------------------===//
3684 // Non-Instruction Patterns
3687 // SXT/UXT with no rotate
3688 let AddedComplexity = 16 in {
3689 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3690 Requires<[IsThumb2]>;
3691 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3692 Requires<[IsThumb2]>;
3693 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3694 Requires<[HasT2ExtractPack, IsThumb2]>;
3695 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3696 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3697 Requires<[HasT2ExtractPack, IsThumb2]>;
3698 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3699 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3700 Requires<[HasT2ExtractPack, IsThumb2]>;
3703 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3704 Requires<[IsThumb2]>;
3705 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3706 Requires<[IsThumb2]>;
3707 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3708 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3709 Requires<[HasT2ExtractPack, IsThumb2]>;
3710 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3711 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3712 Requires<[HasT2ExtractPack, IsThumb2]>;
3714 // Atomic load/store patterns
3715 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3716 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3717 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3718 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3719 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3720 (t2LDRBs t2addrmode_so_reg:$addr)>;
3721 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3722 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3723 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3724 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3725 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3726 (t2LDRHs t2addrmode_so_reg:$addr)>;
3727 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3728 (t2LDRi12 t2addrmode_imm12:$addr)>;
3729 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3730 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3731 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3732 (t2LDRs t2addrmode_so_reg:$addr)>;
3733 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3734 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3735 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3736 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3737 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3738 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3739 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3740 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3741 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3742 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3743 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3744 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3745 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3746 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3747 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3748 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3749 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3750 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3753 //===----------------------------------------------------------------------===//
3754 // Assembler aliases
3757 // Aliases for ADC without the ".w" optional width specifier.
3758 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3759 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3760 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3761 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3762 pred:$p, cc_out:$s)>;
3764 // Aliases for SBC without the ".w" optional width specifier.
3765 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3766 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3767 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3768 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3769 pred:$p, cc_out:$s)>;
3771 // Aliases for ADD without the ".w" optional width specifier.
3772 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3773 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3774 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3775 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3776 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3777 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3778 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3779 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3780 pred:$p, cc_out:$s)>;
3782 // Alias for compares without the ".w" optional width specifier.
3783 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3784 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3785 def : t2InstAlias<"teq${p} $Rn, $Rm",
3786 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3787 def : t2InstAlias<"tst${p} $Rn, $Rm",
3788 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3791 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3792 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3793 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3795 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3797 def : t2InstAlias<"ldr${p} $Rt, $addr",
3798 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3799 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3800 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3801 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3802 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3803 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3804 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3805 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3806 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3808 def : t2InstAlias<"ldr${p} $Rt, $addr",
3809 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3810 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3811 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3812 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3813 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3814 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3815 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3816 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3817 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3819 // Alias for MVN without the ".w" optional width specifier.
3820 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
3821 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
3822 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
3823 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
3825 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
3826 // shift amount is zero (i.e., unspecified).
3827 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
3828 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3829 Requires<[HasT2ExtractPack, IsThumb2]>;
3830 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
3831 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3832 Requires<[HasT2ExtractPack, IsThumb2]>;
3834 // PUSH/POP aliases for STM/LDM
3835 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3836 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3837 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3838 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3840 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
3841 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3842 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3843 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3846 // Alias for RSB without the ".w" optional width specifier, and with optional
3847 // implied destination register.
3848 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
3849 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3850 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
3851 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3852 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
3853 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3854 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
3855 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
3858 // SSAT/USAT optional shift operand.
3859 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
3860 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3861 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
3862 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3864 // STM w/o the .w suffix.
3865 def : t2InstAlias<"stm${p} $Rn, $regs",
3866 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;