1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // Shifted operands. No register controlled shifts for Thumb2.
32 // Note: We do not support rrx shifted operands yet.
33 def t2_so_reg : Operand<i32>, // reg imm
34 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
36 let EncoderMethod = "getT2SORegOpValue";
37 let PrintMethod = "printT2SOOperand";
38 let DecoderMethod = "DecodeSORegImmOperand";
39 let ParserMatchClass = ShiftedImmAsmOperand;
40 let MIOperandInfo = (ops rGPR, i32imm);
43 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
44 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
48 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
49 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
50 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
53 // t2_so_imm - Match a 32-bit immediate operand, which is an
54 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
55 // immediate splatted into multiple bytes of the word.
56 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
57 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
58 return ARM_AM::getT2SOImmVal(Imm) != -1;
60 let ParserMatchClass = t2_so_imm_asmoperand;
61 let EncoderMethod = "getT2SOImmOpValue";
62 let DecoderMethod = "DecodeT2SOImm";
65 // t2_so_imm_not - Match an immediate that is a complement
67 def t2_so_imm_not : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
70 }], t2_so_imm_not_XFORM>;
72 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
73 def t2_so_imm_neg : Operand<i32>,
75 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
76 }], t2_so_imm_neg_XFORM>;
78 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
79 def imm0_4095 : Operand<i32>,
81 return Imm >= 0 && Imm < 4096;
84 def imm0_4095_neg : PatLeaf<(i32 imm), [{
85 return (uint32_t)(-N->getZExtValue()) < 4096;
88 def imm0_255_neg : PatLeaf<(i32 imm), [{
89 return (uint32_t)(-N->getZExtValue()) < 255;
92 def imm0_255_not : PatLeaf<(i32 imm), [{
93 return (uint32_t)(~N->getZExtValue()) < 255;
96 def lo5AllOne : PatLeaf<(i32 imm), [{
97 // Returns true if all low 5-bits are 1.
98 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
101 // Define Thumb2 specific addressing modes.
103 // t2addrmode_imm12 := reg + imm12
104 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
105 def t2addrmode_imm12 : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
107 let PrintMethod = "printAddrModeImm12Operand";
108 let EncoderMethod = "getAddrModeImm12OpValue";
109 let DecoderMethod = "DecodeT2AddrModeImm12";
110 let ParserMatchClass = t2addrmode_imm12_asmoperand;
111 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
114 // t2ldrlabel := imm12
115 def t2ldrlabel : Operand<i32> {
116 let EncoderMethod = "getAddrModeImm12OpValue";
120 // ADR instruction labels.
121 def t2adrlabel : Operand<i32> {
122 let EncoderMethod = "getT2AdrLabelOpValue";
126 // t2addrmode_posimm8 := reg + imm8
127 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
128 def t2addrmode_posimm8 : Operand<i32> {
129 let PrintMethod = "printT2AddrModeImm8Operand";
130 let EncoderMethod = "getT2AddrModeImm8OpValue";
131 let DecoderMethod = "DecodeT2AddrModeImm8";
132 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
133 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
136 // t2addrmode_negimm8 := reg - imm8
137 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
138 def t2addrmode_negimm8 : Operand<i32>,
139 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
140 let PrintMethod = "printT2AddrModeImm8Operand";
141 let EncoderMethod = "getT2AddrModeImm8OpValue";
142 let DecoderMethod = "DecodeT2AddrModeImm8";
143 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
144 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
147 // t2addrmode_imm8 := reg +/- imm8
148 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
149 def t2addrmode_imm8 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
151 let PrintMethod = "printT2AddrModeImm8Operand";
152 let EncoderMethod = "getT2AddrModeImm8OpValue";
153 let DecoderMethod = "DecodeT2AddrModeImm8";
154 let ParserMatchClass = MemImm8OffsetAsmOperand;
155 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
158 def t2am_imm8_offset : Operand<i32>,
159 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
160 [], [SDNPWantRoot]> {
161 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
162 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
163 let DecoderMethod = "DecodeT2Imm8";
166 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
167 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
168 def t2addrmode_imm8s4 : Operand<i32> {
169 let PrintMethod = "printT2AddrModeImm8s4Operand";
170 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
171 let DecoderMethod = "DecodeT2AddrModeImm8s4";
172 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
173 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
176 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
177 def t2am_imm8s4_offset : Operand<i32> {
178 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
179 let EncoderMethod = "getT2Imm8s4OpValue";
180 let DecoderMethod = "DecodeT2Imm8S4";
183 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
184 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
185 let Name = "MemImm0_1020s4Offset";
187 def t2addrmode_imm0_1020s4 : Operand<i32> {
188 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
189 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
190 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
191 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
192 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
195 // t2addrmode_so_reg := reg + (reg << imm2)
196 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
197 def t2addrmode_so_reg : Operand<i32>,
198 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
199 let PrintMethod = "printT2AddrModeSoRegOperand";
200 let EncoderMethod = "getT2AddrModeSORegOpValue";
201 let DecoderMethod = "DecodeT2AddrModeSOReg";
202 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
203 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
206 // Addresses for the TBB/TBH instructions.
207 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
208 def addrmode_tbb : Operand<i32> {
209 let PrintMethod = "printAddrModeTBB";
210 let ParserMatchClass = addrmode_tbb_asmoperand;
211 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
213 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
214 def addrmode_tbh : Operand<i32> {
215 let PrintMethod = "printAddrModeTBH";
216 let ParserMatchClass = addrmode_tbh_asmoperand;
217 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
220 //===----------------------------------------------------------------------===//
221 // Multiclass helpers...
225 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
226 string opc, string asm, list<dag> pattern>
227 : T2I<oops, iops, itin, opc, asm, pattern> {
232 let Inst{26} = imm{11};
233 let Inst{14-12} = imm{10-8};
234 let Inst{7-0} = imm{7-0};
238 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
239 string opc, string asm, list<dag> pattern>
240 : T2sI<oops, iops, itin, opc, asm, pattern> {
246 let Inst{26} = imm{11};
247 let Inst{14-12} = imm{10-8};
248 let Inst{7-0} = imm{7-0};
251 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
252 string opc, string asm, list<dag> pattern>
253 : T2I<oops, iops, itin, opc, asm, pattern> {
257 let Inst{19-16} = Rn;
258 let Inst{26} = imm{11};
259 let Inst{14-12} = imm{10-8};
260 let Inst{7-0} = imm{7-0};
264 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
265 string opc, string asm, list<dag> pattern>
266 : T2I<oops, iops, itin, opc, asm, pattern> {
271 let Inst{3-0} = ShiftedRm{3-0};
272 let Inst{5-4} = ShiftedRm{6-5};
273 let Inst{14-12} = ShiftedRm{11-9};
274 let Inst{7-6} = ShiftedRm{8-7};
277 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
278 string opc, string asm, list<dag> pattern>
279 : T2sI<oops, iops, itin, opc, asm, pattern> {
284 let Inst{3-0} = ShiftedRm{3-0};
285 let Inst{5-4} = ShiftedRm{6-5};
286 let Inst{14-12} = ShiftedRm{11-9};
287 let Inst{7-6} = ShiftedRm{8-7};
290 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
291 string opc, string asm, list<dag> pattern>
292 : T2I<oops, iops, itin, opc, asm, pattern> {
296 let Inst{19-16} = Rn;
297 let Inst{3-0} = ShiftedRm{3-0};
298 let Inst{5-4} = ShiftedRm{6-5};
299 let Inst{14-12} = ShiftedRm{11-9};
300 let Inst{7-6} = ShiftedRm{8-7};
303 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
304 string opc, string asm, list<dag> pattern>
305 : T2I<oops, iops, itin, opc, asm, pattern> {
313 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
314 string opc, string asm, list<dag> pattern>
315 : T2sI<oops, iops, itin, opc, asm, pattern> {
323 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
324 string opc, string asm, list<dag> pattern>
325 : T2I<oops, iops, itin, opc, asm, pattern> {
329 let Inst{19-16} = Rn;
334 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
335 string opc, string asm, list<dag> pattern>
336 : T2I<oops, iops, itin, opc, asm, pattern> {
342 let Inst{19-16} = Rn;
343 let Inst{26} = imm{11};
344 let Inst{14-12} = imm{10-8};
345 let Inst{7-0} = imm{7-0};
348 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
349 string opc, string asm, list<dag> pattern>
350 : T2sI<oops, iops, itin, opc, asm, pattern> {
356 let Inst{19-16} = Rn;
357 let Inst{26} = imm{11};
358 let Inst{14-12} = imm{10-8};
359 let Inst{7-0} = imm{7-0};
362 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
363 string opc, string asm, list<dag> pattern>
364 : T2I<oops, iops, itin, opc, asm, pattern> {
371 let Inst{14-12} = imm{4-2};
372 let Inst{7-6} = imm{1-0};
375 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
376 string opc, string asm, list<dag> pattern>
377 : T2sI<oops, iops, itin, opc, asm, pattern> {
384 let Inst{14-12} = imm{4-2};
385 let Inst{7-6} = imm{1-0};
388 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
389 string opc, string asm, list<dag> pattern>
390 : T2I<oops, iops, itin, opc, asm, pattern> {
396 let Inst{19-16} = Rn;
400 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
401 string opc, string asm, list<dag> pattern>
402 : T2sI<oops, iops, itin, opc, asm, pattern> {
408 let Inst{19-16} = Rn;
412 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
413 string opc, string asm, list<dag> pattern>
414 : T2I<oops, iops, itin, opc, asm, pattern> {
420 let Inst{19-16} = Rn;
421 let Inst{3-0} = ShiftedRm{3-0};
422 let Inst{5-4} = ShiftedRm{6-5};
423 let Inst{14-12} = ShiftedRm{11-9};
424 let Inst{7-6} = ShiftedRm{8-7};
427 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
428 string opc, string asm, list<dag> pattern>
429 : T2sI<oops, iops, itin, opc, asm, pattern> {
435 let Inst{19-16} = Rn;
436 let Inst{3-0} = ShiftedRm{3-0};
437 let Inst{5-4} = ShiftedRm{6-5};
438 let Inst{14-12} = ShiftedRm{11-9};
439 let Inst{7-6} = ShiftedRm{8-7};
442 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
443 string opc, string asm, list<dag> pattern>
444 : T2I<oops, iops, itin, opc, asm, pattern> {
450 let Inst{19-16} = Rn;
451 let Inst{15-12} = Ra;
456 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
457 dag oops, dag iops, InstrItinClass itin,
458 string opc, string asm, list<dag> pattern>
459 : T2I<oops, iops, itin, opc, asm, pattern> {
465 let Inst{31-23} = 0b111110111;
466 let Inst{22-20} = opc22_20;
467 let Inst{19-16} = Rn;
468 let Inst{15-12} = RdLo;
469 let Inst{11-8} = RdHi;
470 let Inst{7-4} = opc7_4;
475 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
476 /// binary operation that produces a value. These are predicable and can be
477 /// changed to modify CPSR.
478 multiclass T2I_bin_irs<bits<4> opcod, string opc,
479 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
480 PatFrag opnode, string baseOpc, bit Commutable = 0,
483 def ri : T2sTwoRegImm<
484 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
485 opc, "\t$Rd, $Rn, $imm",
486 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
487 let Inst{31-27} = 0b11110;
489 let Inst{24-21} = opcod;
493 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
494 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
495 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
496 let isCommutable = Commutable;
497 let Inst{31-27} = 0b11101;
498 let Inst{26-25} = 0b01;
499 let Inst{24-21} = opcod;
500 let Inst{14-12} = 0b000; // imm3
501 let Inst{7-6} = 0b00; // imm2
502 let Inst{5-4} = 0b00; // type
505 def rs : T2sTwoRegShiftedReg<
506 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
507 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
508 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
509 let Inst{31-27} = 0b11101;
510 let Inst{26-25} = 0b01;
511 let Inst{24-21} = opcod;
513 // Assembly aliases for optional destination operand when it's the same
514 // as the source operand.
515 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
516 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
517 t2_so_imm:$imm, pred:$p,
519 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
520 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
523 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
524 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
525 t2_so_reg:$shift, pred:$p,
529 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
530 // the ".w" suffix to indicate that they are wide.
531 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
532 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
533 PatFrag opnode, string baseOpc, bit Commutable = 0> :
534 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
535 // Assembler aliases w/o the ".w" suffix.
536 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
537 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
540 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
541 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
542 t2_so_reg:$shift, pred:$p,
545 // and with the optional destination operand, too.
546 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
547 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
550 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
551 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
552 t2_so_reg:$shift, pred:$p,
556 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
557 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
558 /// it is equivalent to the T2I_bin_irs counterpart.
559 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
561 def ri : T2sTwoRegImm<
562 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
563 opc, ".w\t$Rd, $Rn, $imm",
564 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
565 let Inst{31-27} = 0b11110;
567 let Inst{24-21} = opcod;
571 def rr : T2sThreeReg<
572 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
573 opc, "\t$Rd, $Rn, $Rm",
574 [/* For disassembly only; pattern left blank */]> {
575 let Inst{31-27} = 0b11101;
576 let Inst{26-25} = 0b01;
577 let Inst{24-21} = opcod;
578 let Inst{14-12} = 0b000; // imm3
579 let Inst{7-6} = 0b00; // imm2
580 let Inst{5-4} = 0b00; // type
583 def rs : T2sTwoRegShiftedReg<
584 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
585 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
586 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
587 let Inst{31-27} = 0b11101;
588 let Inst{26-25} = 0b01;
589 let Inst{24-21} = opcod;
593 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
594 /// instruction modifies the CPSR register.
595 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
596 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
597 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
598 PatFrag opnode, bit Commutable = 0> {
600 def ri : T2sTwoRegImm<
601 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
602 opc, ".w\t$Rd, $Rn, $imm",
603 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
604 let Inst{31-27} = 0b11110;
606 let Inst{24-21} = opcod;
610 def rr : T2sThreeReg<
611 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
612 opc, ".w\t$Rd, $Rn, $Rm",
613 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
614 let isCommutable = Commutable;
615 let Inst{31-27} = 0b11101;
616 let Inst{26-25} = 0b01;
617 let Inst{24-21} = opcod;
618 let Inst{14-12} = 0b000; // imm3
619 let Inst{7-6} = 0b00; // imm2
620 let Inst{5-4} = 0b00; // type
623 def rs : T2sTwoRegShiftedReg<
624 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
625 opc, ".w\t$Rd, $Rn, $ShiftedRm",
626 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
627 let Inst{31-27} = 0b11101;
628 let Inst{26-25} = 0b01;
629 let Inst{24-21} = opcod;
634 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
635 /// patterns for a binary operation that produces a value.
636 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
637 bit Commutable = 0> {
639 // The register-immediate version is re-materializable. This is useful
640 // in particular for taking the address of a local.
641 let isReMaterializable = 1 in {
642 def ri : T2sTwoRegImm<
643 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
644 opc, ".w\t$Rd, $Rn, $imm",
645 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
646 let Inst{31-27} = 0b11110;
649 let Inst{23-21} = op23_21;
655 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
656 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
657 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
661 let Inst{31-27} = 0b11110;
662 let Inst{26} = imm{11};
663 let Inst{25-24} = 0b10;
664 let Inst{23-21} = op23_21;
665 let Inst{20} = 0; // The S bit.
666 let Inst{19-16} = Rn;
668 let Inst{14-12} = imm{10-8};
670 let Inst{7-0} = imm{7-0};
673 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
674 opc, ".w\t$Rd, $Rn, $Rm",
675 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
676 let isCommutable = Commutable;
677 let Inst{31-27} = 0b11101;
678 let Inst{26-25} = 0b01;
680 let Inst{23-21} = op23_21;
681 let Inst{14-12} = 0b000; // imm3
682 let Inst{7-6} = 0b00; // imm2
683 let Inst{5-4} = 0b00; // type
686 def rs : T2sTwoRegShiftedReg<
687 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
688 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
689 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
690 let Inst{31-27} = 0b11101;
691 let Inst{26-25} = 0b01;
693 let Inst{23-21} = op23_21;
697 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
698 /// for a binary operation that produces a value and use the carry
699 /// bit. It's not predicable.
700 let Defs = [CPSR], Uses = [CPSR] in {
701 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
702 bit Commutable = 0> {
704 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
705 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
706 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
707 Requires<[IsThumb2]> {
708 let Inst{31-27} = 0b11110;
710 let Inst{24-21} = opcod;
714 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
715 opc, ".w\t$Rd, $Rn, $Rm",
716 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
717 Requires<[IsThumb2]> {
718 let isCommutable = Commutable;
719 let Inst{31-27} = 0b11101;
720 let Inst{26-25} = 0b01;
721 let Inst{24-21} = opcod;
722 let Inst{14-12} = 0b000; // imm3
723 let Inst{7-6} = 0b00; // imm2
724 let Inst{5-4} = 0b00; // type
727 def rs : T2sTwoRegShiftedReg<
728 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
729 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
730 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
731 Requires<[IsThumb2]> {
732 let Inst{31-27} = 0b11101;
733 let Inst{26-25} = 0b01;
734 let Inst{24-21} = opcod;
739 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
740 /// version is not needed since this is only for codegen.
741 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
742 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
744 def ri : T2sTwoRegImm<
745 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
746 opc, ".w\t$Rd, $Rn, $imm",
747 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
748 let Inst{31-27} = 0b11110;
750 let Inst{24-21} = opcod;
754 def rs : T2sTwoRegShiftedReg<
755 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
756 IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
757 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
758 let Inst{31-27} = 0b11101;
759 let Inst{26-25} = 0b01;
760 let Inst{24-21} = opcod;
765 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
766 // rotate operation that produces a value.
767 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
770 def ri : T2sTwoRegShiftImm<
771 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
772 opc, ".w\t$Rd, $Rm, $imm",
773 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
774 let Inst{31-27} = 0b11101;
775 let Inst{26-21} = 0b010010;
776 let Inst{19-16} = 0b1111; // Rn
777 let Inst{5-4} = opcod;
780 def rr : T2sThreeReg<
781 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
782 opc, ".w\t$Rd, $Rn, $Rm",
783 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
784 let Inst{31-27} = 0b11111;
785 let Inst{26-23} = 0b0100;
786 let Inst{22-21} = opcod;
787 let Inst{15-12} = 0b1111;
788 let Inst{7-4} = 0b0000;
791 // Optional destination register
792 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
793 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
796 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
797 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
801 // Assembler aliases w/o the ".w" suffix.
802 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
803 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
806 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
807 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
811 // and with the optional destination operand, too.
812 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
813 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
816 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
817 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
822 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
823 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
824 /// a explicit result, only implicitly set CPSR.
825 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
826 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
827 PatFrag opnode, string baseOpc> {
828 let isCompare = 1, Defs = [CPSR] in {
830 def ri : T2OneRegCmpImm<
831 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
832 opc, ".w\t$Rn, $imm",
833 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
834 let Inst{31-27} = 0b11110;
836 let Inst{24-21} = opcod;
837 let Inst{20} = 1; // The S bit.
839 let Inst{11-8} = 0b1111; // Rd
842 def rr : T2TwoRegCmp<
843 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
845 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
846 let Inst{31-27} = 0b11101;
847 let Inst{26-25} = 0b01;
848 let Inst{24-21} = opcod;
849 let Inst{20} = 1; // The S bit.
850 let Inst{14-12} = 0b000; // imm3
851 let Inst{11-8} = 0b1111; // Rd
852 let Inst{7-6} = 0b00; // imm2
853 let Inst{5-4} = 0b00; // type
856 def rs : T2OneRegCmpShiftedReg<
857 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
858 opc, ".w\t$Rn, $ShiftedRm",
859 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
860 let Inst{31-27} = 0b11101;
861 let Inst{26-25} = 0b01;
862 let Inst{24-21} = opcod;
863 let Inst{20} = 1; // The S bit.
864 let Inst{11-8} = 0b1111; // Rd
868 // Assembler aliases w/o the ".w" suffix.
869 // No alias here for 'rr' version as not all instantiations of this
870 // multiclass want one (CMP in particular, does not).
871 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
872 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
873 t2_so_imm:$imm, pred:$p)>;
874 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
875 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
880 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
881 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
882 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
884 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
885 opc, ".w\t$Rt, $addr",
886 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
889 let Inst{31-25} = 0b1111100;
890 let Inst{24} = signed;
892 let Inst{22-21} = opcod;
893 let Inst{20} = 1; // load
894 let Inst{19-16} = addr{16-13}; // Rn
895 let Inst{15-12} = Rt;
896 let Inst{11-0} = addr{11-0}; // imm
898 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
900 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
903 let Inst{31-27} = 0b11111;
904 let Inst{26-25} = 0b00;
905 let Inst{24} = signed;
907 let Inst{22-21} = opcod;
908 let Inst{20} = 1; // load
909 let Inst{19-16} = addr{12-9}; // Rn
910 let Inst{15-12} = Rt;
912 // Offset: index==TRUE, wback==FALSE
913 let Inst{10} = 1; // The P bit.
914 let Inst{9} = addr{8}; // U
915 let Inst{8} = 0; // The W bit.
916 let Inst{7-0} = addr{7-0}; // imm
918 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
919 opc, ".w\t$Rt, $addr",
920 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
921 let Inst{31-27} = 0b11111;
922 let Inst{26-25} = 0b00;
923 let Inst{24} = signed;
925 let Inst{22-21} = opcod;
926 let Inst{20} = 1; // load
927 let Inst{11-6} = 0b000000;
930 let Inst{15-12} = Rt;
933 let Inst{19-16} = addr{9-6}; // Rn
934 let Inst{3-0} = addr{5-2}; // Rm
935 let Inst{5-4} = addr{1-0}; // imm
937 let DecoderMethod = "DecodeT2LoadShift";
940 // FIXME: Is the pci variant actually needed?
941 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
942 opc, ".w\t$Rt, $addr",
943 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
944 let isReMaterializable = 1;
945 let Inst{31-27} = 0b11111;
946 let Inst{26-25} = 0b00;
947 let Inst{24} = signed;
948 let Inst{23} = ?; // add = (U == '1')
949 let Inst{22-21} = opcod;
950 let Inst{20} = 1; // load
951 let Inst{19-16} = 0b1111; // Rn
954 let Inst{15-12} = Rt{3-0};
955 let Inst{11-0} = addr{11-0};
959 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
960 multiclass T2I_st<bits<2> opcod, string opc,
961 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
963 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
964 opc, ".w\t$Rt, $addr",
965 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
966 let Inst{31-27} = 0b11111;
967 let Inst{26-23} = 0b0001;
968 let Inst{22-21} = opcod;
969 let Inst{20} = 0; // !load
972 let Inst{15-12} = Rt;
975 let addr{12} = 1; // add = TRUE
976 let Inst{19-16} = addr{16-13}; // Rn
977 let Inst{23} = addr{12}; // U
978 let Inst{11-0} = addr{11-0}; // imm
980 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
982 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
983 let Inst{31-27} = 0b11111;
984 let Inst{26-23} = 0b0000;
985 let Inst{22-21} = opcod;
986 let Inst{20} = 0; // !load
988 // Offset: index==TRUE, wback==FALSE
989 let Inst{10} = 1; // The P bit.
990 let Inst{8} = 0; // The W bit.
993 let Inst{15-12} = Rt;
996 let Inst{19-16} = addr{12-9}; // Rn
997 let Inst{9} = addr{8}; // U
998 let Inst{7-0} = addr{7-0}; // imm
1000 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1001 opc, ".w\t$Rt, $addr",
1002 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1003 let Inst{31-27} = 0b11111;
1004 let Inst{26-23} = 0b0000;
1005 let Inst{22-21} = opcod;
1006 let Inst{20} = 0; // !load
1007 let Inst{11-6} = 0b000000;
1010 let Inst{15-12} = Rt;
1013 let Inst{19-16} = addr{9-6}; // Rn
1014 let Inst{3-0} = addr{5-2}; // Rm
1015 let Inst{5-4} = addr{1-0}; // imm
1019 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1020 /// register and one whose operand is a register rotated by 8/16/24.
1021 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1022 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1023 opc, ".w\t$Rd, $Rm$rot",
1024 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1025 Requires<[IsThumb2]> {
1026 let Inst{31-27} = 0b11111;
1027 let Inst{26-23} = 0b0100;
1028 let Inst{22-20} = opcod;
1029 let Inst{19-16} = 0b1111; // Rn
1030 let Inst{15-12} = 0b1111;
1034 let Inst{5-4} = rot{1-0}; // rotate
1037 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1038 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1039 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1040 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1041 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1042 Requires<[HasT2ExtractPack, IsThumb2]> {
1044 let Inst{31-27} = 0b11111;
1045 let Inst{26-23} = 0b0100;
1046 let Inst{22-20} = opcod;
1047 let Inst{19-16} = 0b1111; // Rn
1048 let Inst{15-12} = 0b1111;
1050 let Inst{5-4} = rot;
1053 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1055 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1056 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1057 opc, "\t$Rd, $Rm$rot", []>,
1058 Requires<[IsThumb2, HasT2ExtractPack]> {
1060 let Inst{31-27} = 0b11111;
1061 let Inst{26-23} = 0b0100;
1062 let Inst{22-20} = opcod;
1063 let Inst{19-16} = 0b1111; // Rn
1064 let Inst{15-12} = 0b1111;
1066 let Inst{5-4} = rot;
1069 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1070 /// register and one whose operand is a register rotated by 8/16/24.
1071 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1072 : T2ThreeReg<(outs rGPR:$Rd),
1073 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1074 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1075 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1076 Requires<[HasT2ExtractPack, IsThumb2]> {
1078 let Inst{31-27} = 0b11111;
1079 let Inst{26-23} = 0b0100;
1080 let Inst{22-20} = opcod;
1081 let Inst{15-12} = 0b1111;
1083 let Inst{5-4} = rot;
1086 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1087 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1088 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1090 let Inst{31-27} = 0b11111;
1091 let Inst{26-23} = 0b0100;
1092 let Inst{22-20} = opcod;
1093 let Inst{15-12} = 0b1111;
1095 let Inst{5-4} = rot;
1098 //===----------------------------------------------------------------------===//
1100 //===----------------------------------------------------------------------===//
1102 //===----------------------------------------------------------------------===//
1103 // Miscellaneous Instructions.
1106 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1107 string asm, list<dag> pattern>
1108 : T2XI<oops, iops, itin, asm, pattern> {
1112 let Inst{11-8} = Rd;
1113 let Inst{26} = label{11};
1114 let Inst{14-12} = label{10-8};
1115 let Inst{7-0} = label{7-0};
1118 // LEApcrel - Load a pc-relative address into a register without offending the
1120 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1121 (ins t2adrlabel:$addr, pred:$p),
1122 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1123 let Inst{31-27} = 0b11110;
1124 let Inst{25-24} = 0b10;
1125 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1128 let Inst{19-16} = 0b1111; // Rn
1133 let Inst{11-8} = Rd;
1134 let Inst{23} = addr{12};
1135 let Inst{21} = addr{12};
1136 let Inst{26} = addr{11};
1137 let Inst{14-12} = addr{10-8};
1138 let Inst{7-0} = addr{7-0};
1140 let DecoderMethod = "DecodeT2Adr";
1143 let neverHasSideEffects = 1, isReMaterializable = 1 in
1144 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1146 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1147 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1152 //===----------------------------------------------------------------------===//
1153 // Load / store Instructions.
1157 let canFoldAsLoad = 1, isReMaterializable = 1 in
1158 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1159 UnOpFrag<(load node:$Src)>>;
1161 // Loads with zero extension
1162 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1163 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1164 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1165 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1167 // Loads with sign extension
1168 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1169 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1170 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1171 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1173 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1175 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1176 (ins t2addrmode_imm8s4:$addr),
1177 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1178 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1180 // zextload i1 -> zextload i8
1181 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1182 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1183 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1184 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1185 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1186 (t2LDRBs t2addrmode_so_reg:$addr)>;
1187 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1188 (t2LDRBpci tconstpool:$addr)>;
1190 // extload -> zextload
1191 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1193 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1194 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1195 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1196 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1197 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1198 (t2LDRBs t2addrmode_so_reg:$addr)>;
1199 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1200 (t2LDRBpci tconstpool:$addr)>;
1202 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1203 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1204 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1205 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1206 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1207 (t2LDRBs t2addrmode_so_reg:$addr)>;
1208 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1209 (t2LDRBpci tconstpool:$addr)>;
1211 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1212 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1213 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1214 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1215 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1216 (t2LDRHs t2addrmode_so_reg:$addr)>;
1217 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1218 (t2LDRHpci tconstpool:$addr)>;
1220 // FIXME: The destination register of the loads and stores can't be PC, but
1221 // can be SP. We need another regclass (similar to rGPR) to represent
1222 // that. Not a pressing issue since these are selected manually,
1227 let mayLoad = 1, neverHasSideEffects = 1 in {
1228 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1229 (ins t2addrmode_imm8:$addr),
1230 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1231 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1233 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1236 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1237 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1238 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1239 "ldr", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1241 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1242 (ins t2addrmode_imm8:$addr),
1243 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1244 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1246 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1248 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1249 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1250 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1251 "ldrb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1253 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1254 (ins t2addrmode_imm8:$addr),
1255 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1256 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1258 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1260 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1261 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1262 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1263 "ldrh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1265 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1266 (ins t2addrmode_imm8:$addr),
1267 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1268 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1270 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1272 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1273 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1274 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1275 "ldrsb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1277 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1278 (ins t2addrmode_imm8:$addr),
1279 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1280 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1282 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1284 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1285 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1286 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1287 "ldrsh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1288 } // mayLoad = 1, neverHasSideEffects = 1
1290 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1291 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1292 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1293 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1294 "\t$Rt, $addr", []> {
1297 let Inst{31-27} = 0b11111;
1298 let Inst{26-25} = 0b00;
1299 let Inst{24} = signed;
1301 let Inst{22-21} = type;
1302 let Inst{20} = 1; // load
1303 let Inst{19-16} = addr{12-9};
1304 let Inst{15-12} = Rt;
1306 let Inst{10-8} = 0b110; // PUW.
1307 let Inst{7-0} = addr{7-0};
1310 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1311 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1312 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1313 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1314 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1317 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1318 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1319 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1320 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1321 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1322 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1325 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1326 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1327 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1328 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1331 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1332 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1333 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1334 "str", "\t$Rt, $addr!",
1335 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1336 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1338 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1339 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1340 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1341 "strh", "\t$Rt, $addr!",
1342 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1343 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1346 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1347 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1348 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1349 "strb", "\t$Rt, $addr!",
1350 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1351 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1354 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1355 (ins rGPR:$Rt, addr_offset_none:$Rn,
1356 t2am_imm8_offset:$offset),
1357 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1358 "str", "\t$Rt, $Rn, $offset",
1359 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1360 [(set GPRnopc:$Rn_wb,
1361 (post_store rGPR:$Rt, addr_offset_none:$Rn,
1362 t2am_imm8_offset:$offset))]>;
1364 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1365 (ins rGPR:$Rt, addr_offset_none:$Rn,
1366 t2am_imm8_offset:$offset),
1367 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1368 "strh", "\t$Rt, $Rn, $offset",
1369 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1370 [(set GPRnopc:$Rn_wb,
1371 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1372 t2am_imm8_offset:$offset))]>;
1374 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1375 (ins rGPR:$Rt, addr_offset_none:$Rn,
1376 t2am_imm8_offset:$offset),
1377 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1378 "strb", "\t$Rt, $Rn, $offset",
1379 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1380 [(set GPRnopc:$Rn_wb,
1381 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1382 t2am_imm8_offset:$offset))]>;
1384 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1385 // put the patterns on the instruction definitions directly as ISel wants
1386 // the address base and offset to be separate operands, not a single
1387 // complex operand like we represent the instructions themselves. The
1388 // pseudos map between the two.
1389 let usesCustomInserter = 1,
1390 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1391 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1392 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1394 [(set GPRnopc:$Rn_wb,
1395 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1396 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1397 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1399 [(set GPRnopc:$Rn_wb,
1400 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1401 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1402 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1404 [(set GPRnopc:$Rn_wb,
1405 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1409 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1411 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1412 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1413 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1414 "\t$Rt, $addr", []> {
1415 let Inst{31-27} = 0b11111;
1416 let Inst{26-25} = 0b00;
1417 let Inst{24} = 0; // not signed
1419 let Inst{22-21} = type;
1420 let Inst{20} = 0; // store
1422 let Inst{10-8} = 0b110; // PUW
1426 let Inst{15-12} = Rt;
1427 let Inst{19-16} = addr{12-9};
1428 let Inst{7-0} = addr{7-0};
1431 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1432 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1433 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1435 // ldrd / strd pre / post variants
1436 // For disassembly only.
1438 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1439 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1440 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1441 let AsmMatchConverter = "cvtT2LdrdPre";
1442 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1445 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1446 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1447 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1448 "$addr.base = $wb", []>;
1450 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1451 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1452 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1453 "$addr.base = $wb", []> {
1454 let AsmMatchConverter = "cvtT2StrdPre";
1455 let DecoderMethod = "DecodeT2STRDPreInstruction";
1458 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1459 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1460 t2am_imm8s4_offset:$imm),
1461 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1462 "$addr.base = $wb", []>;
1464 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1465 // data/instruction access. These are for disassembly only.
1466 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1467 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1468 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1470 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1472 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1473 let Inst{31-25} = 0b1111100;
1474 let Inst{24} = instr;
1476 let Inst{21} = write;
1478 let Inst{15-12} = 0b1111;
1481 let addr{12} = 1; // add = TRUE
1482 let Inst{19-16} = addr{16-13}; // Rn
1483 let Inst{23} = addr{12}; // U
1484 let Inst{11-0} = addr{11-0}; // imm12
1487 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1489 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1490 let Inst{31-25} = 0b1111100;
1491 let Inst{24} = instr;
1492 let Inst{23} = 0; // U = 0
1494 let Inst{21} = write;
1496 let Inst{15-12} = 0b1111;
1497 let Inst{11-8} = 0b1100;
1500 let Inst{19-16} = addr{12-9}; // Rn
1501 let Inst{7-0} = addr{7-0}; // imm8
1504 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1506 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1507 let Inst{31-25} = 0b1111100;
1508 let Inst{24} = instr;
1509 let Inst{23} = 0; // add = TRUE for T1
1511 let Inst{21} = write;
1513 let Inst{15-12} = 0b1111;
1514 let Inst{11-6} = 0000000;
1517 let Inst{19-16} = addr{9-6}; // Rn
1518 let Inst{3-0} = addr{5-2}; // Rm
1519 let Inst{5-4} = addr{1-0}; // imm2
1521 let DecoderMethod = "DecodeT2LoadShift";
1525 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1526 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1527 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1529 //===----------------------------------------------------------------------===//
1530 // Load / store multiple Instructions.
1533 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1534 InstrItinClass itin_upd, bit L_bit> {
1536 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1537 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1541 let Inst{31-27} = 0b11101;
1542 let Inst{26-25} = 0b00;
1543 let Inst{24-23} = 0b01; // Increment After
1545 let Inst{21} = 0; // No writeback
1546 let Inst{20} = L_bit;
1547 let Inst{19-16} = Rn;
1549 let Inst{14-0} = regs{14-0};
1552 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1553 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1557 let Inst{31-27} = 0b11101;
1558 let Inst{26-25} = 0b00;
1559 let Inst{24-23} = 0b01; // Increment After
1561 let Inst{21} = 1; // Writeback
1562 let Inst{20} = L_bit;
1563 let Inst{19-16} = Rn;
1565 let Inst{14-0} = regs{14-0};
1568 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1569 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1573 let Inst{31-27} = 0b11101;
1574 let Inst{26-25} = 0b00;
1575 let Inst{24-23} = 0b10; // Decrement Before
1577 let Inst{21} = 0; // No writeback
1578 let Inst{20} = L_bit;
1579 let Inst{19-16} = Rn;
1581 let Inst{14-0} = regs{14-0};
1584 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1585 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1589 let Inst{31-27} = 0b11101;
1590 let Inst{26-25} = 0b00;
1591 let Inst{24-23} = 0b10; // Decrement Before
1593 let Inst{21} = 1; // Writeback
1594 let Inst{20} = L_bit;
1595 let Inst{19-16} = Rn;
1597 let Inst{14-0} = regs{14-0};
1601 let neverHasSideEffects = 1 in {
1603 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1604 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1606 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1607 InstrItinClass itin_upd, bit L_bit> {
1609 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1610 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1614 let Inst{31-27} = 0b11101;
1615 let Inst{26-25} = 0b00;
1616 let Inst{24-23} = 0b01; // Increment After
1618 let Inst{21} = 0; // No writeback
1619 let Inst{20} = L_bit;
1620 let Inst{19-16} = Rn;
1622 let Inst{14} = regs{14};
1624 let Inst{12-0} = regs{12-0};
1627 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1628 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1632 let Inst{31-27} = 0b11101;
1633 let Inst{26-25} = 0b00;
1634 let Inst{24-23} = 0b01; // Increment After
1636 let Inst{21} = 1; // Writeback
1637 let Inst{20} = L_bit;
1638 let Inst{19-16} = Rn;
1640 let Inst{14} = regs{14};
1642 let Inst{12-0} = regs{12-0};
1645 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1646 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1650 let Inst{31-27} = 0b11101;
1651 let Inst{26-25} = 0b00;
1652 let Inst{24-23} = 0b10; // Decrement Before
1654 let Inst{21} = 0; // No writeback
1655 let Inst{20} = L_bit;
1656 let Inst{19-16} = Rn;
1658 let Inst{14} = regs{14};
1660 let Inst{12-0} = regs{12-0};
1663 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1664 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1668 let Inst{31-27} = 0b11101;
1669 let Inst{26-25} = 0b00;
1670 let Inst{24-23} = 0b10; // Decrement Before
1672 let Inst{21} = 1; // Writeback
1673 let Inst{20} = L_bit;
1674 let Inst{19-16} = Rn;
1676 let Inst{14} = regs{14};
1678 let Inst{12-0} = regs{12-0};
1683 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1684 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1686 } // neverHasSideEffects
1689 //===----------------------------------------------------------------------===//
1690 // Move Instructions.
1693 let neverHasSideEffects = 1 in
1694 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1695 "mov", ".w\t$Rd, $Rm", []> {
1696 let Inst{31-27} = 0b11101;
1697 let Inst{26-25} = 0b01;
1698 let Inst{24-21} = 0b0010;
1699 let Inst{19-16} = 0b1111; // Rn
1700 let Inst{14-12} = 0b000;
1701 let Inst{7-4} = 0b0000;
1703 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1705 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1708 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1709 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1710 AddedComplexity = 1 in
1711 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1712 "mov", ".w\t$Rd, $imm",
1713 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1714 let Inst{31-27} = 0b11110;
1716 let Inst{24-21} = 0b0010;
1717 let Inst{19-16} = 0b1111; // Rn
1721 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1722 // Use aliases to get that to play nice here.
1723 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1725 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1728 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1729 pred:$p, zero_reg)>;
1730 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1731 pred:$p, zero_reg)>;
1733 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1734 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1735 "movw", "\t$Rd, $imm",
1736 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1737 let Inst{31-27} = 0b11110;
1739 let Inst{24-21} = 0b0010;
1740 let Inst{20} = 0; // The S bit.
1746 let Inst{11-8} = Rd;
1747 let Inst{19-16} = imm{15-12};
1748 let Inst{26} = imm{11};
1749 let Inst{14-12} = imm{10-8};
1750 let Inst{7-0} = imm{7-0};
1753 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1754 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1756 let Constraints = "$src = $Rd" in {
1757 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1758 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1759 "movt", "\t$Rd, $imm",
1761 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1762 let Inst{31-27} = 0b11110;
1764 let Inst{24-21} = 0b0110;
1765 let Inst{20} = 0; // The S bit.
1771 let Inst{11-8} = Rd;
1772 let Inst{19-16} = imm{15-12};
1773 let Inst{26} = imm{11};
1774 let Inst{14-12} = imm{10-8};
1775 let Inst{7-0} = imm{7-0};
1778 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1779 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1782 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1784 //===----------------------------------------------------------------------===//
1785 // Extend Instructions.
1790 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1791 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1792 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1793 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1794 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1796 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1797 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1798 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1799 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1800 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1804 let AddedComplexity = 16 in {
1805 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1806 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1807 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1808 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1809 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1810 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1812 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1813 // The transformation should probably be done as a combiner action
1814 // instead so we can include a check for masking back in the upper
1815 // eight bits of the source into the lower eight bits of the result.
1816 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1817 // (t2UXTB16 rGPR:$Src, 3)>,
1818 // Requires<[HasT2ExtractPack, IsThumb2]>;
1819 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1820 (t2UXTB16 rGPR:$Src, 1)>,
1821 Requires<[HasT2ExtractPack, IsThumb2]>;
1823 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1824 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1825 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1826 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1827 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1830 //===----------------------------------------------------------------------===//
1831 // Arithmetic Instructions.
1834 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1835 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1836 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1837 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1839 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1840 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1841 // CPSR and the implicit def of CPSR is not needed.
1842 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1843 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1844 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1845 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1846 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1847 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1849 let hasPostISelHook = 1 in {
1850 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1851 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1852 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1853 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1857 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1858 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1860 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1861 // CPSR and the implicit def of CPSR is not needed.
1862 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1863 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1865 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1866 // The assume-no-carry-in form uses the negation of the input since add/sub
1867 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1868 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1870 // The AddedComplexity preferences the first variant over the others since
1871 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1872 let AddedComplexity = 1 in
1873 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1874 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1875 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1876 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1877 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1878 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1879 let AddedComplexity = 1 in
1880 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1881 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1882 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1883 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1884 // The with-carry-in form matches bitwise not instead of the negation.
1885 // Effectively, the inverse interpretation of the carry flag already accounts
1886 // for part of the negation.
1887 let AddedComplexity = 1 in
1888 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1889 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1890 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1891 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1893 // Select Bytes -- for disassembly only
1895 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1896 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1897 Requires<[IsThumb2, HasThumb2DSP]> {
1898 let Inst{31-27} = 0b11111;
1899 let Inst{26-24} = 0b010;
1901 let Inst{22-20} = 0b010;
1902 let Inst{15-12} = 0b1111;
1904 let Inst{6-4} = 0b000;
1907 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1908 // And Miscellaneous operations -- for disassembly only
1909 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1910 list<dag> pat = [/* For disassembly only; pattern left blank */],
1911 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1912 string asm = "\t$Rd, $Rn, $Rm">
1913 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1914 Requires<[IsThumb2, HasThumb2DSP]> {
1915 let Inst{31-27} = 0b11111;
1916 let Inst{26-23} = 0b0101;
1917 let Inst{22-20} = op22_20;
1918 let Inst{15-12} = 0b1111;
1919 let Inst{7-4} = op7_4;
1925 let Inst{11-8} = Rd;
1926 let Inst{19-16} = Rn;
1930 // Saturating add/subtract -- for disassembly only
1932 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1933 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1934 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1935 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1936 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1937 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1938 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1939 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1940 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1941 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1942 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1943 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1944 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1945 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1946 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1947 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1948 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1949 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1950 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1951 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1952 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1953 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1955 // Signed/Unsigned add/subtract -- for disassembly only
1957 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1958 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1959 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1960 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1961 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1962 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1963 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1964 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1965 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1966 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1967 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1968 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1970 // Signed/Unsigned halving add/subtract -- for disassembly only
1972 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1973 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1974 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1975 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1976 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1977 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1978 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1979 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1980 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1981 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1982 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1983 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1985 // Helper class for disassembly only
1986 // A6.3.16 & A6.3.17
1987 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1988 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1989 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1990 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1991 let Inst{31-27} = 0b11111;
1992 let Inst{26-24} = 0b011;
1993 let Inst{23} = long;
1994 let Inst{22-20} = op22_20;
1995 let Inst{7-4} = op7_4;
1998 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1999 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2000 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2001 let Inst{31-27} = 0b11111;
2002 let Inst{26-24} = 0b011;
2003 let Inst{23} = long;
2004 let Inst{22-20} = op22_20;
2005 let Inst{7-4} = op7_4;
2008 // Unsigned Sum of Absolute Differences [and Accumulate].
2009 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2010 (ins rGPR:$Rn, rGPR:$Rm),
2011 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2012 Requires<[IsThumb2, HasThumb2DSP]> {
2013 let Inst{15-12} = 0b1111;
2015 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2016 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2017 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2018 Requires<[IsThumb2, HasThumb2DSP]>;
2020 // Signed/Unsigned saturate.
2021 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2022 string opc, string asm, list<dag> pattern>
2023 : T2I<oops, iops, itin, opc, asm, pattern> {
2029 let Inst{11-8} = Rd;
2030 let Inst{19-16} = Rn;
2031 let Inst{4-0} = sat_imm;
2032 let Inst{21} = sh{5};
2033 let Inst{14-12} = sh{4-2};
2034 let Inst{7-6} = sh{1-0};
2038 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2039 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2040 let Inst{31-27} = 0b11110;
2041 let Inst{25-22} = 0b1100;
2047 def t2SSAT16: T2SatI<
2048 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2049 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2050 Requires<[IsThumb2, HasThumb2DSP]> {
2051 let Inst{31-27} = 0b11110;
2052 let Inst{25-22} = 0b1100;
2055 let Inst{21} = 1; // sh = '1'
2056 let Inst{14-12} = 0b000; // imm3 = '000'
2057 let Inst{7-6} = 0b00; // imm2 = '00'
2058 let Inst{5-4} = 0b00;
2062 (outs rGPR:$Rd), (ins imm0_31:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2063 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2064 let Inst{31-27} = 0b11110;
2065 let Inst{25-22} = 0b1110;
2070 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2072 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2073 Requires<[IsThumb2, HasThumb2DSP]> {
2074 let Inst{31-27} = 0b11110;
2075 let Inst{25-22} = 0b1110;
2078 let Inst{21} = 1; // sh = '1'
2079 let Inst{14-12} = 0b000; // imm3 = '000'
2080 let Inst{7-6} = 0b00; // imm2 = '00'
2083 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2084 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2086 //===----------------------------------------------------------------------===//
2087 // Shift and rotate Instructions.
2090 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2091 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2092 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2093 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2094 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2095 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2096 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2097 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2099 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2100 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2101 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2103 let Uses = [CPSR] in {
2104 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2105 "rrx", "\t$Rd, $Rm",
2106 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2107 let Inst{31-27} = 0b11101;
2108 let Inst{26-25} = 0b01;
2109 let Inst{24-21} = 0b0010;
2110 let Inst{19-16} = 0b1111; // Rn
2111 let Inst{14-12} = 0b000;
2112 let Inst{7-4} = 0b0011;
2116 let isCodeGenOnly = 1, Defs = [CPSR] in {
2117 def t2MOVsrl_flag : T2TwoRegShiftImm<
2118 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2119 "lsrs", ".w\t$Rd, $Rm, #1",
2120 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2121 let Inst{31-27} = 0b11101;
2122 let Inst{26-25} = 0b01;
2123 let Inst{24-21} = 0b0010;
2124 let Inst{20} = 1; // The S bit.
2125 let Inst{19-16} = 0b1111; // Rn
2126 let Inst{5-4} = 0b01; // Shift type.
2127 // Shift amount = Inst{14-12:7-6} = 1.
2128 let Inst{14-12} = 0b000;
2129 let Inst{7-6} = 0b01;
2131 def t2MOVsra_flag : T2TwoRegShiftImm<
2132 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2133 "asrs", ".w\t$Rd, $Rm, #1",
2134 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2135 let Inst{31-27} = 0b11101;
2136 let Inst{26-25} = 0b01;
2137 let Inst{24-21} = 0b0010;
2138 let Inst{20} = 1; // The S bit.
2139 let Inst{19-16} = 0b1111; // Rn
2140 let Inst{5-4} = 0b10; // Shift type.
2141 // Shift amount = Inst{14-12:7-6} = 1.
2142 let Inst{14-12} = 0b000;
2143 let Inst{7-6} = 0b01;
2147 //===----------------------------------------------------------------------===//
2148 // Bitwise Instructions.
2151 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2152 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2153 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2154 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2155 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2156 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2157 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2158 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2159 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2161 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2162 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2163 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2166 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2167 string opc, string asm, list<dag> pattern>
2168 : T2I<oops, iops, itin, opc, asm, pattern> {
2173 let Inst{11-8} = Rd;
2174 let Inst{4-0} = msb{4-0};
2175 let Inst{14-12} = lsb{4-2};
2176 let Inst{7-6} = lsb{1-0};
2179 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2180 string opc, string asm, list<dag> pattern>
2181 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2184 let Inst{19-16} = Rn;
2187 let Constraints = "$src = $Rd" in
2188 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2189 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2190 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2191 let Inst{31-27} = 0b11110;
2192 let Inst{26} = 0; // should be 0.
2194 let Inst{24-20} = 0b10110;
2195 let Inst{19-16} = 0b1111; // Rn
2197 let Inst{5} = 0; // should be 0.
2200 let msb{4-0} = imm{9-5};
2201 let lsb{4-0} = imm{4-0};
2204 def t2SBFX: T2TwoRegBitFI<
2205 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2206 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2207 let Inst{31-27} = 0b11110;
2209 let Inst{24-20} = 0b10100;
2213 def t2UBFX: T2TwoRegBitFI<
2214 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2215 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2216 let Inst{31-27} = 0b11110;
2218 let Inst{24-20} = 0b11100;
2222 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2223 let Constraints = "$src = $Rd" in {
2224 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2225 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2226 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2227 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2228 bf_inv_mask_imm:$imm))]> {
2229 let Inst{31-27} = 0b11110;
2230 let Inst{26} = 0; // should be 0.
2232 let Inst{24-20} = 0b10110;
2234 let Inst{5} = 0; // should be 0.
2237 let msb{4-0} = imm{9-5};
2238 let lsb{4-0} = imm{4-0};
2242 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2243 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2244 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2247 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2248 /// unary operation that produces a value. These are predicable and can be
2249 /// changed to modify CPSR.
2250 multiclass T2I_un_irs<bits<4> opcod, string opc,
2251 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2252 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2254 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2256 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2257 let isAsCheapAsAMove = Cheap;
2258 let isReMaterializable = ReMat;
2259 let Inst{31-27} = 0b11110;
2261 let Inst{24-21} = opcod;
2262 let Inst{19-16} = 0b1111; // Rn
2266 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2267 opc, ".w\t$Rd, $Rm",
2268 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2269 let Inst{31-27} = 0b11101;
2270 let Inst{26-25} = 0b01;
2271 let Inst{24-21} = opcod;
2272 let Inst{19-16} = 0b1111; // Rn
2273 let Inst{14-12} = 0b000; // imm3
2274 let Inst{7-6} = 0b00; // imm2
2275 let Inst{5-4} = 0b00; // type
2278 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2279 opc, ".w\t$Rd, $ShiftedRm",
2280 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2281 let Inst{31-27} = 0b11101;
2282 let Inst{26-25} = 0b01;
2283 let Inst{24-21} = opcod;
2284 let Inst{19-16} = 0b1111; // Rn
2288 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2289 let AddedComplexity = 1 in
2290 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2291 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2292 UnOpFrag<(not node:$Src)>, 1, 1>;
2294 let AddedComplexity = 1 in
2295 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2296 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2298 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2299 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2300 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2301 Requires<[IsThumb2]>;
2303 def : T2Pat<(t2_so_imm_not:$src),
2304 (t2MVNi t2_so_imm_not:$src)>;
2306 //===----------------------------------------------------------------------===//
2307 // Multiply Instructions.
2309 let isCommutable = 1 in
2310 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2311 "mul", "\t$Rd, $Rn, $Rm",
2312 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2313 let Inst{31-27} = 0b11111;
2314 let Inst{26-23} = 0b0110;
2315 let Inst{22-20} = 0b000;
2316 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2317 let Inst{7-4} = 0b0000; // Multiply
2320 def t2MLA: T2FourReg<
2321 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2322 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2323 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2324 let Inst{31-27} = 0b11111;
2325 let Inst{26-23} = 0b0110;
2326 let Inst{22-20} = 0b000;
2327 let Inst{7-4} = 0b0000; // Multiply
2330 def t2MLS: T2FourReg<
2331 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2332 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2333 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2334 let Inst{31-27} = 0b11111;
2335 let Inst{26-23} = 0b0110;
2336 let Inst{22-20} = 0b000;
2337 let Inst{7-4} = 0b0001; // Multiply and Subtract
2340 // Extra precision multiplies with low / high results
2341 let neverHasSideEffects = 1 in {
2342 let isCommutable = 1 in {
2343 def t2SMULL : T2MulLong<0b000, 0b0000,
2344 (outs rGPR:$RdLo, rGPR:$RdHi),
2345 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2346 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2348 def t2UMULL : T2MulLong<0b010, 0b0000,
2349 (outs rGPR:$RdLo, rGPR:$RdHi),
2350 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2351 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2354 // Multiply + accumulate
2355 def t2SMLAL : T2MulLong<0b100, 0b0000,
2356 (outs rGPR:$RdLo, rGPR:$RdHi),
2357 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2358 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2360 def t2UMLAL : T2MulLong<0b110, 0b0000,
2361 (outs rGPR:$RdLo, rGPR:$RdHi),
2362 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2363 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2365 def t2UMAAL : T2MulLong<0b110, 0b0110,
2366 (outs rGPR:$RdLo, rGPR:$RdHi),
2367 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2368 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2369 Requires<[IsThumb2, HasThumb2DSP]>;
2370 } // neverHasSideEffects
2372 // Rounding variants of the below included for disassembly only
2374 // Most significant word multiply
2375 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2376 "smmul", "\t$Rd, $Rn, $Rm",
2377 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2378 Requires<[IsThumb2, HasThumb2DSP]> {
2379 let Inst{31-27} = 0b11111;
2380 let Inst{26-23} = 0b0110;
2381 let Inst{22-20} = 0b101;
2382 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2383 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2386 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2387 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2388 Requires<[IsThumb2, HasThumb2DSP]> {
2389 let Inst{31-27} = 0b11111;
2390 let Inst{26-23} = 0b0110;
2391 let Inst{22-20} = 0b101;
2392 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2393 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2396 def t2SMMLA : T2FourReg<
2397 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2398 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2399 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2400 Requires<[IsThumb2, HasThumb2DSP]> {
2401 let Inst{31-27} = 0b11111;
2402 let Inst{26-23} = 0b0110;
2403 let Inst{22-20} = 0b101;
2404 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2407 def t2SMMLAR: T2FourReg<
2408 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2409 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2410 Requires<[IsThumb2, HasThumb2DSP]> {
2411 let Inst{31-27} = 0b11111;
2412 let Inst{26-23} = 0b0110;
2413 let Inst{22-20} = 0b101;
2414 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2417 def t2SMMLS: T2FourReg<
2418 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2419 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2420 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2421 Requires<[IsThumb2, HasThumb2DSP]> {
2422 let Inst{31-27} = 0b11111;
2423 let Inst{26-23} = 0b0110;
2424 let Inst{22-20} = 0b110;
2425 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2428 def t2SMMLSR:T2FourReg<
2429 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2430 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2431 Requires<[IsThumb2, HasThumb2DSP]> {
2432 let Inst{31-27} = 0b11111;
2433 let Inst{26-23} = 0b0110;
2434 let Inst{22-20} = 0b110;
2435 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2438 multiclass T2I_smul<string opc, PatFrag opnode> {
2439 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2440 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2441 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2442 (sext_inreg rGPR:$Rm, i16)))]>,
2443 Requires<[IsThumb2, HasThumb2DSP]> {
2444 let Inst{31-27} = 0b11111;
2445 let Inst{26-23} = 0b0110;
2446 let Inst{22-20} = 0b001;
2447 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2448 let Inst{7-6} = 0b00;
2449 let Inst{5-4} = 0b00;
2452 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2453 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2454 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2455 (sra rGPR:$Rm, (i32 16))))]>,
2456 Requires<[IsThumb2, HasThumb2DSP]> {
2457 let Inst{31-27} = 0b11111;
2458 let Inst{26-23} = 0b0110;
2459 let Inst{22-20} = 0b001;
2460 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2461 let Inst{7-6} = 0b00;
2462 let Inst{5-4} = 0b01;
2465 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2466 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2467 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2468 (sext_inreg rGPR:$Rm, i16)))]>,
2469 Requires<[IsThumb2, HasThumb2DSP]> {
2470 let Inst{31-27} = 0b11111;
2471 let Inst{26-23} = 0b0110;
2472 let Inst{22-20} = 0b001;
2473 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2474 let Inst{7-6} = 0b00;
2475 let Inst{5-4} = 0b10;
2478 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2479 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2480 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2481 (sra rGPR:$Rm, (i32 16))))]>,
2482 Requires<[IsThumb2, HasThumb2DSP]> {
2483 let Inst{31-27} = 0b11111;
2484 let Inst{26-23} = 0b0110;
2485 let Inst{22-20} = 0b001;
2486 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2487 let Inst{7-6} = 0b00;
2488 let Inst{5-4} = 0b11;
2491 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2492 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2493 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2494 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2495 Requires<[IsThumb2, HasThumb2DSP]> {
2496 let Inst{31-27} = 0b11111;
2497 let Inst{26-23} = 0b0110;
2498 let Inst{22-20} = 0b011;
2499 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2500 let Inst{7-6} = 0b00;
2501 let Inst{5-4} = 0b00;
2504 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2505 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2506 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2507 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2508 Requires<[IsThumb2, HasThumb2DSP]> {
2509 let Inst{31-27} = 0b11111;
2510 let Inst{26-23} = 0b0110;
2511 let Inst{22-20} = 0b011;
2512 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2513 let Inst{7-6} = 0b00;
2514 let Inst{5-4} = 0b01;
2519 multiclass T2I_smla<string opc, PatFrag opnode> {
2521 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2522 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2523 [(set rGPR:$Rd, (add rGPR:$Ra,
2524 (opnode (sext_inreg rGPR:$Rn, i16),
2525 (sext_inreg rGPR:$Rm, i16))))]>,
2526 Requires<[IsThumb2, HasThumb2DSP]> {
2527 let Inst{31-27} = 0b11111;
2528 let Inst{26-23} = 0b0110;
2529 let Inst{22-20} = 0b001;
2530 let Inst{7-6} = 0b00;
2531 let Inst{5-4} = 0b00;
2535 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2536 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2537 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2538 (sra rGPR:$Rm, (i32 16)))))]>,
2539 Requires<[IsThumb2, HasThumb2DSP]> {
2540 let Inst{31-27} = 0b11111;
2541 let Inst{26-23} = 0b0110;
2542 let Inst{22-20} = 0b001;
2543 let Inst{7-6} = 0b00;
2544 let Inst{5-4} = 0b01;
2548 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2549 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2550 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2551 (sext_inreg rGPR:$Rm, i16))))]>,
2552 Requires<[IsThumb2, HasThumb2DSP]> {
2553 let Inst{31-27} = 0b11111;
2554 let Inst{26-23} = 0b0110;
2555 let Inst{22-20} = 0b001;
2556 let Inst{7-6} = 0b00;
2557 let Inst{5-4} = 0b10;
2561 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2562 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2563 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2564 (sra rGPR:$Rm, (i32 16)))))]>,
2565 Requires<[IsThumb2, HasThumb2DSP]> {
2566 let Inst{31-27} = 0b11111;
2567 let Inst{26-23} = 0b0110;
2568 let Inst{22-20} = 0b001;
2569 let Inst{7-6} = 0b00;
2570 let Inst{5-4} = 0b11;
2574 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2575 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2576 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2577 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2578 Requires<[IsThumb2, HasThumb2DSP]> {
2579 let Inst{31-27} = 0b11111;
2580 let Inst{26-23} = 0b0110;
2581 let Inst{22-20} = 0b011;
2582 let Inst{7-6} = 0b00;
2583 let Inst{5-4} = 0b00;
2587 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2588 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2589 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2590 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2591 Requires<[IsThumb2, HasThumb2DSP]> {
2592 let Inst{31-27} = 0b11111;
2593 let Inst{26-23} = 0b0110;
2594 let Inst{22-20} = 0b011;
2595 let Inst{7-6} = 0b00;
2596 let Inst{5-4} = 0b01;
2600 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2601 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2603 // Halfword multiple accumulate long: SMLAL<x><y>
2604 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2605 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2606 [/* For disassembly only; pattern left blank */]>,
2607 Requires<[IsThumb2, HasThumb2DSP]>;
2608 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2609 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2610 [/* For disassembly only; pattern left blank */]>,
2611 Requires<[IsThumb2, HasThumb2DSP]>;
2612 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2613 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2614 [/* For disassembly only; pattern left blank */]>,
2615 Requires<[IsThumb2, HasThumb2DSP]>;
2616 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2617 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2618 [/* For disassembly only; pattern left blank */]>,
2619 Requires<[IsThumb2, HasThumb2DSP]>;
2621 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2622 def t2SMUAD: T2ThreeReg_mac<
2623 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2624 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2625 Requires<[IsThumb2, HasThumb2DSP]> {
2626 let Inst{15-12} = 0b1111;
2628 def t2SMUADX:T2ThreeReg_mac<
2629 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2630 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2631 Requires<[IsThumb2, HasThumb2DSP]> {
2632 let Inst{15-12} = 0b1111;
2634 def t2SMUSD: T2ThreeReg_mac<
2635 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2636 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2637 Requires<[IsThumb2, HasThumb2DSP]> {
2638 let Inst{15-12} = 0b1111;
2640 def t2SMUSDX:T2ThreeReg_mac<
2641 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2642 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2643 Requires<[IsThumb2, HasThumb2DSP]> {
2644 let Inst{15-12} = 0b1111;
2646 def t2SMLAD : T2FourReg_mac<
2647 0, 0b010, 0b0000, (outs rGPR:$Rd),
2648 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2649 "\t$Rd, $Rn, $Rm, $Ra", []>,
2650 Requires<[IsThumb2, HasThumb2DSP]>;
2651 def t2SMLADX : T2FourReg_mac<
2652 0, 0b010, 0b0001, (outs rGPR:$Rd),
2653 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2654 "\t$Rd, $Rn, $Rm, $Ra", []>,
2655 Requires<[IsThumb2, HasThumb2DSP]>;
2656 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2657 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2658 "\t$Rd, $Rn, $Rm, $Ra", []>,
2659 Requires<[IsThumb2, HasThumb2DSP]>;
2660 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2661 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2662 "\t$Rd, $Rn, $Rm, $Ra", []>,
2663 Requires<[IsThumb2, HasThumb2DSP]>;
2664 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2665 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2666 "\t$Ra, $Rd, $Rn, $Rm", []>,
2667 Requires<[IsThumb2, HasThumb2DSP]>;
2668 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2669 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2670 "\t$Ra, $Rd, $Rn, $Rm", []>,
2671 Requires<[IsThumb2, HasThumb2DSP]>;
2672 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2673 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2674 "\t$Ra, $Rd, $Rn, $Rm", []>,
2675 Requires<[IsThumb2, HasThumb2DSP]>;
2676 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2677 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2678 "\t$Ra, $Rd, $Rn, $Rm", []>,
2679 Requires<[IsThumb2, HasThumb2DSP]>;
2681 //===----------------------------------------------------------------------===//
2682 // Division Instructions.
2683 // Signed and unsigned division on v7-M
2685 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2686 "sdiv", "\t$Rd, $Rn, $Rm",
2687 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2688 Requires<[HasDivide, IsThumb2]> {
2689 let Inst{31-27} = 0b11111;
2690 let Inst{26-21} = 0b011100;
2692 let Inst{15-12} = 0b1111;
2693 let Inst{7-4} = 0b1111;
2696 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2697 "udiv", "\t$Rd, $Rn, $Rm",
2698 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2699 Requires<[HasDivide, IsThumb2]> {
2700 let Inst{31-27} = 0b11111;
2701 let Inst{26-21} = 0b011101;
2703 let Inst{15-12} = 0b1111;
2704 let Inst{7-4} = 0b1111;
2707 //===----------------------------------------------------------------------===//
2708 // Misc. Arithmetic Instructions.
2711 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2712 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2713 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2714 let Inst{31-27} = 0b11111;
2715 let Inst{26-22} = 0b01010;
2716 let Inst{21-20} = op1;
2717 let Inst{15-12} = 0b1111;
2718 let Inst{7-6} = 0b10;
2719 let Inst{5-4} = op2;
2723 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2724 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2726 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2727 "rbit", "\t$Rd, $Rm",
2728 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2730 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2731 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2733 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2734 "rev16", ".w\t$Rd, $Rm",
2735 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2737 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2738 "revsh", ".w\t$Rd, $Rm",
2739 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2741 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2742 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2743 (t2REVSH rGPR:$Rm)>;
2745 def t2PKHBT : T2ThreeReg<
2746 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2747 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2748 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2749 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2751 Requires<[HasT2ExtractPack, IsThumb2]> {
2752 let Inst{31-27} = 0b11101;
2753 let Inst{26-25} = 0b01;
2754 let Inst{24-20} = 0b01100;
2755 let Inst{5} = 0; // BT form
2759 let Inst{14-12} = sh{4-2};
2760 let Inst{7-6} = sh{1-0};
2763 // Alternate cases for PKHBT where identities eliminate some nodes.
2764 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2765 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2766 Requires<[HasT2ExtractPack, IsThumb2]>;
2767 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2768 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2769 Requires<[HasT2ExtractPack, IsThumb2]>;
2771 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2772 // will match the pattern below.
2773 def t2PKHTB : T2ThreeReg<
2774 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2775 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2776 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2777 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2779 Requires<[HasT2ExtractPack, IsThumb2]> {
2780 let Inst{31-27} = 0b11101;
2781 let Inst{26-25} = 0b01;
2782 let Inst{24-20} = 0b01100;
2783 let Inst{5} = 1; // TB form
2787 let Inst{14-12} = sh{4-2};
2788 let Inst{7-6} = sh{1-0};
2791 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2792 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2793 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2794 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2795 Requires<[HasT2ExtractPack, IsThumb2]>;
2796 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2797 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2798 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2799 Requires<[HasT2ExtractPack, IsThumb2]>;
2801 //===----------------------------------------------------------------------===//
2802 // Comparison Instructions...
2804 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2805 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2806 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2808 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2809 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2810 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2811 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2812 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2813 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2815 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2816 // Compare-to-zero still works out, just not the relationals
2817 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2818 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2819 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2820 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2821 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2824 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2825 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2827 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2828 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2830 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2831 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2832 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2834 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2835 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2836 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2839 // Conditional moves
2840 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2841 // a two-value operand where a dag node expects two operands. :(
2842 let neverHasSideEffects = 1 in {
2843 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2844 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2846 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2847 RegConstraint<"$false = $Rd">;
2849 let isMoveImm = 1 in
2850 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2851 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2853 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2854 RegConstraint<"$false = $Rd">;
2856 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2857 let isCodeGenOnly = 1 in {
2858 let isMoveImm = 1 in
2859 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2861 "movw", "\t$Rd, $imm", []>,
2862 RegConstraint<"$false = $Rd"> {
2863 let Inst{31-27} = 0b11110;
2865 let Inst{24-21} = 0b0010;
2866 let Inst{20} = 0; // The S bit.
2872 let Inst{11-8} = Rd;
2873 let Inst{19-16} = imm{15-12};
2874 let Inst{26} = imm{11};
2875 let Inst{14-12} = imm{10-8};
2876 let Inst{7-0} = imm{7-0};
2879 let isMoveImm = 1 in
2880 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2881 (ins rGPR:$false, i32imm:$src, pred:$p),
2882 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2884 let isMoveImm = 1 in
2885 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2886 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2887 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2888 imm:$cc, CCR:$ccr))*/]>,
2889 RegConstraint<"$false = $Rd"> {
2890 let Inst{31-27} = 0b11110;
2892 let Inst{24-21} = 0b0011;
2893 let Inst{20} = 0; // The S bit.
2894 let Inst{19-16} = 0b1111; // Rn
2898 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2899 string opc, string asm, list<dag> pattern>
2900 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2901 let Inst{31-27} = 0b11101;
2902 let Inst{26-25} = 0b01;
2903 let Inst{24-21} = 0b0010;
2904 let Inst{20} = 0; // The S bit.
2905 let Inst{19-16} = 0b1111; // Rn
2906 let Inst{5-4} = opcod; // Shift type.
2908 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2909 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2910 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2911 RegConstraint<"$false = $Rd">;
2912 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2913 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2914 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2915 RegConstraint<"$false = $Rd">;
2916 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2917 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2918 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2919 RegConstraint<"$false = $Rd">;
2920 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2921 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2922 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2923 RegConstraint<"$false = $Rd">;
2924 } // isCodeGenOnly = 1
2925 } // neverHasSideEffects
2927 //===----------------------------------------------------------------------===//
2928 // Atomic operations intrinsics
2931 // memory barriers protect the atomic sequences
2932 let hasSideEffects = 1 in {
2933 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2934 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2935 Requires<[IsThumb, HasDB]> {
2937 let Inst{31-4} = 0xf3bf8f5;
2938 let Inst{3-0} = opt;
2942 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2943 "dsb", "\t$opt", []>,
2944 Requires<[IsThumb, HasDB]> {
2946 let Inst{31-4} = 0xf3bf8f4;
2947 let Inst{3-0} = opt;
2950 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2952 []>, Requires<[IsThumb2, HasDB]> {
2954 let Inst{31-4} = 0xf3bf8f6;
2955 let Inst{3-0} = opt;
2958 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2959 InstrItinClass itin, string opc, string asm, string cstr,
2960 list<dag> pattern, bits<4> rt2 = 0b1111>
2961 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2962 let Inst{31-27} = 0b11101;
2963 let Inst{26-20} = 0b0001101;
2964 let Inst{11-8} = rt2;
2965 let Inst{7-6} = 0b01;
2966 let Inst{5-4} = opcod;
2967 let Inst{3-0} = 0b1111;
2971 let Inst{19-16} = addr;
2972 let Inst{15-12} = Rt;
2974 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2975 InstrItinClass itin, string opc, string asm, string cstr,
2976 list<dag> pattern, bits<4> rt2 = 0b1111>
2977 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2978 let Inst{31-27} = 0b11101;
2979 let Inst{26-20} = 0b0001100;
2980 let Inst{11-8} = rt2;
2981 let Inst{7-6} = 0b01;
2982 let Inst{5-4} = opcod;
2988 let Inst{19-16} = addr;
2989 let Inst{15-12} = Rt;
2992 let mayLoad = 1 in {
2993 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2994 AddrModeNone, 4, NoItinerary,
2995 "ldrexb", "\t$Rt, $addr", "", []>;
2996 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2997 AddrModeNone, 4, NoItinerary,
2998 "ldrexh", "\t$Rt, $addr", "", []>;
2999 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3000 AddrModeNone, 4, NoItinerary,
3001 "ldrex", "\t$Rt, $addr", "", []> {
3004 let Inst{31-27} = 0b11101;
3005 let Inst{26-20} = 0b0000101;
3006 let Inst{19-16} = addr{11-8};
3007 let Inst{15-12} = Rt;
3008 let Inst{11-8} = 0b1111;
3009 let Inst{7-0} = addr{7-0};
3011 let hasExtraDefRegAllocReq = 1 in
3012 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3013 (ins addr_offset_none:$addr),
3014 AddrModeNone, 4, NoItinerary,
3015 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3018 let Inst{11-8} = Rt2;
3022 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3023 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3024 (ins rGPR:$Rt, addr_offset_none:$addr),
3025 AddrModeNone, 4, NoItinerary,
3026 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3027 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3028 (ins rGPR:$Rt, addr_offset_none:$addr),
3029 AddrModeNone, 4, NoItinerary,
3030 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3031 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3032 t2addrmode_imm0_1020s4:$addr),
3033 AddrModeNone, 4, NoItinerary,
3034 "strex", "\t$Rd, $Rt, $addr", "",
3039 let Inst{31-27} = 0b11101;
3040 let Inst{26-20} = 0b0000100;
3041 let Inst{19-16} = addr{11-8};
3042 let Inst{15-12} = Rt;
3043 let Inst{11-8} = Rd;
3044 let Inst{7-0} = addr{7-0};
3048 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3049 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3050 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3051 AddrModeNone, 4, NoItinerary,
3052 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3055 let Inst{11-8} = Rt2;
3058 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3059 Requires<[IsThumb2, HasV7]> {
3060 let Inst{31-16} = 0xf3bf;
3061 let Inst{15-14} = 0b10;
3064 let Inst{11-8} = 0b1111;
3065 let Inst{7-4} = 0b0010;
3066 let Inst{3-0} = 0b1111;
3069 //===----------------------------------------------------------------------===//
3070 // SJLJ Exception handling intrinsics
3071 // eh_sjlj_setjmp() is an instruction sequence to store the return
3072 // address and save #0 in R0 for the non-longjmp case.
3073 // Since by its nature we may be coming from some other function to get
3074 // here, and we're using the stack frame for the containing function to
3075 // save/restore registers, we can't keep anything live in regs across
3076 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3077 // when we get here from a longjmp(). We force everything out of registers
3078 // except for our own input by listing the relevant registers in Defs. By
3079 // doing so, we also cause the prologue/epilogue code to actively preserve
3080 // all of the callee-saved resgisters, which is exactly what we want.
3081 // $val is a scratch register for our use.
3083 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3084 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
3085 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3086 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3087 AddrModeNone, 0, NoItinerary, "", "",
3088 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3089 Requires<[IsThumb2, HasVFP2]>;
3093 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3094 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3095 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3096 AddrModeNone, 0, NoItinerary, "", "",
3097 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3098 Requires<[IsThumb2, NoVFP]>;
3102 //===----------------------------------------------------------------------===//
3103 // Control-Flow Instructions
3106 // FIXME: remove when we have a way to marking a MI with these properties.
3107 // FIXME: Should pc be an implicit operand like PICADD, etc?
3108 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3109 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3110 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3111 reglist:$regs, variable_ops),
3112 4, IIC_iLoad_mBr, [],
3113 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3114 RegConstraint<"$Rn = $wb">;
3116 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3117 let isPredicable = 1 in
3118 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3120 [(br bb:$target)]> {
3121 let Inst{31-27} = 0b11110;
3122 let Inst{15-14} = 0b10;
3126 let Inst{26} = target{19};
3127 let Inst{11} = target{18};
3128 let Inst{13} = target{17};
3129 let Inst{21-16} = target{16-11};
3130 let Inst{10-0} = target{10-0};
3133 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3134 def t2BR_JT : t2PseudoInst<(outs),
3135 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3137 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3139 // FIXME: Add a non-pc based case that can be predicated.
3140 def t2TBB_JT : t2PseudoInst<(outs),
3141 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3143 def t2TBH_JT : t2PseudoInst<(outs),
3144 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3146 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3147 "tbb", "\t$addr", []> {
3150 let Inst{31-20} = 0b111010001101;
3151 let Inst{19-16} = Rn;
3152 let Inst{15-5} = 0b11110000000;
3153 let Inst{4} = 0; // B form
3156 let DecoderMethod = "DecodeThumbTableBranch";
3159 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3160 "tbh", "\t$addr", []> {
3163 let Inst{31-20} = 0b111010001101;
3164 let Inst{19-16} = Rn;
3165 let Inst{15-5} = 0b11110000000;
3166 let Inst{4} = 1; // H form
3169 let DecoderMethod = "DecodeThumbTableBranch";
3171 } // isNotDuplicable, isIndirectBranch
3173 } // isBranch, isTerminator, isBarrier
3175 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3176 // a two-value operand where a dag node expects ", "two operands. :(
3177 let isBranch = 1, isTerminator = 1 in
3178 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3180 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3181 let Inst{31-27} = 0b11110;
3182 let Inst{15-14} = 0b10;
3186 let Inst{25-22} = p;
3189 let Inst{26} = target{20};
3190 let Inst{11} = target{19};
3191 let Inst{13} = target{18};
3192 let Inst{21-16} = target{17-12};
3193 let Inst{10-0} = target{11-1};
3195 let DecoderMethod = "DecodeThumb2BCCInstruction";
3198 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3200 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3202 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3204 def tTAILJMPd: tPseudoExpand<(outs),
3205 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3207 (t2B uncondbrtarget:$dst, pred:$p)>,
3208 Requires<[IsThumb2, IsDarwin]>;
3212 let Defs = [ITSTATE] in
3213 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3214 AddrModeNone, 2, IIC_iALUx,
3215 "it$mask\t$cc", "", []> {
3216 // 16-bit instruction.
3217 let Inst{31-16} = 0x0000;
3218 let Inst{15-8} = 0b10111111;
3223 let Inst{3-0} = mask;
3225 let DecoderMethod = "DecodeIT";
3228 // Branch and Exchange Jazelle -- for disassembly only
3230 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3232 let Inst{31-27} = 0b11110;
3234 let Inst{25-20} = 0b111100;
3235 let Inst{19-16} = func;
3236 let Inst{15-0} = 0b1000111100000000;
3239 // Compare and branch on zero / non-zero
3240 let isBranch = 1, isTerminator = 1 in {
3241 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3242 "cbz\t$Rn, $target", []>,
3243 T1Misc<{0,0,?,1,?,?,?}>,
3244 Requires<[IsThumb2]> {
3248 let Inst{9} = target{5};
3249 let Inst{7-3} = target{4-0};
3253 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3254 "cbnz\t$Rn, $target", []>,
3255 T1Misc<{1,0,?,1,?,?,?}>,
3256 Requires<[IsThumb2]> {
3260 let Inst{9} = target{5};
3261 let Inst{7-3} = target{4-0};
3267 // Change Processor State is a system instruction.
3268 // FIXME: Since the asm parser has currently no clean way to handle optional
3269 // operands, create 3 versions of the same instruction. Once there's a clean
3270 // framework to represent optional operands, change this behavior.
3271 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3272 !strconcat("cps", asm_op), []> {
3278 let Inst{31-27} = 0b11110;
3280 let Inst{25-20} = 0b111010;
3281 let Inst{19-16} = 0b1111;
3282 let Inst{15-14} = 0b10;
3284 let Inst{10-9} = imod;
3286 let Inst{7-5} = iflags;
3287 let Inst{4-0} = mode;
3288 let DecoderMethod = "DecodeT2CPSInstruction";
3292 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3293 "$imod.w\t$iflags, $mode">;
3294 let mode = 0, M = 0 in
3295 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3296 "$imod.w\t$iflags">;
3297 let imod = 0, iflags = 0, M = 1 in
3298 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3300 // A6.3.4 Branches and miscellaneous control
3301 // Table A6-14 Change Processor State, and hint instructions
3302 class T2I_hint<bits<8> op7_0, string opc, string asm>
3303 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3304 let Inst{31-20} = 0xf3a;
3305 let Inst{19-16} = 0b1111;
3306 let Inst{15-14} = 0b10;
3308 let Inst{10-8} = 0b000;
3309 let Inst{7-0} = op7_0;
3312 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3313 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3314 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3315 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3316 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3318 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3320 let Inst{31-20} = 0b111100111010;
3321 let Inst{19-16} = 0b1111;
3322 let Inst{15-8} = 0b10000000;
3323 let Inst{7-4} = 0b1111;
3324 let Inst{3-0} = opt;
3327 // Secure Monitor Call is a system instruction.
3328 // Option = Inst{19-16}
3329 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3330 let Inst{31-27} = 0b11110;
3331 let Inst{26-20} = 0b1111111;
3332 let Inst{15-12} = 0b1000;
3335 let Inst{19-16} = opt;
3338 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3339 string opc, string asm, list<dag> pattern>
3340 : T2I<oops, iops, itin, opc, asm, pattern> {
3342 let Inst{31-25} = 0b1110100;
3343 let Inst{24-23} = Op;
3346 let Inst{20-16} = 0b01101;
3347 let Inst{15-5} = 0b11000000000;
3348 let Inst{4-0} = mode{4-0};
3351 // Store Return State is a system instruction.
3352 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3353 "srsdb", "\tsp!, $mode", []>;
3354 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3355 "srsdb","\tsp, $mode", []>;
3356 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3357 "srsia","\tsp!, $mode", []>;
3358 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3359 "srsia","\tsp, $mode", []>;
3361 // Return From Exception is a system instruction.
3362 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3363 string opc, string asm, list<dag> pattern>
3364 : T2I<oops, iops, itin, opc, asm, pattern> {
3365 let Inst{31-20} = op31_20{11-0};
3368 let Inst{19-16} = Rn;
3369 let Inst{15-0} = 0xc000;
3372 def t2RFEDBW : T2RFE<0b111010000011,
3373 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3374 [/* For disassembly only; pattern left blank */]>;
3375 def t2RFEDB : T2RFE<0b111010000001,
3376 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3377 [/* For disassembly only; pattern left blank */]>;
3378 def t2RFEIAW : T2RFE<0b111010011011,
3379 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3380 [/* For disassembly only; pattern left blank */]>;
3381 def t2RFEIA : T2RFE<0b111010011001,
3382 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3383 [/* For disassembly only; pattern left blank */]>;
3385 //===----------------------------------------------------------------------===//
3386 // Non-Instruction Patterns
3389 // 32-bit immediate using movw + movt.
3390 // This is a single pseudo instruction to make it re-materializable.
3391 // FIXME: Remove this when we can do generalized remat.
3392 let isReMaterializable = 1, isMoveImm = 1 in
3393 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3394 [(set rGPR:$dst, (i32 imm:$src))]>,
3395 Requires<[IsThumb, HasV6T2]>;
3397 // Pseudo instruction that combines movw + movt + add pc (if pic).
3398 // It also makes it possible to rematerialize the instructions.
3399 // FIXME: Remove this when we can do generalized remat and when machine licm
3400 // can properly the instructions.
3401 let isReMaterializable = 1 in {
3402 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3404 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3405 Requires<[IsThumb2, UseMovt]>;
3407 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3409 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3410 Requires<[IsThumb2, UseMovt]>;
3413 // ConstantPool, GlobalAddress, and JumpTable
3414 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3415 Requires<[IsThumb2, DontUseMovt]>;
3416 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3417 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3418 Requires<[IsThumb2, UseMovt]>;
3420 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3421 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3423 // Pseudo instruction that combines ldr from constpool and add pc. This should
3424 // be expanded into two instructions late to allow if-conversion and
3426 let canFoldAsLoad = 1, isReMaterializable = 1 in
3427 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3429 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3431 Requires<[IsThumb2]>;
3432 //===----------------------------------------------------------------------===//
3433 // Coprocessor load/store -- for disassembly only
3435 class T2CI<dag oops, dag iops, string opc, string asm>
3436 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3437 let Inst{27-25} = 0b110;
3440 multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
3441 def _OFFSET : T2CI<(outs),
3442 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3443 opc, "\tp$cop, cr$CRd, $addr"> {
3444 let Inst{31-28} = op31_28;
3445 let Inst{24} = 1; // P = 1
3446 let Inst{21} = 0; // W = 0
3447 let Inst{22} = 0; // D = 0
3448 let Inst{20} = load;
3449 let DecoderMethod = "DecodeCopMemInstruction";
3452 def _PRE : T2CI<(outs),
3453 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3454 opc, "\tp$cop, cr$CRd, $addr!"> {
3455 let Inst{31-28} = op31_28;
3456 let Inst{24} = 1; // P = 1
3457 let Inst{21} = 1; // W = 1
3458 let Inst{22} = 0; // D = 0
3459 let Inst{20} = load;
3460 let DecoderMethod = "DecodeCopMemInstruction";
3463 def _POST : T2CI<(outs),
3464 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3465 opc, "\tp$cop, cr$CRd, $addr"> {
3466 let Inst{31-28} = op31_28;
3467 let Inst{24} = 0; // P = 0
3468 let Inst{21} = 1; // W = 1
3469 let Inst{22} = 0; // D = 0
3470 let Inst{20} = load;
3471 let DecoderMethod = "DecodeCopMemInstruction";
3474 def _OPTION : T2CI<(outs),
3475 (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3476 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3477 let Inst{31-28} = op31_28;
3478 let Inst{24} = 0; // P = 0
3479 let Inst{23} = 1; // U = 1
3480 let Inst{21} = 0; // W = 0
3481 let Inst{22} = 0; // D = 0
3482 let Inst{20} = load;
3483 let DecoderMethod = "DecodeCopMemInstruction";
3486 def L_OFFSET : T2CI<(outs),
3487 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3488 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3489 let Inst{31-28} = op31_28;
3490 let Inst{24} = 1; // P = 1
3491 let Inst{21} = 0; // W = 0
3492 let Inst{22} = 1; // D = 1
3493 let Inst{20} = load;
3494 let DecoderMethod = "DecodeCopMemInstruction";
3497 def L_PRE : T2CI<(outs),
3498 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3499 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3500 let Inst{31-28} = op31_28;
3501 let Inst{24} = 1; // P = 1
3502 let Inst{21} = 1; // W = 1
3503 let Inst{22} = 1; // D = 1
3504 let Inst{20} = load;
3505 let DecoderMethod = "DecodeCopMemInstruction";
3508 def L_POST : T2CI<(outs),
3509 (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
3510 postidx_imm8s4:$offset),
3511 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
3512 let Inst{31-28} = op31_28;
3513 let Inst{24} = 0; // P = 0
3514 let Inst{21} = 1; // W = 1
3515 let Inst{22} = 1; // D = 1
3516 let Inst{20} = load;
3517 let DecoderMethod = "DecodeCopMemInstruction";
3520 def L_OPTION : T2CI<(outs),
3521 (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3522 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3523 let Inst{31-28} = op31_28;
3524 let Inst{24} = 0; // P = 0
3525 let Inst{23} = 1; // U = 1
3526 let Inst{21} = 0; // W = 0
3527 let Inst{22} = 1; // D = 1
3528 let Inst{20} = load;
3529 let DecoderMethod = "DecodeCopMemInstruction";
3533 defm t2LDC : T2LdStCop<0b1111, 1, "ldc">;
3534 defm t2STC : T2LdStCop<0b1111, 0, "stc">;
3537 //===----------------------------------------------------------------------===//
3538 // Move between special register and ARM core register -- for disassembly only
3540 // Move to ARM core register from Special Register
3541 def t2MRS : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> {
3543 let Inst{31-12} = 0b11110011111011111000;
3544 let Inst{11-8} = Rd;
3545 let Inst{7-0} = 0b0000;
3548 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS GPR:$Rd, pred:$p)>;
3550 def t2MRSsys:T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> {
3552 let Inst{31-12} = 0b11110011111111111000;
3553 let Inst{11-8} = Rd;
3554 let Inst{7-0} = 0b0000;
3557 // Move from ARM core register to Special Register
3559 // No need to have both system and application versions, the encodings are the
3560 // same and the assembly parser has no way to distinguish between them. The mask
3561 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3562 // the mask with the fields to be accessed in the special register.
3563 def t2MSR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3564 NoItinerary, "msr", "\t$mask, $Rn", []> {
3567 let Inst{31-21} = 0b11110011100;
3568 let Inst{20} = mask{4}; // R Bit
3569 let Inst{19-16} = Rn;
3570 let Inst{15-12} = 0b1000;
3571 let Inst{11-8} = mask{3-0};
3575 //===----------------------------------------------------------------------===//
3576 // Move between coprocessor and ARM core register
3579 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3581 : T2Cop<Op, oops, iops,
3582 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3584 let Inst{27-24} = 0b1110;
3585 let Inst{20} = direction;
3595 let Inst{15-12} = Rt;
3596 let Inst{11-8} = cop;
3597 let Inst{23-21} = opc1;
3598 let Inst{7-5} = opc2;
3599 let Inst{3-0} = CRm;
3600 let Inst{19-16} = CRn;
3603 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3604 list<dag> pattern = []>
3606 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3607 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3608 let Inst{27-24} = 0b1100;
3609 let Inst{23-21} = 0b010;
3610 let Inst{20} = direction;
3618 let Inst{15-12} = Rt;
3619 let Inst{19-16} = Rt2;
3620 let Inst{11-8} = cop;
3621 let Inst{7-4} = opc1;
3622 let Inst{3-0} = CRm;
3625 /* from ARM core register to coprocessor */
3626 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3628 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3629 c_imm:$CRm, imm0_7:$opc2),
3630 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3631 imm:$CRm, imm:$opc2)]>;
3632 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3633 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3634 c_imm:$CRm, imm0_7:$opc2),
3635 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3636 imm:$CRm, imm:$opc2)]>;
3638 /* from coprocessor to ARM core register */
3639 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3640 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3641 c_imm:$CRm, imm0_7:$opc2), []>;
3643 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3644 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3645 c_imm:$CRm, imm0_7:$opc2), []>;
3647 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3648 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3650 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3651 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3654 /* from ARM core register to coprocessor */
3655 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3656 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3658 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3659 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3660 GPR:$Rt2, imm:$CRm)]>;
3661 /* from coprocessor to ARM core register */
3662 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3664 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3666 //===----------------------------------------------------------------------===//
3667 // Other Coprocessor Instructions.
3670 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3671 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3672 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3673 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3674 imm:$CRm, imm:$opc2)]> {
3675 let Inst{27-24} = 0b1110;
3684 let Inst{3-0} = CRm;
3686 let Inst{7-5} = opc2;
3687 let Inst{11-8} = cop;
3688 let Inst{15-12} = CRd;
3689 let Inst{19-16} = CRn;
3690 let Inst{23-20} = opc1;
3693 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3694 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3695 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3696 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3697 imm:$CRm, imm:$opc2)]> {
3698 let Inst{27-24} = 0b1110;
3707 let Inst{3-0} = CRm;
3709 let Inst{7-5} = opc2;
3710 let Inst{11-8} = cop;
3711 let Inst{15-12} = CRd;
3712 let Inst{19-16} = CRn;
3713 let Inst{23-20} = opc1;
3718 //===----------------------------------------------------------------------===//
3719 // Non-Instruction Patterns
3722 // SXT/UXT with no rotate
3723 let AddedComplexity = 16 in {
3724 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3725 Requires<[IsThumb2]>;
3726 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3727 Requires<[IsThumb2]>;
3728 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3729 Requires<[HasT2ExtractPack, IsThumb2]>;
3730 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3731 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3732 Requires<[HasT2ExtractPack, IsThumb2]>;
3733 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3734 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3735 Requires<[HasT2ExtractPack, IsThumb2]>;
3738 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3739 Requires<[IsThumb2]>;
3740 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3741 Requires<[IsThumb2]>;
3742 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3743 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3744 Requires<[HasT2ExtractPack, IsThumb2]>;
3745 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3746 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3747 Requires<[HasT2ExtractPack, IsThumb2]>;
3749 // Atomic load/store patterns
3750 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3751 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3752 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3753 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3754 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3755 (t2LDRBs t2addrmode_so_reg:$addr)>;
3756 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3757 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3758 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3759 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3760 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3761 (t2LDRHs t2addrmode_so_reg:$addr)>;
3762 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3763 (t2LDRi12 t2addrmode_imm12:$addr)>;
3764 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3765 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3766 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3767 (t2LDRs t2addrmode_so_reg:$addr)>;
3768 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3769 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3770 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3771 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3772 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3773 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3774 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3775 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3776 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3777 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3778 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3779 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3780 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3781 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3782 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3783 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3784 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3785 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3788 //===----------------------------------------------------------------------===//
3789 // Assembler aliases
3792 // Aliases for ADC without the ".w" optional width specifier.
3793 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3794 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3795 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3796 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3797 pred:$p, cc_out:$s)>;
3799 // Aliases for SBC without the ".w" optional width specifier.
3800 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3801 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3802 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3803 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3804 pred:$p, cc_out:$s)>;
3806 // Aliases for ADD without the ".w" optional width specifier.
3807 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3808 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3809 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3810 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3811 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3812 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3813 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3814 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3815 pred:$p, cc_out:$s)>;
3817 // Aliases for SUB without the ".w" optional width specifier.
3818 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3819 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3820 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3821 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3822 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3823 (t2SUBrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3824 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3825 (t2SUBrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3826 pred:$p, cc_out:$s)>;
3828 // Alias for compares without the ".w" optional width specifier.
3829 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3830 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3831 def : t2InstAlias<"teq${p} $Rn, $Rm",
3832 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3833 def : t2InstAlias<"tst${p} $Rn, $Rm",
3834 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3837 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3838 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3839 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3841 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3843 def : t2InstAlias<"ldr${p} $Rt, $addr",
3844 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3845 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3846 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3847 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3848 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3849 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3850 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3851 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3852 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3854 def : t2InstAlias<"ldr${p} $Rt, $addr",
3855 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3856 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3857 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3858 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3859 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3860 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3861 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3862 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3863 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3865 // Alias for MVN without the ".w" optional width specifier.
3866 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
3867 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
3868 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
3869 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
3871 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
3872 // shift amount is zero (i.e., unspecified).
3873 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
3874 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3875 Requires<[HasT2ExtractPack, IsThumb2]>;
3876 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
3877 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3878 Requires<[HasT2ExtractPack, IsThumb2]>;
3880 // PUSH/POP aliases for STM/LDM
3881 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3882 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3883 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3884 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3886 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
3887 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3888 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3889 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3892 // Alias for RSB without the ".w" optional width specifier, and with optional
3893 // implied destination register.
3894 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
3895 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3896 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
3897 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3898 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
3899 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3900 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
3901 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
3904 // SSAT/USAT optional shift operand.
3905 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
3906 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3907 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
3908 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3910 // STM w/o the .w suffix.
3911 def : t2InstAlias<"stm${p} $Rn, $regs",
3912 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
3914 // Alias for STR, STRB, and STRH without the ".w" optional
3916 def : t2InstAlias<"str${p} $Rt, $addr",
3917 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3918 def : t2InstAlias<"strb${p} $Rt, $addr",
3919 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3920 def : t2InstAlias<"strh${p} $Rt, $addr",
3921 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3923 def : t2InstAlias<"str${p} $Rt, $addr",
3924 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3925 def : t2InstAlias<"strb${p} $Rt, $addr",
3926 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3927 def : t2InstAlias<"strh${p} $Rt, $addr",
3928 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3930 // Extend instruction optional rotate operand.
3931 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
3932 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3933 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
3934 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3935 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
3936 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3937 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
3938 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3939 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
3940 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3941 def : t2InstAlias<"sxth${p} $Rd, $Rm",
3942 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3944 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
3945 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3946 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
3947 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3948 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
3949 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3950 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
3951 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3952 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
3953 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3954 def : t2InstAlias<"uxth${p} $Rd, $Rm",
3955 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3957 // Extend instruction w/o the ".w" optional width specifier.
3958 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
3959 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3960 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
3961 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3962 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
3963 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3965 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
3966 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3967 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
3968 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3969 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
3970 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;