1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let EncoderMethod = "getT2SORegOpValue";
30 let PrintMethod = "printT2SOOperand";
31 let MIOperandInfo = (ops rGPR, i32imm);
34 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
44 // t2_so_imm - Match a 32-bit immediate operand, which is an
45 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46 // immediate splatted into multiple bytes of the word.
47 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
48 return ARM_AM::getT2SOImmVal(Imm) != -1;
50 let EncoderMethod = "getT2SOImmOpValue";
53 // t2_so_imm_not - Match an immediate that is a complement
55 def t2_so_imm_not : Operand<i32>,
57 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
58 }], t2_so_imm_not_XFORM>;
60 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
61 def t2_so_imm_neg : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_neg_XFORM>;
66 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
67 def imm1_31 : ImmLeaf<i32, [{
68 return (int32_t)Imm >= 1 && (int32_t)Imm < 32;
71 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
72 def imm0_4095 : Operand<i32>,
74 return Imm >= 0 && Imm < 4096;
77 def imm0_4095_neg : PatLeaf<(i32 imm), [{
78 return (uint32_t)(-N->getZExtValue()) < 4096;
81 def imm0_255_neg : PatLeaf<(i32 imm), [{
82 return (uint32_t)(-N->getZExtValue()) < 255;
85 def imm0_255_not : PatLeaf<(i32 imm), [{
86 return (uint32_t)(~N->getZExtValue()) < 255;
89 def lo5AllOne : PatLeaf<(i32 imm), [{
90 // Returns true if all low 5-bits are 1.
91 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
94 // Define Thumb2 specific addressing modes.
96 // t2addrmode_imm12 := reg + imm12
97 def t2addrmode_imm12 : Operand<i32>,
98 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
99 let PrintMethod = "printAddrModeImm12Operand";
100 let EncoderMethod = "getAddrModeImm12OpValue";
101 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
102 let ParserMatchClass = MemMode5AsmOperand;
105 // t2ldrlabel := imm12
106 def t2ldrlabel : Operand<i32> {
107 let EncoderMethod = "getAddrModeImm12OpValue";
111 // ADR instruction labels.
112 def t2adrlabel : Operand<i32> {
113 let EncoderMethod = "getT2AdrLabelOpValue";
117 // t2addrmode_imm8 := reg +/- imm8
118 def t2addrmode_imm8 : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
120 let PrintMethod = "printT2AddrModeImm8Operand";
121 let EncoderMethod = "getT2AddrModeImm8OpValue";
122 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
123 let ParserMatchClass = MemMode5AsmOperand;
126 def t2am_imm8_offset : Operand<i32>,
127 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
128 [], [SDNPWantRoot]> {
129 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
130 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
131 let ParserMatchClass = MemMode5AsmOperand;
134 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
135 def t2addrmode_imm8s4 : Operand<i32> {
136 let PrintMethod = "printT2AddrModeImm8s4Operand";
137 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
139 let ParserMatchClass = MemMode5AsmOperand;
142 def t2am_imm8s4_offset : Operand<i32> {
143 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
146 // t2addrmode_so_reg := reg + (reg << imm2)
147 def t2addrmode_so_reg : Operand<i32>,
148 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
149 let PrintMethod = "printT2AddrModeSoRegOperand";
150 let EncoderMethod = "getT2AddrModeSORegOpValue";
151 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
152 let ParserMatchClass = MemMode5AsmOperand;
155 // t2addrmode_reg := reg
156 // Used by load/store exclusive instructions. Useful to enable right assembly
157 // parsing and printing. Not used for any codegen matching.
159 def t2addrmode_reg : Operand<i32> {
160 let PrintMethod = "printAddrMode7Operand";
161 let MIOperandInfo = (ops GPR);
162 let ParserMatchClass = MemMode7AsmOperand;
165 //===----------------------------------------------------------------------===//
166 // Multiclass helpers...
170 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
171 string opc, string asm, list<dag> pattern>
172 : T2I<oops, iops, itin, opc, asm, pattern> {
177 let Inst{26} = imm{11};
178 let Inst{14-12} = imm{10-8};
179 let Inst{7-0} = imm{7-0};
183 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
184 string opc, string asm, list<dag> pattern>
185 : T2sI<oops, iops, itin, opc, asm, pattern> {
191 let Inst{26} = imm{11};
192 let Inst{14-12} = imm{10-8};
193 let Inst{7-0} = imm{7-0};
196 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
197 string opc, string asm, list<dag> pattern>
198 : T2I<oops, iops, itin, opc, asm, pattern> {
202 let Inst{19-16} = Rn;
203 let Inst{26} = imm{11};
204 let Inst{14-12} = imm{10-8};
205 let Inst{7-0} = imm{7-0};
209 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
210 string opc, string asm, list<dag> pattern>
211 : T2I<oops, iops, itin, opc, asm, pattern> {
216 let Inst{3-0} = ShiftedRm{3-0};
217 let Inst{5-4} = ShiftedRm{6-5};
218 let Inst{14-12} = ShiftedRm{11-9};
219 let Inst{7-6} = ShiftedRm{8-7};
222 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
223 string opc, string asm, list<dag> pattern>
224 : T2sI<oops, iops, itin, opc, asm, pattern> {
229 let Inst{3-0} = ShiftedRm{3-0};
230 let Inst{5-4} = ShiftedRm{6-5};
231 let Inst{14-12} = ShiftedRm{11-9};
232 let Inst{7-6} = ShiftedRm{8-7};
235 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
236 string opc, string asm, list<dag> pattern>
237 : T2I<oops, iops, itin, opc, asm, pattern> {
241 let Inst{19-16} = Rn;
242 let Inst{3-0} = ShiftedRm{3-0};
243 let Inst{5-4} = ShiftedRm{6-5};
244 let Inst{14-12} = ShiftedRm{11-9};
245 let Inst{7-6} = ShiftedRm{8-7};
248 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
249 string opc, string asm, list<dag> pattern>
250 : T2I<oops, iops, itin, opc, asm, pattern> {
258 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
259 string opc, string asm, list<dag> pattern>
260 : T2sI<oops, iops, itin, opc, asm, pattern> {
268 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
269 string opc, string asm, list<dag> pattern>
270 : T2I<oops, iops, itin, opc, asm, pattern> {
274 let Inst{19-16} = Rn;
279 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
280 string opc, string asm, list<dag> pattern>
281 : T2I<oops, iops, itin, opc, asm, pattern> {
287 let Inst{19-16} = Rn;
288 let Inst{26} = imm{11};
289 let Inst{14-12} = imm{10-8};
290 let Inst{7-0} = imm{7-0};
293 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
294 string opc, string asm, list<dag> pattern>
295 : T2sI<oops, iops, itin, opc, asm, pattern> {
301 let Inst{19-16} = Rn;
302 let Inst{26} = imm{11};
303 let Inst{14-12} = imm{10-8};
304 let Inst{7-0} = imm{7-0};
307 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
308 string opc, string asm, list<dag> pattern>
309 : T2I<oops, iops, itin, opc, asm, pattern> {
316 let Inst{14-12} = imm{4-2};
317 let Inst{7-6} = imm{1-0};
320 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
321 string opc, string asm, list<dag> pattern>
322 : T2sI<oops, iops, itin, opc, asm, pattern> {
329 let Inst{14-12} = imm{4-2};
330 let Inst{7-6} = imm{1-0};
333 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
334 string opc, string asm, list<dag> pattern>
335 : T2I<oops, iops, itin, opc, asm, pattern> {
341 let Inst{19-16} = Rn;
345 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
346 string opc, string asm, list<dag> pattern>
347 : T2sI<oops, iops, itin, opc, asm, pattern> {
353 let Inst{19-16} = Rn;
357 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
358 string opc, string asm, list<dag> pattern>
359 : T2I<oops, iops, itin, opc, asm, pattern> {
365 let Inst{19-16} = Rn;
366 let Inst{3-0} = ShiftedRm{3-0};
367 let Inst{5-4} = ShiftedRm{6-5};
368 let Inst{14-12} = ShiftedRm{11-9};
369 let Inst{7-6} = ShiftedRm{8-7};
372 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
373 string opc, string asm, list<dag> pattern>
374 : T2sI<oops, iops, itin, opc, asm, pattern> {
380 let Inst{19-16} = Rn;
381 let Inst{3-0} = ShiftedRm{3-0};
382 let Inst{5-4} = ShiftedRm{6-5};
383 let Inst{14-12} = ShiftedRm{11-9};
384 let Inst{7-6} = ShiftedRm{8-7};
387 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
388 string opc, string asm, list<dag> pattern>
389 : T2I<oops, iops, itin, opc, asm, pattern> {
395 let Inst{19-16} = Rn;
396 let Inst{15-12} = Ra;
401 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
402 dag oops, dag iops, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : T2I<oops, iops, itin, opc, asm, pattern> {
410 let Inst{31-23} = 0b111110111;
411 let Inst{22-20} = opc22_20;
412 let Inst{19-16} = Rn;
413 let Inst{15-12} = RdLo;
414 let Inst{11-8} = RdHi;
415 let Inst{7-4} = opc7_4;
420 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
421 /// unary operation that produces a value. These are predicable and can be
422 /// changed to modify CPSR.
423 multiclass T2I_un_irs<bits<4> opcod, string opc,
424 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
425 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
427 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
429 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
430 let isAsCheapAsAMove = Cheap;
431 let isReMaterializable = ReMat;
432 let Inst{31-27} = 0b11110;
434 let Inst{24-21} = opcod;
435 let Inst{19-16} = 0b1111; // Rn
439 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
441 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
442 let Inst{31-27} = 0b11101;
443 let Inst{26-25} = 0b01;
444 let Inst{24-21} = opcod;
445 let Inst{19-16} = 0b1111; // Rn
446 let Inst{14-12} = 0b000; // imm3
447 let Inst{7-6} = 0b00; // imm2
448 let Inst{5-4} = 0b00; // type
451 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
452 opc, ".w\t$Rd, $ShiftedRm",
453 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
454 let Inst{31-27} = 0b11101;
455 let Inst{26-25} = 0b01;
456 let Inst{24-21} = opcod;
457 let Inst{19-16} = 0b1111; // Rn
461 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
462 /// binary operation that produces a value. These are predicable and can be
463 /// changed to modify CPSR.
464 multiclass T2I_bin_irs<bits<4> opcod, string opc,
465 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
466 PatFrag opnode, bit Commutable = 0, string wide = ""> {
468 def ri : T2sTwoRegImm<
469 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
470 opc, "\t$Rd, $Rn, $imm",
471 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
472 let Inst{31-27} = 0b11110;
474 let Inst{24-21} = opcod;
478 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
479 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
480 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
481 let isCommutable = Commutable;
482 let Inst{31-27} = 0b11101;
483 let Inst{26-25} = 0b01;
484 let Inst{24-21} = opcod;
485 let Inst{14-12} = 0b000; // imm3
486 let Inst{7-6} = 0b00; // imm2
487 let Inst{5-4} = 0b00; // type
490 def rs : T2sTwoRegShiftedReg<
491 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
492 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
493 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
494 let Inst{31-27} = 0b11101;
495 let Inst{26-25} = 0b01;
496 let Inst{24-21} = opcod;
500 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
501 // the ".w" prefix to indicate that they are wide.
502 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
503 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
504 PatFrag opnode, bit Commutable = 0> :
505 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">;
507 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
508 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
509 /// it is equivalent to the T2I_bin_irs counterpart.
510 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
512 def ri : T2sTwoRegImm<
513 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
514 opc, ".w\t$Rd, $Rn, $imm",
515 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
516 let Inst{31-27} = 0b11110;
518 let Inst{24-21} = opcod;
522 def rr : T2sThreeReg<
523 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
524 opc, "\t$Rd, $Rn, $Rm",
525 [/* For disassembly only; pattern left blank */]> {
526 let Inst{31-27} = 0b11101;
527 let Inst{26-25} = 0b01;
528 let Inst{24-21} = opcod;
529 let Inst{14-12} = 0b000; // imm3
530 let Inst{7-6} = 0b00; // imm2
531 let Inst{5-4} = 0b00; // type
534 def rs : T2sTwoRegShiftedReg<
535 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
536 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
537 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
538 let Inst{31-27} = 0b11101;
539 let Inst{26-25} = 0b01;
540 let Inst{24-21} = opcod;
544 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
545 /// instruction modifies the CPSR register.
546 let isCodeGenOnly = 1, Defs = [CPSR] in {
547 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
548 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
549 PatFrag opnode, bit Commutable = 0> {
551 def ri : T2TwoRegImm<
552 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
553 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
554 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
555 let Inst{31-27} = 0b11110;
557 let Inst{24-21} = opcod;
558 let Inst{20} = 1; // The S bit.
563 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
564 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
565 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
566 let isCommutable = Commutable;
567 let Inst{31-27} = 0b11101;
568 let Inst{26-25} = 0b01;
569 let Inst{24-21} = opcod;
570 let Inst{20} = 1; // The S bit.
571 let Inst{14-12} = 0b000; // imm3
572 let Inst{7-6} = 0b00; // imm2
573 let Inst{5-4} = 0b00; // type
576 def rs : T2TwoRegShiftedReg<
577 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
578 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
579 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
580 let Inst{31-27} = 0b11101;
581 let Inst{26-25} = 0b01;
582 let Inst{24-21} = opcod;
583 let Inst{20} = 1; // The S bit.
588 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
589 /// patterns for a binary operation that produces a value.
590 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
591 bit Commutable = 0> {
593 // The register-immediate version is re-materializable. This is useful
594 // in particular for taking the address of a local.
595 let isReMaterializable = 1 in {
596 def ri : T2sTwoRegImm<
597 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
598 opc, ".w\t$Rd, $Rn, $imm",
599 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
600 let Inst{31-27} = 0b11110;
603 let Inst{23-21} = op23_21;
609 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
610 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
611 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
615 let Inst{31-27} = 0b11110;
616 let Inst{26} = imm{11};
617 let Inst{25-24} = 0b10;
618 let Inst{23-21} = op23_21;
619 let Inst{20} = 0; // The S bit.
620 let Inst{19-16} = Rn;
622 let Inst{14-12} = imm{10-8};
624 let Inst{7-0} = imm{7-0};
627 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
628 opc, ".w\t$Rd, $Rn, $Rm",
629 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
630 let isCommutable = Commutable;
631 let Inst{31-27} = 0b11101;
632 let Inst{26-25} = 0b01;
634 let Inst{23-21} = op23_21;
635 let Inst{14-12} = 0b000; // imm3
636 let Inst{7-6} = 0b00; // imm2
637 let Inst{5-4} = 0b00; // type
640 def rs : T2sTwoRegShiftedReg<
641 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
642 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
643 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
644 let Inst{31-27} = 0b11101;
645 let Inst{26-25} = 0b01;
647 let Inst{23-21} = op23_21;
651 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
652 /// for a binary operation that produces a value and use the carry
653 /// bit. It's not predicable.
654 let Uses = [CPSR] in {
655 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
656 bit Commutable = 0> {
658 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
659 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
660 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
661 Requires<[IsThumb2]> {
662 let Inst{31-27} = 0b11110;
664 let Inst{24-21} = opcod;
668 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
669 opc, ".w\t$Rd, $Rn, $Rm",
670 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
671 Requires<[IsThumb2]> {
672 let isCommutable = Commutable;
673 let Inst{31-27} = 0b11101;
674 let Inst{26-25} = 0b01;
675 let Inst{24-21} = opcod;
676 let Inst{14-12} = 0b000; // imm3
677 let Inst{7-6} = 0b00; // imm2
678 let Inst{5-4} = 0b00; // type
681 def rs : T2sTwoRegShiftedReg<
682 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
683 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
684 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
685 Requires<[IsThumb2]> {
686 let Inst{31-27} = 0b11101;
687 let Inst{26-25} = 0b01;
688 let Inst{24-21} = opcod;
693 // Carry setting variants
694 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
695 let usesCustomInserter = 1 in {
696 multiclass T2I_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
698 def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
699 Size4Bytes, IIC_iALUi,
700 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>;
702 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
703 Size4Bytes, IIC_iALUr,
704 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
705 let isCommutable = Commutable;
708 def rs : t2PseudoInst<
709 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
710 Size4Bytes, IIC_iALUsi,
711 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>;
715 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
716 /// version is not needed since this is only for codegen.
717 let isCodeGenOnly = 1, Defs = [CPSR] in {
718 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
720 def ri : T2TwoRegImm<
721 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
722 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
723 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
724 let Inst{31-27} = 0b11110;
726 let Inst{24-21} = opcod;
727 let Inst{20} = 1; // The S bit.
731 def rs : T2TwoRegShiftedReg<
732 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
733 IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
734 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
735 let Inst{31-27} = 0b11101;
736 let Inst{26-25} = 0b01;
737 let Inst{24-21} = opcod;
738 let Inst{20} = 1; // The S bit.
743 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
744 // rotate operation that produces a value.
745 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
747 def ri : T2sTwoRegShiftImm<
748 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
749 opc, ".w\t$Rd, $Rm, $imm",
750 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
751 let Inst{31-27} = 0b11101;
752 let Inst{26-21} = 0b010010;
753 let Inst{19-16} = 0b1111; // Rn
754 let Inst{5-4} = opcod;
757 def rr : T2sThreeReg<
758 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
759 opc, ".w\t$Rd, $Rn, $Rm",
760 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
761 let Inst{31-27} = 0b11111;
762 let Inst{26-23} = 0b0100;
763 let Inst{22-21} = opcod;
764 let Inst{15-12} = 0b1111;
765 let Inst{7-4} = 0b0000;
769 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
770 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
771 /// a explicit result, only implicitly set CPSR.
772 let isCompare = 1, Defs = [CPSR] in {
773 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
774 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
777 def ri : T2OneRegCmpImm<
778 (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
779 opc, ".w\t$Rn, $imm",
780 [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
781 let Inst{31-27} = 0b11110;
783 let Inst{24-21} = opcod;
784 let Inst{20} = 1; // The S bit.
786 let Inst{11-8} = 0b1111; // Rd
789 def rr : T2TwoRegCmp<
790 (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
791 opc, ".w\t$lhs, $rhs",
792 [(opnode GPR:$lhs, rGPR:$rhs)]> {
793 let Inst{31-27} = 0b11101;
794 let Inst{26-25} = 0b01;
795 let Inst{24-21} = opcod;
796 let Inst{20} = 1; // The S bit.
797 let Inst{14-12} = 0b000; // imm3
798 let Inst{11-8} = 0b1111; // Rd
799 let Inst{7-6} = 0b00; // imm2
800 let Inst{5-4} = 0b00; // type
803 def rs : T2OneRegCmpShiftedReg<
804 (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
805 opc, ".w\t$Rn, $ShiftedRm",
806 [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
807 let Inst{31-27} = 0b11101;
808 let Inst{26-25} = 0b01;
809 let Inst{24-21} = opcod;
810 let Inst{20} = 1; // The S bit.
811 let Inst{11-8} = 0b1111; // Rd
816 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
817 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
818 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
819 def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
820 opc, ".w\t$Rt, $addr",
821 [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
822 let Inst{31-27} = 0b11111;
823 let Inst{26-25} = 0b00;
824 let Inst{24} = signed;
826 let Inst{22-21} = opcod;
827 let Inst{20} = 1; // load
830 let Inst{15-12} = Rt;
833 let addr{12} = 1; // add = TRUE
834 let Inst{19-16} = addr{16-13}; // Rn
835 let Inst{23} = addr{12}; // U
836 let Inst{11-0} = addr{11-0}; // imm
838 def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
840 [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
841 let Inst{31-27} = 0b11111;
842 let Inst{26-25} = 0b00;
843 let Inst{24} = signed;
845 let Inst{22-21} = opcod;
846 let Inst{20} = 1; // load
848 // Offset: index==TRUE, wback==FALSE
849 let Inst{10} = 1; // The P bit.
850 let Inst{8} = 0; // The W bit.
853 let Inst{15-12} = Rt;
856 let Inst{19-16} = addr{12-9}; // Rn
857 let Inst{9} = addr{8}; // U
858 let Inst{7-0} = addr{7-0}; // imm
860 def s : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
861 opc, ".w\t$Rt, $addr",
862 [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
863 let Inst{31-27} = 0b11111;
864 let Inst{26-25} = 0b00;
865 let Inst{24} = signed;
867 let Inst{22-21} = opcod;
868 let Inst{20} = 1; // load
869 let Inst{11-6} = 0b000000;
872 let Inst{15-12} = Rt;
875 let Inst{19-16} = addr{9-6}; // Rn
876 let Inst{3-0} = addr{5-2}; // Rm
877 let Inst{5-4} = addr{1-0}; // imm
880 // FIXME: Is the pci variant actually needed?
881 def pci : T2Ipc <(outs GPR:$Rt), (ins t2ldrlabel:$addr), iii,
882 opc, ".w\t$Rt, $addr",
883 [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
884 let isReMaterializable = 1;
885 let Inst{31-27} = 0b11111;
886 let Inst{26-25} = 0b00;
887 let Inst{24} = signed;
888 let Inst{23} = ?; // add = (U == '1')
889 let Inst{22-21} = opcod;
890 let Inst{20} = 1; // load
891 let Inst{19-16} = 0b1111; // Rn
894 let Inst{15-12} = Rt{3-0};
895 let Inst{11-0} = addr{11-0};
899 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
900 multiclass T2I_st<bits<2> opcod, string opc,
901 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
902 def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
903 opc, ".w\t$Rt, $addr",
904 [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
905 let Inst{31-27} = 0b11111;
906 let Inst{26-23} = 0b0001;
907 let Inst{22-21} = opcod;
908 let Inst{20} = 0; // !load
911 let Inst{15-12} = Rt;
914 let addr{12} = 1; // add = TRUE
915 let Inst{19-16} = addr{16-13}; // Rn
916 let Inst{23} = addr{12}; // U
917 let Inst{11-0} = addr{11-0}; // imm
919 def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
921 [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
922 let Inst{31-27} = 0b11111;
923 let Inst{26-23} = 0b0000;
924 let Inst{22-21} = opcod;
925 let Inst{20} = 0; // !load
927 // Offset: index==TRUE, wback==FALSE
928 let Inst{10} = 1; // The P bit.
929 let Inst{8} = 0; // The W bit.
932 let Inst{15-12} = Rt;
935 let Inst{19-16} = addr{12-9}; // Rn
936 let Inst{9} = addr{8}; // U
937 let Inst{7-0} = addr{7-0}; // imm
939 def s : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
940 opc, ".w\t$Rt, $addr",
941 [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
942 let Inst{31-27} = 0b11111;
943 let Inst{26-23} = 0b0000;
944 let Inst{22-21} = opcod;
945 let Inst{20} = 0; // !load
946 let Inst{11-6} = 0b000000;
949 let Inst{15-12} = Rt;
952 let Inst{19-16} = addr{9-6}; // Rn
953 let Inst{3-0} = addr{5-2}; // Rm
954 let Inst{5-4} = addr{1-0}; // imm
958 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
959 /// register and one whose operand is a register rotated by 8/16/24.
960 multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
961 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
963 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
964 let Inst{31-27} = 0b11111;
965 let Inst{26-23} = 0b0100;
966 let Inst{22-20} = opcod;
967 let Inst{19-16} = 0b1111; // Rn
968 let Inst{15-12} = 0b1111;
970 let Inst{5-4} = 0b00; // rotate
972 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
973 opc, ".w\t$Rd, $Rm, ror $rot",
974 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
975 let Inst{31-27} = 0b11111;
976 let Inst{26-23} = 0b0100;
977 let Inst{22-20} = opcod;
978 let Inst{19-16} = 0b1111; // Rn
979 let Inst{15-12} = 0b1111;
983 let Inst{5-4} = rot{1-0}; // rotate
987 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
988 multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
989 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
991 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
992 Requires<[HasT2ExtractPack, IsThumb2]> {
993 let Inst{31-27} = 0b11111;
994 let Inst{26-23} = 0b0100;
995 let Inst{22-20} = opcod;
996 let Inst{19-16} = 0b1111; // Rn
997 let Inst{15-12} = 0b1111;
999 let Inst{5-4} = 0b00; // rotate
1001 def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
1002 IIC_iEXTr, opc, "\t$dst, $Rm, ror $rot",
1003 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1004 Requires<[HasT2ExtractPack, IsThumb2]> {
1005 let Inst{31-27} = 0b11111;
1006 let Inst{26-23} = 0b0100;
1007 let Inst{22-20} = opcod;
1008 let Inst{19-16} = 0b1111; // Rn
1009 let Inst{15-12} = 0b1111;
1013 let Inst{5-4} = rot{1-0}; // rotate
1017 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1019 multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1020 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1021 opc, "\t$Rd, $Rm", []> {
1022 let Inst{31-27} = 0b11111;
1023 let Inst{26-23} = 0b0100;
1024 let Inst{22-20} = opcod;
1025 let Inst{19-16} = 0b1111; // Rn
1026 let Inst{15-12} = 0b1111;
1028 let Inst{5-4} = 0b00; // rotate
1030 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1031 opc, "\t$Rd, $Rm, ror $rot", []> {
1032 let Inst{31-27} = 0b11111;
1033 let Inst{26-23} = 0b0100;
1034 let Inst{22-20} = opcod;
1035 let Inst{19-16} = 0b1111; // Rn
1036 let Inst{15-12} = 0b1111;
1040 let Inst{5-4} = rot{1-0}; // rotate
1044 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1045 /// register and one whose operand is a register rotated by 8/16/24.
1046 multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1047 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1048 opc, "\t$Rd, $Rn, $Rm",
1049 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1050 Requires<[HasT2ExtractPack, IsThumb2]> {
1051 let Inst{31-27} = 0b11111;
1052 let Inst{26-23} = 0b0100;
1053 let Inst{22-20} = opcod;
1054 let Inst{15-12} = 0b1111;
1056 let Inst{5-4} = 0b00; // rotate
1058 def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
1059 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1060 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1061 [(set rGPR:$Rd, (opnode rGPR:$Rn,
1062 (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1063 Requires<[HasT2ExtractPack, IsThumb2]> {
1064 let Inst{31-27} = 0b11111;
1065 let Inst{26-23} = 0b0100;
1066 let Inst{22-20} = opcod;
1067 let Inst{15-12} = 0b1111;
1071 let Inst{5-4} = rot{1-0}; // rotate
1075 // DO variant - disassembly only, no pattern
1077 multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
1078 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1079 opc, "\t$Rd, $Rn, $Rm", []> {
1080 let Inst{31-27} = 0b11111;
1081 let Inst{26-23} = 0b0100;
1082 let Inst{22-20} = opcod;
1083 let Inst{15-12} = 0b1111;
1085 let Inst{5-4} = 0b00; // rotate
1087 def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1088 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
1089 let Inst{31-27} = 0b11111;
1090 let Inst{26-23} = 0b0100;
1091 let Inst{22-20} = opcod;
1092 let Inst{15-12} = 0b1111;
1096 let Inst{5-4} = rot{1-0}; // rotate
1100 //===----------------------------------------------------------------------===//
1102 //===----------------------------------------------------------------------===//
1104 //===----------------------------------------------------------------------===//
1105 // Miscellaneous Instructions.
1108 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1109 string asm, list<dag> pattern>
1110 : T2XI<oops, iops, itin, asm, pattern> {
1114 let Inst{11-8} = Rd;
1115 let Inst{26} = label{11};
1116 let Inst{14-12} = label{10-8};
1117 let Inst{7-0} = label{7-0};
1120 // LEApcrel - Load a pc-relative address into a register without offending the
1122 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1123 (ins t2adrlabel:$addr, pred:$p),
1124 IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1125 let Inst{31-27} = 0b11110;
1126 let Inst{25-24} = 0b10;
1127 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1130 let Inst{19-16} = 0b1111; // Rn
1135 let Inst{11-8} = Rd;
1136 let Inst{23} = addr{12};
1137 let Inst{21} = addr{12};
1138 let Inst{26} = addr{11};
1139 let Inst{14-12} = addr{10-8};
1140 let Inst{7-0} = addr{7-0};
1143 let neverHasSideEffects = 1, isReMaterializable = 1 in
1144 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1145 Size4Bytes, IIC_iALUi, []>;
1146 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1147 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1148 Size4Bytes, IIC_iALUi,
1152 // FIXME: None of these add/sub SP special instructions should be necessary
1153 // at all for thumb2 since they use the same encodings as the generic
1154 // add/sub instructions. In thumb1 we need them since they have dedicated
1155 // encodings. At the least, they should be pseudo instructions.
1156 // ADD r, sp, {so_imm|i12}
1157 let isCodeGenOnly = 1 in {
1158 def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1159 IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> {
1160 let Inst{31-27} = 0b11110;
1162 let Inst{24-21} = 0b1000;
1165 def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1166 IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> {
1167 let Inst{31-27} = 0b11110;
1168 let Inst{25-20} = 0b100000;
1172 // ADD r, sp, so_reg
1173 def t2ADDrSPs : T2sTwoRegShiftedReg<
1174 (outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
1175 IIC_iALUsi, "add", ".w\t$Rd, $Rn, $ShiftedRm", []> {
1176 let Inst{31-27} = 0b11101;
1177 let Inst{26-25} = 0b01;
1178 let Inst{24-21} = 0b1000;
1182 // SUB r, sp, {so_imm|i12}
1183 def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1184 IIC_iALUi, "sub", ".w\t$Rd, $Rn, $imm", []> {
1185 let Inst{31-27} = 0b11110;
1187 let Inst{24-21} = 0b1101;
1190 def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1191 IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> {
1192 let Inst{31-27} = 0b11110;
1193 let Inst{25-20} = 0b101010;
1197 // SUB r, sp, so_reg
1198 def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm),
1200 "sub", "\t$Rd, $Rn, $imm", []> {
1201 let Inst{31-27} = 0b11101;
1202 let Inst{26-25} = 0b01;
1203 let Inst{24-21} = 0b1101;
1204 let Inst{19-16} = 0b1101; // Rn = sp
1207 } // end isCodeGenOnly = 1
1209 // Signed and unsigned division on v7-M
1210 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1211 "sdiv", "\t$Rd, $Rn, $Rm",
1212 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
1213 Requires<[HasDivide, IsThumb2]> {
1214 let Inst{31-27} = 0b11111;
1215 let Inst{26-21} = 0b011100;
1217 let Inst{15-12} = 0b1111;
1218 let Inst{7-4} = 0b1111;
1221 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1222 "udiv", "\t$Rd, $Rn, $Rm",
1223 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
1224 Requires<[HasDivide, IsThumb2]> {
1225 let Inst{31-27} = 0b11111;
1226 let Inst{26-21} = 0b011101;
1228 let Inst{15-12} = 0b1111;
1229 let Inst{7-4} = 0b1111;
1232 //===----------------------------------------------------------------------===//
1233 // Load / store Instructions.
1237 let canFoldAsLoad = 1, isReMaterializable = 1 in
1238 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1239 UnOpFrag<(load node:$Src)>>;
1241 // Loads with zero extension
1242 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1243 UnOpFrag<(zextloadi16 node:$Src)>>;
1244 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1245 UnOpFrag<(zextloadi8 node:$Src)>>;
1247 // Loads with sign extension
1248 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1249 UnOpFrag<(sextloadi16 node:$Src)>>;
1250 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1251 UnOpFrag<(sextloadi8 node:$Src)>>;
1253 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1255 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1256 (ins t2addrmode_imm8s4:$addr),
1257 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1258 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1260 // zextload i1 -> zextload i8
1261 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1262 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1263 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1264 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1265 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1266 (t2LDRBs t2addrmode_so_reg:$addr)>;
1267 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1268 (t2LDRBpci tconstpool:$addr)>;
1270 // extload -> zextload
1271 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1273 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1274 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1275 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1276 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1277 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1278 (t2LDRBs t2addrmode_so_reg:$addr)>;
1279 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1280 (t2LDRBpci tconstpool:$addr)>;
1282 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1283 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1284 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1285 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1286 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1287 (t2LDRBs t2addrmode_so_reg:$addr)>;
1288 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1289 (t2LDRBpci tconstpool:$addr)>;
1291 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1292 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1293 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1294 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1295 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1296 (t2LDRHs t2addrmode_so_reg:$addr)>;
1297 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1298 (t2LDRHpci tconstpool:$addr)>;
1300 // FIXME: The destination register of the loads and stores can't be PC, but
1301 // can be SP. We need another regclass (similar to rGPR) to represent
1302 // that. Not a pressing issue since these are selected manually,
1307 let mayLoad = 1, neverHasSideEffects = 1 in {
1308 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1309 (ins t2addrmode_imm8:$addr),
1310 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1311 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1314 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1315 (ins GPR:$base, t2am_imm8_offset:$addr),
1316 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1317 "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1320 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1321 (ins t2addrmode_imm8:$addr),
1322 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1323 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1325 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1326 (ins GPR:$base, t2am_imm8_offset:$addr),
1327 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1328 "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1331 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1332 (ins t2addrmode_imm8:$addr),
1333 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1334 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1336 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1337 (ins GPR:$base, t2am_imm8_offset:$addr),
1338 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1339 "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1342 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1343 (ins t2addrmode_imm8:$addr),
1344 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1345 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1347 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1348 (ins GPR:$base, t2am_imm8_offset:$addr),
1349 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1350 "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1353 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1354 (ins t2addrmode_imm8:$addr),
1355 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1356 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1358 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
1359 (ins GPR:$base, t2am_imm8_offset:$addr),
1360 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1361 "ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
1363 } // mayLoad = 1, neverHasSideEffects = 1
1365 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1366 // for disassembly only.
1367 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1368 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1369 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1370 "\t$Rt, $addr", []> {
1371 let Inst{31-27} = 0b11111;
1372 let Inst{26-25} = 0b00;
1373 let Inst{24} = signed;
1375 let Inst{22-21} = type;
1376 let Inst{20} = 1; // load
1378 let Inst{10-8} = 0b110; // PUW.
1382 let Inst{15-12} = Rt;
1383 let Inst{19-16} = addr{12-9};
1384 let Inst{7-0} = addr{7-0};
1387 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1388 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1389 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1390 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1391 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1394 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1395 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1396 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1397 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1398 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1399 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1402 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1403 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1404 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1405 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1408 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1409 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1410 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1411 "str", "\t$Rt, [$Rn, $addr]!",
1412 "$Rn = $base_wb,@earlyclobber $base_wb",
1414 (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1416 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1417 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1418 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1419 "str", "\t$Rt, [$Rn], $addr",
1420 "$Rn = $base_wb,@earlyclobber $base_wb",
1422 (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1424 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1425 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1426 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1427 "strh", "\t$Rt, [$Rn, $addr]!",
1428 "$Rn = $base_wb,@earlyclobber $base_wb",
1430 (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1432 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1433 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1434 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1435 "strh", "\t$Rt, [$Rn], $addr",
1436 "$Rn = $base_wb,@earlyclobber $base_wb",
1438 (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1440 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1441 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1442 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1443 "strb", "\t$Rt, [$Rn, $addr]!",
1444 "$Rn = $base_wb,@earlyclobber $base_wb",
1446 (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1448 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1449 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1450 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1451 "strb", "\t$Rt, [$Rn], $addr",
1452 "$Rn = $base_wb,@earlyclobber $base_wb",
1454 (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1456 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1458 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1459 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1460 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1461 "\t$Rt, $addr", []> {
1462 let Inst{31-27} = 0b11111;
1463 let Inst{26-25} = 0b00;
1464 let Inst{24} = 0; // not signed
1466 let Inst{22-21} = type;
1467 let Inst{20} = 0; // store
1469 let Inst{10-8} = 0b110; // PUW
1473 let Inst{15-12} = Rt;
1474 let Inst{19-16} = addr{12-9};
1475 let Inst{7-0} = addr{7-0};
1478 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1479 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1480 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1482 // ldrd / strd pre / post variants
1483 // For disassembly only.
1485 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1486 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1487 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1489 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1490 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1491 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1493 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1494 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1495 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1497 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1498 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1499 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1501 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1502 // data/instruction access. These are for disassembly only.
1503 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1504 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1505 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1507 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1509 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1510 let Inst{31-25} = 0b1111100;
1511 let Inst{24} = instr;
1513 let Inst{21} = write;
1515 let Inst{15-12} = 0b1111;
1518 let addr{12} = 1; // add = TRUE
1519 let Inst{19-16} = addr{16-13}; // Rn
1520 let Inst{23} = addr{12}; // U
1521 let Inst{11-0} = addr{11-0}; // imm12
1524 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1526 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1527 let Inst{31-25} = 0b1111100;
1528 let Inst{24} = instr;
1529 let Inst{23} = 0; // U = 0
1531 let Inst{21} = write;
1533 let Inst{15-12} = 0b1111;
1534 let Inst{11-8} = 0b1100;
1537 let Inst{19-16} = addr{12-9}; // Rn
1538 let Inst{7-0} = addr{7-0}; // imm8
1541 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1543 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1544 let Inst{31-25} = 0b1111100;
1545 let Inst{24} = instr;
1546 let Inst{23} = 0; // add = TRUE for T1
1548 let Inst{21} = write;
1550 let Inst{15-12} = 0b1111;
1551 let Inst{11-6} = 0000000;
1554 let Inst{19-16} = addr{9-6}; // Rn
1555 let Inst{3-0} = addr{5-2}; // Rm
1556 let Inst{5-4} = addr{1-0}; // imm2
1560 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1561 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1562 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1564 //===----------------------------------------------------------------------===//
1565 // Load / store multiple Instructions.
1568 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1569 InstrItinClass itin_upd, bit L_bit> {
1571 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1572 itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1576 let Inst{31-27} = 0b11101;
1577 let Inst{26-25} = 0b00;
1578 let Inst{24-23} = 0b01; // Increment After
1580 let Inst{21} = 0; // No writeback
1581 let Inst{20} = L_bit;
1582 let Inst{19-16} = Rn;
1583 let Inst{15-0} = regs;
1586 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1587 itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1591 let Inst{31-27} = 0b11101;
1592 let Inst{26-25} = 0b00;
1593 let Inst{24-23} = 0b01; // Increment After
1595 let Inst{21} = 1; // Writeback
1596 let Inst{20} = L_bit;
1597 let Inst{19-16} = Rn;
1598 let Inst{15-0} = regs;
1601 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1602 itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1606 let Inst{31-27} = 0b11101;
1607 let Inst{26-25} = 0b00;
1608 let Inst{24-23} = 0b10; // Decrement Before
1610 let Inst{21} = 0; // No writeback
1611 let Inst{20} = L_bit;
1612 let Inst{19-16} = Rn;
1613 let Inst{15-0} = regs;
1616 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1617 itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1621 let Inst{31-27} = 0b11101;
1622 let Inst{26-25} = 0b00;
1623 let Inst{24-23} = 0b10; // Decrement Before
1625 let Inst{21} = 1; // Writeback
1626 let Inst{20} = L_bit;
1627 let Inst{19-16} = Rn;
1628 let Inst{15-0} = regs;
1632 let neverHasSideEffects = 1 in {
1634 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1635 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1637 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1638 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1640 } // neverHasSideEffects
1643 //===----------------------------------------------------------------------===//
1644 // Move Instructions.
1647 let neverHasSideEffects = 1 in
1648 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1649 "mov", ".w\t$Rd, $Rm", []> {
1650 let Inst{31-27} = 0b11101;
1651 let Inst{26-25} = 0b01;
1652 let Inst{24-21} = 0b0010;
1653 let Inst{19-16} = 0b1111; // Rn
1654 let Inst{14-12} = 0b000;
1655 let Inst{7-4} = 0b0000;
1658 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1659 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1660 AddedComplexity = 1 in
1661 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1662 "mov", ".w\t$Rd, $imm",
1663 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1664 let Inst{31-27} = 0b11110;
1666 let Inst{24-21} = 0b0010;
1667 let Inst{19-16} = 0b1111; // Rn
1671 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1672 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi,
1673 "movw", "\t$Rd, $imm",
1674 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1675 let Inst{31-27} = 0b11110;
1677 let Inst{24-21} = 0b0010;
1678 let Inst{20} = 0; // The S bit.
1684 let Inst{11-8} = Rd;
1685 let Inst{19-16} = imm{15-12};
1686 let Inst{26} = imm{11};
1687 let Inst{14-12} = imm{10-8};
1688 let Inst{7-0} = imm{7-0};
1691 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1692 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1694 let Constraints = "$src = $Rd" in {
1695 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1696 (ins rGPR:$src, i32imm_hilo16:$imm), IIC_iMOVi,
1697 "movt", "\t$Rd, $imm",
1699 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1700 let Inst{31-27} = 0b11110;
1702 let Inst{24-21} = 0b0110;
1703 let Inst{20} = 0; // The S bit.
1709 let Inst{11-8} = Rd;
1710 let Inst{19-16} = imm{15-12};
1711 let Inst{26} = imm{11};
1712 let Inst{14-12} = imm{10-8};
1713 let Inst{7-0} = imm{7-0};
1716 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1717 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1720 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1722 //===----------------------------------------------------------------------===//
1723 // Extend Instructions.
1728 defm t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1729 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1730 defm t2SXTH : T2I_ext_rrot<0b000, "sxth",
1731 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1732 defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1734 defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1735 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1736 defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1737 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1738 defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1740 // TODO: SXT(A){B|H}16 - done for disassembly only
1744 let AddedComplexity = 16 in {
1745 defm t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1746 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1747 defm t2UXTH : T2I_ext_rrot<0b001, "uxth",
1748 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1749 defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1750 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1752 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1753 // The transformation should probably be done as a combiner action
1754 // instead so we can include a check for masking back in the upper
1755 // eight bits of the source into the lower eight bits of the result.
1756 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1757 // (t2UXTB16r_rot rGPR:$Src, 24)>,
1758 // Requires<[HasT2ExtractPack, IsThumb2]>;
1759 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1760 (t2UXTB16r_rot rGPR:$Src, 8)>,
1761 Requires<[HasT2ExtractPack, IsThumb2]>;
1763 defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1764 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1765 defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1766 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1767 defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1770 //===----------------------------------------------------------------------===//
1771 // Arithmetic Instructions.
1774 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1775 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1776 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1777 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1779 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1780 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1781 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1782 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1783 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1784 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1785 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1787 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1788 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1789 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1790 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1791 defm t2ADCS : T2I_adde_sube_s_irs<BinOpFrag<(adde_live_carry node:$LHS,
1793 defm t2SBCS : T2I_adde_sube_s_irs<BinOpFrag<(sube_live_carry node:$LHS,
1797 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1798 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1799 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1800 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1802 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1803 // The assume-no-carry-in form uses the negation of the input since add/sub
1804 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1805 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1807 // The AddedComplexity preferences the first variant over the others since
1808 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1809 let AddedComplexity = 1 in
1810 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1811 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1812 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1813 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1814 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1815 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1816 let AddedComplexity = 1 in
1817 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1818 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1819 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1820 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1821 // The with-carry-in form matches bitwise not instead of the negation.
1822 // Effectively, the inverse interpretation of the carry flag already accounts
1823 // for part of the negation.
1824 let AddedComplexity = 1 in
1825 def : T2Pat<(adde_dead_carry rGPR:$src, imm0_255_not:$imm),
1826 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1827 def : T2Pat<(adde_dead_carry rGPR:$src, t2_so_imm_not:$imm),
1828 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1829 let AddedComplexity = 1 in
1830 def : T2Pat<(adde_live_carry rGPR:$src, imm0_255_not:$imm),
1831 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1832 def : T2Pat<(adde_live_carry rGPR:$src, t2_so_imm_not:$imm),
1833 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1835 // Select Bytes -- for disassembly only
1837 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1838 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
1839 let Inst{31-27} = 0b11111;
1840 let Inst{26-24} = 0b010;
1842 let Inst{22-20} = 0b010;
1843 let Inst{15-12} = 0b1111;
1845 let Inst{6-4} = 0b000;
1848 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1849 // And Miscellaneous operations -- for disassembly only
1850 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1851 list<dag> pat = [/* For disassembly only; pattern left blank */],
1852 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1853 string asm = "\t$Rd, $Rn, $Rm">
1854 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat> {
1855 let Inst{31-27} = 0b11111;
1856 let Inst{26-23} = 0b0101;
1857 let Inst{22-20} = op22_20;
1858 let Inst{15-12} = 0b1111;
1859 let Inst{7-4} = op7_4;
1865 let Inst{11-8} = Rd;
1866 let Inst{19-16} = Rn;
1870 // Saturating add/subtract -- for disassembly only
1872 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1873 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1874 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1875 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1876 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1877 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1878 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1879 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1880 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1881 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1882 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1883 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1884 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1885 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1886 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1887 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1888 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1889 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1890 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1891 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1892 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1893 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1895 // Signed/Unsigned add/subtract -- for disassembly only
1897 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1898 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1899 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1900 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1901 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1902 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1903 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1904 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1905 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1906 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1907 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1908 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1910 // Signed/Unsigned halving add/subtract -- for disassembly only
1912 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1913 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1914 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1915 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1916 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1917 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1918 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1919 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1920 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1921 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1922 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1923 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1925 // Helper class for disassembly only
1926 // A6.3.16 & A6.3.17
1927 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1928 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1929 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1930 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1931 let Inst{31-27} = 0b11111;
1932 let Inst{26-24} = 0b011;
1933 let Inst{23} = long;
1934 let Inst{22-20} = op22_20;
1935 let Inst{7-4} = op7_4;
1938 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1939 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1940 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1941 let Inst{31-27} = 0b11111;
1942 let Inst{26-24} = 0b011;
1943 let Inst{23} = long;
1944 let Inst{22-20} = op22_20;
1945 let Inst{7-4} = op7_4;
1948 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1950 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1951 (ins rGPR:$Rn, rGPR:$Rm),
1952 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
1953 let Inst{15-12} = 0b1111;
1955 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1956 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1957 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
1959 // Signed/Unsigned saturate -- for disassembly only
1961 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1962 string opc, string asm, list<dag> pattern>
1963 : T2I<oops, iops, itin, opc, asm, pattern> {
1969 let Inst{11-8} = Rd;
1970 let Inst{19-16} = Rn;
1971 let Inst{4-0} = sat_imm{4-0};
1972 let Inst{21} = sh{6};
1973 let Inst{14-12} = sh{4-2};
1974 let Inst{7-6} = sh{1-0};
1978 (outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1979 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1980 [/* For disassembly only; pattern left blank */]> {
1981 let Inst{31-27} = 0b11110;
1982 let Inst{25-22} = 0b1100;
1987 def t2SSAT16: T2SatI<
1988 (outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn), NoItinerary,
1989 "ssat16", "\t$Rd, $sat_imm, $Rn",
1990 [/* For disassembly only; pattern left blank */]> {
1991 let Inst{31-27} = 0b11110;
1992 let Inst{25-22} = 0b1100;
1995 let Inst{21} = 1; // sh = '1'
1996 let Inst{14-12} = 0b000; // imm3 = '000'
1997 let Inst{7-6} = 0b00; // imm2 = '00'
2001 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2002 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
2003 [/* For disassembly only; pattern left blank */]> {
2004 let Inst{31-27} = 0b11110;
2005 let Inst{25-22} = 0b1110;
2010 def t2USAT16: T2SatI<(outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn),
2012 "usat16", "\t$dst, $sat_imm, $Rn",
2013 [/* For disassembly only; pattern left blank */]> {
2014 let Inst{31-27} = 0b11110;
2015 let Inst{25-22} = 0b1110;
2018 let Inst{21} = 1; // sh = '1'
2019 let Inst{14-12} = 0b000; // imm3 = '000'
2020 let Inst{7-6} = 0b00; // imm2 = '00'
2023 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2024 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2026 //===----------------------------------------------------------------------===//
2027 // Shift and rotate Instructions.
2030 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2031 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2032 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2033 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2035 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2036 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2037 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2039 let Uses = [CPSR] in {
2040 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2041 "rrx", "\t$Rd, $Rm",
2042 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2043 let Inst{31-27} = 0b11101;
2044 let Inst{26-25} = 0b01;
2045 let Inst{24-21} = 0b0010;
2046 let Inst{19-16} = 0b1111; // Rn
2047 let Inst{14-12} = 0b000;
2048 let Inst{7-4} = 0b0011;
2052 let isCodeGenOnly = 1, Defs = [CPSR] in {
2053 def t2MOVsrl_flag : T2TwoRegShiftImm<
2054 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2055 "lsrs", ".w\t$Rd, $Rm, #1",
2056 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2057 let Inst{31-27} = 0b11101;
2058 let Inst{26-25} = 0b01;
2059 let Inst{24-21} = 0b0010;
2060 let Inst{20} = 1; // The S bit.
2061 let Inst{19-16} = 0b1111; // Rn
2062 let Inst{5-4} = 0b01; // Shift type.
2063 // Shift amount = Inst{14-12:7-6} = 1.
2064 let Inst{14-12} = 0b000;
2065 let Inst{7-6} = 0b01;
2067 def t2MOVsra_flag : T2TwoRegShiftImm<
2068 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2069 "asrs", ".w\t$Rd, $Rm, #1",
2070 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2071 let Inst{31-27} = 0b11101;
2072 let Inst{26-25} = 0b01;
2073 let Inst{24-21} = 0b0010;
2074 let Inst{20} = 1; // The S bit.
2075 let Inst{19-16} = 0b1111; // Rn
2076 let Inst{5-4} = 0b10; // Shift type.
2077 // Shift amount = Inst{14-12:7-6} = 1.
2078 let Inst{14-12} = 0b000;
2079 let Inst{7-6} = 0b01;
2083 //===----------------------------------------------------------------------===//
2084 // Bitwise Instructions.
2087 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2088 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2089 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2090 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2091 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2092 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2093 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2094 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2095 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2097 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2098 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2099 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2101 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2102 string opc, string asm, list<dag> pattern>
2103 : T2I<oops, iops, itin, opc, asm, pattern> {
2108 let Inst{11-8} = Rd;
2109 let Inst{4-0} = msb{4-0};
2110 let Inst{14-12} = lsb{4-2};
2111 let Inst{7-6} = lsb{1-0};
2114 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2115 string opc, string asm, list<dag> pattern>
2116 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2119 let Inst{19-16} = Rn;
2122 let Constraints = "$src = $Rd" in
2123 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2124 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2125 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2126 let Inst{31-27} = 0b11110;
2127 let Inst{26} = 0; // should be 0.
2129 let Inst{24-20} = 0b10110;
2130 let Inst{19-16} = 0b1111; // Rn
2132 let Inst{5} = 0; // should be 0.
2135 let msb{4-0} = imm{9-5};
2136 let lsb{4-0} = imm{4-0};
2139 def t2SBFX: T2TwoRegBitFI<
2140 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2141 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2142 let Inst{31-27} = 0b11110;
2144 let Inst{24-20} = 0b10100;
2148 def t2UBFX: T2TwoRegBitFI<
2149 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2150 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2151 let Inst{31-27} = 0b11110;
2153 let Inst{24-20} = 0b11100;
2157 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2158 let Constraints = "$src = $Rd" in {
2159 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2160 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2161 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2162 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2163 bf_inv_mask_imm:$imm))]> {
2164 let Inst{31-27} = 0b11110;
2165 let Inst{26} = 0; // should be 0.
2167 let Inst{24-20} = 0b10110;
2169 let Inst{5} = 0; // should be 0.
2172 let msb{4-0} = imm{9-5};
2173 let lsb{4-0} = imm{4-0};
2176 // GNU as only supports this form of bfi (w/ 4 arguments)
2177 let isAsmParserOnly = 1 in
2178 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2179 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2181 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2183 let Inst{31-27} = 0b11110;
2184 let Inst{26} = 0; // should be 0.
2186 let Inst{24-20} = 0b10110;
2188 let Inst{5} = 0; // should be 0.
2192 let msb{4-0} = width; // Custom encoder => lsb+width-1
2193 let lsb{4-0} = lsbit;
2197 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2198 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2199 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2201 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2202 let AddedComplexity = 1 in
2203 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2204 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2205 UnOpFrag<(not node:$Src)>, 1, 1>;
2208 let AddedComplexity = 1 in
2209 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2210 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2212 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2213 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2214 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2215 Requires<[IsThumb2]>;
2217 def : T2Pat<(t2_so_imm_not:$src),
2218 (t2MVNi t2_so_imm_not:$src)>;
2220 //===----------------------------------------------------------------------===//
2221 // Multiply Instructions.
2223 let isCommutable = 1 in
2224 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2225 "mul", "\t$Rd, $Rn, $Rm",
2226 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2227 let Inst{31-27} = 0b11111;
2228 let Inst{26-23} = 0b0110;
2229 let Inst{22-20} = 0b000;
2230 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2231 let Inst{7-4} = 0b0000; // Multiply
2234 def t2MLA: T2FourReg<
2235 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2236 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2237 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2238 let Inst{31-27} = 0b11111;
2239 let Inst{26-23} = 0b0110;
2240 let Inst{22-20} = 0b000;
2241 let Inst{7-4} = 0b0000; // Multiply
2244 def t2MLS: T2FourReg<
2245 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2246 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2247 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2248 let Inst{31-27} = 0b11111;
2249 let Inst{26-23} = 0b0110;
2250 let Inst{22-20} = 0b000;
2251 let Inst{7-4} = 0b0001; // Multiply and Subtract
2254 // Extra precision multiplies with low / high results
2255 let neverHasSideEffects = 1 in {
2256 let isCommutable = 1 in {
2257 def t2SMULL : T2MulLong<0b000, 0b0000,
2258 (outs rGPR:$Rd, rGPR:$Ra),
2259 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2260 "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
2262 def t2UMULL : T2MulLong<0b010, 0b0000,
2263 (outs rGPR:$RdLo, rGPR:$RdHi),
2264 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2265 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2268 // Multiply + accumulate
2269 def t2SMLAL : T2MulLong<0b100, 0b0000,
2270 (outs rGPR:$RdLo, rGPR:$RdHi),
2271 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2272 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2274 def t2UMLAL : T2MulLong<0b110, 0b0000,
2275 (outs rGPR:$RdLo, rGPR:$RdHi),
2276 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2277 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2279 def t2UMAAL : T2MulLong<0b110, 0b0110,
2280 (outs rGPR:$RdLo, rGPR:$RdHi),
2281 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2282 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2283 } // neverHasSideEffects
2285 // Rounding variants of the below included for disassembly only
2287 // Most significant word multiply
2288 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2289 "smmul", "\t$Rd, $Rn, $Rm",
2290 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
2291 let Inst{31-27} = 0b11111;
2292 let Inst{26-23} = 0b0110;
2293 let Inst{22-20} = 0b101;
2294 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2295 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2298 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2299 "smmulr", "\t$Rd, $Rn, $Rm", []> {
2300 let Inst{31-27} = 0b11111;
2301 let Inst{26-23} = 0b0110;
2302 let Inst{22-20} = 0b101;
2303 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2304 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2307 def t2SMMLA : T2FourReg<
2308 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2309 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2310 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
2311 let Inst{31-27} = 0b11111;
2312 let Inst{26-23} = 0b0110;
2313 let Inst{22-20} = 0b101;
2314 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2317 def t2SMMLAR: T2FourReg<
2318 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2319 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
2320 let Inst{31-27} = 0b11111;
2321 let Inst{26-23} = 0b0110;
2322 let Inst{22-20} = 0b101;
2323 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2326 def t2SMMLS: T2FourReg<
2327 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2328 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2329 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
2330 let Inst{31-27} = 0b11111;
2331 let Inst{26-23} = 0b0110;
2332 let Inst{22-20} = 0b110;
2333 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2336 def t2SMMLSR:T2FourReg<
2337 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2338 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
2339 let Inst{31-27} = 0b11111;
2340 let Inst{26-23} = 0b0110;
2341 let Inst{22-20} = 0b110;
2342 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2345 multiclass T2I_smul<string opc, PatFrag opnode> {
2346 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2347 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2348 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2349 (sext_inreg rGPR:$Rm, i16)))]> {
2350 let Inst{31-27} = 0b11111;
2351 let Inst{26-23} = 0b0110;
2352 let Inst{22-20} = 0b001;
2353 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2354 let Inst{7-6} = 0b00;
2355 let Inst{5-4} = 0b00;
2358 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2359 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2360 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2361 (sra rGPR:$Rm, (i32 16))))]> {
2362 let Inst{31-27} = 0b11111;
2363 let Inst{26-23} = 0b0110;
2364 let Inst{22-20} = 0b001;
2365 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2366 let Inst{7-6} = 0b00;
2367 let Inst{5-4} = 0b01;
2370 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2371 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2372 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2373 (sext_inreg rGPR:$Rm, i16)))]> {
2374 let Inst{31-27} = 0b11111;
2375 let Inst{26-23} = 0b0110;
2376 let Inst{22-20} = 0b001;
2377 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2378 let Inst{7-6} = 0b00;
2379 let Inst{5-4} = 0b10;
2382 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2383 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2384 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2385 (sra rGPR:$Rm, (i32 16))))]> {
2386 let Inst{31-27} = 0b11111;
2387 let Inst{26-23} = 0b0110;
2388 let Inst{22-20} = 0b001;
2389 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2390 let Inst{7-6} = 0b00;
2391 let Inst{5-4} = 0b11;
2394 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2395 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2396 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2397 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
2398 let Inst{31-27} = 0b11111;
2399 let Inst{26-23} = 0b0110;
2400 let Inst{22-20} = 0b011;
2401 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2402 let Inst{7-6} = 0b00;
2403 let Inst{5-4} = 0b00;
2406 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2407 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2408 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2409 (sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
2410 let Inst{31-27} = 0b11111;
2411 let Inst{26-23} = 0b0110;
2412 let Inst{22-20} = 0b011;
2413 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2414 let Inst{7-6} = 0b00;
2415 let Inst{5-4} = 0b01;
2420 multiclass T2I_smla<string opc, PatFrag opnode> {
2422 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2423 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2424 [(set rGPR:$Rd, (add rGPR:$Ra,
2425 (opnode (sext_inreg rGPR:$Rn, i16),
2426 (sext_inreg rGPR:$Rm, i16))))]> {
2427 let Inst{31-27} = 0b11111;
2428 let Inst{26-23} = 0b0110;
2429 let Inst{22-20} = 0b001;
2430 let Inst{7-6} = 0b00;
2431 let Inst{5-4} = 0b00;
2435 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2436 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2437 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2438 (sra rGPR:$Rm, (i32 16)))))]> {
2439 let Inst{31-27} = 0b11111;
2440 let Inst{26-23} = 0b0110;
2441 let Inst{22-20} = 0b001;
2442 let Inst{7-6} = 0b00;
2443 let Inst{5-4} = 0b01;
2447 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2448 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2449 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2450 (sext_inreg rGPR:$Rm, i16))))]> {
2451 let Inst{31-27} = 0b11111;
2452 let Inst{26-23} = 0b0110;
2453 let Inst{22-20} = 0b001;
2454 let Inst{7-6} = 0b00;
2455 let Inst{5-4} = 0b10;
2459 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2460 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2461 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2462 (sra rGPR:$Rm, (i32 16)))))]> {
2463 let Inst{31-27} = 0b11111;
2464 let Inst{26-23} = 0b0110;
2465 let Inst{22-20} = 0b001;
2466 let Inst{7-6} = 0b00;
2467 let Inst{5-4} = 0b11;
2471 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2472 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2473 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2474 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
2475 let Inst{31-27} = 0b11111;
2476 let Inst{26-23} = 0b0110;
2477 let Inst{22-20} = 0b011;
2478 let Inst{7-6} = 0b00;
2479 let Inst{5-4} = 0b00;
2483 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2484 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2485 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2486 (sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
2487 let Inst{31-27} = 0b11111;
2488 let Inst{26-23} = 0b0110;
2489 let Inst{22-20} = 0b011;
2490 let Inst{7-6} = 0b00;
2491 let Inst{5-4} = 0b01;
2495 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2496 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2498 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2499 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2500 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2501 [/* For disassembly only; pattern left blank */]>;
2502 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2503 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2504 [/* For disassembly only; pattern left blank */]>;
2505 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2506 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2507 [/* For disassembly only; pattern left blank */]>;
2508 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2509 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2510 [/* For disassembly only; pattern left blank */]>;
2512 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2513 // These are for disassembly only.
2515 def t2SMUAD: T2ThreeReg_mac<
2516 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2517 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
2518 let Inst{15-12} = 0b1111;
2520 def t2SMUADX:T2ThreeReg_mac<
2521 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2522 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
2523 let Inst{15-12} = 0b1111;
2525 def t2SMUSD: T2ThreeReg_mac<
2526 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2527 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
2528 let Inst{15-12} = 0b1111;
2530 def t2SMUSDX:T2ThreeReg_mac<
2531 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2532 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
2533 let Inst{15-12} = 0b1111;
2535 def t2SMLAD : T2ThreeReg_mac<
2536 0, 0b010, 0b0000, (outs rGPR:$Rd),
2537 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2538 "\t$Rd, $Rn, $Rm, $Ra", []>;
2539 def t2SMLADX : T2FourReg_mac<
2540 0, 0b010, 0b0001, (outs rGPR:$Rd),
2541 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2542 "\t$Rd, $Rn, $Rm, $Ra", []>;
2543 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2544 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2545 "\t$Rd, $Rn, $Rm, $Ra", []>;
2546 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2547 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2548 "\t$Rd, $Rn, $Rm, $Ra", []>;
2549 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2550 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2551 "\t$Ra, $Rd, $Rm, $Rn", []>;
2552 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2553 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2554 "\t$Ra, $Rd, $Rm, $Rn", []>;
2555 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2556 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2557 "\t$Ra, $Rd, $Rm, $Rn", []>;
2558 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2559 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2560 "\t$Ra, $Rd, $Rm, $Rn", []>;
2562 //===----------------------------------------------------------------------===//
2563 // Misc. Arithmetic Instructions.
2566 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2567 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2568 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2569 let Inst{31-27} = 0b11111;
2570 let Inst{26-22} = 0b01010;
2571 let Inst{21-20} = op1;
2572 let Inst{15-12} = 0b1111;
2573 let Inst{7-6} = 0b10;
2574 let Inst{5-4} = op2;
2578 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2579 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2581 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2582 "rbit", "\t$Rd, $Rm",
2583 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2585 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2586 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2588 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2589 "rev16", ".w\t$Rd, $Rm",
2591 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF),
2592 (or (and (shl rGPR:$Rm, (i32 8)), 0xFF00),
2593 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
2594 (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
2596 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2597 "revsh", ".w\t$Rd, $Rm",
2600 (or (srl rGPR:$Rm, (i32 8)),
2601 (shl rGPR:$Rm, (i32 8))), i16))]>;
2603 def : T2Pat<(sext_inreg (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
2604 (shl rGPR:$Rm, (i32 8))), i16),
2605 (t2REVSH rGPR:$Rm)>;
2607 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2608 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2609 (t2REVSH rGPR:$Rm)>;
2611 def : T2Pat<(sra (bswap rGPR:$Rm), (i32 16)), (t2REVSH rGPR:$Rm)>;
2613 def t2PKHBT : T2ThreeReg<
2614 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2615 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2616 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2617 (and (shl rGPR:$Rm, lsl_amt:$sh),
2619 Requires<[HasT2ExtractPack, IsThumb2]> {
2620 let Inst{31-27} = 0b11101;
2621 let Inst{26-25} = 0b01;
2622 let Inst{24-20} = 0b01100;
2623 let Inst{5} = 0; // BT form
2627 let Inst{14-12} = sh{7-5};
2628 let Inst{7-6} = sh{4-3};
2631 // Alternate cases for PKHBT where identities eliminate some nodes.
2632 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2633 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2634 Requires<[HasT2ExtractPack, IsThumb2]>;
2635 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2636 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2637 Requires<[HasT2ExtractPack, IsThumb2]>;
2639 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2640 // will match the pattern below.
2641 def t2PKHTB : T2ThreeReg<
2642 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2643 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2644 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2645 (and (sra rGPR:$Rm, asr_amt:$sh),
2647 Requires<[HasT2ExtractPack, IsThumb2]> {
2648 let Inst{31-27} = 0b11101;
2649 let Inst{26-25} = 0b01;
2650 let Inst{24-20} = 0b01100;
2651 let Inst{5} = 1; // TB form
2655 let Inst{14-12} = sh{7-5};
2656 let Inst{7-6} = sh{4-3};
2659 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2660 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2661 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2662 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2663 Requires<[HasT2ExtractPack, IsThumb2]>;
2664 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2665 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2666 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2667 Requires<[HasT2ExtractPack, IsThumb2]>;
2669 //===----------------------------------------------------------------------===//
2670 // Comparison Instructions...
2672 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2673 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2674 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2676 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
2677 (t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
2678 def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
2679 (t2CMPrr GPR:$lhs, rGPR:$rhs)>;
2680 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
2681 (t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
2683 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2684 // Compare-to-zero still works out, just not the relationals
2685 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2686 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2687 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2688 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2689 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2691 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2692 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2694 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2695 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2697 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2698 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2699 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2700 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2701 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2702 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2704 // Conditional moves
2705 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2706 // a two-value operand where a dag node expects two operands. :(
2707 let neverHasSideEffects = 1 in {
2708 def t2MOVCCr : T2TwoReg<
2709 (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
2710 "mov", ".w\t$Rd, $Rm",
2711 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2712 RegConstraint<"$false = $Rd"> {
2713 let Inst{31-27} = 0b11101;
2714 let Inst{26-25} = 0b01;
2715 let Inst{24-21} = 0b0010;
2716 let Inst{20} = 0; // The S bit.
2717 let Inst{19-16} = 0b1111; // Rn
2718 let Inst{14-12} = 0b000;
2719 let Inst{7-4} = 0b0000;
2722 let isMoveImm = 1 in
2723 def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2724 IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
2725 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2726 RegConstraint<"$false = $Rd"> {
2727 let Inst{31-27} = 0b11110;
2729 let Inst{24-21} = 0b0010;
2730 let Inst{20} = 0; // The S bit.
2731 let Inst{19-16} = 0b1111; // Rn
2735 let isMoveImm = 1 in
2736 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm_hilo16:$imm),
2738 "movw", "\t$Rd, $imm", []>,
2739 RegConstraint<"$false = $Rd"> {
2740 let Inst{31-27} = 0b11110;
2742 let Inst{24-21} = 0b0010;
2743 let Inst{20} = 0; // The S bit.
2749 let Inst{11-8} = Rd;
2750 let Inst{19-16} = imm{15-12};
2751 let Inst{26} = imm{11};
2752 let Inst{14-12} = imm{10-8};
2753 let Inst{7-0} = imm{7-0};
2756 let isMoveImm = 1 in
2757 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2758 (ins rGPR:$false, i32imm:$src, pred:$p),
2759 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2761 let isMoveImm = 1 in
2762 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2763 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2764 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2765 imm:$cc, CCR:$ccr))*/]>,
2766 RegConstraint<"$false = $Rd"> {
2767 let Inst{31-27} = 0b11110;
2769 let Inst{24-21} = 0b0011;
2770 let Inst{20} = 0; // The S bit.
2771 let Inst{19-16} = 0b1111; // Rn
2775 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2776 string opc, string asm, list<dag> pattern>
2777 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2778 let Inst{31-27} = 0b11101;
2779 let Inst{26-25} = 0b01;
2780 let Inst{24-21} = 0b0010;
2781 let Inst{20} = 0; // The S bit.
2782 let Inst{19-16} = 0b1111; // Rn
2783 let Inst{5-4} = opcod; // Shift type.
2785 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2786 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2787 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2788 RegConstraint<"$false = $Rd">;
2789 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2790 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2791 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2792 RegConstraint<"$false = $Rd">;
2793 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2794 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2795 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2796 RegConstraint<"$false = $Rd">;
2797 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2798 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2799 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2800 RegConstraint<"$false = $Rd">;
2801 } // neverHasSideEffects
2803 //===----------------------------------------------------------------------===//
2804 // Atomic operations intrinsics
2807 // memory barriers protect the atomic sequences
2808 let hasSideEffects = 1 in {
2809 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2810 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2811 Requires<[IsThumb, HasDB]> {
2813 let Inst{31-4} = 0xf3bf8f5;
2814 let Inst{3-0} = opt;
2818 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2820 [/* For disassembly only; pattern left blank */]>,
2821 Requires<[IsThumb, HasDB]> {
2823 let Inst{31-4} = 0xf3bf8f4;
2824 let Inst{3-0} = opt;
2827 // ISB has only full system option -- for disassembly only
2828 def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2829 [/* For disassembly only; pattern left blank */]>,
2830 Requires<[IsThumb2, HasV7]> {
2831 let Inst{31-4} = 0xf3bf8f6;
2832 let Inst{3-0} = 0b1111;
2835 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2836 InstrItinClass itin, string opc, string asm, string cstr,
2837 list<dag> pattern, bits<4> rt2 = 0b1111>
2838 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2839 let Inst{31-27} = 0b11101;
2840 let Inst{26-20} = 0b0001101;
2841 let Inst{11-8} = rt2;
2842 let Inst{7-6} = 0b01;
2843 let Inst{5-4} = opcod;
2844 let Inst{3-0} = 0b1111;
2848 let Inst{19-16} = addr;
2849 let Inst{15-12} = Rt;
2851 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2852 InstrItinClass itin, string opc, string asm, string cstr,
2853 list<dag> pattern, bits<4> rt2 = 0b1111>
2854 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2855 let Inst{31-27} = 0b11101;
2856 let Inst{26-20} = 0b0001100;
2857 let Inst{11-8} = rt2;
2858 let Inst{7-6} = 0b01;
2859 let Inst{5-4} = opcod;
2865 let Inst{19-16} = addr;
2866 let Inst{15-12} = Rt;
2869 let mayLoad = 1 in {
2870 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2871 AddrModeNone, Size4Bytes, NoItinerary,
2872 "ldrexb", "\t$Rt, $addr", "", []>;
2873 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2874 AddrModeNone, Size4Bytes, NoItinerary,
2875 "ldrexh", "\t$Rt, $addr", "", []>;
2876 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2877 AddrModeNone, Size4Bytes, NoItinerary,
2878 "ldrex", "\t$Rt, $addr", "", []> {
2879 let Inst{31-27} = 0b11101;
2880 let Inst{26-20} = 0b0000101;
2881 let Inst{11-8} = 0b1111;
2882 let Inst{7-0} = 0b00000000; // imm8 = 0
2886 let Inst{19-16} = addr;
2887 let Inst{15-12} = Rt;
2889 let hasExtraDefRegAllocReq = 1 in
2890 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2891 (ins t2addrmode_reg:$addr),
2892 AddrModeNone, Size4Bytes, NoItinerary,
2893 "ldrexd", "\t$Rt, $Rt2, $addr", "",
2896 let Inst{11-8} = Rt2;
2900 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2901 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2902 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2903 AddrModeNone, Size4Bytes, NoItinerary,
2904 "strexb", "\t$Rd, $Rt, $addr", "", []>;
2905 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2906 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2907 AddrModeNone, Size4Bytes, NoItinerary,
2908 "strexh", "\t$Rd, $Rt, $addr", "", []>;
2909 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2910 AddrModeNone, Size4Bytes, NoItinerary,
2911 "strex", "\t$Rd, $Rt, $addr", "",
2913 let Inst{31-27} = 0b11101;
2914 let Inst{26-20} = 0b0000100;
2915 let Inst{7-0} = 0b00000000; // imm8 = 0
2920 let Inst{11-8} = Rd;
2921 let Inst{19-16} = addr;
2922 let Inst{15-12} = Rt;
2926 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2927 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2928 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2929 AddrModeNone, Size4Bytes, NoItinerary,
2930 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2933 let Inst{11-8} = Rt2;
2936 // Clear-Exclusive is for disassembly only.
2937 def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
2938 [/* For disassembly only; pattern left blank */]>,
2939 Requires<[IsThumb2, HasV7]> {
2940 let Inst{31-16} = 0xf3bf;
2941 let Inst{15-14} = 0b10;
2944 let Inst{11-8} = 0b1111;
2945 let Inst{7-4} = 0b0010;
2946 let Inst{3-0} = 0b1111;
2949 //===----------------------------------------------------------------------===//
2953 // __aeabi_read_tp preserves the registers r1-r3.
2955 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
2956 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2957 "bl\t__aeabi_read_tp",
2958 [(set R0, ARMthread_pointer)]> {
2959 let Inst{31-27} = 0b11110;
2960 let Inst{15-14} = 0b11;
2965 //===----------------------------------------------------------------------===//
2966 // SJLJ Exception handling intrinsics
2967 // eh_sjlj_setjmp() is an instruction sequence to store the return
2968 // address and save #0 in R0 for the non-longjmp case.
2969 // Since by its nature we may be coming from some other function to get
2970 // here, and we're using the stack frame for the containing function to
2971 // save/restore registers, we can't keep anything live in regs across
2972 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2973 // when we get here from a longjmp(). We force everything out of registers
2974 // except for our own input by listing the relevant registers in Defs. By
2975 // doing so, we also cause the prologue/epilogue code to actively preserve
2976 // all of the callee-saved resgisters, which is exactly what we want.
2977 // $val is a scratch register for our use.
2979 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
2980 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2981 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2982 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2983 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2984 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2985 Requires<[IsThumb2, HasVFP2]>;
2989 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
2990 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2991 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2992 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2993 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2994 Requires<[IsThumb2, NoVFP]>;
2998 //===----------------------------------------------------------------------===//
2999 // Control-Flow Instructions
3002 // FIXME: remove when we have a way to marking a MI with these properties.
3003 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
3005 // FIXME: Should pc be an implicit operand like PICADD, etc?
3006 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3007 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3008 def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3009 reglist:$regs, variable_ops),
3011 "ldmia${p}.w\t$Rn!, $regs",
3016 let Inst{31-27} = 0b11101;
3017 let Inst{26-25} = 0b00;
3018 let Inst{24-23} = 0b01; // Increment After
3020 let Inst{21} = 1; // Writeback
3022 let Inst{19-16} = Rn;
3023 let Inst{15-0} = regs;
3026 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3027 let isPredicable = 1 in
3028 def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
3030 [(br bb:$target)]> {
3031 let Inst{31-27} = 0b11110;
3032 let Inst{15-14} = 0b10;
3036 let Inst{26} = target{19};
3037 let Inst{11} = target{18};
3038 let Inst{13} = target{17};
3039 let Inst{21-16} = target{16-11};
3040 let Inst{10-0} = target{10-0};
3043 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3044 def t2BR_JT : t2PseudoInst<(outs),
3045 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3046 SizeSpecial, IIC_Br,
3047 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3049 // FIXME: Add a non-pc based case that can be predicated.
3050 def t2TBB_JT : t2PseudoInst<(outs),
3051 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3052 SizeSpecial, IIC_Br, []>;
3054 def t2TBH_JT : t2PseudoInst<(outs),
3055 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3056 SizeSpecial, IIC_Br, []>;
3058 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3059 "tbb", "\t[$Rn, $Rm]", []> {
3062 let Inst{31-20} = 0b111010001101;
3063 let Inst{19-16} = Rn;
3064 let Inst{15-5} = 0b11110000000;
3065 let Inst{4} = 0; // B form
3069 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3070 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3073 let Inst{31-20} = 0b111010001101;
3074 let Inst{19-16} = Rn;
3075 let Inst{15-5} = 0b11110000000;
3076 let Inst{4} = 1; // H form
3079 } // isNotDuplicable, isIndirectBranch
3081 } // isBranch, isTerminator, isBarrier
3083 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3084 // a two-value operand where a dag node expects two operands. :(
3085 let isBranch = 1, isTerminator = 1 in
3086 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3088 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3089 let Inst{31-27} = 0b11110;
3090 let Inst{15-14} = 0b10;
3094 let Inst{25-22} = p;
3097 let Inst{26} = target{20};
3098 let Inst{11} = target{19};
3099 let Inst{13} = target{18};
3100 let Inst{21-16} = target{17-12};
3101 let Inst{10-0} = target{11-1};
3106 let Defs = [ITSTATE] in
3107 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3108 AddrModeNone, Size2Bytes, IIC_iALUx,
3109 "it$mask\t$cc", "", []> {
3110 // 16-bit instruction.
3111 let Inst{31-16} = 0x0000;
3112 let Inst{15-8} = 0b10111111;
3117 let Inst{3-0} = mask;
3120 // Branch and Exchange Jazelle -- for disassembly only
3122 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3123 [/* For disassembly only; pattern left blank */]> {
3124 let Inst{31-27} = 0b11110;
3126 let Inst{25-20} = 0b111100;
3127 let Inst{15-14} = 0b10;
3131 let Inst{19-16} = func;
3134 // Change Processor State is a system instruction -- for disassembly and
3136 // FIXME: Since the asm parser has currently no clean way to handle optional
3137 // operands, create 3 versions of the same instruction. Once there's a clean
3138 // framework to represent optional operands, change this behavior.
3139 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3140 !strconcat("cps", asm_op),
3141 [/* For disassembly only; pattern left blank */]> {
3147 let Inst{31-27} = 0b11110;
3149 let Inst{25-20} = 0b111010;
3150 let Inst{19-16} = 0b1111;
3151 let Inst{15-14} = 0b10;
3153 let Inst{10-9} = imod;
3155 let Inst{7-5} = iflags;
3156 let Inst{4-0} = mode;
3160 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3161 "$imod.w\t$iflags, $mode">;
3162 let mode = 0, M = 0 in
3163 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3164 "$imod.w\t$iflags">;
3165 let imod = 0, iflags = 0, M = 1 in
3166 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3168 // A6.3.4 Branches and miscellaneous control
3169 // Table A6-14 Change Processor State, and hint instructions
3170 // Helper class for disassembly only.
3171 class T2I_hint<bits<8> op7_0, string opc, string asm>
3172 : T2I<(outs), (ins), NoItinerary, opc, asm,
3173 [/* For disassembly only; pattern left blank */]> {
3174 let Inst{31-20} = 0xf3a;
3175 let Inst{19-16} = 0b1111;
3176 let Inst{15-14} = 0b10;
3178 let Inst{10-8} = 0b000;
3179 let Inst{7-0} = op7_0;
3182 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3183 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3184 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3185 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3186 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3188 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
3189 [/* For disassembly only; pattern left blank */]> {
3190 let Inst{31-20} = 0xf3a;
3191 let Inst{15-14} = 0b10;
3193 let Inst{10-8} = 0b000;
3194 let Inst{7-4} = 0b1111;
3197 let Inst{3-0} = opt;
3200 // Secure Monitor Call is a system instruction -- for disassembly only
3201 // Option = Inst{19-16}
3202 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
3203 [/* For disassembly only; pattern left blank */]> {
3204 let Inst{31-27} = 0b11110;
3205 let Inst{26-20} = 0b1111111;
3206 let Inst{15-12} = 0b1000;
3209 let Inst{19-16} = opt;
3212 class T2SRS<bits<12> op31_20,
3213 dag oops, dag iops, InstrItinClass itin,
3214 string opc, string asm, list<dag> pattern>
3215 : T2I<oops, iops, itin, opc, asm, pattern> {
3216 let Inst{31-20} = op31_20{11-0};
3219 let Inst{4-0} = mode{4-0};
3222 // Store Return State is a system instruction -- for disassembly only
3223 def t2SRSDBW : T2SRS<0b111010000010,
3224 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3225 [/* For disassembly only; pattern left blank */]>;
3226 def t2SRSDB : T2SRS<0b111010000000,
3227 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3228 [/* For disassembly only; pattern left blank */]>;
3229 def t2SRSIAW : T2SRS<0b111010011010,
3230 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3231 [/* For disassembly only; pattern left blank */]>;
3232 def t2SRSIA : T2SRS<0b111010011000,
3233 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3234 [/* For disassembly only; pattern left blank */]>;
3236 // Return From Exception is a system instruction -- for disassembly only
3238 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3239 string opc, string asm, list<dag> pattern>
3240 : T2I<oops, iops, itin, opc, asm, pattern> {
3241 let Inst{31-20} = op31_20{11-0};
3244 let Inst{19-16} = Rn;
3245 let Inst{15-0} = 0xc000;
3248 def t2RFEDBW : T2RFE<0b111010000011,
3249 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3250 [/* For disassembly only; pattern left blank */]>;
3251 def t2RFEDB : T2RFE<0b111010000001,
3252 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3253 [/* For disassembly only; pattern left blank */]>;
3254 def t2RFEIAW : T2RFE<0b111010011011,
3255 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3256 [/* For disassembly only; pattern left blank */]>;
3257 def t2RFEIA : T2RFE<0b111010011001,
3258 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3259 [/* For disassembly only; pattern left blank */]>;
3261 //===----------------------------------------------------------------------===//
3262 // Non-Instruction Patterns
3265 // 32-bit immediate using movw + movt.
3266 // This is a single pseudo instruction to make it re-materializable.
3267 // FIXME: Remove this when we can do generalized remat.
3268 let isReMaterializable = 1, isMoveImm = 1 in
3269 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3270 [(set rGPR:$dst, (i32 imm:$src))]>,
3271 Requires<[IsThumb, HasV6T2]>;
3273 // Pseudo instruction that combines movw + movt + add pc (if pic).
3274 // It also makes it possible to rematerialize the instructions.
3275 // FIXME: Remove this when we can do generalized remat and when machine licm
3276 // can properly the instructions.
3277 let isReMaterializable = 1 in {
3278 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3280 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3281 Requires<[IsThumb2, UseMovt]>;
3283 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3285 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3286 Requires<[IsThumb2, UseMovt]>;
3289 // ConstantPool, GlobalAddress, and JumpTable
3290 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3291 Requires<[IsThumb2, DontUseMovt]>;
3292 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3293 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3294 Requires<[IsThumb2, UseMovt]>;
3296 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3297 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3299 // Pseudo instruction that combines ldr from constpool and add pc. This should
3300 // be expanded into two instructions late to allow if-conversion and
3302 let canFoldAsLoad = 1, isReMaterializable = 1 in
3303 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3305 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3307 Requires<[IsThumb2]>;
3309 //===----------------------------------------------------------------------===//
3310 // Move between special register and ARM core register -- for disassembly only
3313 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3314 dag oops, dag iops, InstrItinClass itin,
3315 string opc, string asm, list<dag> pattern>
3316 : T2I<oops, iops, itin, opc, asm, pattern> {
3317 let Inst{31-20} = op31_20{11-0};
3318 let Inst{15-14} = op15_14{1-0};
3319 let Inst{12} = op12{0};
3322 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3323 dag oops, dag iops, InstrItinClass itin,
3324 string opc, string asm, list<dag> pattern>
3325 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3327 let Inst{11-8} = Rd;
3328 let Inst{19-16} = 0b1111;
3331 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3332 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3333 [/* For disassembly only; pattern left blank */]>;
3334 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3335 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3336 [/* For disassembly only; pattern left blank */]>;
3338 // Move from ARM core register to Special Register
3340 // No need to have both system and application versions, the encodings are the
3341 // same and the assembly parser has no way to distinguish between them. The mask
3342 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3343 // the mask with the fields to be accessed in the special register.
3344 def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3345 0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3346 NoItinerary, "msr", "\t$mask, $Rn",
3347 [/* For disassembly only; pattern left blank */]> {
3350 let Inst{19-16} = Rn;
3351 let Inst{20} = mask{4}; // R Bit
3353 let Inst{11-8} = mask{3-0};
3356 //===----------------------------------------------------------------------===//
3357 // Move between coprocessor and ARM core register -- for disassembly only
3360 class t2MovRCopro<string opc, bit direction, dag oops, dag iops,
3362 : T2Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3364 let Inst{27-24} = 0b1110;
3365 let Inst{20} = direction;
3375 let Inst{15-12} = Rt;
3376 let Inst{11-8} = cop;
3377 let Inst{23-21} = opc1;
3378 let Inst{7-5} = opc2;
3379 let Inst{3-0} = CRm;
3380 let Inst{19-16} = CRn;
3383 def t2MCR2 : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */,
3384 (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3385 c_imm:$CRm, i32imm:$opc2),
3386 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3387 imm:$CRm, imm:$opc2)]>;
3388 def t2MRC2 : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */,
3389 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
3390 c_imm:$CRm, i32imm:$opc2), []>;
3392 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3393 imm:$CRm, imm:$opc2),
3394 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3396 class t2MovRRCopro<string opc, bit direction,
3397 list<dag> pattern = [/* For disassembly only */]>
3398 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3399 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3400 let Inst{27-24} = 0b1100;
3401 let Inst{23-21} = 0b010;
3402 let Inst{20} = direction;
3410 let Inst{15-12} = Rt;
3411 let Inst{19-16} = Rt2;
3412 let Inst{11-8} = cop;
3413 let Inst{7-4} = opc1;
3414 let Inst{3-0} = CRm;
3417 def t2MCRR2 : t2MovRRCopro<"mcrr2",
3418 0 /* from ARM core register to coprocessor */,
3419 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3420 GPR:$Rt2, imm:$CRm)]>;
3421 def t2MRRC2 : t2MovRRCopro<"mrrc2",
3422 1 /* from coprocessor to ARM core register */>;
3424 //===----------------------------------------------------------------------===//
3425 // Other Coprocessor Instructions. For disassembly only.
3428 def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
3429 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3430 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3431 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3432 imm:$CRm, imm:$opc2)]> {
3433 let Inst{27-24} = 0b1110;
3442 let Inst{3-0} = CRm;
3444 let Inst{7-5} = opc2;
3445 let Inst{11-8} = cop;
3446 let Inst{15-12} = CRd;
3447 let Inst{19-16} = CRn;
3448 let Inst{23-20} = opc1;