1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 // Define Thumb2 specific addressing modes.
127 // t2addrmode_imm12 := reg + imm12
128 def t2addrmode_imm12 : Operand<i32>,
129 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
130 let PrintMethod = "printT2AddrModeImm12Operand";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
134 // t2addrmode_imm8 := reg - imm8
135 def t2addrmode_imm8 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137 let PrintMethod = "printT2AddrModeImm8Operand";
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141 def t2am_imm8_offset : Operand<i32>,
142 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
143 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
147 def t2addrmode_imm8s4 : Operand<i32>,
148 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
149 let PrintMethod = "printT2AddrModeImm8s4Operand";
150 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
153 // t2addrmode_so_reg := reg + (reg << imm2)
154 def t2addrmode_so_reg : Operand<i32>,
155 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
156 let PrintMethod = "printT2AddrModeSoRegOperand";
157 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
161 //===----------------------------------------------------------------------===//
162 // Multiclass helpers...
165 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
166 /// unary operation that produces a value. These are predicable and can be
167 /// changed to modify CPSR.
168 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
169 bit Cheap = 0, bit ReMat = 0> {
171 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
173 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
174 let isAsCheapAsAMove = Cheap;
175 let isReMaterializable = ReMat;
176 let Inst{31-27} = 0b11110;
178 let Inst{24-21} = opcod;
179 let Inst{20} = ?; // The S bit.
180 let Inst{19-16} = 0b1111; // Rn
184 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
185 opc, ".w\t$dst, $src",
186 [(set GPR:$dst, (opnode GPR:$src))]> {
187 let Inst{31-27} = 0b11101;
188 let Inst{26-25} = 0b01;
189 let Inst{24-21} = opcod;
190 let Inst{20} = ?; // The S bit.
191 let Inst{19-16} = 0b1111; // Rn
192 let Inst{14-12} = 0b000; // imm3
193 let Inst{7-6} = 0b00; // imm2
194 let Inst{5-4} = 0b00; // type
197 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
198 opc, ".w\t$dst, $src",
199 [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
200 let Inst{31-27} = 0b11101;
201 let Inst{26-25} = 0b01;
202 let Inst{24-21} = opcod;
203 let Inst{20} = ?; // The S bit.
204 let Inst{19-16} = 0b1111; // Rn
208 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
209 // binary operation that produces a value. These are predicable and can be
210 /// changed to modify CPSR.
211 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
212 bit Commutable = 0, string wide =""> {
214 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
215 opc, "\t$dst, $lhs, $rhs",
216 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
217 let Inst{31-27} = 0b11110;
219 let Inst{24-21} = opcod;
220 let Inst{20} = ?; // The S bit.
224 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
225 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
226 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
227 let isCommutable = Commutable;
228 let Inst{31-27} = 0b11101;
229 let Inst{26-25} = 0b01;
230 let Inst{24-21} = opcod;
231 let Inst{20} = ?; // The S bit.
232 let Inst{14-12} = 0b000; // imm3
233 let Inst{7-6} = 0b00; // imm2
234 let Inst{5-4} = 0b00; // type
237 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
238 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
239 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
240 let Inst{31-27} = 0b11101;
241 let Inst{26-25} = 0b01;
242 let Inst{24-21} = opcod;
243 let Inst{20} = ?; // The S bit.
247 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
248 // the ".w" prefix to indicate that they are wide.
249 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
250 bit Commutable = 0> :
251 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
253 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
254 /// reversed. It doesn't define the 'rr' form since it's handled by its
255 /// T2I_bin_irs counterpart.
256 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
258 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
259 opc, ".w\t$dst, $rhs, $lhs",
260 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
261 let Inst{31-27} = 0b11110;
263 let Inst{24-21} = opcod;
264 let Inst{20} = 0; // The S bit.
268 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
269 opc, "\t$dst, $rhs, $lhs",
270 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
271 let Inst{31-27} = 0b11101;
272 let Inst{26-25} = 0b01;
273 let Inst{24-21} = opcod;
274 let Inst{20} = 0; // The S bit.
278 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
279 /// instruction modifies the CPSR register.
280 let Defs = [CPSR] in {
281 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
282 bit Commutable = 0> {
284 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
285 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
286 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
287 let Inst{31-27} = 0b11110;
289 let Inst{24-21} = opcod;
290 let Inst{20} = 1; // The S bit.
294 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
295 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
296 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
297 let isCommutable = Commutable;
298 let Inst{31-27} = 0b11101;
299 let Inst{26-25} = 0b01;
300 let Inst{24-21} = opcod;
301 let Inst{20} = 1; // The S bit.
302 let Inst{14-12} = 0b000; // imm3
303 let Inst{7-6} = 0b00; // imm2
304 let Inst{5-4} = 0b00; // type
307 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
308 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
309 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
310 let Inst{31-27} = 0b11101;
311 let Inst{26-25} = 0b01;
312 let Inst{24-21} = opcod;
313 let Inst{20} = 1; // The S bit.
318 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
319 /// patterns for a binary operation that produces a value.
320 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
321 bit Commutable = 0> {
323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
324 opc, ".w\t$dst, $lhs, $rhs",
325 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
326 let Inst{31-27} = 0b11110;
329 let Inst{23-21} = op23_21;
330 let Inst{20} = 0; // The S bit.
334 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
335 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
336 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
337 let Inst{31-27} = 0b11110;
340 let Inst{23-21} = op23_21;
341 let Inst{20} = 0; // The S bit.
345 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
346 opc, ".w\t$dst, $lhs, $rhs",
347 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
348 let isCommutable = Commutable;
349 let Inst{31-27} = 0b11101;
350 let Inst{26-25} = 0b01;
352 let Inst{23-21} = op23_21;
353 let Inst{20} = 0; // The S bit.
354 let Inst{14-12} = 0b000; // imm3
355 let Inst{7-6} = 0b00; // imm2
356 let Inst{5-4} = 0b00; // type
359 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
360 opc, ".w\t$dst, $lhs, $rhs",
361 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
362 let Inst{31-27} = 0b11101;
363 let Inst{26-25} = 0b01;
365 let Inst{23-21} = op23_21;
366 let Inst{20} = 0; // The S bit.
370 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
371 /// for a binary operation that produces a value and use and define the carry
372 /// bit. It's not predicable.
373 let Uses = [CPSR] in {
374 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, bit Commutable = 0> {
376 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
377 opc, "\t$dst, $lhs, $rhs",
378 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
379 Requires<[IsThumb2, CarryDefIsUnused]> {
380 let Inst{31-27} = 0b11110;
382 let Inst{24-21} = opcod;
383 let Inst{20} = 0; // The S bit.
387 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
388 opc, ".w\t$dst, $lhs, $rhs",
389 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
390 Requires<[IsThumb2, CarryDefIsUnused]> {
391 let isCommutable = Commutable;
392 let Inst{31-27} = 0b11101;
393 let Inst{26-25} = 0b01;
394 let Inst{24-21} = opcod;
395 let Inst{20} = 0; // The S bit.
396 let Inst{14-12} = 0b000; // imm3
397 let Inst{7-6} = 0b00; // imm2
398 let Inst{5-4} = 0b00; // type
401 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
402 opc, ".w\t$dst, $lhs, $rhs",
403 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
404 Requires<[IsThumb2, CarryDefIsUnused]> {
405 let Inst{31-27} = 0b11101;
406 let Inst{26-25} = 0b01;
407 let Inst{24-21} = opcod;
408 let Inst{20} = 0; // The S bit.
410 // Carry setting variants
412 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
413 !strconcat(opc, "s\t$dst, $lhs, $rhs"),
414 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
415 Requires<[IsThumb2, CarryDefIsUsed]> {
417 let Inst{31-27} = 0b11110;
419 let Inst{24-21} = opcod;
420 let Inst{20} = 1; // The S bit.
424 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
425 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
426 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
427 Requires<[IsThumb2, CarryDefIsUsed]> {
429 let isCommutable = Commutable;
430 let Inst{31-27} = 0b11101;
431 let Inst{26-25} = 0b01;
432 let Inst{24-21} = opcod;
433 let Inst{20} = 1; // The S bit.
434 let Inst{14-12} = 0b000; // imm3
435 let Inst{7-6} = 0b00; // imm2
436 let Inst{5-4} = 0b00; // type
439 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
440 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
441 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
442 Requires<[IsThumb2, CarryDefIsUsed]> {
444 let Inst{31-27} = 0b11101;
445 let Inst{26-25} = 0b01;
446 let Inst{24-21} = opcod;
447 let Inst{20} = 1; // The S bit.
452 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
453 let Defs = [CPSR] in {
454 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
456 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
458 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"),
459 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
460 let Inst{31-27} = 0b11110;
462 let Inst{24-21} = opcod;
463 let Inst{20} = 1; // The S bit.
467 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
469 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"),
470 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
471 let Inst{31-27} = 0b11101;
472 let Inst{26-25} = 0b01;
473 let Inst{24-21} = opcod;
474 let Inst{20} = 1; // The S bit.
479 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
480 // rotate operation that produces a value.
481 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
483 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
484 opc, ".w\t$dst, $lhs, $rhs",
485 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
486 let Inst{31-27} = 0b11101;
487 let Inst{26-21} = 0b010010;
488 let Inst{19-16} = 0b1111; // Rn
489 let Inst{5-4} = opcod;
492 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
493 opc, ".w\t$dst, $lhs, $rhs",
494 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
495 let Inst{31-27} = 0b11111;
496 let Inst{26-23} = 0b0100;
497 let Inst{22-21} = opcod;
498 let Inst{15-12} = 0b1111;
499 let Inst{7-4} = 0b0000;
503 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
504 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
505 /// a explicit result, only implicitly set CPSR.
506 let Defs = [CPSR] in {
507 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
509 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
510 opc, ".w\t$lhs, $rhs",
511 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
512 let Inst{31-27} = 0b11110;
514 let Inst{24-21} = opcod;
515 let Inst{20} = 1; // The S bit.
517 let Inst{11-8} = 0b1111; // Rd
520 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
521 opc, ".w\t$lhs, $rhs",
522 [(opnode GPR:$lhs, GPR:$rhs)]> {
523 let Inst{31-27} = 0b11101;
524 let Inst{26-25} = 0b01;
525 let Inst{24-21} = opcod;
526 let Inst{20} = 1; // The S bit.
527 let Inst{14-12} = 0b000; // imm3
528 let Inst{11-8} = 0b1111; // Rd
529 let Inst{7-6} = 0b00; // imm2
530 let Inst{5-4} = 0b00; // type
533 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
534 opc, ".w\t$lhs, $rhs",
535 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
536 let Inst{31-27} = 0b11101;
537 let Inst{26-25} = 0b01;
538 let Inst{24-21} = opcod;
539 let Inst{20} = 1; // The S bit.
540 let Inst{11-8} = 0b1111; // Rd
545 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
546 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
547 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
548 opc, ".w\t$dst, $addr",
549 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
550 let Inst{31-27} = 0b11111;
551 let Inst{26-25} = 0b00;
552 let Inst{24} = signed;
554 let Inst{22-21} = opcod;
555 let Inst{20} = 1; // load
557 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
558 opc, "\t$dst, $addr",
559 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
560 let Inst{31-27} = 0b11111;
561 let Inst{26-25} = 0b00;
562 let Inst{24} = signed;
564 let Inst{22-21} = opcod;
565 let Inst{20} = 1; // load
567 // Offset: index==TRUE, wback==FALSE
568 let Inst{10} = 1; // The P bit.
569 let Inst{8} = 0; // The W bit.
571 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
572 opc, ".w\t$dst, $addr",
573 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
574 let Inst{31-27} = 0b11111;
575 let Inst{26-25} = 0b00;
576 let Inst{24} = signed;
578 let Inst{22-21} = opcod;
579 let Inst{20} = 1; // load
580 let Inst{11-6} = 0b000000;
582 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
583 opc, ".w\t$dst, $addr",
584 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
585 let isReMaterializable = 1;
586 let Inst{31-27} = 0b11111;
587 let Inst{26-25} = 0b00;
588 let Inst{24} = signed;
589 let Inst{23} = ?; // add = (U == '1')
590 let Inst{22-21} = opcod;
591 let Inst{20} = 1; // load
592 let Inst{19-16} = 0b1111; // Rn
596 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
597 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
598 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
599 opc, ".w\t$src, $addr",
600 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
601 let Inst{31-27} = 0b11111;
602 let Inst{26-23} = 0b0001;
603 let Inst{22-21} = opcod;
604 let Inst{20} = 0; // !load
606 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
607 opc, "\t$src, $addr",
608 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
609 let Inst{31-27} = 0b11111;
610 let Inst{26-23} = 0b0000;
611 let Inst{22-21} = opcod;
612 let Inst{20} = 0; // !load
614 // Offset: index==TRUE, wback==FALSE
615 let Inst{10} = 1; // The P bit.
616 let Inst{8} = 0; // The W bit.
618 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
619 opc, ".w\t$src, $addr",
620 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
621 let Inst{31-27} = 0b11111;
622 let Inst{26-23} = 0b0000;
623 let Inst{22-21} = opcod;
624 let Inst{20} = 0; // !load
625 let Inst{11-6} = 0b000000;
629 /// T2I_picld - Defines the PIC load pattern.
630 class T2I_picld<string opc, PatFrag opnode> :
631 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi,
632 !strconcat("\n${addr:label}:\n\t", opc), "\t$dst, $addr",
633 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
635 /// T2I_picst - Defines the PIC store pattern.
636 class T2I_picst<string opc, PatFrag opnode> :
637 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer,
638 !strconcat("\n${addr:label}:\n\t", opc), "\t$src, $addr",
639 [(opnode GPR:$src, addrmodepc:$addr)]>;
642 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
643 /// register and one whose operand is a register rotated by 8/16/24.
644 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
645 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
646 opc, ".w\t$dst, $src",
647 [(set GPR:$dst, (opnode GPR:$src))]> {
648 let Inst{31-27} = 0b11111;
649 let Inst{26-23} = 0b0100;
650 let Inst{22-20} = opcod;
651 let Inst{19-16} = 0b1111; // Rn
652 let Inst{15-12} = 0b1111;
654 let Inst{5-4} = 0b00; // rotate
656 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
657 opc, ".w\t$dst, $src, ror $rot",
658 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
659 let Inst{31-27} = 0b11111;
660 let Inst{26-23} = 0b0100;
661 let Inst{22-20} = opcod;
662 let Inst{19-16} = 0b1111; // Rn
663 let Inst{15-12} = 0b1111;
665 let Inst{5-4} = {?,?}; // rotate
669 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
670 /// register and one whose operand is a register rotated by 8/16/24.
671 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
672 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
673 opc, "\t$dst, $LHS, $RHS",
674 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]> {
675 let Inst{31-27} = 0b11111;
676 let Inst{26-23} = 0b0100;
677 let Inst{22-20} = opcod;
678 let Inst{15-12} = 0b1111;
680 let Inst{5-4} = 0b00; // rotate
682 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
683 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
684 [(set GPR:$dst, (opnode GPR:$LHS,
685 (rotr GPR:$RHS, rot_imm:$rot)))]> {
686 let Inst{31-27} = 0b11111;
687 let Inst{26-23} = 0b0100;
688 let Inst{22-20} = opcod;
689 let Inst{15-12} = 0b1111;
691 let Inst{5-4} = {?,?}; // rotate
695 //===----------------------------------------------------------------------===//
697 //===----------------------------------------------------------------------===//
699 //===----------------------------------------------------------------------===//
700 // Miscellaneous Instructions.
703 // LEApcrel - Load a pc-relative address into a register without offending the
705 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
706 "adr$p.w\t$dst, #$label", []> {
707 let Inst{31-27} = 0b11110;
708 let Inst{25-24} = 0b10;
709 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
712 let Inst{19-16} = 0b1111; // Rn
715 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
716 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
717 "adr$p.w\t$dst, #${label}_${id}", []> {
718 let Inst{31-27} = 0b11110;
719 let Inst{25-24} = 0b10;
720 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
723 let Inst{19-16} = 0b1111; // Rn
727 // ADD r, sp, {so_imm|i12}
728 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
729 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
730 let Inst{31-27} = 0b11110;
732 let Inst{24-21} = 0b1000;
733 let Inst{20} = ?; // The S bit.
734 let Inst{19-16} = 0b1101; // Rn = sp
737 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
738 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
739 let Inst{31-27} = 0b11110;
741 let Inst{24-21} = 0b0000;
742 let Inst{20} = 0; // The S bit.
743 let Inst{19-16} = 0b1101; // Rn = sp
748 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
749 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
750 let Inst{31-27} = 0b11101;
751 let Inst{26-25} = 0b01;
752 let Inst{24-21} = 0b1000;
753 let Inst{20} = ?; // The S bit.
754 let Inst{19-16} = 0b1101; // Rn = sp
758 // SUB r, sp, {so_imm|i12}
759 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
760 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
761 let Inst{31-27} = 0b11110;
763 let Inst{24-21} = 0b1101;
764 let Inst{20} = ?; // The S bit.
765 let Inst{19-16} = 0b1101; // Rn = sp
768 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
769 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
770 let Inst{31-27} = 0b11110;
772 let Inst{24-21} = 0b0101;
773 let Inst{20} = 0; // The S bit.
774 let Inst{19-16} = 0b1101; // Rn = sp
779 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
781 "sub", "\t$dst, $sp, $rhs", []> {
782 let Inst{31-27} = 0b11101;
783 let Inst{26-25} = 0b01;
784 let Inst{24-21} = 0b1101;
785 let Inst{20} = ?; // The S bit.
786 let Inst{19-16} = 0b1101; // Rn = sp
790 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
791 let usesCustomInserter = 1 in { // Expanded after instruction selection.
792 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
793 NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
794 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
795 NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
796 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
797 NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
798 } // usesCustomInserter
801 //===----------------------------------------------------------------------===//
802 // Load / store Instructions.
806 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
807 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
809 // Loads with zero extension
810 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
811 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
813 // Loads with sign extension
814 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
815 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
817 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
819 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
820 (ins t2addrmode_imm8s4:$addr),
821 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
822 def t2LDRDpci : T2Ii8s4<?, ?, 1, (outs GPR:$dst1, GPR:$dst2),
823 (ins i32imm:$addr), IIC_iLoadi,
824 "ldrd", "\t$dst1, $addr", []> {
825 let Inst{19-16} = 0b1111; // Rn
829 // zextload i1 -> zextload i8
830 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
831 (t2LDRBi12 t2addrmode_imm12:$addr)>;
832 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
833 (t2LDRBi8 t2addrmode_imm8:$addr)>;
834 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
835 (t2LDRBs t2addrmode_so_reg:$addr)>;
836 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
837 (t2LDRBpci tconstpool:$addr)>;
839 // extload -> zextload
840 // FIXME: Reduce the number of patterns by legalizing extload to zextload
842 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
843 (t2LDRBi12 t2addrmode_imm12:$addr)>;
844 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
845 (t2LDRBi8 t2addrmode_imm8:$addr)>;
846 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
847 (t2LDRBs t2addrmode_so_reg:$addr)>;
848 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
849 (t2LDRBpci tconstpool:$addr)>;
851 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
852 (t2LDRBi12 t2addrmode_imm12:$addr)>;
853 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
854 (t2LDRBi8 t2addrmode_imm8:$addr)>;
855 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
856 (t2LDRBs t2addrmode_so_reg:$addr)>;
857 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
858 (t2LDRBpci tconstpool:$addr)>;
860 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
861 (t2LDRHi12 t2addrmode_imm12:$addr)>;
862 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
863 (t2LDRHi8 t2addrmode_imm8:$addr)>;
864 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
865 (t2LDRHs t2addrmode_so_reg:$addr)>;
866 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
867 (t2LDRHpci tconstpool:$addr)>;
871 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
872 (ins t2addrmode_imm8:$addr),
873 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
874 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
877 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
878 (ins GPR:$base, t2am_imm8_offset:$offset),
879 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
880 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
883 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
884 (ins t2addrmode_imm8:$addr),
885 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
886 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
888 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
889 (ins GPR:$base, t2am_imm8_offset:$offset),
890 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
891 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
894 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
895 (ins t2addrmode_imm8:$addr),
896 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
897 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
899 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
900 (ins GPR:$base, t2am_imm8_offset:$offset),
901 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
902 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
905 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
906 (ins t2addrmode_imm8:$addr),
907 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
908 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
910 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
911 (ins GPR:$base, t2am_imm8_offset:$offset),
912 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
913 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
916 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
917 (ins t2addrmode_imm8:$addr),
918 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
919 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
921 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
922 (ins GPR:$base, t2am_imm8_offset:$offset),
923 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
924 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
929 defm t2STR : T2I_st<0b10, "str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
930 defm t2STRB : T2I_st<0b00, "strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
931 defm t2STRH : T2I_st<0b01, "strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
934 let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
935 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
936 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
937 IIC_iStorer, "strd", "\t$src1, $addr", []>;
940 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
941 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
942 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
943 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
945 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
947 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
948 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
949 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
950 "str", "\t$src, [$base], $offset", "$base = $base_wb",
952 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
954 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
955 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
956 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
957 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
959 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
961 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
962 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
963 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
964 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
966 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
968 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
969 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
970 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
971 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
973 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
975 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
976 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
977 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
978 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
980 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
983 // FIXME: ldrd / strd pre / post variants
985 //===----------------------------------------------------------------------===//
986 // Load / store multiple Instructions.
989 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
990 def t2LDM : T2XI<(outs),
991 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
992 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
993 let Inst{31-27} = 0b11101;
994 let Inst{26-25} = 0b00;
995 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
997 let Inst{21} = ?; // The W bit.
998 let Inst{20} = 1; // Load
1001 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1002 def t2STM : T2XI<(outs),
1003 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1004 IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1005 let Inst{31-27} = 0b11101;
1006 let Inst{26-25} = 0b00;
1007 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1009 let Inst{21} = ?; // The W bit.
1010 let Inst{20} = 0; // Store
1013 //===----------------------------------------------------------------------===//
1014 // Move Instructions.
1017 let neverHasSideEffects = 1 in
1018 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1019 "mov", ".w\t$dst, $src", []> {
1020 let Inst{31-27} = 0b11101;
1021 let Inst{26-25} = 0b01;
1022 let Inst{24-21} = 0b0010;
1023 let Inst{20} = ?; // The S bit.
1024 let Inst{19-16} = 0b1111; // Rn
1025 let Inst{14-12} = 0b000;
1026 let Inst{7-4} = 0b0000;
1029 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1030 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1031 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1032 "mov", ".w\t$dst, $src",
1033 [(set GPR:$dst, t2_so_imm:$src)]> {
1034 let Inst{31-27} = 0b11110;
1036 let Inst{24-21} = 0b0010;
1037 let Inst{20} = ?; // The S bit.
1038 let Inst{19-16} = 0b1111; // Rn
1042 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1043 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1044 "movw", "\t$dst, $src",
1045 [(set GPR:$dst, imm0_65535:$src)]> {
1046 let Inst{31-27} = 0b11110;
1048 let Inst{24-21} = 0b0010;
1049 let Inst{20} = 0; // The S bit.
1053 let Constraints = "$src = $dst" in
1054 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
1055 "movt", "\t$dst, $imm",
1057 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
1058 let Inst{31-27} = 0b11110;
1060 let Inst{24-21} = 0b0110;
1061 let Inst{20} = 0; // The S bit.
1065 def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
1067 //===----------------------------------------------------------------------===//
1068 // Extend Instructions.
1073 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1074 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1075 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1076 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1078 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1079 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1080 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1081 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1083 // TODO: SXT(A){B|H}16
1087 let AddedComplexity = 16 in {
1088 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1089 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1090 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1091 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1092 defm t2UXTB16 : T2I_unary_rrot<0b011, "uxtb16",
1093 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1095 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1096 (t2UXTB16r_rot GPR:$Src, 24)>;
1097 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1098 (t2UXTB16r_rot GPR:$Src, 8)>;
1100 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1101 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1102 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1103 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1106 //===----------------------------------------------------------------------===//
1107 // Arithmetic Instructions.
1110 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1111 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1112 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1113 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1115 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1116 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1117 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1118 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1119 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1121 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1122 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1123 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1124 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1127 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1128 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1129 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1130 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1132 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1133 let AddedComplexity = 1 in
1134 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1135 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1136 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1137 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1138 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1139 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1142 //===----------------------------------------------------------------------===//
1143 // Shift and rotate Instructions.
1146 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1147 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1148 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1149 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1151 let Uses = [CPSR] in {
1152 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1153 "rrx", "\t$dst, $src",
1154 [(set GPR:$dst, (ARMrrx GPR:$src))]> {
1155 let Inst{31-27} = 0b11101;
1156 let Inst{26-25} = 0b01;
1157 let Inst{24-21} = 0b0010;
1158 let Inst{20} = ?; // The S bit.
1159 let Inst{19-16} = 0b1111; // Rn
1160 let Inst{14-12} = 0b000;
1161 let Inst{7-4} = 0b0011;
1165 let Defs = [CPSR] in {
1166 def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1167 "lsrs.w\t$dst, $src, #1",
1168 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
1169 let Inst{31-27} = 0b11101;
1170 let Inst{26-25} = 0b01;
1171 let Inst{24-21} = 0b0010;
1172 let Inst{20} = 1; // The S bit.
1173 let Inst{19-16} = 0b1111; // Rn
1174 let Inst{5-4} = 0b01; // Shift type.
1175 // Shift amount = Inst{14-12:7-6} = 1.
1176 let Inst{14-12} = 0b000;
1177 let Inst{7-6} = 0b01;
1179 def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1180 "asrs.w\t$dst, $src, #1",
1181 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
1182 let Inst{31-27} = 0b11101;
1183 let Inst{26-25} = 0b01;
1184 let Inst{24-21} = 0b0010;
1185 let Inst{20} = 1; // The S bit.
1186 let Inst{19-16} = 0b1111; // Rn
1187 let Inst{5-4} = 0b10; // Shift type.
1188 // Shift amount = Inst{14-12:7-6} = 1.
1189 let Inst{14-12} = 0b000;
1190 let Inst{7-6} = 0b01;
1194 //===----------------------------------------------------------------------===//
1195 // Bitwise Instructions.
1198 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1199 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1200 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1201 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1202 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1203 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1205 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1206 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1208 let Constraints = "$src = $dst" in
1209 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1210 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1211 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
1212 let Inst{31-27} = 0b11110;
1214 let Inst{24-20} = 0b10110;
1215 let Inst{19-16} = 0b1111; // Rn
1219 def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1220 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1221 let Inst{31-27} = 0b11110;
1223 let Inst{24-20} = 0b10100;
1227 def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1228 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1229 let Inst{31-27} = 0b11110;
1231 let Inst{24-20} = 0b11100;
1235 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1236 // Added for disassembler with the pattern field purposely left blank.
1237 // FIXME: Utilize this instruction in codgen.
1238 def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1239 IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> {
1240 let Inst{31-27} = 0b11110;
1242 let Inst{24-20} = 0b10110;
1246 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1249 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1250 let AddedComplexity = 1 in
1251 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1254 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
1255 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
1257 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1258 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
1259 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
1260 Requires<[IsThumb2]>;
1262 def : T2Pat<(t2_so_imm_not:$src),
1263 (t2MVNi t2_so_imm_not:$src)>;
1265 //===----------------------------------------------------------------------===//
1266 // Multiply Instructions.
1268 let isCommutable = 1 in
1269 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1270 "mul", "\t$dst, $a, $b",
1271 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
1272 let Inst{31-27} = 0b11111;
1273 let Inst{26-23} = 0b0110;
1274 let Inst{22-20} = 0b000;
1275 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1276 let Inst{7-4} = 0b0000; // Multiply
1279 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1280 "mla", "\t$dst, $a, $b, $c",
1281 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
1282 let Inst{31-27} = 0b11111;
1283 let Inst{26-23} = 0b0110;
1284 let Inst{22-20} = 0b000;
1285 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1286 let Inst{7-4} = 0b0000; // Multiply
1289 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1290 "mls", "\t$dst, $a, $b, $c",
1291 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
1292 let Inst{31-27} = 0b11111;
1293 let Inst{26-23} = 0b0110;
1294 let Inst{22-20} = 0b000;
1295 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1296 let Inst{7-4} = 0b0001; // Multiply and Subtract
1299 // Extra precision multiplies with low / high results
1300 let neverHasSideEffects = 1 in {
1301 let isCommutable = 1 in {
1302 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1303 "smull", "\t$ldst, $hdst, $a, $b", []> {
1304 let Inst{31-27} = 0b11111;
1305 let Inst{26-23} = 0b0111;
1306 let Inst{22-20} = 0b000;
1307 let Inst{7-4} = 0b0000;
1310 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1311 "umull", "\t$ldst, $hdst, $a, $b", []> {
1312 let Inst{31-27} = 0b11111;
1313 let Inst{26-23} = 0b0111;
1314 let Inst{22-20} = 0b010;
1315 let Inst{7-4} = 0b0000;
1319 // Multiply + accumulate
1320 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1321 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1322 let Inst{31-27} = 0b11111;
1323 let Inst{26-23} = 0b0111;
1324 let Inst{22-20} = 0b100;
1325 let Inst{7-4} = 0b0000;
1328 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1329 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1330 let Inst{31-27} = 0b11111;
1331 let Inst{26-23} = 0b0111;
1332 let Inst{22-20} = 0b110;
1333 let Inst{7-4} = 0b0000;
1336 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1337 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1338 let Inst{31-27} = 0b11111;
1339 let Inst{26-23} = 0b0111;
1340 let Inst{22-20} = 0b110;
1341 let Inst{7-4} = 0b0110;
1343 } // neverHasSideEffects
1345 // Most significant word multiply
1346 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1347 "smmul", "\t$dst, $a, $b",
1348 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
1349 let Inst{31-27} = 0b11111;
1350 let Inst{26-23} = 0b0110;
1351 let Inst{22-20} = 0b101;
1352 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1353 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1356 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1357 "smmla", "\t$dst, $a, $b, $c",
1358 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
1359 let Inst{31-27} = 0b11111;
1360 let Inst{26-23} = 0b0110;
1361 let Inst{22-20} = 0b101;
1362 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1363 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1367 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1368 "smmls", "\t$dst, $a, $b, $c",
1369 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
1370 let Inst{31-27} = 0b11111;
1371 let Inst{26-23} = 0b0110;
1372 let Inst{22-20} = 0b110;
1373 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1374 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1377 multiclass T2I_smul<string opc, PatFrag opnode> {
1378 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1379 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1380 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1381 (sext_inreg GPR:$b, i16)))]> {
1382 let Inst{31-27} = 0b11111;
1383 let Inst{26-23} = 0b0110;
1384 let Inst{22-20} = 0b001;
1385 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1386 let Inst{7-6} = 0b00;
1387 let Inst{5-4} = 0b00;
1390 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1391 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1392 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1393 (sra GPR:$b, (i32 16))))]> {
1394 let Inst{31-27} = 0b11111;
1395 let Inst{26-23} = 0b0110;
1396 let Inst{22-20} = 0b001;
1397 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1398 let Inst{7-6} = 0b00;
1399 let Inst{5-4} = 0b01;
1402 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1403 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1404 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1405 (sext_inreg GPR:$b, i16)))]> {
1406 let Inst{31-27} = 0b11111;
1407 let Inst{26-23} = 0b0110;
1408 let Inst{22-20} = 0b001;
1409 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1410 let Inst{7-6} = 0b00;
1411 let Inst{5-4} = 0b10;
1414 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1415 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1416 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1417 (sra GPR:$b, (i32 16))))]> {
1418 let Inst{31-27} = 0b11111;
1419 let Inst{26-23} = 0b0110;
1420 let Inst{22-20} = 0b001;
1421 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1422 let Inst{7-6} = 0b00;
1423 let Inst{5-4} = 0b11;
1426 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1427 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1428 [(set GPR:$dst, (sra (opnode GPR:$a,
1429 (sext_inreg GPR:$b, i16)), (i32 16)))]> {
1430 let Inst{31-27} = 0b11111;
1431 let Inst{26-23} = 0b0110;
1432 let Inst{22-20} = 0b011;
1433 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1434 let Inst{7-6} = 0b00;
1435 let Inst{5-4} = 0b00;
1438 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1439 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1440 [(set GPR:$dst, (sra (opnode GPR:$a,
1441 (sra GPR:$b, (i32 16))), (i32 16)))]> {
1442 let Inst{31-27} = 0b11111;
1443 let Inst{26-23} = 0b0110;
1444 let Inst{22-20} = 0b011;
1445 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1446 let Inst{7-6} = 0b00;
1447 let Inst{5-4} = 0b01;
1452 multiclass T2I_smla<string opc, PatFrag opnode> {
1453 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1454 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1455 [(set GPR:$dst, (add GPR:$acc,
1456 (opnode (sext_inreg GPR:$a, i16),
1457 (sext_inreg GPR:$b, i16))))]> {
1458 let Inst{31-27} = 0b11111;
1459 let Inst{26-23} = 0b0110;
1460 let Inst{22-20} = 0b001;
1461 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1462 let Inst{7-6} = 0b00;
1463 let Inst{5-4} = 0b00;
1466 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1467 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1468 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1469 (sra GPR:$b, (i32 16)))))]> {
1470 let Inst{31-27} = 0b11111;
1471 let Inst{26-23} = 0b0110;
1472 let Inst{22-20} = 0b001;
1473 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1474 let Inst{7-6} = 0b00;
1475 let Inst{5-4} = 0b01;
1478 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1479 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1480 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1481 (sext_inreg GPR:$b, i16))))]> {
1482 let Inst{31-27} = 0b11111;
1483 let Inst{26-23} = 0b0110;
1484 let Inst{22-20} = 0b001;
1485 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1486 let Inst{7-6} = 0b00;
1487 let Inst{5-4} = 0b10;
1490 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1491 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1492 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1493 (sra GPR:$b, (i32 16)))))]> {
1494 let Inst{31-27} = 0b11111;
1495 let Inst{26-23} = 0b0110;
1496 let Inst{22-20} = 0b001;
1497 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1498 let Inst{7-6} = 0b00;
1499 let Inst{5-4} = 0b11;
1502 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1503 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1504 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1505 (sext_inreg GPR:$b, i16)), (i32 16))))]> {
1506 let Inst{31-27} = 0b11111;
1507 let Inst{26-23} = 0b0110;
1508 let Inst{22-20} = 0b011;
1509 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1510 let Inst{7-6} = 0b00;
1511 let Inst{5-4} = 0b00;
1514 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1515 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1516 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1517 (sra GPR:$b, (i32 16))), (i32 16))))]> {
1518 let Inst{31-27} = 0b11111;
1519 let Inst{26-23} = 0b0110;
1520 let Inst{22-20} = 0b011;
1521 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1522 let Inst{7-6} = 0b00;
1523 let Inst{5-4} = 0b01;
1527 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1528 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1530 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1531 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1534 //===----------------------------------------------------------------------===//
1535 // Misc. Arithmetic Instructions.
1538 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, InstrItinClass itin,
1539 string opc, string asm, list<dag> pattern>
1540 : T2I<oops, iops, itin, opc, asm, pattern> {
1541 let Inst{31-27} = 0b11111;
1542 let Inst{26-22} = 0b01010;
1543 let Inst{21-20} = op1;
1544 let Inst{15-12} = 0b1111;
1545 let Inst{7-6} = 0b10;
1546 let Inst{5-4} = op2;
1549 def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1550 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
1552 def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1553 "rbit", "\t$dst, $src",
1554 [(set GPR:$dst, (ARMrbit GPR:$src))]>;
1556 def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1557 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
1559 def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1560 "rev16", ".w\t$dst, $src",
1562 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1563 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1564 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1565 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
1567 def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1568 "revsh", ".w\t$dst, $src",
1571 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1572 (shl GPR:$src, (i32 8))), i16))]>;
1574 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1575 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1576 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1577 (and (shl GPR:$src2, (i32 imm:$shamt)),
1579 let Inst{31-27} = 0b11101;
1580 let Inst{26-25} = 0b01;
1581 let Inst{24-20} = 0b01100;
1582 let Inst{5} = 0; // BT form
1586 // Alternate cases for PKHBT where identities eliminate some nodes.
1587 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1588 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
1589 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1590 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1592 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1593 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1594 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1595 (and (sra GPR:$src2, imm16_31:$shamt),
1597 let Inst{31-27} = 0b11101;
1598 let Inst{26-25} = 0b01;
1599 let Inst{24-20} = 0b01100;
1600 let Inst{5} = 1; // TB form
1604 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1605 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1606 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1607 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
1608 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
1609 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1610 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1612 //===----------------------------------------------------------------------===//
1613 // Comparison Instructions...
1616 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
1617 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1618 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
1619 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1621 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
1622 // Compare-to-zero still works out, just not the relationals
1623 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
1624 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1625 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
1626 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1628 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1629 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1631 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1632 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
1634 defm t2TST : T2I_cmp_irs<0b0000, "tst",
1635 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1636 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
1637 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1639 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1640 // Short range conditional branch. Looks awesome for loops. Need to figure
1641 // out how to use this one.
1644 // Conditional moves
1645 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1646 // a two-value operand where a dag node expects two operands. :(
1647 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
1648 "mov", ".w\t$dst, $true",
1649 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1650 RegConstraint<"$false = $dst"> {
1651 let Inst{31-27} = 0b11101;
1652 let Inst{26-25} = 0b01;
1653 let Inst{24-21} = 0b0010;
1654 let Inst{20} = 0; // The S bit.
1655 let Inst{19-16} = 0b1111; // Rn
1656 let Inst{14-12} = 0b000;
1657 let Inst{7-4} = 0b0000;
1660 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1661 IIC_iCMOVi, "mov", ".w\t$dst, $true",
1662 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1663 RegConstraint<"$false = $dst"> {
1664 let Inst{31-27} = 0b11110;
1666 let Inst{24-21} = 0b0010;
1667 let Inst{20} = 0; // The S bit.
1668 let Inst{19-16} = 0b1111; // Rn
1672 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
1673 string opc, string asm, list<dag> pattern>
1674 : T2I<oops, iops, itin, opc, asm, pattern> {
1675 let Inst{31-27} = 0b11101;
1676 let Inst{26-25} = 0b01;
1677 let Inst{24-21} = 0b0010;
1678 let Inst{20} = 0; // The S bit.
1679 let Inst{19-16} = 0b1111; // Rn
1680 let Inst{5-4} = opcod; // Shift type.
1682 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
1683 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1684 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
1685 RegConstraint<"$false = $dst">;
1686 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
1687 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1688 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
1689 RegConstraint<"$false = $dst">;
1690 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
1691 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1692 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
1693 RegConstraint<"$false = $dst">;
1694 def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
1695 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1696 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
1697 RegConstraint<"$false = $dst">;
1699 //===----------------------------------------------------------------------===//
1700 // Atomic operations intrinsics
1703 // memory barriers protect the atomic sequences
1704 let hasSideEffects = 1 in {
1705 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
1706 Pseudo, NoItinerary,
1708 [(ARMMemBarrierV7)]>,
1709 Requires<[IsThumb2]> {
1710 let Inst{31-4} = 0xF3BF8F5;
1711 // FIXME: add support for options other than a full system DMB
1712 let Inst{3-0} = 0b1111;
1715 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
1716 Pseudo, NoItinerary,
1718 [(ARMSyncBarrierV7)]>,
1719 Requires<[IsThumb2]> {
1720 let Inst{31-4} = 0xF3BF8F4;
1721 // FIXME: add support for options other than a full system DSB
1722 let Inst{3-0} = 0b1111;
1726 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1727 InstrItinClass itin, string opc, string asm, string cstr,
1728 list<dag> pattern, bits<4> rt2 = 0b1111>
1729 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
1730 let Inst{31-27} = 0b11101;
1731 let Inst{26-20} = 0b0001101;
1732 let Inst{11-8} = rt2;
1733 let Inst{7-6} = 0b01;
1734 let Inst{5-4} = opcod;
1735 let Inst{3-0} = 0b1111;
1737 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1738 InstrItinClass itin, string opc, string asm, string cstr,
1739 list<dag> pattern, bits<4> rt2 = 0b1111>
1740 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
1741 let Inst{31-27} = 0b11101;
1742 let Inst{26-20} = 0b0001100;
1743 let Inst{11-8} = rt2;
1744 let Inst{7-6} = 0b01;
1745 let Inst{5-4} = opcod;
1748 let mayLoad = 1 in {
1749 def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
1750 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
1752 def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
1753 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
1755 def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
1756 Size4Bytes, NoItinerary,
1757 "ldrex", "\t$dest, [$ptr]", "",
1759 let Inst{31-27} = 0b11101;
1760 let Inst{26-20} = 0b0000101;
1761 let Inst{11-8} = 0b1111;
1762 let Inst{7-0} = 0b00000000; // imm8 = 0
1764 def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
1765 AddrModeNone, Size4Bytes, NoItinerary,
1766 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
1770 let mayStore = 1, Constraints = "@earlyclobber $success" in {
1771 def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1772 AddrModeNone, Size4Bytes, NoItinerary,
1773 "strexb", "\t$success, $src, [$ptr]", "", []>;
1774 def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1775 AddrModeNone, Size4Bytes, NoItinerary,
1776 "strexh", "\t$success, $src, [$ptr]", "", []>;
1777 def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1778 AddrModeNone, Size4Bytes, NoItinerary,
1779 "strex", "\t$success, $src, [$ptr]", "",
1781 let Inst{31-27} = 0b11101;
1782 let Inst{26-20} = 0b0000100;
1783 let Inst{7-0} = 0b00000000; // imm8 = 0
1785 def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
1786 (ins GPR:$src, GPR:$src2, GPR:$ptr),
1787 AddrModeNone, Size4Bytes, NoItinerary,
1788 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
1792 //===----------------------------------------------------------------------===//
1796 // __aeabi_read_tp preserves the registers r1-r3.
1798 Defs = [R0, R12, LR, CPSR] in {
1799 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
1800 "bl\t__aeabi_read_tp",
1801 [(set R0, ARMthread_pointer)]> {
1802 let Inst{31-27} = 0b11110;
1803 let Inst{15-14} = 0b11;
1808 //===----------------------------------------------------------------------===//
1809 // SJLJ Exception handling intrinsics
1810 // eh_sjlj_setjmp() is an instruction sequence to store the return
1811 // address and save #0 in R0 for the non-longjmp case.
1812 // Since by its nature we may be coming from some other function to get
1813 // here, and we're using the stack frame for the containing function to
1814 // save/restore registers, we can't keep anything live in regs across
1815 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1816 // when we get here from a longjmp(). We force everthing out of registers
1817 // except for our own input by listing the relevant registers in Defs. By
1818 // doing so, we also cause the prologue/epilogue code to actively preserve
1819 // all of the callee-saved resgisters, which is exactly what we want.
1820 // The current SP is passed in $val, and we reuse the reg as a scratch.
1822 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1823 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1824 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1826 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
1827 AddrModeNone, SizeSpecial, NoItinerary,
1828 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
1830 "\tadds\t$val, #9\n"
1831 "\tstr\t$val, [$src, #4]\n"
1834 "\tmovs\tr0, #1\t@ end eh.setjmp\n"
1836 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>;
1841 //===----------------------------------------------------------------------===//
1842 // Control-Flow Instructions
1845 // FIXME: remove when we have a way to marking a MI with these properties.
1846 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1848 // FIXME: Should pc be an implicit operand like PICADD, etc?
1849 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1850 hasExtraDefRegAllocReq = 1 in
1851 def t2LDM_RET : T2XI<(outs),
1852 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1853 IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb",
1855 let Inst{31-27} = 0b11101;
1856 let Inst{26-25} = 0b00;
1857 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1859 let Inst{21} = ?; // The W bit.
1860 let Inst{20} = 1; // Load
1863 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1864 let isPredicable = 1 in
1865 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
1867 [(br bb:$target)]> {
1868 let Inst{31-27} = 0b11110;
1869 let Inst{15-14} = 0b10;
1873 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1876 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
1877 IIC_Br, "mov\tpc, $target\n$jt",
1878 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
1879 let Inst{31-27} = 0b11101;
1880 let Inst{26-20} = 0b0100100;
1881 let Inst{19-16} = 0b1111;
1882 let Inst{14-12} = 0b000;
1883 let Inst{11-8} = 0b1111; // Rd = pc
1884 let Inst{7-4} = 0b0000;
1887 // FIXME: Add a non-pc based case that can be predicated.
1890 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1891 IIC_Br, "tbb\t$index\n$jt", []> {
1892 let Inst{31-27} = 0b11101;
1893 let Inst{26-20} = 0b0001101;
1894 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
1895 let Inst{15-8} = 0b11110000;
1896 let Inst{7-4} = 0b0000; // B form
1901 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1902 IIC_Br, "tbh\t$index\n$jt", []> {
1903 let Inst{31-27} = 0b11101;
1904 let Inst{26-20} = 0b0001101;
1905 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
1906 let Inst{15-8} = 0b11110000;
1907 let Inst{7-4} = 0b0001; // H form
1909 } // isNotDuplicable, isIndirectBranch
1911 } // isBranch, isTerminator, isBarrier
1913 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1914 // a two-value operand where a dag node expects two operands. :(
1915 let isBranch = 1, isTerminator = 1 in
1916 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
1918 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
1919 let Inst{31-27} = 0b11110;
1920 let Inst{15-14} = 0b10;
1926 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1927 AddrModeNone, Size2Bytes, IIC_iALUx,
1928 "it$mask\t$cc", "", []> {
1929 // 16-bit instruction.
1930 let Inst{31-16} = 0x0000;
1931 let Inst{15-8} = 0b10111111;
1934 //===----------------------------------------------------------------------===//
1935 // Non-Instruction Patterns
1938 // Two piece so_imms.
1939 def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
1940 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
1941 (t2_so_imm2part_2 imm:$RHS))>;
1942 def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
1943 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
1944 (t2_so_imm2part_2 imm:$RHS))>;
1945 def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
1946 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
1947 (t2_so_imm2part_2 imm:$RHS))>;
1948 def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS),
1949 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
1950 (t2_so_neg_imm2part_2 imm:$RHS))>;
1952 // 32-bit immediate using movw + movt.
1953 // This is a single pseudo instruction to make it re-materializable. Remove
1954 // when we can do generalized remat.
1955 let isReMaterializable = 1 in
1956 def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1957 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
1958 [(set GPR:$dst, (i32 imm:$src))]>;
1960 // ConstantPool, GlobalAddress, and JumpTable
1961 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
1962 Requires<[IsThumb2, DontUseMovt]>;
1963 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1964 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
1965 Requires<[IsThumb2, UseMovt]>;
1967 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1968 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1970 // Pseudo instruction that combines ldr from constpool and add pc. This should
1971 // be expanded into two instructions late to allow if-conversion and
1973 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1974 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1975 NoItinerary, "@ ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
1976 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1978 Requires<[IsThumb2]>;