1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // t2_so_imm - Match a 32-bit immediate operand, which is an
66 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
67 // immediate splatted into multiple bytes of the word.
68 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
69 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
70 return ARM_AM::getT2SOImmVal(Imm) != -1;
72 let ParserMatchClass = t2_so_imm_asmoperand;
73 let EncoderMethod = "getT2SOImmOpValue";
74 let DecoderMethod = "DecodeT2SOImm";
77 // t2_so_imm_not - Match an immediate that is a complement
79 // Note: this pattern doesn't require an encoder method and such, as it's
80 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
81 // is handled by the destination instructions, which use t2_so_imm.
82 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
83 def t2_so_imm_not : Operand<i32>,
85 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
86 }], t2_so_imm_not_XFORM> {
87 let ParserMatchClass = t2_so_imm_not_asmoperand;
90 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
91 def t2_so_imm_neg : Operand<i32>,
93 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
94 }], t2_so_imm_neg_XFORM>;
96 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
97 def imm0_4095 : Operand<i32>,
99 return Imm >= 0 && Imm < 4096;
102 def imm0_4095_neg : PatLeaf<(i32 imm), [{
103 return (uint32_t)(-N->getZExtValue()) < 4096;
106 def imm0_255_neg : PatLeaf<(i32 imm), [{
107 return (uint32_t)(-N->getZExtValue()) < 255;
110 def imm0_255_not : PatLeaf<(i32 imm), [{
111 return (uint32_t)(~N->getZExtValue()) < 255;
114 def lo5AllOne : PatLeaf<(i32 imm), [{
115 // Returns true if all low 5-bits are 1.
116 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
119 // Define Thumb2 specific addressing modes.
121 // t2addrmode_imm12 := reg + imm12
122 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
123 def t2addrmode_imm12 : Operand<i32>,
124 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
125 let PrintMethod = "printAddrModeImm12Operand";
126 let EncoderMethod = "getAddrModeImm12OpValue";
127 let DecoderMethod = "DecodeT2AddrModeImm12";
128 let ParserMatchClass = t2addrmode_imm12_asmoperand;
129 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
132 // t2ldrlabel := imm12
133 def t2ldrlabel : Operand<i32> {
134 let EncoderMethod = "getAddrModeImm12OpValue";
135 let PrintMethod = "printT2LdrLabelOperand";
139 // ADR instruction labels.
140 def t2adrlabel : Operand<i32> {
141 let EncoderMethod = "getT2AdrLabelOpValue";
145 // t2addrmode_posimm8 := reg + imm8
146 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
147 def t2addrmode_posimm8 : Operand<i32> {
148 let PrintMethod = "printT2AddrModeImm8Operand";
149 let EncoderMethod = "getT2AddrModeImm8OpValue";
150 let DecoderMethod = "DecodeT2AddrModeImm8";
151 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
152 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
155 // t2addrmode_negimm8 := reg - imm8
156 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
157 def t2addrmode_negimm8 : Operand<i32>,
158 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
159 let PrintMethod = "printT2AddrModeImm8Operand";
160 let EncoderMethod = "getT2AddrModeImm8OpValue";
161 let DecoderMethod = "DecodeT2AddrModeImm8";
162 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
163 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
166 // t2addrmode_imm8 := reg +/- imm8
167 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
168 def t2addrmode_imm8 : Operand<i32>,
169 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
170 let PrintMethod = "printT2AddrModeImm8Operand";
171 let EncoderMethod = "getT2AddrModeImm8OpValue";
172 let DecoderMethod = "DecodeT2AddrModeImm8";
173 let ParserMatchClass = MemImm8OffsetAsmOperand;
174 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
177 def t2am_imm8_offset : Operand<i32>,
178 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
179 [], [SDNPWantRoot]> {
180 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
181 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
182 let DecoderMethod = "DecodeT2Imm8";
185 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
186 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
187 def t2addrmode_imm8s4 : Operand<i32> {
188 let PrintMethod = "printT2AddrModeImm8s4Operand";
189 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
190 let DecoderMethod = "DecodeT2AddrModeImm8s4";
191 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
192 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
195 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
196 def t2am_imm8s4_offset : Operand<i32> {
197 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
198 let EncoderMethod = "getT2Imm8s4OpValue";
199 let DecoderMethod = "DecodeT2Imm8S4";
202 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
203 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
204 let Name = "MemImm0_1020s4Offset";
206 def t2addrmode_imm0_1020s4 : Operand<i32> {
207 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
208 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
209 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
210 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
211 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
214 // t2addrmode_so_reg := reg + (reg << imm2)
215 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
216 def t2addrmode_so_reg : Operand<i32>,
217 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
218 let PrintMethod = "printT2AddrModeSoRegOperand";
219 let EncoderMethod = "getT2AddrModeSORegOpValue";
220 let DecoderMethod = "DecodeT2AddrModeSOReg";
221 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
222 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
225 // Addresses for the TBB/TBH instructions.
226 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
227 def addrmode_tbb : Operand<i32> {
228 let PrintMethod = "printAddrModeTBB";
229 let ParserMatchClass = addrmode_tbb_asmoperand;
230 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
232 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
233 def addrmode_tbh : Operand<i32> {
234 let PrintMethod = "printAddrModeTBH";
235 let ParserMatchClass = addrmode_tbh_asmoperand;
236 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
239 //===----------------------------------------------------------------------===//
240 // Multiclass helpers...
244 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
245 string opc, string asm, list<dag> pattern>
246 : T2I<oops, iops, itin, opc, asm, pattern> {
251 let Inst{26} = imm{11};
252 let Inst{14-12} = imm{10-8};
253 let Inst{7-0} = imm{7-0};
257 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
258 string opc, string asm, list<dag> pattern>
259 : T2sI<oops, iops, itin, opc, asm, pattern> {
265 let Inst{26} = imm{11};
266 let Inst{14-12} = imm{10-8};
267 let Inst{7-0} = imm{7-0};
270 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
271 string opc, string asm, list<dag> pattern>
272 : T2I<oops, iops, itin, opc, asm, pattern> {
276 let Inst{19-16} = Rn;
277 let Inst{26} = imm{11};
278 let Inst{14-12} = imm{10-8};
279 let Inst{7-0} = imm{7-0};
283 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
284 string opc, string asm, list<dag> pattern>
285 : T2I<oops, iops, itin, opc, asm, pattern> {
290 let Inst{3-0} = ShiftedRm{3-0};
291 let Inst{5-4} = ShiftedRm{6-5};
292 let Inst{14-12} = ShiftedRm{11-9};
293 let Inst{7-6} = ShiftedRm{8-7};
296 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
297 string opc, string asm, list<dag> pattern>
298 : T2sI<oops, iops, itin, opc, asm, pattern> {
303 let Inst{3-0} = ShiftedRm{3-0};
304 let Inst{5-4} = ShiftedRm{6-5};
305 let Inst{14-12} = ShiftedRm{11-9};
306 let Inst{7-6} = ShiftedRm{8-7};
309 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
310 string opc, string asm, list<dag> pattern>
311 : T2I<oops, iops, itin, opc, asm, pattern> {
315 let Inst{19-16} = Rn;
316 let Inst{3-0} = ShiftedRm{3-0};
317 let Inst{5-4} = ShiftedRm{6-5};
318 let Inst{14-12} = ShiftedRm{11-9};
319 let Inst{7-6} = ShiftedRm{8-7};
322 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
323 string opc, string asm, list<dag> pattern>
324 : T2I<oops, iops, itin, opc, asm, pattern> {
332 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
333 string opc, string asm, list<dag> pattern>
334 : T2sI<oops, iops, itin, opc, asm, pattern> {
342 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
343 string opc, string asm, list<dag> pattern>
344 : T2I<oops, iops, itin, opc, asm, pattern> {
348 let Inst{19-16} = Rn;
353 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
354 string opc, string asm, list<dag> pattern>
355 : T2I<oops, iops, itin, opc, asm, pattern> {
361 let Inst{19-16} = Rn;
362 let Inst{26} = imm{11};
363 let Inst{14-12} = imm{10-8};
364 let Inst{7-0} = imm{7-0};
367 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
368 string opc, string asm, list<dag> pattern>
369 : T2sI<oops, iops, itin, opc, asm, pattern> {
375 let Inst{19-16} = Rn;
376 let Inst{26} = imm{11};
377 let Inst{14-12} = imm{10-8};
378 let Inst{7-0} = imm{7-0};
381 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
382 string opc, string asm, list<dag> pattern>
383 : T2I<oops, iops, itin, opc, asm, pattern> {
390 let Inst{14-12} = imm{4-2};
391 let Inst{7-6} = imm{1-0};
394 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
395 string opc, string asm, list<dag> pattern>
396 : T2sI<oops, iops, itin, opc, asm, pattern> {
403 let Inst{14-12} = imm{4-2};
404 let Inst{7-6} = imm{1-0};
407 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
408 string opc, string asm, list<dag> pattern>
409 : T2I<oops, iops, itin, opc, asm, pattern> {
415 let Inst{19-16} = Rn;
419 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
420 string opc, string asm, list<dag> pattern>
421 : T2sI<oops, iops, itin, opc, asm, pattern> {
427 let Inst{19-16} = Rn;
431 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
432 string opc, string asm, list<dag> pattern>
433 : T2I<oops, iops, itin, opc, asm, pattern> {
439 let Inst{19-16} = Rn;
440 let Inst{3-0} = ShiftedRm{3-0};
441 let Inst{5-4} = ShiftedRm{6-5};
442 let Inst{14-12} = ShiftedRm{11-9};
443 let Inst{7-6} = ShiftedRm{8-7};
446 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
447 string opc, string asm, list<dag> pattern>
448 : T2sI<oops, iops, itin, opc, asm, pattern> {
454 let Inst{19-16} = Rn;
455 let Inst{3-0} = ShiftedRm{3-0};
456 let Inst{5-4} = ShiftedRm{6-5};
457 let Inst{14-12} = ShiftedRm{11-9};
458 let Inst{7-6} = ShiftedRm{8-7};
461 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
462 string opc, string asm, list<dag> pattern>
463 : T2I<oops, iops, itin, opc, asm, pattern> {
469 let Inst{19-16} = Rn;
470 let Inst{15-12} = Ra;
475 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
476 dag oops, dag iops, InstrItinClass itin,
477 string opc, string asm, list<dag> pattern>
478 : T2I<oops, iops, itin, opc, asm, pattern> {
484 let Inst{31-23} = 0b111110111;
485 let Inst{22-20} = opc22_20;
486 let Inst{19-16} = Rn;
487 let Inst{15-12} = RdLo;
488 let Inst{11-8} = RdHi;
489 let Inst{7-4} = opc7_4;
494 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
495 /// binary operation that produces a value. These are predicable and can be
496 /// changed to modify CPSR.
497 multiclass T2I_bin_irs<bits<4> opcod, string opc,
498 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
499 PatFrag opnode, string baseOpc, bit Commutable = 0,
502 def ri : T2sTwoRegImm<
503 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
504 opc, "\t$Rd, $Rn, $imm",
505 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
506 let Inst{31-27} = 0b11110;
508 let Inst{24-21} = opcod;
512 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
513 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
514 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
515 let isCommutable = Commutable;
516 let Inst{31-27} = 0b11101;
517 let Inst{26-25} = 0b01;
518 let Inst{24-21} = opcod;
519 let Inst{14-12} = 0b000; // imm3
520 let Inst{7-6} = 0b00; // imm2
521 let Inst{5-4} = 0b00; // type
524 def rs : T2sTwoRegShiftedReg<
525 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
526 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
527 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
528 let Inst{31-27} = 0b11101;
529 let Inst{26-25} = 0b01;
530 let Inst{24-21} = opcod;
532 // Assembly aliases for optional destination operand when it's the same
533 // as the source operand.
534 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
535 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
536 t2_so_imm:$imm, pred:$p,
538 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
539 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
542 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
543 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
544 t2_so_reg:$shift, pred:$p,
548 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
549 // the ".w" suffix to indicate that they are wide.
550 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
551 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
552 PatFrag opnode, string baseOpc, bit Commutable = 0> :
553 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
554 // Assembler aliases w/o the ".w" suffix.
555 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
556 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
559 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
560 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
561 t2_so_reg:$shift, pred:$p,
564 // and with the optional destination operand, too.
565 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
566 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
569 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
570 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
571 t2_so_reg:$shift, pred:$p,
575 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
576 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
577 /// it is equivalent to the T2I_bin_irs counterpart.
578 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
580 def ri : T2sTwoRegImm<
581 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
582 opc, ".w\t$Rd, $Rn, $imm",
583 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
584 let Inst{31-27} = 0b11110;
586 let Inst{24-21} = opcod;
590 def rr : T2sThreeReg<
591 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
592 opc, "\t$Rd, $Rn, $Rm",
593 [/* For disassembly only; pattern left blank */]> {
594 let Inst{31-27} = 0b11101;
595 let Inst{26-25} = 0b01;
596 let Inst{24-21} = opcod;
597 let Inst{14-12} = 0b000; // imm3
598 let Inst{7-6} = 0b00; // imm2
599 let Inst{5-4} = 0b00; // type
602 def rs : T2sTwoRegShiftedReg<
603 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
604 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
605 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
606 let Inst{31-27} = 0b11101;
607 let Inst{26-25} = 0b01;
608 let Inst{24-21} = opcod;
612 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
613 /// instruction modifies the CPSR register.
615 /// These opcodes will be converted to the real non-S opcodes by
616 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
617 let hasPostISelHook = 1, Defs = [CPSR] in {
618 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
619 InstrItinClass iis, PatFrag opnode,
620 bit Commutable = 0> {
622 def ri : t2PseudoInst<(outs rGPR:$Rd),
623 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
625 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
628 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
630 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
632 let isCommutable = Commutable;
635 def rs : t2PseudoInst<(outs rGPR:$Rd),
636 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
638 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
639 t2_so_reg:$ShiftedRm))]>;
643 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
644 /// operands are reversed.
645 let hasPostISelHook = 1, Defs = [CPSR] in {
646 multiclass T2I_rbin_s_is<PatFrag opnode> {
648 def ri : t2PseudoInst<(outs rGPR:$Rd),
649 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
651 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
654 def rs : t2PseudoInst<(outs rGPR:$Rd),
655 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
657 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
662 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
663 /// patterns for a binary operation that produces a value.
664 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
665 bit Commutable = 0> {
667 // The register-immediate version is re-materializable. This is useful
668 // in particular for taking the address of a local.
669 let isReMaterializable = 1 in {
670 def ri : T2sTwoRegImm<
671 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
672 opc, ".w\t$Rd, $Rn, $imm",
673 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
674 let Inst{31-27} = 0b11110;
677 let Inst{23-21} = op23_21;
683 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
684 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
685 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
689 let Inst{31-27} = 0b11110;
690 let Inst{26} = imm{11};
691 let Inst{25-24} = 0b10;
692 let Inst{23-21} = op23_21;
693 let Inst{20} = 0; // The S bit.
694 let Inst{19-16} = Rn;
696 let Inst{14-12} = imm{10-8};
698 let Inst{7-0} = imm{7-0};
701 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
702 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
703 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
704 let isCommutable = Commutable;
705 let Inst{31-27} = 0b11101;
706 let Inst{26-25} = 0b01;
708 let Inst{23-21} = op23_21;
709 let Inst{14-12} = 0b000; // imm3
710 let Inst{7-6} = 0b00; // imm2
711 let Inst{5-4} = 0b00; // type
714 def rs : T2sTwoRegShiftedReg<
715 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
716 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
717 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
718 let Inst{31-27} = 0b11101;
719 let Inst{26-25} = 0b01;
721 let Inst{23-21} = op23_21;
725 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
726 /// for a binary operation that produces a value and use the carry
727 /// bit. It's not predicable.
728 let Defs = [CPSR], Uses = [CPSR] in {
729 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
730 bit Commutable = 0> {
732 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
733 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
734 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
735 Requires<[IsThumb2]> {
736 let Inst{31-27} = 0b11110;
738 let Inst{24-21} = opcod;
742 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
743 opc, ".w\t$Rd, $Rn, $Rm",
744 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
745 Requires<[IsThumb2]> {
746 let isCommutable = Commutable;
747 let Inst{31-27} = 0b11101;
748 let Inst{26-25} = 0b01;
749 let Inst{24-21} = opcod;
750 let Inst{14-12} = 0b000; // imm3
751 let Inst{7-6} = 0b00; // imm2
752 let Inst{5-4} = 0b00; // type
755 def rs : T2sTwoRegShiftedReg<
756 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
757 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
758 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
759 Requires<[IsThumb2]> {
760 let Inst{31-27} = 0b11101;
761 let Inst{26-25} = 0b01;
762 let Inst{24-21} = opcod;
767 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
768 // rotate operation that produces a value.
769 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
772 def ri : T2sTwoRegShiftImm<
773 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
774 opc, ".w\t$Rd, $Rm, $imm",
775 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
776 let Inst{31-27} = 0b11101;
777 let Inst{26-21} = 0b010010;
778 let Inst{19-16} = 0b1111; // Rn
779 let Inst{5-4} = opcod;
782 def rr : T2sThreeReg<
783 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
784 opc, ".w\t$Rd, $Rn, $Rm",
785 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
786 let Inst{31-27} = 0b11111;
787 let Inst{26-23} = 0b0100;
788 let Inst{22-21} = opcod;
789 let Inst{15-12} = 0b1111;
790 let Inst{7-4} = 0b0000;
793 // Optional destination register
794 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
795 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
798 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
799 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
803 // Assembler aliases w/o the ".w" suffix.
804 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
805 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
808 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
809 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
813 // and with the optional destination operand, too.
814 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
815 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
818 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
819 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
824 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
825 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
826 /// a explicit result, only implicitly set CPSR.
827 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
828 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
829 PatFrag opnode, string baseOpc> {
830 let isCompare = 1, Defs = [CPSR] in {
832 def ri : T2OneRegCmpImm<
833 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
834 opc, ".w\t$Rn, $imm",
835 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
836 let Inst{31-27} = 0b11110;
838 let Inst{24-21} = opcod;
839 let Inst{20} = 1; // The S bit.
841 let Inst{11-8} = 0b1111; // Rd
844 def rr : T2TwoRegCmp<
845 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
847 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
848 let Inst{31-27} = 0b11101;
849 let Inst{26-25} = 0b01;
850 let Inst{24-21} = opcod;
851 let Inst{20} = 1; // The S bit.
852 let Inst{14-12} = 0b000; // imm3
853 let Inst{11-8} = 0b1111; // Rd
854 let Inst{7-6} = 0b00; // imm2
855 let Inst{5-4} = 0b00; // type
858 def rs : T2OneRegCmpShiftedReg<
859 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
860 opc, ".w\t$Rn, $ShiftedRm",
861 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
862 let Inst{31-27} = 0b11101;
863 let Inst{26-25} = 0b01;
864 let Inst{24-21} = opcod;
865 let Inst{20} = 1; // The S bit.
866 let Inst{11-8} = 0b1111; // Rd
870 // Assembler aliases w/o the ".w" suffix.
871 // No alias here for 'rr' version as not all instantiations of this
872 // multiclass want one (CMP in particular, does not).
873 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
874 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
875 t2_so_imm:$imm, pred:$p)>;
876 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
877 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
882 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
883 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
884 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
886 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
887 opc, ".w\t$Rt, $addr",
888 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
891 let Inst{31-25} = 0b1111100;
892 let Inst{24} = signed;
894 let Inst{22-21} = opcod;
895 let Inst{20} = 1; // load
896 let Inst{19-16} = addr{16-13}; // Rn
897 let Inst{15-12} = Rt;
898 let Inst{11-0} = addr{11-0}; // imm
900 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
902 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
905 let Inst{31-27} = 0b11111;
906 let Inst{26-25} = 0b00;
907 let Inst{24} = signed;
909 let Inst{22-21} = opcod;
910 let Inst{20} = 1; // load
911 let Inst{19-16} = addr{12-9}; // Rn
912 let Inst{15-12} = Rt;
914 // Offset: index==TRUE, wback==FALSE
915 let Inst{10} = 1; // The P bit.
916 let Inst{9} = addr{8}; // U
917 let Inst{8} = 0; // The W bit.
918 let Inst{7-0} = addr{7-0}; // imm
920 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
921 opc, ".w\t$Rt, $addr",
922 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
923 let Inst{31-27} = 0b11111;
924 let Inst{26-25} = 0b00;
925 let Inst{24} = signed;
927 let Inst{22-21} = opcod;
928 let Inst{20} = 1; // load
929 let Inst{11-6} = 0b000000;
932 let Inst{15-12} = Rt;
935 let Inst{19-16} = addr{9-6}; // Rn
936 let Inst{3-0} = addr{5-2}; // Rm
937 let Inst{5-4} = addr{1-0}; // imm
939 let DecoderMethod = "DecodeT2LoadShift";
942 // FIXME: Is the pci variant actually needed?
943 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
944 opc, ".w\t$Rt, $addr",
945 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
946 let isReMaterializable = 1;
947 let Inst{31-27} = 0b11111;
948 let Inst{26-25} = 0b00;
949 let Inst{24} = signed;
950 let Inst{23} = ?; // add = (U == '1')
951 let Inst{22-21} = opcod;
952 let Inst{20} = 1; // load
953 let Inst{19-16} = 0b1111; // Rn
956 let Inst{15-12} = Rt{3-0};
957 let Inst{11-0} = addr{11-0};
961 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
962 multiclass T2I_st<bits<2> opcod, string opc,
963 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
965 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
966 opc, ".w\t$Rt, $addr",
967 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
968 let Inst{31-27} = 0b11111;
969 let Inst{26-23} = 0b0001;
970 let Inst{22-21} = opcod;
971 let Inst{20} = 0; // !load
974 let Inst{15-12} = Rt;
977 let addr{12} = 1; // add = TRUE
978 let Inst{19-16} = addr{16-13}; // Rn
979 let Inst{23} = addr{12}; // U
980 let Inst{11-0} = addr{11-0}; // imm
982 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
984 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
985 let Inst{31-27} = 0b11111;
986 let Inst{26-23} = 0b0000;
987 let Inst{22-21} = opcod;
988 let Inst{20} = 0; // !load
990 // Offset: index==TRUE, wback==FALSE
991 let Inst{10} = 1; // The P bit.
992 let Inst{8} = 0; // The W bit.
995 let Inst{15-12} = Rt;
998 let Inst{19-16} = addr{12-9}; // Rn
999 let Inst{9} = addr{8}; // U
1000 let Inst{7-0} = addr{7-0}; // imm
1002 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1003 opc, ".w\t$Rt, $addr",
1004 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1005 let Inst{31-27} = 0b11111;
1006 let Inst{26-23} = 0b0000;
1007 let Inst{22-21} = opcod;
1008 let Inst{20} = 0; // !load
1009 let Inst{11-6} = 0b000000;
1012 let Inst{15-12} = Rt;
1015 let Inst{19-16} = addr{9-6}; // Rn
1016 let Inst{3-0} = addr{5-2}; // Rm
1017 let Inst{5-4} = addr{1-0}; // imm
1021 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1022 /// register and one whose operand is a register rotated by 8/16/24.
1023 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1024 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1025 opc, ".w\t$Rd, $Rm$rot",
1026 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1027 Requires<[IsThumb2]> {
1028 let Inst{31-27} = 0b11111;
1029 let Inst{26-23} = 0b0100;
1030 let Inst{22-20} = opcod;
1031 let Inst{19-16} = 0b1111; // Rn
1032 let Inst{15-12} = 0b1111;
1036 let Inst{5-4} = rot{1-0}; // rotate
1039 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1040 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1041 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1042 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1043 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1044 Requires<[HasT2ExtractPack, IsThumb2]> {
1046 let Inst{31-27} = 0b11111;
1047 let Inst{26-23} = 0b0100;
1048 let Inst{22-20} = opcod;
1049 let Inst{19-16} = 0b1111; // Rn
1050 let Inst{15-12} = 0b1111;
1052 let Inst{5-4} = rot;
1055 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1057 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1058 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1059 opc, "\t$Rd, $Rm$rot", []>,
1060 Requires<[IsThumb2, HasT2ExtractPack]> {
1062 let Inst{31-27} = 0b11111;
1063 let Inst{26-23} = 0b0100;
1064 let Inst{22-20} = opcod;
1065 let Inst{19-16} = 0b1111; // Rn
1066 let Inst{15-12} = 0b1111;
1068 let Inst{5-4} = rot;
1071 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1072 /// register and one whose operand is a register rotated by 8/16/24.
1073 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1074 : T2ThreeReg<(outs rGPR:$Rd),
1075 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1076 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1077 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1078 Requires<[HasT2ExtractPack, IsThumb2]> {
1080 let Inst{31-27} = 0b11111;
1081 let Inst{26-23} = 0b0100;
1082 let Inst{22-20} = opcod;
1083 let Inst{15-12} = 0b1111;
1085 let Inst{5-4} = rot;
1088 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1089 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1090 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1092 let Inst{31-27} = 0b11111;
1093 let Inst{26-23} = 0b0100;
1094 let Inst{22-20} = opcod;
1095 let Inst{15-12} = 0b1111;
1097 let Inst{5-4} = rot;
1100 //===----------------------------------------------------------------------===//
1102 //===----------------------------------------------------------------------===//
1104 //===----------------------------------------------------------------------===//
1105 // Miscellaneous Instructions.
1108 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1109 string asm, list<dag> pattern>
1110 : T2XI<oops, iops, itin, asm, pattern> {
1114 let Inst{11-8} = Rd;
1115 let Inst{26} = label{11};
1116 let Inst{14-12} = label{10-8};
1117 let Inst{7-0} = label{7-0};
1120 // LEApcrel - Load a pc-relative address into a register without offending the
1122 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1123 (ins t2adrlabel:$addr, pred:$p),
1124 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1125 let Inst{31-27} = 0b11110;
1126 let Inst{25-24} = 0b10;
1127 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1130 let Inst{19-16} = 0b1111; // Rn
1135 let Inst{11-8} = Rd;
1136 let Inst{23} = addr{12};
1137 let Inst{21} = addr{12};
1138 let Inst{26} = addr{11};
1139 let Inst{14-12} = addr{10-8};
1140 let Inst{7-0} = addr{7-0};
1142 let DecoderMethod = "DecodeT2Adr";
1145 let neverHasSideEffects = 1, isReMaterializable = 1 in
1146 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1148 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1149 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1154 //===----------------------------------------------------------------------===//
1155 // Load / store Instructions.
1159 let canFoldAsLoad = 1, isReMaterializable = 1 in
1160 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1161 UnOpFrag<(load node:$Src)>>;
1163 // Loads with zero extension
1164 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1165 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1166 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1167 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1169 // Loads with sign extension
1170 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1171 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1172 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1173 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1175 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1177 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1178 (ins t2addrmode_imm8s4:$addr),
1179 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1180 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1182 // zextload i1 -> zextload i8
1183 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1184 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1185 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1186 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1187 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1188 (t2LDRBs t2addrmode_so_reg:$addr)>;
1189 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1190 (t2LDRBpci tconstpool:$addr)>;
1192 // extload -> zextload
1193 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1195 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1196 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1197 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1198 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1199 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1200 (t2LDRBs t2addrmode_so_reg:$addr)>;
1201 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1202 (t2LDRBpci tconstpool:$addr)>;
1204 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1205 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1206 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1207 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1208 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1209 (t2LDRBs t2addrmode_so_reg:$addr)>;
1210 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1211 (t2LDRBpci tconstpool:$addr)>;
1213 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1214 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1215 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1216 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1217 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1218 (t2LDRHs t2addrmode_so_reg:$addr)>;
1219 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1220 (t2LDRHpci tconstpool:$addr)>;
1222 // FIXME: The destination register of the loads and stores can't be PC, but
1223 // can be SP. We need another regclass (similar to rGPR) to represent
1224 // that. Not a pressing issue since these are selected manually,
1229 let mayLoad = 1, neverHasSideEffects = 1 in {
1230 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1231 (ins t2addrmode_imm8:$addr),
1232 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1233 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1235 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1238 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1239 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1240 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1241 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1243 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1244 (ins t2addrmode_imm8:$addr),
1245 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1246 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1248 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1250 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1251 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1252 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1253 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1255 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1256 (ins t2addrmode_imm8:$addr),
1257 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1258 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1260 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1262 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1263 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1264 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1265 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1267 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1268 (ins t2addrmode_imm8:$addr),
1269 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1270 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1272 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1274 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1275 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1276 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1277 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1279 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1280 (ins t2addrmode_imm8:$addr),
1281 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1282 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1284 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1286 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1287 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1288 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1289 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1290 } // mayLoad = 1, neverHasSideEffects = 1
1292 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1293 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1294 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1295 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1296 "\t$Rt, $addr", []> {
1299 let Inst{31-27} = 0b11111;
1300 let Inst{26-25} = 0b00;
1301 let Inst{24} = signed;
1303 let Inst{22-21} = type;
1304 let Inst{20} = 1; // load
1305 let Inst{19-16} = addr{12-9};
1306 let Inst{15-12} = Rt;
1308 let Inst{10-8} = 0b110; // PUW.
1309 let Inst{7-0} = addr{7-0};
1312 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1313 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1314 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1315 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1316 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1319 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1320 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1321 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1322 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1323 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1324 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1327 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1328 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1329 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1330 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1334 let mayStore = 1, neverHasSideEffects = 1 in {
1335 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1336 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1337 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1338 "str", "\t$Rt, $addr!",
1339 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1340 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1342 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1343 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1344 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1345 "strh", "\t$Rt, $addr!",
1346 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1347 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1350 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1351 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1352 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1353 "strb", "\t$Rt, $addr!",
1354 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1355 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1357 } // mayStore = 1, neverHasSideEffects = 1
1359 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1360 (ins rGPR:$Rt, addr_offset_none:$Rn,
1361 t2am_imm8_offset:$offset),
1362 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1363 "str", "\t$Rt, $Rn$offset",
1364 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1365 [(set GPRnopc:$Rn_wb,
1366 (post_store rGPR:$Rt, addr_offset_none:$Rn,
1367 t2am_imm8_offset:$offset))]>;
1369 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1370 (ins rGPR:$Rt, addr_offset_none:$Rn,
1371 t2am_imm8_offset:$offset),
1372 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1373 "strh", "\t$Rt, $Rn$offset",
1374 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1375 [(set GPRnopc:$Rn_wb,
1376 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1377 t2am_imm8_offset:$offset))]>;
1379 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1380 (ins rGPR:$Rt, addr_offset_none:$Rn,
1381 t2am_imm8_offset:$offset),
1382 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1383 "strb", "\t$Rt, $Rn$offset",
1384 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1385 [(set GPRnopc:$Rn_wb,
1386 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1387 t2am_imm8_offset:$offset))]>;
1389 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1390 // put the patterns on the instruction definitions directly as ISel wants
1391 // the address base and offset to be separate operands, not a single
1392 // complex operand like we represent the instructions themselves. The
1393 // pseudos map between the two.
1394 let usesCustomInserter = 1,
1395 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1396 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1397 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1399 [(set GPRnopc:$Rn_wb,
1400 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1401 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1402 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1404 [(set GPRnopc:$Rn_wb,
1405 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1406 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1407 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1409 [(set GPRnopc:$Rn_wb,
1410 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1413 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1415 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1416 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1417 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1418 "\t$Rt, $addr", []> {
1419 let Inst{31-27} = 0b11111;
1420 let Inst{26-25} = 0b00;
1421 let Inst{24} = 0; // not signed
1423 let Inst{22-21} = type;
1424 let Inst{20} = 0; // store
1426 let Inst{10-8} = 0b110; // PUW
1430 let Inst{15-12} = Rt;
1431 let Inst{19-16} = addr{12-9};
1432 let Inst{7-0} = addr{7-0};
1435 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1436 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1437 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1439 // ldrd / strd pre / post variants
1440 // For disassembly only.
1442 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1443 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1444 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1445 let AsmMatchConverter = "cvtT2LdrdPre";
1446 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1449 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1450 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1451 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1452 "$addr.base = $wb", []>;
1454 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1455 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1456 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1457 "$addr.base = $wb", []> {
1458 let AsmMatchConverter = "cvtT2StrdPre";
1459 let DecoderMethod = "DecodeT2STRDPreInstruction";
1462 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1463 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1464 t2am_imm8s4_offset:$imm),
1465 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1466 "$addr.base = $wb", []>;
1468 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1469 // data/instruction access.
1470 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1471 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1472 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1474 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1476 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1477 let Inst{31-25} = 0b1111100;
1478 let Inst{24} = instr;
1480 let Inst{21} = write;
1482 let Inst{15-12} = 0b1111;
1485 let addr{12} = 1; // add = TRUE
1486 let Inst{19-16} = addr{16-13}; // Rn
1487 let Inst{23} = addr{12}; // U
1488 let Inst{11-0} = addr{11-0}; // imm12
1491 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1493 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1494 let Inst{31-25} = 0b1111100;
1495 let Inst{24} = instr;
1496 let Inst{23} = 0; // U = 0
1498 let Inst{21} = write;
1500 let Inst{15-12} = 0b1111;
1501 let Inst{11-8} = 0b1100;
1504 let Inst{19-16} = addr{12-9}; // Rn
1505 let Inst{7-0} = addr{7-0}; // imm8
1508 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1510 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1511 let Inst{31-25} = 0b1111100;
1512 let Inst{24} = instr;
1513 let Inst{23} = 0; // add = TRUE for T1
1515 let Inst{21} = write;
1517 let Inst{15-12} = 0b1111;
1518 let Inst{11-6} = 0000000;
1521 let Inst{19-16} = addr{9-6}; // Rn
1522 let Inst{3-0} = addr{5-2}; // Rm
1523 let Inst{5-4} = addr{1-0}; // imm2
1525 let DecoderMethod = "DecodeT2LoadShift";
1527 // FIXME: We should have a separate 'pci' variant here. As-is we represent
1528 // it via the i12 variant, which it's related to, but that means we can
1529 // represent negative immediates, which aren't legal for anything except
1530 // the 'pci' case (Rn == 15).
1533 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1534 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1535 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1537 //===----------------------------------------------------------------------===//
1538 // Load / store multiple Instructions.
1541 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1542 InstrItinClass itin_upd, bit L_bit> {
1544 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1545 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1549 let Inst{31-27} = 0b11101;
1550 let Inst{26-25} = 0b00;
1551 let Inst{24-23} = 0b01; // Increment After
1553 let Inst{21} = 0; // No writeback
1554 let Inst{20} = L_bit;
1555 let Inst{19-16} = Rn;
1556 let Inst{15-0} = regs;
1559 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1560 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1564 let Inst{31-27} = 0b11101;
1565 let Inst{26-25} = 0b00;
1566 let Inst{24-23} = 0b01; // Increment After
1568 let Inst{21} = 1; // Writeback
1569 let Inst{20} = L_bit;
1570 let Inst{19-16} = Rn;
1571 let Inst{15-0} = regs;
1574 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1575 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1579 let Inst{31-27} = 0b11101;
1580 let Inst{26-25} = 0b00;
1581 let Inst{24-23} = 0b10; // Decrement Before
1583 let Inst{21} = 0; // No writeback
1584 let Inst{20} = L_bit;
1585 let Inst{19-16} = Rn;
1586 let Inst{15-0} = regs;
1589 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1590 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1594 let Inst{31-27} = 0b11101;
1595 let Inst{26-25} = 0b00;
1596 let Inst{24-23} = 0b10; // Decrement Before
1598 let Inst{21} = 1; // Writeback
1599 let Inst{20} = L_bit;
1600 let Inst{19-16} = Rn;
1601 let Inst{15-0} = regs;
1605 let neverHasSideEffects = 1 in {
1607 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1608 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1610 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1611 InstrItinClass itin_upd, bit L_bit> {
1613 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1614 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1618 let Inst{31-27} = 0b11101;
1619 let Inst{26-25} = 0b00;
1620 let Inst{24-23} = 0b01; // Increment After
1622 let Inst{21} = 0; // No writeback
1623 let Inst{20} = L_bit;
1624 let Inst{19-16} = Rn;
1626 let Inst{14} = regs{14};
1628 let Inst{12-0} = regs{12-0};
1631 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1632 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1636 let Inst{31-27} = 0b11101;
1637 let Inst{26-25} = 0b00;
1638 let Inst{24-23} = 0b01; // Increment After
1640 let Inst{21} = 1; // Writeback
1641 let Inst{20} = L_bit;
1642 let Inst{19-16} = Rn;
1644 let Inst{14} = regs{14};
1646 let Inst{12-0} = regs{12-0};
1649 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1650 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1654 let Inst{31-27} = 0b11101;
1655 let Inst{26-25} = 0b00;
1656 let Inst{24-23} = 0b10; // Decrement Before
1658 let Inst{21} = 0; // No writeback
1659 let Inst{20} = L_bit;
1660 let Inst{19-16} = Rn;
1662 let Inst{14} = regs{14};
1664 let Inst{12-0} = regs{12-0};
1667 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1668 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1672 let Inst{31-27} = 0b11101;
1673 let Inst{26-25} = 0b00;
1674 let Inst{24-23} = 0b10; // Decrement Before
1676 let Inst{21} = 1; // Writeback
1677 let Inst{20} = L_bit;
1678 let Inst{19-16} = Rn;
1680 let Inst{14} = regs{14};
1682 let Inst{12-0} = regs{12-0};
1687 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1688 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1690 } // neverHasSideEffects
1693 //===----------------------------------------------------------------------===//
1694 // Move Instructions.
1697 let neverHasSideEffects = 1 in
1698 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1699 "mov", ".w\t$Rd, $Rm", []> {
1700 let Inst{31-27} = 0b11101;
1701 let Inst{26-25} = 0b01;
1702 let Inst{24-21} = 0b0010;
1703 let Inst{19-16} = 0b1111; // Rn
1704 let Inst{14-12} = 0b000;
1705 let Inst{7-4} = 0b0000;
1707 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1708 pred:$p, zero_reg)>;
1709 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1711 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1714 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1715 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1716 AddedComplexity = 1 in
1717 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1718 "mov", ".w\t$Rd, $imm",
1719 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1720 let Inst{31-27} = 0b11110;
1722 let Inst{24-21} = 0b0010;
1723 let Inst{19-16} = 0b1111; // Rn
1727 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1728 // Use aliases to get that to play nice here.
1729 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1731 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1734 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1735 pred:$p, zero_reg)>;
1736 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1737 pred:$p, zero_reg)>;
1739 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1740 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1741 "movw", "\t$Rd, $imm",
1742 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1743 let Inst{31-27} = 0b11110;
1745 let Inst{24-21} = 0b0010;
1746 let Inst{20} = 0; // The S bit.
1752 let Inst{11-8} = Rd;
1753 let Inst{19-16} = imm{15-12};
1754 let Inst{26} = imm{11};
1755 let Inst{14-12} = imm{10-8};
1756 let Inst{7-0} = imm{7-0};
1757 let DecoderMethod = "DecodeT2MOVTWInstruction";
1760 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1761 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1763 let Constraints = "$src = $Rd" in {
1764 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1765 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1766 "movt", "\t$Rd, $imm",
1768 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1769 let Inst{31-27} = 0b11110;
1771 let Inst{24-21} = 0b0110;
1772 let Inst{20} = 0; // The S bit.
1778 let Inst{11-8} = Rd;
1779 let Inst{19-16} = imm{15-12};
1780 let Inst{26} = imm{11};
1781 let Inst{14-12} = imm{10-8};
1782 let Inst{7-0} = imm{7-0};
1783 let DecoderMethod = "DecodeT2MOVTWInstruction";
1786 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1787 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1790 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1792 //===----------------------------------------------------------------------===//
1793 // Extend Instructions.
1798 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1799 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1800 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1801 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1802 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1804 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1805 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1806 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1807 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1808 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1812 let AddedComplexity = 16 in {
1813 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1814 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1815 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1816 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1817 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1818 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1820 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1821 // The transformation should probably be done as a combiner action
1822 // instead so we can include a check for masking back in the upper
1823 // eight bits of the source into the lower eight bits of the result.
1824 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1825 // (t2UXTB16 rGPR:$Src, 3)>,
1826 // Requires<[HasT2ExtractPack, IsThumb2]>;
1827 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1828 (t2UXTB16 rGPR:$Src, 1)>,
1829 Requires<[HasT2ExtractPack, IsThumb2]>;
1831 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1832 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1833 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1834 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1835 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1838 //===----------------------------------------------------------------------===//
1839 // Arithmetic Instructions.
1842 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1843 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1844 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1845 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1847 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1849 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1850 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1851 // AdjustInstrPostInstrSelection where we determine whether or not to
1852 // set the "s" bit based on CPSR liveness.
1854 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1855 // support for an optional CPSR definition that corresponds to the DAG
1856 // node's second value. We can then eliminate the implicit def of CPSR.
1857 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1858 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1859 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1860 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1862 let hasPostISelHook = 1 in {
1863 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1864 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1865 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1866 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1870 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1871 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1873 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1874 // CPSR and the implicit def of CPSR is not needed.
1875 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1877 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1878 // The assume-no-carry-in form uses the negation of the input since add/sub
1879 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1880 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1882 // The AddedComplexity preferences the first variant over the others since
1883 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1884 let AddedComplexity = 1 in
1885 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1886 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1887 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1888 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1889 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1890 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1891 let AddedComplexity = 1 in
1892 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1893 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1894 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1895 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1896 // The with-carry-in form matches bitwise not instead of the negation.
1897 // Effectively, the inverse interpretation of the carry flag already accounts
1898 // for part of the negation.
1899 let AddedComplexity = 1 in
1900 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1901 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1902 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1903 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1905 // Select Bytes -- for disassembly only
1907 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1908 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1909 Requires<[IsThumb2, HasThumb2DSP]> {
1910 let Inst{31-27} = 0b11111;
1911 let Inst{26-24} = 0b010;
1913 let Inst{22-20} = 0b010;
1914 let Inst{15-12} = 0b1111;
1916 let Inst{6-4} = 0b000;
1919 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1920 // And Miscellaneous operations -- for disassembly only
1921 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1922 list<dag> pat = [/* For disassembly only; pattern left blank */],
1923 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1924 string asm = "\t$Rd, $Rn, $Rm">
1925 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1926 Requires<[IsThumb2, HasThumb2DSP]> {
1927 let Inst{31-27} = 0b11111;
1928 let Inst{26-23} = 0b0101;
1929 let Inst{22-20} = op22_20;
1930 let Inst{15-12} = 0b1111;
1931 let Inst{7-4} = op7_4;
1937 let Inst{11-8} = Rd;
1938 let Inst{19-16} = Rn;
1942 // Saturating add/subtract -- for disassembly only
1944 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1945 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1946 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1947 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1948 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1949 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1950 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1951 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1952 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1953 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1954 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1955 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1956 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1957 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1958 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1959 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1960 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1961 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1962 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1963 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1964 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1965 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1967 // Signed/Unsigned add/subtract -- for disassembly only
1969 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1970 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1971 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1972 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1973 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1974 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1975 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1976 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1977 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1978 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1979 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1980 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1982 // Signed/Unsigned halving add/subtract -- for disassembly only
1984 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1985 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1986 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1987 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1988 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1989 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1990 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1991 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1992 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1993 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1994 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1995 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1997 // Helper class for disassembly only
1998 // A6.3.16 & A6.3.17
1999 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2000 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2001 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2002 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2003 let Inst{31-27} = 0b11111;
2004 let Inst{26-24} = 0b011;
2005 let Inst{23} = long;
2006 let Inst{22-20} = op22_20;
2007 let Inst{7-4} = op7_4;
2010 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2011 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2012 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2013 let Inst{31-27} = 0b11111;
2014 let Inst{26-24} = 0b011;
2015 let Inst{23} = long;
2016 let Inst{22-20} = op22_20;
2017 let Inst{7-4} = op7_4;
2020 // Unsigned Sum of Absolute Differences [and Accumulate].
2021 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2022 (ins rGPR:$Rn, rGPR:$Rm),
2023 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2024 Requires<[IsThumb2, HasThumb2DSP]> {
2025 let Inst{15-12} = 0b1111;
2027 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2028 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2029 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2030 Requires<[IsThumb2, HasThumb2DSP]>;
2032 // Signed/Unsigned saturate.
2033 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2034 string opc, string asm, list<dag> pattern>
2035 : T2I<oops, iops, itin, opc, asm, pattern> {
2041 let Inst{11-8} = Rd;
2042 let Inst{19-16} = Rn;
2043 let Inst{4-0} = sat_imm;
2044 let Inst{21} = sh{5};
2045 let Inst{14-12} = sh{4-2};
2046 let Inst{7-6} = sh{1-0};
2051 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2052 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2053 let Inst{31-27} = 0b11110;
2054 let Inst{25-22} = 0b1100;
2060 def t2SSAT16: T2SatI<
2061 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2062 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2063 Requires<[IsThumb2, HasThumb2DSP]> {
2064 let Inst{31-27} = 0b11110;
2065 let Inst{25-22} = 0b1100;
2068 let Inst{21} = 1; // sh = '1'
2069 let Inst{14-12} = 0b000; // imm3 = '000'
2070 let Inst{7-6} = 0b00; // imm2 = '00'
2071 let Inst{5-4} = 0b00;
2076 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2077 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2078 let Inst{31-27} = 0b11110;
2079 let Inst{25-22} = 0b1110;
2084 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2086 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2087 Requires<[IsThumb2, HasThumb2DSP]> {
2088 let Inst{31-22} = 0b1111001110;
2091 let Inst{21} = 1; // sh = '1'
2092 let Inst{14-12} = 0b000; // imm3 = '000'
2093 let Inst{7-6} = 0b00; // imm2 = '00'
2094 let Inst{5-4} = 0b00;
2097 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2098 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2100 //===----------------------------------------------------------------------===//
2101 // Shift and rotate Instructions.
2104 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2105 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2106 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2107 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2108 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2109 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2110 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2111 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2113 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2114 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2115 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2117 let Uses = [CPSR] in {
2118 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2119 "rrx", "\t$Rd, $Rm",
2120 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2121 let Inst{31-27} = 0b11101;
2122 let Inst{26-25} = 0b01;
2123 let Inst{24-21} = 0b0010;
2124 let Inst{19-16} = 0b1111; // Rn
2125 let Inst{14-12} = 0b000;
2126 let Inst{7-4} = 0b0011;
2130 let isCodeGenOnly = 1, Defs = [CPSR] in {
2131 def t2MOVsrl_flag : T2TwoRegShiftImm<
2132 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2133 "lsrs", ".w\t$Rd, $Rm, #1",
2134 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2135 let Inst{31-27} = 0b11101;
2136 let Inst{26-25} = 0b01;
2137 let Inst{24-21} = 0b0010;
2138 let Inst{20} = 1; // The S bit.
2139 let Inst{19-16} = 0b1111; // Rn
2140 let Inst{5-4} = 0b01; // Shift type.
2141 // Shift amount = Inst{14-12:7-6} = 1.
2142 let Inst{14-12} = 0b000;
2143 let Inst{7-6} = 0b01;
2145 def t2MOVsra_flag : T2TwoRegShiftImm<
2146 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2147 "asrs", ".w\t$Rd, $Rm, #1",
2148 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2149 let Inst{31-27} = 0b11101;
2150 let Inst{26-25} = 0b01;
2151 let Inst{24-21} = 0b0010;
2152 let Inst{20} = 1; // The S bit.
2153 let Inst{19-16} = 0b1111; // Rn
2154 let Inst{5-4} = 0b10; // Shift type.
2155 // Shift amount = Inst{14-12:7-6} = 1.
2156 let Inst{14-12} = 0b000;
2157 let Inst{7-6} = 0b01;
2161 //===----------------------------------------------------------------------===//
2162 // Bitwise Instructions.
2165 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2166 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2167 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2168 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2169 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2170 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2171 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2172 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2173 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2175 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2176 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2177 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2180 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2181 string opc, string asm, list<dag> pattern>
2182 : T2I<oops, iops, itin, opc, asm, pattern> {
2187 let Inst{11-8} = Rd;
2188 let Inst{4-0} = msb{4-0};
2189 let Inst{14-12} = lsb{4-2};
2190 let Inst{7-6} = lsb{1-0};
2193 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2194 string opc, string asm, list<dag> pattern>
2195 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2198 let Inst{19-16} = Rn;
2201 let Constraints = "$src = $Rd" in
2202 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2203 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2204 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2205 let Inst{31-27} = 0b11110;
2206 let Inst{26} = 0; // should be 0.
2208 let Inst{24-20} = 0b10110;
2209 let Inst{19-16} = 0b1111; // Rn
2211 let Inst{5} = 0; // should be 0.
2214 let msb{4-0} = imm{9-5};
2215 let lsb{4-0} = imm{4-0};
2218 def t2SBFX: T2TwoRegBitFI<
2219 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2220 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2221 let Inst{31-27} = 0b11110;
2223 let Inst{24-20} = 0b10100;
2227 def t2UBFX: T2TwoRegBitFI<
2228 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2229 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2230 let Inst{31-27} = 0b11110;
2232 let Inst{24-20} = 0b11100;
2236 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2237 let Constraints = "$src = $Rd" in {
2238 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2239 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2240 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2241 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2242 bf_inv_mask_imm:$imm))]> {
2243 let Inst{31-27} = 0b11110;
2244 let Inst{26} = 0; // should be 0.
2246 let Inst{24-20} = 0b10110;
2248 let Inst{5} = 0; // should be 0.
2251 let msb{4-0} = imm{9-5};
2252 let lsb{4-0} = imm{4-0};
2256 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2257 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2258 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2261 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2262 /// unary operation that produces a value. These are predicable and can be
2263 /// changed to modify CPSR.
2264 multiclass T2I_un_irs<bits<4> opcod, string opc,
2265 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2266 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2268 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2270 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2271 let isAsCheapAsAMove = Cheap;
2272 let isReMaterializable = ReMat;
2273 let Inst{31-27} = 0b11110;
2275 let Inst{24-21} = opcod;
2276 let Inst{19-16} = 0b1111; // Rn
2280 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2281 opc, ".w\t$Rd, $Rm",
2282 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2283 let Inst{31-27} = 0b11101;
2284 let Inst{26-25} = 0b01;
2285 let Inst{24-21} = opcod;
2286 let Inst{19-16} = 0b1111; // Rn
2287 let Inst{14-12} = 0b000; // imm3
2288 let Inst{7-6} = 0b00; // imm2
2289 let Inst{5-4} = 0b00; // type
2292 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2293 opc, ".w\t$Rd, $ShiftedRm",
2294 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2295 let Inst{31-27} = 0b11101;
2296 let Inst{26-25} = 0b01;
2297 let Inst{24-21} = opcod;
2298 let Inst{19-16} = 0b1111; // Rn
2302 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2303 let AddedComplexity = 1 in
2304 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2305 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2306 UnOpFrag<(not node:$Src)>, 1, 1>;
2308 let AddedComplexity = 1 in
2309 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2310 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2312 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2313 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2314 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2315 Requires<[IsThumb2]>;
2317 def : T2Pat<(t2_so_imm_not:$src),
2318 (t2MVNi t2_so_imm_not:$src)>;
2320 //===----------------------------------------------------------------------===//
2321 // Multiply Instructions.
2323 let isCommutable = 1 in
2324 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2325 "mul", "\t$Rd, $Rn, $Rm",
2326 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2327 let Inst{31-27} = 0b11111;
2328 let Inst{26-23} = 0b0110;
2329 let Inst{22-20} = 0b000;
2330 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2331 let Inst{7-4} = 0b0000; // Multiply
2334 def t2MLA: T2FourReg<
2335 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2336 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2337 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2338 let Inst{31-27} = 0b11111;
2339 let Inst{26-23} = 0b0110;
2340 let Inst{22-20} = 0b000;
2341 let Inst{7-4} = 0b0000; // Multiply
2344 def t2MLS: T2FourReg<
2345 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2346 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2347 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2348 let Inst{31-27} = 0b11111;
2349 let Inst{26-23} = 0b0110;
2350 let Inst{22-20} = 0b000;
2351 let Inst{7-4} = 0b0001; // Multiply and Subtract
2354 // Extra precision multiplies with low / high results
2355 let neverHasSideEffects = 1 in {
2356 let isCommutable = 1 in {
2357 def t2SMULL : T2MulLong<0b000, 0b0000,
2358 (outs rGPR:$RdLo, rGPR:$RdHi),
2359 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2360 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2362 def t2UMULL : T2MulLong<0b010, 0b0000,
2363 (outs rGPR:$RdLo, rGPR:$RdHi),
2364 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2365 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2368 // Multiply + accumulate
2369 def t2SMLAL : T2MulLong<0b100, 0b0000,
2370 (outs rGPR:$RdLo, rGPR:$RdHi),
2371 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2372 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2374 def t2UMLAL : T2MulLong<0b110, 0b0000,
2375 (outs rGPR:$RdLo, rGPR:$RdHi),
2376 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2377 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2379 def t2UMAAL : T2MulLong<0b110, 0b0110,
2380 (outs rGPR:$RdLo, rGPR:$RdHi),
2381 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2382 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2383 Requires<[IsThumb2, HasThumb2DSP]>;
2384 } // neverHasSideEffects
2386 // Rounding variants of the below included for disassembly only
2388 // Most significant word multiply
2389 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2390 "smmul", "\t$Rd, $Rn, $Rm",
2391 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2392 Requires<[IsThumb2, HasThumb2DSP]> {
2393 let Inst{31-27} = 0b11111;
2394 let Inst{26-23} = 0b0110;
2395 let Inst{22-20} = 0b101;
2396 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2397 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2400 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2401 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2402 Requires<[IsThumb2, HasThumb2DSP]> {
2403 let Inst{31-27} = 0b11111;
2404 let Inst{26-23} = 0b0110;
2405 let Inst{22-20} = 0b101;
2406 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2407 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2410 def t2SMMLA : T2FourReg<
2411 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2412 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2413 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2414 Requires<[IsThumb2, HasThumb2DSP]> {
2415 let Inst{31-27} = 0b11111;
2416 let Inst{26-23} = 0b0110;
2417 let Inst{22-20} = 0b101;
2418 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2421 def t2SMMLAR: T2FourReg<
2422 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2423 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2424 Requires<[IsThumb2, HasThumb2DSP]> {
2425 let Inst{31-27} = 0b11111;
2426 let Inst{26-23} = 0b0110;
2427 let Inst{22-20} = 0b101;
2428 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2431 def t2SMMLS: T2FourReg<
2432 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2433 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2434 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2435 Requires<[IsThumb2, HasThumb2DSP]> {
2436 let Inst{31-27} = 0b11111;
2437 let Inst{26-23} = 0b0110;
2438 let Inst{22-20} = 0b110;
2439 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2442 def t2SMMLSR:T2FourReg<
2443 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2444 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2445 Requires<[IsThumb2, HasThumb2DSP]> {
2446 let Inst{31-27} = 0b11111;
2447 let Inst{26-23} = 0b0110;
2448 let Inst{22-20} = 0b110;
2449 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2452 multiclass T2I_smul<string opc, PatFrag opnode> {
2453 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2454 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2455 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2456 (sext_inreg rGPR:$Rm, i16)))]>,
2457 Requires<[IsThumb2, HasThumb2DSP]> {
2458 let Inst{31-27} = 0b11111;
2459 let Inst{26-23} = 0b0110;
2460 let Inst{22-20} = 0b001;
2461 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2462 let Inst{7-6} = 0b00;
2463 let Inst{5-4} = 0b00;
2466 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2467 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2468 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2469 (sra rGPR:$Rm, (i32 16))))]>,
2470 Requires<[IsThumb2, HasThumb2DSP]> {
2471 let Inst{31-27} = 0b11111;
2472 let Inst{26-23} = 0b0110;
2473 let Inst{22-20} = 0b001;
2474 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2475 let Inst{7-6} = 0b00;
2476 let Inst{5-4} = 0b01;
2479 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2480 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2481 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2482 (sext_inreg rGPR:$Rm, i16)))]>,
2483 Requires<[IsThumb2, HasThumb2DSP]> {
2484 let Inst{31-27} = 0b11111;
2485 let Inst{26-23} = 0b0110;
2486 let Inst{22-20} = 0b001;
2487 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2488 let Inst{7-6} = 0b00;
2489 let Inst{5-4} = 0b10;
2492 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2493 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2494 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2495 (sra rGPR:$Rm, (i32 16))))]>,
2496 Requires<[IsThumb2, HasThumb2DSP]> {
2497 let Inst{31-27} = 0b11111;
2498 let Inst{26-23} = 0b0110;
2499 let Inst{22-20} = 0b001;
2500 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2501 let Inst{7-6} = 0b00;
2502 let Inst{5-4} = 0b11;
2505 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2506 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2507 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2508 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2509 Requires<[IsThumb2, HasThumb2DSP]> {
2510 let Inst{31-27} = 0b11111;
2511 let Inst{26-23} = 0b0110;
2512 let Inst{22-20} = 0b011;
2513 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2514 let Inst{7-6} = 0b00;
2515 let Inst{5-4} = 0b00;
2518 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2519 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2520 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2521 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2522 Requires<[IsThumb2, HasThumb2DSP]> {
2523 let Inst{31-27} = 0b11111;
2524 let Inst{26-23} = 0b0110;
2525 let Inst{22-20} = 0b011;
2526 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2527 let Inst{7-6} = 0b00;
2528 let Inst{5-4} = 0b01;
2533 multiclass T2I_smla<string opc, PatFrag opnode> {
2535 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2536 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2537 [(set rGPR:$Rd, (add rGPR:$Ra,
2538 (opnode (sext_inreg rGPR:$Rn, i16),
2539 (sext_inreg rGPR:$Rm, i16))))]>,
2540 Requires<[IsThumb2, HasThumb2DSP]> {
2541 let Inst{31-27} = 0b11111;
2542 let Inst{26-23} = 0b0110;
2543 let Inst{22-20} = 0b001;
2544 let Inst{7-6} = 0b00;
2545 let Inst{5-4} = 0b00;
2549 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2550 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2551 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2552 (sra rGPR:$Rm, (i32 16)))))]>,
2553 Requires<[IsThumb2, HasThumb2DSP]> {
2554 let Inst{31-27} = 0b11111;
2555 let Inst{26-23} = 0b0110;
2556 let Inst{22-20} = 0b001;
2557 let Inst{7-6} = 0b00;
2558 let Inst{5-4} = 0b01;
2562 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2563 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2564 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2565 (sext_inreg rGPR:$Rm, i16))))]>,
2566 Requires<[IsThumb2, HasThumb2DSP]> {
2567 let Inst{31-27} = 0b11111;
2568 let Inst{26-23} = 0b0110;
2569 let Inst{22-20} = 0b001;
2570 let Inst{7-6} = 0b00;
2571 let Inst{5-4} = 0b10;
2575 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2576 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2577 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2578 (sra rGPR:$Rm, (i32 16)))))]>,
2579 Requires<[IsThumb2, HasThumb2DSP]> {
2580 let Inst{31-27} = 0b11111;
2581 let Inst{26-23} = 0b0110;
2582 let Inst{22-20} = 0b001;
2583 let Inst{7-6} = 0b00;
2584 let Inst{5-4} = 0b11;
2588 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2589 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2590 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2591 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2592 Requires<[IsThumb2, HasThumb2DSP]> {
2593 let Inst{31-27} = 0b11111;
2594 let Inst{26-23} = 0b0110;
2595 let Inst{22-20} = 0b011;
2596 let Inst{7-6} = 0b00;
2597 let Inst{5-4} = 0b00;
2601 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2602 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2603 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2604 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2605 Requires<[IsThumb2, HasThumb2DSP]> {
2606 let Inst{31-27} = 0b11111;
2607 let Inst{26-23} = 0b0110;
2608 let Inst{22-20} = 0b011;
2609 let Inst{7-6} = 0b00;
2610 let Inst{5-4} = 0b01;
2614 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2615 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2617 // Halfword multiple accumulate long: SMLAL<x><y>
2618 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2619 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2620 [/* For disassembly only; pattern left blank */]>,
2621 Requires<[IsThumb2, HasThumb2DSP]>;
2622 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2623 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2624 [/* For disassembly only; pattern left blank */]>,
2625 Requires<[IsThumb2, HasThumb2DSP]>;
2626 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2627 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2628 [/* For disassembly only; pattern left blank */]>,
2629 Requires<[IsThumb2, HasThumb2DSP]>;
2630 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2631 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2632 [/* For disassembly only; pattern left blank */]>,
2633 Requires<[IsThumb2, HasThumb2DSP]>;
2635 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2636 def t2SMUAD: T2ThreeReg_mac<
2637 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2638 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2639 Requires<[IsThumb2, HasThumb2DSP]> {
2640 let Inst{15-12} = 0b1111;
2642 def t2SMUADX:T2ThreeReg_mac<
2643 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2644 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2645 Requires<[IsThumb2, HasThumb2DSP]> {
2646 let Inst{15-12} = 0b1111;
2648 def t2SMUSD: T2ThreeReg_mac<
2649 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2650 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2651 Requires<[IsThumb2, HasThumb2DSP]> {
2652 let Inst{15-12} = 0b1111;
2654 def t2SMUSDX:T2ThreeReg_mac<
2655 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2656 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2657 Requires<[IsThumb2, HasThumb2DSP]> {
2658 let Inst{15-12} = 0b1111;
2660 def t2SMLAD : T2FourReg_mac<
2661 0, 0b010, 0b0000, (outs rGPR:$Rd),
2662 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2663 "\t$Rd, $Rn, $Rm, $Ra", []>,
2664 Requires<[IsThumb2, HasThumb2DSP]>;
2665 def t2SMLADX : T2FourReg_mac<
2666 0, 0b010, 0b0001, (outs rGPR:$Rd),
2667 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2668 "\t$Rd, $Rn, $Rm, $Ra", []>,
2669 Requires<[IsThumb2, HasThumb2DSP]>;
2670 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2671 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2672 "\t$Rd, $Rn, $Rm, $Ra", []>,
2673 Requires<[IsThumb2, HasThumb2DSP]>;
2674 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2675 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2676 "\t$Rd, $Rn, $Rm, $Ra", []>,
2677 Requires<[IsThumb2, HasThumb2DSP]>;
2678 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2679 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2680 "\t$Ra, $Rd, $Rn, $Rm", []>,
2681 Requires<[IsThumb2, HasThumb2DSP]>;
2682 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2683 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2684 "\t$Ra, $Rd, $Rn, $Rm", []>,
2685 Requires<[IsThumb2, HasThumb2DSP]>;
2686 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2687 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2688 "\t$Ra, $Rd, $Rn, $Rm", []>,
2689 Requires<[IsThumb2, HasThumb2DSP]>;
2690 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2691 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2692 "\t$Ra, $Rd, $Rn, $Rm", []>,
2693 Requires<[IsThumb2, HasThumb2DSP]>;
2695 //===----------------------------------------------------------------------===//
2696 // Division Instructions.
2697 // Signed and unsigned division on v7-M
2699 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2700 "sdiv", "\t$Rd, $Rn, $Rm",
2701 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2702 Requires<[HasDivide, IsThumb2]> {
2703 let Inst{31-27} = 0b11111;
2704 let Inst{26-21} = 0b011100;
2706 let Inst{15-12} = 0b1111;
2707 let Inst{7-4} = 0b1111;
2710 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2711 "udiv", "\t$Rd, $Rn, $Rm",
2712 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2713 Requires<[HasDivide, IsThumb2]> {
2714 let Inst{31-27} = 0b11111;
2715 let Inst{26-21} = 0b011101;
2717 let Inst{15-12} = 0b1111;
2718 let Inst{7-4} = 0b1111;
2721 //===----------------------------------------------------------------------===//
2722 // Misc. Arithmetic Instructions.
2725 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2726 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2727 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2728 let Inst{31-27} = 0b11111;
2729 let Inst{26-22} = 0b01010;
2730 let Inst{21-20} = op1;
2731 let Inst{15-12} = 0b1111;
2732 let Inst{7-6} = 0b10;
2733 let Inst{5-4} = op2;
2737 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2738 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2740 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2741 "rbit", "\t$Rd, $Rm",
2742 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2744 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2745 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2747 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2748 "rev16", ".w\t$Rd, $Rm",
2749 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2751 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2752 "revsh", ".w\t$Rd, $Rm",
2753 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2755 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2756 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2757 (t2REVSH rGPR:$Rm)>;
2759 def t2PKHBT : T2ThreeReg<
2760 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2761 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2762 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2763 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2765 Requires<[HasT2ExtractPack, IsThumb2]> {
2766 let Inst{31-27} = 0b11101;
2767 let Inst{26-25} = 0b01;
2768 let Inst{24-20} = 0b01100;
2769 let Inst{5} = 0; // BT form
2773 let Inst{14-12} = sh{4-2};
2774 let Inst{7-6} = sh{1-0};
2777 // Alternate cases for PKHBT where identities eliminate some nodes.
2778 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2779 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2780 Requires<[HasT2ExtractPack, IsThumb2]>;
2781 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2782 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2783 Requires<[HasT2ExtractPack, IsThumb2]>;
2785 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2786 // will match the pattern below.
2787 def t2PKHTB : T2ThreeReg<
2788 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2789 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2790 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2791 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2793 Requires<[HasT2ExtractPack, IsThumb2]> {
2794 let Inst{31-27} = 0b11101;
2795 let Inst{26-25} = 0b01;
2796 let Inst{24-20} = 0b01100;
2797 let Inst{5} = 1; // TB form
2801 let Inst{14-12} = sh{4-2};
2802 let Inst{7-6} = sh{1-0};
2805 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2806 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2807 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2808 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2809 Requires<[HasT2ExtractPack, IsThumb2]>;
2810 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2811 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2812 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2813 Requires<[HasT2ExtractPack, IsThumb2]>;
2815 //===----------------------------------------------------------------------===//
2816 // Comparison Instructions...
2818 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2819 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2820 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2822 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2823 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2824 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2825 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2826 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2827 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2829 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2830 // Compare-to-zero still works out, just not the relationals
2831 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2832 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2833 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2834 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2835 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2838 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2839 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2841 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2842 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2844 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2845 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2846 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2848 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2849 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2850 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2853 // Conditional moves
2854 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2855 // a two-value operand where a dag node expects two operands. :(
2856 let neverHasSideEffects = 1 in {
2857 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2858 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2860 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2861 RegConstraint<"$false = $Rd">;
2863 let isMoveImm = 1 in
2864 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2865 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2867 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2868 RegConstraint<"$false = $Rd">;
2870 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2871 let isCodeGenOnly = 1 in {
2872 let isMoveImm = 1 in
2873 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2875 "movw", "\t$Rd, $imm", []>,
2876 RegConstraint<"$false = $Rd"> {
2877 let Inst{31-27} = 0b11110;
2879 let Inst{24-21} = 0b0010;
2880 let Inst{20} = 0; // The S bit.
2886 let Inst{11-8} = Rd;
2887 let Inst{19-16} = imm{15-12};
2888 let Inst{26} = imm{11};
2889 let Inst{14-12} = imm{10-8};
2890 let Inst{7-0} = imm{7-0};
2893 let isMoveImm = 1 in
2894 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2895 (ins rGPR:$false, i32imm:$src, pred:$p),
2896 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2898 let isMoveImm = 1 in
2899 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2900 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
2901 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2902 imm:$cc, CCR:$ccr))*/]>,
2903 RegConstraint<"$false = $Rd"> {
2904 let Inst{31-27} = 0b11110;
2906 let Inst{24-21} = 0b0011;
2907 let Inst{20} = 0; // The S bit.
2908 let Inst{19-16} = 0b1111; // Rn
2912 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2913 string opc, string asm, list<dag> pattern>
2914 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2915 let Inst{31-27} = 0b11101;
2916 let Inst{26-25} = 0b01;
2917 let Inst{24-21} = 0b0010;
2918 let Inst{20} = 0; // The S bit.
2919 let Inst{19-16} = 0b1111; // Rn
2920 let Inst{5-4} = opcod; // Shift type.
2922 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2923 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2924 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2925 RegConstraint<"$false = $Rd">;
2926 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2927 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2928 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2929 RegConstraint<"$false = $Rd">;
2930 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2931 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2932 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2933 RegConstraint<"$false = $Rd">;
2934 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2935 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2936 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2937 RegConstraint<"$false = $Rd">;
2938 } // isCodeGenOnly = 1
2939 } // neverHasSideEffects
2941 //===----------------------------------------------------------------------===//
2942 // Atomic operations intrinsics
2945 // memory barriers protect the atomic sequences
2946 let hasSideEffects = 1 in {
2947 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2948 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2949 Requires<[IsThumb, HasDB]> {
2951 let Inst{31-4} = 0xf3bf8f5;
2952 let Inst{3-0} = opt;
2956 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2957 "dsb", "\t$opt", []>,
2958 Requires<[IsThumb, HasDB]> {
2960 let Inst{31-4} = 0xf3bf8f4;
2961 let Inst{3-0} = opt;
2964 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2966 []>, Requires<[IsThumb2, HasDB]> {
2968 let Inst{31-4} = 0xf3bf8f6;
2969 let Inst{3-0} = opt;
2972 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2973 InstrItinClass itin, string opc, string asm, string cstr,
2974 list<dag> pattern, bits<4> rt2 = 0b1111>
2975 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2976 let Inst{31-27} = 0b11101;
2977 let Inst{26-20} = 0b0001101;
2978 let Inst{11-8} = rt2;
2979 let Inst{7-6} = 0b01;
2980 let Inst{5-4} = opcod;
2981 let Inst{3-0} = 0b1111;
2985 let Inst{19-16} = addr;
2986 let Inst{15-12} = Rt;
2988 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2989 InstrItinClass itin, string opc, string asm, string cstr,
2990 list<dag> pattern, bits<4> rt2 = 0b1111>
2991 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2992 let Inst{31-27} = 0b11101;
2993 let Inst{26-20} = 0b0001100;
2994 let Inst{11-8} = rt2;
2995 let Inst{7-6} = 0b01;
2996 let Inst{5-4} = opcod;
3002 let Inst{19-16} = addr;
3003 let Inst{15-12} = Rt;
3006 let mayLoad = 1 in {
3007 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3008 AddrModeNone, 4, NoItinerary,
3009 "ldrexb", "\t$Rt, $addr", "", []>;
3010 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3011 AddrModeNone, 4, NoItinerary,
3012 "ldrexh", "\t$Rt, $addr", "", []>;
3013 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3014 AddrModeNone, 4, NoItinerary,
3015 "ldrex", "\t$Rt, $addr", "", []> {
3018 let Inst{31-27} = 0b11101;
3019 let Inst{26-20} = 0b0000101;
3020 let Inst{19-16} = addr{11-8};
3021 let Inst{15-12} = Rt;
3022 let Inst{11-8} = 0b1111;
3023 let Inst{7-0} = addr{7-0};
3025 let hasExtraDefRegAllocReq = 1 in
3026 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3027 (ins addr_offset_none:$addr),
3028 AddrModeNone, 4, NoItinerary,
3029 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3032 let Inst{11-8} = Rt2;
3036 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3037 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3038 (ins rGPR:$Rt, addr_offset_none:$addr),
3039 AddrModeNone, 4, NoItinerary,
3040 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3041 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3042 (ins rGPR:$Rt, addr_offset_none:$addr),
3043 AddrModeNone, 4, NoItinerary,
3044 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3045 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3046 t2addrmode_imm0_1020s4:$addr),
3047 AddrModeNone, 4, NoItinerary,
3048 "strex", "\t$Rd, $Rt, $addr", "",
3053 let Inst{31-27} = 0b11101;
3054 let Inst{26-20} = 0b0000100;
3055 let Inst{19-16} = addr{11-8};
3056 let Inst{15-12} = Rt;
3057 let Inst{11-8} = Rd;
3058 let Inst{7-0} = addr{7-0};
3062 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3063 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3064 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3065 AddrModeNone, 4, NoItinerary,
3066 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3069 let Inst{11-8} = Rt2;
3072 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3073 Requires<[IsThumb2, HasV7]> {
3074 let Inst{31-16} = 0xf3bf;
3075 let Inst{15-14} = 0b10;
3078 let Inst{11-8} = 0b1111;
3079 let Inst{7-4} = 0b0010;
3080 let Inst{3-0} = 0b1111;
3083 //===----------------------------------------------------------------------===//
3084 // SJLJ Exception handling intrinsics
3085 // eh_sjlj_setjmp() is an instruction sequence to store the return
3086 // address and save #0 in R0 for the non-longjmp case.
3087 // Since by its nature we may be coming from some other function to get
3088 // here, and we're using the stack frame for the containing function to
3089 // save/restore registers, we can't keep anything live in regs across
3090 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3091 // when we get here from a longjmp(). We force everything out of registers
3092 // except for our own input by listing the relevant registers in Defs. By
3093 // doing so, we also cause the prologue/epilogue code to actively preserve
3094 // all of the callee-saved resgisters, which is exactly what we want.
3095 // $val is a scratch register for our use.
3097 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3098 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
3099 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3100 usesCustomInserter = 1 in {
3101 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3102 AddrModeNone, 0, NoItinerary, "", "",
3103 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3104 Requires<[IsThumb2, HasVFP2]>;
3108 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3109 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3110 usesCustomInserter = 1 in {
3111 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3112 AddrModeNone, 0, NoItinerary, "", "",
3113 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3114 Requires<[IsThumb2, NoVFP]>;
3118 //===----------------------------------------------------------------------===//
3119 // Control-Flow Instructions
3122 // FIXME: remove when we have a way to marking a MI with these properties.
3123 // FIXME: Should pc be an implicit operand like PICADD, etc?
3124 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3125 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3126 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3127 reglist:$regs, variable_ops),
3128 4, IIC_iLoad_mBr, [],
3129 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3130 RegConstraint<"$Rn = $wb">;
3132 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3133 let isPredicable = 1 in
3134 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3136 [(br bb:$target)]> {
3137 let Inst{31-27} = 0b11110;
3138 let Inst{15-14} = 0b10;
3142 let Inst{26} = target{19};
3143 let Inst{11} = target{18};
3144 let Inst{13} = target{17};
3145 let Inst{21-16} = target{16-11};
3146 let Inst{10-0} = target{10-0};
3149 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3150 def t2BR_JT : t2PseudoInst<(outs),
3151 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3153 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3155 // FIXME: Add a non-pc based case that can be predicated.
3156 def t2TBB_JT : t2PseudoInst<(outs),
3157 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3159 def t2TBH_JT : t2PseudoInst<(outs),
3160 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3162 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3163 "tbb", "\t$addr", []> {
3166 let Inst{31-20} = 0b111010001101;
3167 let Inst{19-16} = Rn;
3168 let Inst{15-5} = 0b11110000000;
3169 let Inst{4} = 0; // B form
3172 let DecoderMethod = "DecodeThumbTableBranch";
3175 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3176 "tbh", "\t$addr", []> {
3179 let Inst{31-20} = 0b111010001101;
3180 let Inst{19-16} = Rn;
3181 let Inst{15-5} = 0b11110000000;
3182 let Inst{4} = 1; // H form
3185 let DecoderMethod = "DecodeThumbTableBranch";
3187 } // isNotDuplicable, isIndirectBranch
3189 } // isBranch, isTerminator, isBarrier
3191 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3192 // a two-value operand where a dag node expects ", "two operands. :(
3193 let isBranch = 1, isTerminator = 1 in
3194 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3196 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3197 let Inst{31-27} = 0b11110;
3198 let Inst{15-14} = 0b10;
3202 let Inst{25-22} = p;
3205 let Inst{26} = target{20};
3206 let Inst{11} = target{19};
3207 let Inst{13} = target{18};
3208 let Inst{21-16} = target{17-12};
3209 let Inst{10-0} = target{11-1};
3211 let DecoderMethod = "DecodeThumb2BCCInstruction";
3214 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3216 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3218 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3220 def tTAILJMPd: tPseudoExpand<(outs),
3221 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3223 (t2B uncondbrtarget:$dst, pred:$p)>,
3224 Requires<[IsThumb2, IsDarwin]>;
3228 let Defs = [ITSTATE] in
3229 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3230 AddrModeNone, 2, IIC_iALUx,
3231 "it$mask\t$cc", "", []> {
3232 // 16-bit instruction.
3233 let Inst{31-16} = 0x0000;
3234 let Inst{15-8} = 0b10111111;
3239 let Inst{3-0} = mask;
3241 let DecoderMethod = "DecodeIT";
3244 // Branch and Exchange Jazelle -- for disassembly only
3246 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3248 let Inst{31-27} = 0b11110;
3250 let Inst{25-20} = 0b111100;
3251 let Inst{19-16} = func;
3252 let Inst{15-0} = 0b1000111100000000;
3255 // Compare and branch on zero / non-zero
3256 let isBranch = 1, isTerminator = 1 in {
3257 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3258 "cbz\t$Rn, $target", []>,
3259 T1Misc<{0,0,?,1,?,?,?}>,
3260 Requires<[IsThumb2]> {
3264 let Inst{9} = target{5};
3265 let Inst{7-3} = target{4-0};
3269 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3270 "cbnz\t$Rn, $target", []>,
3271 T1Misc<{1,0,?,1,?,?,?}>,
3272 Requires<[IsThumb2]> {
3276 let Inst{9} = target{5};
3277 let Inst{7-3} = target{4-0};
3283 // Change Processor State is a system instruction.
3284 // FIXME: Since the asm parser has currently no clean way to handle optional
3285 // operands, create 3 versions of the same instruction. Once there's a clean
3286 // framework to represent optional operands, change this behavior.
3287 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3288 !strconcat("cps", asm_op), []> {
3294 let Inst{31-27} = 0b11110;
3296 let Inst{25-20} = 0b111010;
3297 let Inst{19-16} = 0b1111;
3298 let Inst{15-14} = 0b10;
3300 let Inst{10-9} = imod;
3302 let Inst{7-5} = iflags;
3303 let Inst{4-0} = mode;
3304 let DecoderMethod = "DecodeT2CPSInstruction";
3308 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3309 "$imod.w\t$iflags, $mode">;
3310 let mode = 0, M = 0 in
3311 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3312 "$imod.w\t$iflags">;
3313 let imod = 0, iflags = 0, M = 1 in
3314 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3316 // A6.3.4 Branches and miscellaneous control
3317 // Table A6-14 Change Processor State, and hint instructions
3318 class T2I_hint<bits<8> op7_0, string opc, string asm>
3319 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3320 let Inst{31-20} = 0xf3a;
3321 let Inst{19-16} = 0b1111;
3322 let Inst{15-14} = 0b10;
3324 let Inst{10-8} = 0b000;
3325 let Inst{7-0} = op7_0;
3328 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3329 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3330 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3331 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3332 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3334 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3336 let Inst{31-20} = 0b111100111010;
3337 let Inst{19-16} = 0b1111;
3338 let Inst{15-8} = 0b10000000;
3339 let Inst{7-4} = 0b1111;
3340 let Inst{3-0} = opt;
3343 // Secure Monitor Call is a system instruction.
3344 // Option = Inst{19-16}
3345 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3346 let Inst{31-27} = 0b11110;
3347 let Inst{26-20} = 0b1111111;
3348 let Inst{15-12} = 0b1000;
3351 let Inst{19-16} = opt;
3354 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3355 string opc, string asm, list<dag> pattern>
3356 : T2I<oops, iops, itin, opc, asm, pattern> {
3358 let Inst{31-25} = 0b1110100;
3359 let Inst{24-23} = Op;
3362 let Inst{20-16} = 0b01101;
3363 let Inst{15-5} = 0b11000000000;
3364 let Inst{4-0} = mode{4-0};
3367 // Store Return State is a system instruction.
3368 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3369 "srsdb", "\tsp!, $mode", []>;
3370 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3371 "srsdb","\tsp, $mode", []>;
3372 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3373 "srsia","\tsp!, $mode", []>;
3374 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3375 "srsia","\tsp, $mode", []>;
3377 // Return From Exception is a system instruction.
3378 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3379 string opc, string asm, list<dag> pattern>
3380 : T2I<oops, iops, itin, opc, asm, pattern> {
3381 let Inst{31-20} = op31_20{11-0};
3384 let Inst{19-16} = Rn;
3385 let Inst{15-0} = 0xc000;
3388 def t2RFEDBW : T2RFE<0b111010000011,
3389 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3390 [/* For disassembly only; pattern left blank */]>;
3391 def t2RFEDB : T2RFE<0b111010000001,
3392 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3393 [/* For disassembly only; pattern left blank */]>;
3394 def t2RFEIAW : T2RFE<0b111010011011,
3395 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3396 [/* For disassembly only; pattern left blank */]>;
3397 def t2RFEIA : T2RFE<0b111010011001,
3398 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3399 [/* For disassembly only; pattern left blank */]>;
3401 //===----------------------------------------------------------------------===//
3402 // Non-Instruction Patterns
3405 // 32-bit immediate using movw + movt.
3406 // This is a single pseudo instruction to make it re-materializable.
3407 // FIXME: Remove this when we can do generalized remat.
3408 let isReMaterializable = 1, isMoveImm = 1 in
3409 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3410 [(set rGPR:$dst, (i32 imm:$src))]>,
3411 Requires<[IsThumb, HasV6T2]>;
3413 // Pseudo instruction that combines movw + movt + add pc (if pic).
3414 // It also makes it possible to rematerialize the instructions.
3415 // FIXME: Remove this when we can do generalized remat and when machine licm
3416 // can properly the instructions.
3417 let isReMaterializable = 1 in {
3418 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3420 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3421 Requires<[IsThumb2, UseMovt]>;
3423 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3425 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3426 Requires<[IsThumb2, UseMovt]>;
3429 // ConstantPool, GlobalAddress, and JumpTable
3430 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3431 Requires<[IsThumb2, DontUseMovt]>;
3432 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3433 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3434 Requires<[IsThumb2, UseMovt]>;
3436 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3437 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3439 // Pseudo instruction that combines ldr from constpool and add pc. This should
3440 // be expanded into two instructions late to allow if-conversion and
3442 let canFoldAsLoad = 1, isReMaterializable = 1 in
3443 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3445 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3447 Requires<[IsThumb2]>;
3449 // Pseudo isntruction that combines movs + predicated rsbmi
3450 // to implement integer ABS
3451 let usesCustomInserter = 1, Defs = [CPSR] in {
3452 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3453 NoItinerary, []>, Requires<[IsThumb2]>;
3456 //===----------------------------------------------------------------------===//
3457 // Coprocessor load/store -- for disassembly only
3459 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3460 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3461 let Inst{31-28} = op31_28;
3462 let Inst{27-25} = 0b110;
3465 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3466 def _OFFSET : T2CI<op31_28,
3467 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3468 asm, "\t$cop, $CRd, $addr"> {
3472 let Inst{24} = 1; // P = 1
3473 let Inst{23} = addr{8};
3474 let Inst{22} = Dbit;
3475 let Inst{21} = 0; // W = 0
3476 let Inst{20} = load;
3477 let Inst{19-16} = addr{12-9};
3478 let Inst{15-12} = CRd;
3479 let Inst{11-8} = cop;
3480 let Inst{7-0} = addr{7-0};
3481 let DecoderMethod = "DecodeCopMemInstruction";
3483 def _PRE : T2CI<op31_28,
3484 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3485 asm, "\t$cop, $CRd, $addr!"> {
3489 let Inst{24} = 1; // P = 1
3490 let Inst{23} = addr{8};
3491 let Inst{22} = Dbit;
3492 let Inst{21} = 1; // W = 1
3493 let Inst{20} = load;
3494 let Inst{19-16} = addr{12-9};
3495 let Inst{15-12} = CRd;
3496 let Inst{11-8} = cop;
3497 let Inst{7-0} = addr{7-0};
3498 let DecoderMethod = "DecodeCopMemInstruction";
3500 def _POST: T2CI<op31_28,
3501 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3502 postidx_imm8s4:$offset),
3503 asm, "\t$cop, $CRd, $addr, $offset"> {
3508 let Inst{24} = 0; // P = 0
3509 let Inst{23} = offset{8};
3510 let Inst{22} = Dbit;
3511 let Inst{21} = 1; // W = 1
3512 let Inst{20} = load;
3513 let Inst{19-16} = addr;
3514 let Inst{15-12} = CRd;
3515 let Inst{11-8} = cop;
3516 let Inst{7-0} = offset{7-0};
3517 let DecoderMethod = "DecodeCopMemInstruction";
3519 def _OPTION : T2CI<op31_28, (outs),
3520 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3521 coproc_option_imm:$option),
3522 asm, "\t$cop, $CRd, $addr, $option"> {
3527 let Inst{24} = 0; // P = 0
3528 let Inst{23} = 1; // U = 1
3529 let Inst{22} = Dbit;
3530 let Inst{21} = 0; // W = 0
3531 let Inst{20} = load;
3532 let Inst{19-16} = addr;
3533 let Inst{15-12} = CRd;
3534 let Inst{11-8} = cop;
3535 let Inst{7-0} = option;
3536 let DecoderMethod = "DecodeCopMemInstruction";
3540 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3541 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3542 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3543 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3544 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3545 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3546 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3547 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3550 //===----------------------------------------------------------------------===//
3551 // Move between special register and ARM core register -- for disassembly only
3553 // Move to ARM core register from Special Register
3557 // A/R class can only move from CPSR or SPSR.
3558 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>,
3559 Requires<[IsThumb2,IsARClass]> {
3561 let Inst{31-12} = 0b11110011111011111000;
3562 let Inst{11-8} = Rd;
3563 let Inst{7-0} = 0b0000;
3566 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3568 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>,
3569 Requires<[IsThumb2,IsARClass]> {
3571 let Inst{31-12} = 0b11110011111111111000;
3572 let Inst{11-8} = Rd;
3573 let Inst{7-0} = 0b0000;
3578 // This MRS has a mask field in bits 7-0 and can take more values than
3579 // the A/R class (a full msr_mask).
3580 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3581 "mrs", "\t$Rd, $mask", []>,
3582 Requires<[IsThumb2,IsMClass]> {
3585 let Inst{31-12} = 0b11110011111011111000;
3586 let Inst{11-8} = Rd;
3587 let Inst{19-16} = 0b1111;
3588 let Inst{7-0} = mask;
3592 // Move from ARM core register to Special Register
3596 // No need to have both system and application versions, the encodings are the
3597 // same and the assembly parser has no way to distinguish between them. The mask
3598 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3599 // the mask with the fields to be accessed in the special register.
3600 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3601 NoItinerary, "msr", "\t$mask, $Rn", []>,
3602 Requires<[IsThumb2,IsARClass]> {
3605 let Inst{31-21} = 0b11110011100;
3606 let Inst{20} = mask{4}; // R Bit
3607 let Inst{19-16} = Rn;
3608 let Inst{15-12} = 0b1000;
3609 let Inst{11-8} = mask{3-0};
3615 // Move from ARM core register to Special Register
3616 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3617 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3618 Requires<[IsThumb2,IsMClass]> {
3621 let Inst{31-21} = 0b11110011100;
3623 let Inst{19-16} = Rn;
3624 let Inst{15-12} = 0b1000;
3625 let Inst{7-0} = SYSm;
3629 //===----------------------------------------------------------------------===//
3630 // Move between coprocessor and ARM core register
3633 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3635 : T2Cop<Op, oops, iops,
3636 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3638 let Inst{27-24} = 0b1110;
3639 let Inst{20} = direction;
3649 let Inst{15-12} = Rt;
3650 let Inst{11-8} = cop;
3651 let Inst{23-21} = opc1;
3652 let Inst{7-5} = opc2;
3653 let Inst{3-0} = CRm;
3654 let Inst{19-16} = CRn;
3657 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3658 list<dag> pattern = []>
3660 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3661 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3662 let Inst{27-24} = 0b1100;
3663 let Inst{23-21} = 0b010;
3664 let Inst{20} = direction;
3672 let Inst{15-12} = Rt;
3673 let Inst{19-16} = Rt2;
3674 let Inst{11-8} = cop;
3675 let Inst{7-4} = opc1;
3676 let Inst{3-0} = CRm;
3679 /* from ARM core register to coprocessor */
3680 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3682 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3683 c_imm:$CRm, imm0_7:$opc2),
3684 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3685 imm:$CRm, imm:$opc2)]>;
3686 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3687 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3688 c_imm:$CRm, imm0_7:$opc2),
3689 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3690 imm:$CRm, imm:$opc2)]>;
3692 /* from coprocessor to ARM core register */
3693 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3694 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3695 c_imm:$CRm, imm0_7:$opc2), []>;
3697 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3698 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3699 c_imm:$CRm, imm0_7:$opc2), []>;
3701 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3702 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3704 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3705 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3708 /* from ARM core register to coprocessor */
3709 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3710 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3712 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3713 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3714 GPR:$Rt2, imm:$CRm)]>;
3715 /* from coprocessor to ARM core register */
3716 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3718 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3720 //===----------------------------------------------------------------------===//
3721 // Other Coprocessor Instructions.
3724 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3725 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3726 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3727 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3728 imm:$CRm, imm:$opc2)]> {
3729 let Inst{27-24} = 0b1110;
3738 let Inst{3-0} = CRm;
3740 let Inst{7-5} = opc2;
3741 let Inst{11-8} = cop;
3742 let Inst{15-12} = CRd;
3743 let Inst{19-16} = CRn;
3744 let Inst{23-20} = opc1;
3747 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3748 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3749 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3750 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3751 imm:$CRm, imm:$opc2)]> {
3752 let Inst{27-24} = 0b1110;
3761 let Inst{3-0} = CRm;
3763 let Inst{7-5} = opc2;
3764 let Inst{11-8} = cop;
3765 let Inst{15-12} = CRd;
3766 let Inst{19-16} = CRn;
3767 let Inst{23-20} = opc1;
3772 //===----------------------------------------------------------------------===//
3773 // Non-Instruction Patterns
3776 // SXT/UXT with no rotate
3777 let AddedComplexity = 16 in {
3778 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3779 Requires<[IsThumb2]>;
3780 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3781 Requires<[IsThumb2]>;
3782 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3783 Requires<[HasT2ExtractPack, IsThumb2]>;
3784 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3785 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3786 Requires<[HasT2ExtractPack, IsThumb2]>;
3787 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3788 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3789 Requires<[HasT2ExtractPack, IsThumb2]>;
3792 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3793 Requires<[IsThumb2]>;
3794 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3795 Requires<[IsThumb2]>;
3796 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3797 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3798 Requires<[HasT2ExtractPack, IsThumb2]>;
3799 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3800 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3801 Requires<[HasT2ExtractPack, IsThumb2]>;
3803 // Atomic load/store patterns
3804 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3805 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3806 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3807 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3808 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3809 (t2LDRBs t2addrmode_so_reg:$addr)>;
3810 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3811 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3812 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3813 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3814 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3815 (t2LDRHs t2addrmode_so_reg:$addr)>;
3816 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3817 (t2LDRi12 t2addrmode_imm12:$addr)>;
3818 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3819 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3820 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3821 (t2LDRs t2addrmode_so_reg:$addr)>;
3822 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3823 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3824 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3825 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3826 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3827 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3828 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3829 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3830 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3831 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3832 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3833 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3834 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3835 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3836 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3837 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3838 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3839 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3842 //===----------------------------------------------------------------------===//
3843 // Assembler aliases
3846 // Aliases for ADC without the ".w" optional width specifier.
3847 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3848 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3849 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3850 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3851 pred:$p, cc_out:$s)>;
3853 // Aliases for SBC without the ".w" optional width specifier.
3854 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3855 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3856 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3857 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3858 pred:$p, cc_out:$s)>;
3860 // Aliases for ADD without the ".w" optional width specifier.
3861 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3862 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3863 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3864 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3865 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3866 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3867 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3868 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3869 pred:$p, cc_out:$s)>;
3870 // ... and with the destination and source register combined.
3871 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
3872 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3873 def : t2InstAlias<"add${p} $Rdn, $imm",
3874 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3875 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
3876 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3877 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
3878 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
3879 pred:$p, cc_out:$s)>;
3881 // Aliases for SUB without the ".w" optional width specifier.
3882 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3883 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3884 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3885 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3886 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3887 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3888 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3889 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3890 pred:$p, cc_out:$s)>;
3891 // ... and with the destination and source register combined.
3892 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
3893 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3894 def : t2InstAlias<"sub${p} $Rdn, $imm",
3895 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3896 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
3897 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3898 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
3899 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
3900 pred:$p, cc_out:$s)>;
3903 // Alias for compares without the ".w" optional width specifier.
3904 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3905 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3906 def : t2InstAlias<"teq${p} $Rn, $Rm",
3907 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3908 def : t2InstAlias<"tst${p} $Rn, $Rm",
3909 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3912 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3913 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3914 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3916 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3918 def : t2InstAlias<"ldr${p} $Rt, $addr",
3919 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3920 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3921 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3922 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3923 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3924 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3925 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3926 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3927 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3929 def : t2InstAlias<"ldr${p} $Rt, $addr",
3930 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3931 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3932 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3933 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3934 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3935 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3936 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3937 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3938 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3940 def : t2InstAlias<"ldr${p} $Rt, $addr",
3941 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3942 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3943 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3944 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3945 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3946 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3947 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3948 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3949 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3951 // Alias for MVN with(out) the ".w" optional width specifier.
3952 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
3953 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3954 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
3955 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
3956 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
3957 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
3959 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
3960 // shift amount is zero (i.e., unspecified).
3961 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
3962 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3963 Requires<[HasT2ExtractPack, IsThumb2]>;
3964 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
3965 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3966 Requires<[HasT2ExtractPack, IsThumb2]>;
3968 // PUSH/POP aliases for STM/LDM
3969 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3970 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3971 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3972 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3974 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
3975 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
3976 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
3977 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
3978 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
3980 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
3981 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
3982 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
3983 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
3984 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
3986 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
3987 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3988 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3989 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3992 // Alias for RSB without the ".w" optional width specifier, and with optional
3993 // implied destination register.
3994 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
3995 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3996 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
3997 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3998 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
3999 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4000 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4001 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4004 // SSAT/USAT optional shift operand.
4005 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4006 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4007 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4008 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4010 // STM w/o the .w suffix.
4011 def : t2InstAlias<"stm${p} $Rn, $regs",
4012 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4014 // Alias for STR, STRB, and STRH without the ".w" optional
4016 def : t2InstAlias<"str${p} $Rt, $addr",
4017 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4018 def : t2InstAlias<"strb${p} $Rt, $addr",
4019 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4020 def : t2InstAlias<"strh${p} $Rt, $addr",
4021 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4023 def : t2InstAlias<"str${p} $Rt, $addr",
4024 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4025 def : t2InstAlias<"strb${p} $Rt, $addr",
4026 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4027 def : t2InstAlias<"strh${p} $Rt, $addr",
4028 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4030 // Extend instruction optional rotate operand.
4031 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4032 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4033 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4034 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4035 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4036 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4038 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4039 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4040 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4041 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4042 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4043 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4044 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4045 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4046 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4047 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4049 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4050 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4051 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4052 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4053 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4054 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4055 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4056 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4057 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4058 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4059 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4060 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4062 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4063 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4064 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4065 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4067 // Extend instruction w/o the ".w" optional width specifier.
4068 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4069 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4070 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4071 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4072 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4073 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4075 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4076 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4077 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4078 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4079 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4080 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4083 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4085 def : t2InstAlias<"mov${p} $Rd, $imm",
4086 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4089 // Wide 'mul' encoding can be specified with only two operands.
4090 def : t2InstAlias<"mul${p} $Rn, $Rm",
4091 (t2MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p)>;