1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // t2_so_imm - Match a 32-bit immediate operand, which is an
66 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
67 // immediate splatted into multiple bytes of the word.
68 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
69 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
70 return ARM_AM::getT2SOImmVal(Imm) != -1;
72 let ParserMatchClass = t2_so_imm_asmoperand;
73 let EncoderMethod = "getT2SOImmOpValue";
74 let DecoderMethod = "DecodeT2SOImm";
77 // t2_so_imm_not - Match an immediate that is a complement
79 // Note: this pattern doesn't require an encoder method and such, as it's
80 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
81 // is handled by the destination instructions, which use t2_so_imm.
82 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
83 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
84 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
85 }], t2_so_imm_not_XFORM> {
86 let ParserMatchClass = t2_so_imm_not_asmoperand;
89 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
90 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
91 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
93 }], t2_so_imm_neg_XFORM> {
94 let ParserMatchClass = t2_so_imm_neg_asmoperand;
97 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
98 def imm0_4095 : Operand<i32>,
100 return Imm >= 0 && Imm < 4096;
103 def imm0_4095_neg : PatLeaf<(i32 imm), [{
104 return (uint32_t)(-N->getZExtValue()) < 4096;
107 def imm0_255_neg : PatLeaf<(i32 imm), [{
108 return (uint32_t)(-N->getZExtValue()) < 255;
111 def imm0_255_not : PatLeaf<(i32 imm), [{
112 return (uint32_t)(~N->getZExtValue()) < 255;
115 def lo5AllOne : PatLeaf<(i32 imm), [{
116 // Returns true if all low 5-bits are 1.
117 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
120 // Define Thumb2 specific addressing modes.
122 // t2addrmode_imm12 := reg + imm12
123 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
124 def t2addrmode_imm12 : Operand<i32>,
125 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
126 let PrintMethod = "printAddrModeImm12Operand";
127 let EncoderMethod = "getAddrModeImm12OpValue";
128 let DecoderMethod = "DecodeT2AddrModeImm12";
129 let ParserMatchClass = t2addrmode_imm12_asmoperand;
130 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
133 // t2ldrlabel := imm12
134 def t2ldrlabel : Operand<i32> {
135 let EncoderMethod = "getAddrModeImm12OpValue";
136 let PrintMethod = "printT2LdrLabelOperand";
139 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
140 def t2ldr_pcrel_imm12 : Operand<i32> {
141 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
142 // used for assembler pseudo instruction and maps to t2ldrlabel, so
143 // doesn't need encoder or print methods of its own.
146 // ADR instruction labels.
147 def t2adrlabel : Operand<i32> {
148 let EncoderMethod = "getT2AdrLabelOpValue";
152 // t2addrmode_posimm8 := reg + imm8
153 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
154 def t2addrmode_posimm8 : Operand<i32> {
155 let PrintMethod = "printT2AddrModeImm8Operand";
156 let EncoderMethod = "getT2AddrModeImm8OpValue";
157 let DecoderMethod = "DecodeT2AddrModeImm8";
158 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
159 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
162 // t2addrmode_negimm8 := reg - imm8
163 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
164 def t2addrmode_negimm8 : Operand<i32>,
165 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
166 let PrintMethod = "printT2AddrModeImm8Operand";
167 let EncoderMethod = "getT2AddrModeImm8OpValue";
168 let DecoderMethod = "DecodeT2AddrModeImm8";
169 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
170 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
173 // t2addrmode_imm8 := reg +/- imm8
174 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
175 def t2addrmode_imm8 : Operand<i32>,
176 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
177 let PrintMethod = "printT2AddrModeImm8Operand";
178 let EncoderMethod = "getT2AddrModeImm8OpValue";
179 let DecoderMethod = "DecodeT2AddrModeImm8";
180 let ParserMatchClass = MemImm8OffsetAsmOperand;
181 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
184 def t2am_imm8_offset : Operand<i32>,
185 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
186 [], [SDNPWantRoot]> {
187 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
188 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
189 let DecoderMethod = "DecodeT2Imm8";
192 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
193 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
194 def t2addrmode_imm8s4 : Operand<i32> {
195 let PrintMethod = "printT2AddrModeImm8s4Operand";
196 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
197 let DecoderMethod = "DecodeT2AddrModeImm8s4";
198 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
199 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
202 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
203 def t2am_imm8s4_offset : Operand<i32> {
204 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
205 let EncoderMethod = "getT2Imm8s4OpValue";
206 let DecoderMethod = "DecodeT2Imm8S4";
209 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
210 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
211 let Name = "MemImm0_1020s4Offset";
213 def t2addrmode_imm0_1020s4 : Operand<i32> {
214 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
215 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
216 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
217 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
218 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
221 // t2addrmode_so_reg := reg + (reg << imm2)
222 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
223 def t2addrmode_so_reg : Operand<i32>,
224 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
225 let PrintMethod = "printT2AddrModeSoRegOperand";
226 let EncoderMethod = "getT2AddrModeSORegOpValue";
227 let DecoderMethod = "DecodeT2AddrModeSOReg";
228 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
229 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
232 // Addresses for the TBB/TBH instructions.
233 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
234 def addrmode_tbb : Operand<i32> {
235 let PrintMethod = "printAddrModeTBB";
236 let ParserMatchClass = addrmode_tbb_asmoperand;
237 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
239 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
240 def addrmode_tbh : Operand<i32> {
241 let PrintMethod = "printAddrModeTBH";
242 let ParserMatchClass = addrmode_tbh_asmoperand;
243 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
246 //===----------------------------------------------------------------------===//
247 // Multiclass helpers...
251 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
252 string opc, string asm, list<dag> pattern>
253 : T2I<oops, iops, itin, opc, asm, pattern> {
258 let Inst{26} = imm{11};
259 let Inst{14-12} = imm{10-8};
260 let Inst{7-0} = imm{7-0};
264 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
265 string opc, string asm, list<dag> pattern>
266 : T2sI<oops, iops, itin, opc, asm, pattern> {
272 let Inst{26} = imm{11};
273 let Inst{14-12} = imm{10-8};
274 let Inst{7-0} = imm{7-0};
277 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
278 string opc, string asm, list<dag> pattern>
279 : T2I<oops, iops, itin, opc, asm, pattern> {
283 let Inst{19-16} = Rn;
284 let Inst{26} = imm{11};
285 let Inst{14-12} = imm{10-8};
286 let Inst{7-0} = imm{7-0};
290 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
291 string opc, string asm, list<dag> pattern>
292 : T2I<oops, iops, itin, opc, asm, pattern> {
297 let Inst{3-0} = ShiftedRm{3-0};
298 let Inst{5-4} = ShiftedRm{6-5};
299 let Inst{14-12} = ShiftedRm{11-9};
300 let Inst{7-6} = ShiftedRm{8-7};
303 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
304 string opc, string asm, list<dag> pattern>
305 : T2sI<oops, iops, itin, opc, asm, pattern> {
310 let Inst{3-0} = ShiftedRm{3-0};
311 let Inst{5-4} = ShiftedRm{6-5};
312 let Inst{14-12} = ShiftedRm{11-9};
313 let Inst{7-6} = ShiftedRm{8-7};
316 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
317 string opc, string asm, list<dag> pattern>
318 : T2I<oops, iops, itin, opc, asm, pattern> {
322 let Inst{19-16} = Rn;
323 let Inst{3-0} = ShiftedRm{3-0};
324 let Inst{5-4} = ShiftedRm{6-5};
325 let Inst{14-12} = ShiftedRm{11-9};
326 let Inst{7-6} = ShiftedRm{8-7};
329 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
330 string opc, string asm, list<dag> pattern>
331 : T2I<oops, iops, itin, opc, asm, pattern> {
339 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
340 string opc, string asm, list<dag> pattern>
341 : T2sI<oops, iops, itin, opc, asm, pattern> {
349 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
350 string opc, string asm, list<dag> pattern>
351 : T2I<oops, iops, itin, opc, asm, pattern> {
355 let Inst{19-16} = Rn;
360 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : T2I<oops, iops, itin, opc, asm, pattern> {
368 let Inst{19-16} = Rn;
369 let Inst{26} = imm{11};
370 let Inst{14-12} = imm{10-8};
371 let Inst{7-0} = imm{7-0};
374 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
375 string opc, string asm, list<dag> pattern>
376 : T2sI<oops, iops, itin, opc, asm, pattern> {
382 let Inst{19-16} = Rn;
383 let Inst{26} = imm{11};
384 let Inst{14-12} = imm{10-8};
385 let Inst{7-0} = imm{7-0};
388 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
389 string opc, string asm, list<dag> pattern>
390 : T2I<oops, iops, itin, opc, asm, pattern> {
397 let Inst{14-12} = imm{4-2};
398 let Inst{7-6} = imm{1-0};
401 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
402 string opc, string asm, list<dag> pattern>
403 : T2sI<oops, iops, itin, opc, asm, pattern> {
410 let Inst{14-12} = imm{4-2};
411 let Inst{7-6} = imm{1-0};
414 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
415 string opc, string asm, list<dag> pattern>
416 : T2I<oops, iops, itin, opc, asm, pattern> {
422 let Inst{19-16} = Rn;
426 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
427 string opc, string asm, list<dag> pattern>
428 : T2sI<oops, iops, itin, opc, asm, pattern> {
434 let Inst{19-16} = Rn;
438 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
439 string opc, string asm, list<dag> pattern>
440 : T2I<oops, iops, itin, opc, asm, pattern> {
446 let Inst{19-16} = Rn;
447 let Inst{3-0} = ShiftedRm{3-0};
448 let Inst{5-4} = ShiftedRm{6-5};
449 let Inst{14-12} = ShiftedRm{11-9};
450 let Inst{7-6} = ShiftedRm{8-7};
453 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
454 string opc, string asm, list<dag> pattern>
455 : T2sI<oops, iops, itin, opc, asm, pattern> {
461 let Inst{19-16} = Rn;
462 let Inst{3-0} = ShiftedRm{3-0};
463 let Inst{5-4} = ShiftedRm{6-5};
464 let Inst{14-12} = ShiftedRm{11-9};
465 let Inst{7-6} = ShiftedRm{8-7};
468 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : T2I<oops, iops, itin, opc, asm, pattern> {
476 let Inst{19-16} = Rn;
477 let Inst{15-12} = Ra;
482 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
483 dag oops, dag iops, InstrItinClass itin,
484 string opc, string asm, list<dag> pattern>
485 : T2I<oops, iops, itin, opc, asm, pattern> {
491 let Inst{31-23} = 0b111110111;
492 let Inst{22-20} = opc22_20;
493 let Inst{19-16} = Rn;
494 let Inst{15-12} = RdLo;
495 let Inst{11-8} = RdHi;
496 let Inst{7-4} = opc7_4;
501 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
502 /// binary operation that produces a value. These are predicable and can be
503 /// changed to modify CPSR.
504 multiclass T2I_bin_irs<bits<4> opcod, string opc,
505 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
506 PatFrag opnode, string baseOpc, bit Commutable = 0,
509 def ri : T2sTwoRegImm<
510 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
511 opc, "\t$Rd, $Rn, $imm",
512 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
513 let Inst{31-27} = 0b11110;
515 let Inst{24-21} = opcod;
519 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
520 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
521 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
522 let isCommutable = Commutable;
523 let Inst{31-27} = 0b11101;
524 let Inst{26-25} = 0b01;
525 let Inst{24-21} = opcod;
526 let Inst{14-12} = 0b000; // imm3
527 let Inst{7-6} = 0b00; // imm2
528 let Inst{5-4} = 0b00; // type
531 def rs : T2sTwoRegShiftedReg<
532 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
533 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
534 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
535 let Inst{31-27} = 0b11101;
536 let Inst{26-25} = 0b01;
537 let Inst{24-21} = opcod;
539 // Assembly aliases for optional destination operand when it's the same
540 // as the source operand.
541 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
542 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
543 t2_so_imm:$imm, pred:$p,
545 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
546 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
549 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
550 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
551 t2_so_reg:$shift, pred:$p,
555 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
556 // the ".w" suffix to indicate that they are wide.
557 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
558 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
559 PatFrag opnode, string baseOpc, bit Commutable = 0> :
560 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
561 // Assembler aliases w/o the ".w" suffix.
562 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
563 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
566 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
567 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
568 t2_so_reg:$shift, pred:$p,
571 // and with the optional destination operand, too.
572 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
573 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
576 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
577 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
578 t2_so_reg:$shift, pred:$p,
582 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
583 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
584 /// it is equivalent to the T2I_bin_irs counterpart.
585 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
587 def ri : T2sTwoRegImm<
588 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
589 opc, ".w\t$Rd, $Rn, $imm",
590 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
591 let Inst{31-27} = 0b11110;
593 let Inst{24-21} = opcod;
597 def rr : T2sThreeReg<
598 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
599 opc, "\t$Rd, $Rn, $Rm",
600 [/* For disassembly only; pattern left blank */]> {
601 let Inst{31-27} = 0b11101;
602 let Inst{26-25} = 0b01;
603 let Inst{24-21} = opcod;
604 let Inst{14-12} = 0b000; // imm3
605 let Inst{7-6} = 0b00; // imm2
606 let Inst{5-4} = 0b00; // type
609 def rs : T2sTwoRegShiftedReg<
610 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
611 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
612 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
613 let Inst{31-27} = 0b11101;
614 let Inst{26-25} = 0b01;
615 let Inst{24-21} = opcod;
619 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
620 /// instruction modifies the CPSR register.
622 /// These opcodes will be converted to the real non-S opcodes by
623 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
624 let hasPostISelHook = 1, Defs = [CPSR] in {
625 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
626 InstrItinClass iis, PatFrag opnode,
627 bit Commutable = 0> {
629 def ri : t2PseudoInst<(outs rGPR:$Rd),
630 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
632 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
635 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
637 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
639 let isCommutable = Commutable;
642 def rs : t2PseudoInst<(outs rGPR:$Rd),
643 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
645 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
646 t2_so_reg:$ShiftedRm))]>;
650 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
651 /// operands are reversed.
652 let hasPostISelHook = 1, Defs = [CPSR] in {
653 multiclass T2I_rbin_s_is<PatFrag opnode> {
655 def ri : t2PseudoInst<(outs rGPR:$Rd),
656 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
658 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
661 def rs : t2PseudoInst<(outs rGPR:$Rd),
662 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
664 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
669 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
670 /// patterns for a binary operation that produces a value.
671 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
672 bit Commutable = 0> {
674 // The register-immediate version is re-materializable. This is useful
675 // in particular for taking the address of a local.
676 let isReMaterializable = 1 in {
677 def ri : T2sTwoRegImm<
678 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
679 opc, ".w\t$Rd, $Rn, $imm",
680 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
681 let Inst{31-27} = 0b11110;
684 let Inst{23-21} = op23_21;
690 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
691 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
692 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
696 let Inst{31-27} = 0b11110;
697 let Inst{26} = imm{11};
698 let Inst{25-24} = 0b10;
699 let Inst{23-21} = op23_21;
700 let Inst{20} = 0; // The S bit.
701 let Inst{19-16} = Rn;
703 let Inst{14-12} = imm{10-8};
705 let Inst{7-0} = imm{7-0};
708 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
709 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
710 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
711 let isCommutable = Commutable;
712 let Inst{31-27} = 0b11101;
713 let Inst{26-25} = 0b01;
715 let Inst{23-21} = op23_21;
716 let Inst{14-12} = 0b000; // imm3
717 let Inst{7-6} = 0b00; // imm2
718 let Inst{5-4} = 0b00; // type
721 def rs : T2sTwoRegShiftedReg<
722 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
723 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
724 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
725 let Inst{31-27} = 0b11101;
726 let Inst{26-25} = 0b01;
728 let Inst{23-21} = op23_21;
732 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
733 /// for a binary operation that produces a value and use the carry
734 /// bit. It's not predicable.
735 let Defs = [CPSR], Uses = [CPSR] in {
736 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
737 bit Commutable = 0> {
739 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
740 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
741 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
742 Requires<[IsThumb2]> {
743 let Inst{31-27} = 0b11110;
745 let Inst{24-21} = opcod;
749 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
750 opc, ".w\t$Rd, $Rn, $Rm",
751 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
752 Requires<[IsThumb2]> {
753 let isCommutable = Commutable;
754 let Inst{31-27} = 0b11101;
755 let Inst{26-25} = 0b01;
756 let Inst{24-21} = opcod;
757 let Inst{14-12} = 0b000; // imm3
758 let Inst{7-6} = 0b00; // imm2
759 let Inst{5-4} = 0b00; // type
762 def rs : T2sTwoRegShiftedReg<
763 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
764 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
765 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
766 Requires<[IsThumb2]> {
767 let Inst{31-27} = 0b11101;
768 let Inst{26-25} = 0b01;
769 let Inst{24-21} = opcod;
774 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
775 // rotate operation that produces a value.
776 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
779 def ri : T2sTwoRegShiftImm<
780 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
781 opc, ".w\t$Rd, $Rm, $imm",
782 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
783 let Inst{31-27} = 0b11101;
784 let Inst{26-21} = 0b010010;
785 let Inst{19-16} = 0b1111; // Rn
786 let Inst{5-4} = opcod;
789 def rr : T2sThreeReg<
790 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
791 opc, ".w\t$Rd, $Rn, $Rm",
792 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
793 let Inst{31-27} = 0b11111;
794 let Inst{26-23} = 0b0100;
795 let Inst{22-21} = opcod;
796 let Inst{15-12} = 0b1111;
797 let Inst{7-4} = 0b0000;
800 // Optional destination register
801 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
802 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
805 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
806 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
810 // Assembler aliases w/o the ".w" suffix.
811 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
812 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
815 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
816 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
820 // and with the optional destination operand, too.
821 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
822 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
825 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
826 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
831 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
832 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
833 /// a explicit result, only implicitly set CPSR.
834 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
835 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
836 PatFrag opnode, string baseOpc> {
837 let isCompare = 1, Defs = [CPSR] in {
839 def ri : T2OneRegCmpImm<
840 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
841 opc, ".w\t$Rn, $imm",
842 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
843 let Inst{31-27} = 0b11110;
845 let Inst{24-21} = opcod;
846 let Inst{20} = 1; // The S bit.
848 let Inst{11-8} = 0b1111; // Rd
851 def rr : T2TwoRegCmp<
852 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
854 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
855 let Inst{31-27} = 0b11101;
856 let Inst{26-25} = 0b01;
857 let Inst{24-21} = opcod;
858 let Inst{20} = 1; // The S bit.
859 let Inst{14-12} = 0b000; // imm3
860 let Inst{11-8} = 0b1111; // Rd
861 let Inst{7-6} = 0b00; // imm2
862 let Inst{5-4} = 0b00; // type
865 def rs : T2OneRegCmpShiftedReg<
866 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
867 opc, ".w\t$Rn, $ShiftedRm",
868 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
869 let Inst{31-27} = 0b11101;
870 let Inst{26-25} = 0b01;
871 let Inst{24-21} = opcod;
872 let Inst{20} = 1; // The S bit.
873 let Inst{11-8} = 0b1111; // Rd
877 // Assembler aliases w/o the ".w" suffix.
878 // No alias here for 'rr' version as not all instantiations of this
879 // multiclass want one (CMP in particular, does not).
880 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
881 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
882 t2_so_imm:$imm, pred:$p)>;
883 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
884 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
889 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
890 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
891 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
893 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
894 opc, ".w\t$Rt, $addr",
895 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
898 let Inst{31-25} = 0b1111100;
899 let Inst{24} = signed;
901 let Inst{22-21} = opcod;
902 let Inst{20} = 1; // load
903 let Inst{19-16} = addr{16-13}; // Rn
904 let Inst{15-12} = Rt;
905 let Inst{11-0} = addr{11-0}; // imm
907 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
909 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
912 let Inst{31-27} = 0b11111;
913 let Inst{26-25} = 0b00;
914 let Inst{24} = signed;
916 let Inst{22-21} = opcod;
917 let Inst{20} = 1; // load
918 let Inst{19-16} = addr{12-9}; // Rn
919 let Inst{15-12} = Rt;
921 // Offset: index==TRUE, wback==FALSE
922 let Inst{10} = 1; // The P bit.
923 let Inst{9} = addr{8}; // U
924 let Inst{8} = 0; // The W bit.
925 let Inst{7-0} = addr{7-0}; // imm
927 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
928 opc, ".w\t$Rt, $addr",
929 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
930 let Inst{31-27} = 0b11111;
931 let Inst{26-25} = 0b00;
932 let Inst{24} = signed;
934 let Inst{22-21} = opcod;
935 let Inst{20} = 1; // load
936 let Inst{11-6} = 0b000000;
939 let Inst{15-12} = Rt;
942 let Inst{19-16} = addr{9-6}; // Rn
943 let Inst{3-0} = addr{5-2}; // Rm
944 let Inst{5-4} = addr{1-0}; // imm
946 let DecoderMethod = "DecodeT2LoadShift";
949 // pci variant is very similar to i12, but supports negative offsets
951 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
952 opc, ".w\t$Rt, $addr",
953 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
954 let isReMaterializable = 1;
955 let Inst{31-27} = 0b11111;
956 let Inst{26-25} = 0b00;
957 let Inst{24} = signed;
958 let Inst{23} = ?; // add = (U == '1')
959 let Inst{22-21} = opcod;
960 let Inst{20} = 1; // load
961 let Inst{19-16} = 0b1111; // Rn
964 let Inst{15-12} = Rt{3-0};
965 let Inst{11-0} = addr{11-0};
969 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
970 multiclass T2I_st<bits<2> opcod, string opc,
971 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
973 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
974 opc, ".w\t$Rt, $addr",
975 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
976 let Inst{31-27} = 0b11111;
977 let Inst{26-23} = 0b0001;
978 let Inst{22-21} = opcod;
979 let Inst{20} = 0; // !load
982 let Inst{15-12} = Rt;
985 let addr{12} = 1; // add = TRUE
986 let Inst{19-16} = addr{16-13}; // Rn
987 let Inst{23} = addr{12}; // U
988 let Inst{11-0} = addr{11-0}; // imm
990 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
992 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
993 let Inst{31-27} = 0b11111;
994 let Inst{26-23} = 0b0000;
995 let Inst{22-21} = opcod;
996 let Inst{20} = 0; // !load
998 // Offset: index==TRUE, wback==FALSE
999 let Inst{10} = 1; // The P bit.
1000 let Inst{8} = 0; // The W bit.
1003 let Inst{15-12} = Rt;
1006 let Inst{19-16} = addr{12-9}; // Rn
1007 let Inst{9} = addr{8}; // U
1008 let Inst{7-0} = addr{7-0}; // imm
1010 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1011 opc, ".w\t$Rt, $addr",
1012 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1013 let Inst{31-27} = 0b11111;
1014 let Inst{26-23} = 0b0000;
1015 let Inst{22-21} = opcod;
1016 let Inst{20} = 0; // !load
1017 let Inst{11-6} = 0b000000;
1020 let Inst{15-12} = Rt;
1023 let Inst{19-16} = addr{9-6}; // Rn
1024 let Inst{3-0} = addr{5-2}; // Rm
1025 let Inst{5-4} = addr{1-0}; // imm
1029 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1030 /// register and one whose operand is a register rotated by 8/16/24.
1031 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1032 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1033 opc, ".w\t$Rd, $Rm$rot",
1034 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1035 Requires<[IsThumb2]> {
1036 let Inst{31-27} = 0b11111;
1037 let Inst{26-23} = 0b0100;
1038 let Inst{22-20} = opcod;
1039 let Inst{19-16} = 0b1111; // Rn
1040 let Inst{15-12} = 0b1111;
1044 let Inst{5-4} = rot{1-0}; // rotate
1047 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1048 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1049 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1050 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1051 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1052 Requires<[HasT2ExtractPack, IsThumb2]> {
1054 let Inst{31-27} = 0b11111;
1055 let Inst{26-23} = 0b0100;
1056 let Inst{22-20} = opcod;
1057 let Inst{19-16} = 0b1111; // Rn
1058 let Inst{15-12} = 0b1111;
1060 let Inst{5-4} = rot;
1063 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1065 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1066 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1067 opc, "\t$Rd, $Rm$rot", []>,
1068 Requires<[IsThumb2, HasT2ExtractPack]> {
1070 let Inst{31-27} = 0b11111;
1071 let Inst{26-23} = 0b0100;
1072 let Inst{22-20} = opcod;
1073 let Inst{19-16} = 0b1111; // Rn
1074 let Inst{15-12} = 0b1111;
1076 let Inst{5-4} = rot;
1079 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1080 /// register and one whose operand is a register rotated by 8/16/24.
1081 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1082 : T2ThreeReg<(outs rGPR:$Rd),
1083 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1084 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1085 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1086 Requires<[HasT2ExtractPack, IsThumb2]> {
1088 let Inst{31-27} = 0b11111;
1089 let Inst{26-23} = 0b0100;
1090 let Inst{22-20} = opcod;
1091 let Inst{15-12} = 0b1111;
1093 let Inst{5-4} = rot;
1096 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1097 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1098 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1100 let Inst{31-27} = 0b11111;
1101 let Inst{26-23} = 0b0100;
1102 let Inst{22-20} = opcod;
1103 let Inst{15-12} = 0b1111;
1105 let Inst{5-4} = rot;
1108 //===----------------------------------------------------------------------===//
1110 //===----------------------------------------------------------------------===//
1112 //===----------------------------------------------------------------------===//
1113 // Miscellaneous Instructions.
1116 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1117 string asm, list<dag> pattern>
1118 : T2XI<oops, iops, itin, asm, pattern> {
1122 let Inst{11-8} = Rd;
1123 let Inst{26} = label{11};
1124 let Inst{14-12} = label{10-8};
1125 let Inst{7-0} = label{7-0};
1128 // LEApcrel - Load a pc-relative address into a register without offending the
1130 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1131 (ins t2adrlabel:$addr, pred:$p),
1132 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1133 let Inst{31-27} = 0b11110;
1134 let Inst{25-24} = 0b10;
1135 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1138 let Inst{19-16} = 0b1111; // Rn
1143 let Inst{11-8} = Rd;
1144 let Inst{23} = addr{12};
1145 let Inst{21} = addr{12};
1146 let Inst{26} = addr{11};
1147 let Inst{14-12} = addr{10-8};
1148 let Inst{7-0} = addr{7-0};
1150 let DecoderMethod = "DecodeT2Adr";
1153 let neverHasSideEffects = 1, isReMaterializable = 1 in
1154 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1156 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1157 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1162 //===----------------------------------------------------------------------===//
1163 // Load / store Instructions.
1167 let canFoldAsLoad = 1, isReMaterializable = 1 in
1168 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1169 UnOpFrag<(load node:$Src)>>;
1171 // Loads with zero extension
1172 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1173 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1174 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1175 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1177 // Loads with sign extension
1178 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1179 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1180 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1181 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1183 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1185 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1186 (ins t2addrmode_imm8s4:$addr),
1187 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1188 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1190 // zextload i1 -> zextload i8
1191 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1192 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1193 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1194 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1195 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1196 (t2LDRBs t2addrmode_so_reg:$addr)>;
1197 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1198 (t2LDRBpci tconstpool:$addr)>;
1200 // extload -> zextload
1201 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1203 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1204 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1205 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1206 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1207 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1208 (t2LDRBs t2addrmode_so_reg:$addr)>;
1209 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1210 (t2LDRBpci tconstpool:$addr)>;
1212 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1213 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1214 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1215 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1216 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1217 (t2LDRBs t2addrmode_so_reg:$addr)>;
1218 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1219 (t2LDRBpci tconstpool:$addr)>;
1221 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1222 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1223 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1224 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1225 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1226 (t2LDRHs t2addrmode_so_reg:$addr)>;
1227 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1228 (t2LDRHpci tconstpool:$addr)>;
1230 // FIXME: The destination register of the loads and stores can't be PC, but
1231 // can be SP. We need another regclass (similar to rGPR) to represent
1232 // that. Not a pressing issue since these are selected manually,
1237 let mayLoad = 1, neverHasSideEffects = 1 in {
1238 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1239 (ins t2addrmode_imm8:$addr),
1240 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1241 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1243 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1246 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1247 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1248 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1249 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1251 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1252 (ins t2addrmode_imm8:$addr),
1253 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1254 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1256 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1258 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1259 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1260 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1261 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1263 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1264 (ins t2addrmode_imm8:$addr),
1265 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1266 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1268 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1270 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1271 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1272 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1273 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1275 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1276 (ins t2addrmode_imm8:$addr),
1277 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1278 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1280 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1282 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1283 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1284 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1285 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1287 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1288 (ins t2addrmode_imm8:$addr),
1289 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1290 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1292 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1294 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1295 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1296 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1297 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1298 } // mayLoad = 1, neverHasSideEffects = 1
1300 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1301 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1302 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1303 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1304 "\t$Rt, $addr", []> {
1307 let Inst{31-27} = 0b11111;
1308 let Inst{26-25} = 0b00;
1309 let Inst{24} = signed;
1311 let Inst{22-21} = type;
1312 let Inst{20} = 1; // load
1313 let Inst{19-16} = addr{12-9};
1314 let Inst{15-12} = Rt;
1316 let Inst{10-8} = 0b110; // PUW.
1317 let Inst{7-0} = addr{7-0};
1320 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1321 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1322 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1323 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1324 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1327 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1328 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1329 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1330 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1331 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1332 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1335 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1336 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1337 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1338 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1342 let mayStore = 1, neverHasSideEffects = 1 in {
1343 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1344 (ins GPRnopc:$Rt, t2addrmode_imm8:$addr),
1345 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1346 "str", "\t$Rt, $addr!",
1347 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1348 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1350 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1351 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1352 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1353 "strh", "\t$Rt, $addr!",
1354 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1355 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1358 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1359 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1360 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1361 "strb", "\t$Rt, $addr!",
1362 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1363 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1365 } // mayStore = 1, neverHasSideEffects = 1
1367 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1368 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1369 t2am_imm8_offset:$offset),
1370 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1371 "str", "\t$Rt, $Rn$offset",
1372 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1373 [(set GPRnopc:$Rn_wb,
1374 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1375 t2am_imm8_offset:$offset))]>;
1377 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1378 (ins rGPR:$Rt, addr_offset_none:$Rn,
1379 t2am_imm8_offset:$offset),
1380 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1381 "strh", "\t$Rt, $Rn$offset",
1382 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1383 [(set GPRnopc:$Rn_wb,
1384 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1385 t2am_imm8_offset:$offset))]>;
1387 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1388 (ins rGPR:$Rt, addr_offset_none:$Rn,
1389 t2am_imm8_offset:$offset),
1390 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1391 "strb", "\t$Rt, $Rn$offset",
1392 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1393 [(set GPRnopc:$Rn_wb,
1394 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1395 t2am_imm8_offset:$offset))]>;
1397 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1398 // put the patterns on the instruction definitions directly as ISel wants
1399 // the address base and offset to be separate operands, not a single
1400 // complex operand like we represent the instructions themselves. The
1401 // pseudos map between the two.
1402 let usesCustomInserter = 1,
1403 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1404 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1405 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1407 [(set GPRnopc:$Rn_wb,
1408 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1409 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1410 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1412 [(set GPRnopc:$Rn_wb,
1413 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1414 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1415 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1417 [(set GPRnopc:$Rn_wb,
1418 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1421 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1423 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1424 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1425 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1426 "\t$Rt, $addr", []> {
1427 let Inst{31-27} = 0b11111;
1428 let Inst{26-25} = 0b00;
1429 let Inst{24} = 0; // not signed
1431 let Inst{22-21} = type;
1432 let Inst{20} = 0; // store
1434 let Inst{10-8} = 0b110; // PUW
1438 let Inst{15-12} = Rt;
1439 let Inst{19-16} = addr{12-9};
1440 let Inst{7-0} = addr{7-0};
1443 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1444 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1445 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1447 // ldrd / strd pre / post variants
1448 // For disassembly only.
1450 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1451 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1452 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1453 let AsmMatchConverter = "cvtT2LdrdPre";
1454 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1457 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1458 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1459 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1460 "$addr.base = $wb", []>;
1462 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1463 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1464 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1465 "$addr.base = $wb", []> {
1466 let AsmMatchConverter = "cvtT2StrdPre";
1467 let DecoderMethod = "DecodeT2STRDPreInstruction";
1470 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1471 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1472 t2am_imm8s4_offset:$imm),
1473 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1474 "$addr.base = $wb", []>;
1476 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1477 // data/instruction access.
1478 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1479 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1480 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1482 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1484 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1485 let Inst{31-25} = 0b1111100;
1486 let Inst{24} = instr;
1488 let Inst{21} = write;
1490 let Inst{15-12} = 0b1111;
1493 let addr{12} = 1; // add = TRUE
1494 let Inst{19-16} = addr{16-13}; // Rn
1495 let Inst{23} = addr{12}; // U
1496 let Inst{11-0} = addr{11-0}; // imm12
1499 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1501 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1502 let Inst{31-25} = 0b1111100;
1503 let Inst{24} = instr;
1504 let Inst{23} = 0; // U = 0
1506 let Inst{21} = write;
1508 let Inst{15-12} = 0b1111;
1509 let Inst{11-8} = 0b1100;
1512 let Inst{19-16} = addr{12-9}; // Rn
1513 let Inst{7-0} = addr{7-0}; // imm8
1516 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1518 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1519 let Inst{31-25} = 0b1111100;
1520 let Inst{24} = instr;
1521 let Inst{23} = 0; // add = TRUE for T1
1523 let Inst{21} = write;
1525 let Inst{15-12} = 0b1111;
1526 let Inst{11-6} = 0000000;
1529 let Inst{19-16} = addr{9-6}; // Rn
1530 let Inst{3-0} = addr{5-2}; // Rm
1531 let Inst{5-4} = addr{1-0}; // imm2
1533 let DecoderMethod = "DecodeT2LoadShift";
1535 // FIXME: We should have a separate 'pci' variant here. As-is we represent
1536 // it via the i12 variant, which it's related to, but that means we can
1537 // represent negative immediates, which aren't legal for anything except
1538 // the 'pci' case (Rn == 15).
1541 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1542 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1543 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1545 //===----------------------------------------------------------------------===//
1546 // Load / store multiple Instructions.
1549 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1550 InstrItinClass itin_upd, bit L_bit> {
1552 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1553 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1557 let Inst{31-27} = 0b11101;
1558 let Inst{26-25} = 0b00;
1559 let Inst{24-23} = 0b01; // Increment After
1561 let Inst{21} = 0; // No writeback
1562 let Inst{20} = L_bit;
1563 let Inst{19-16} = Rn;
1564 let Inst{15-0} = regs;
1567 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1568 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1572 let Inst{31-27} = 0b11101;
1573 let Inst{26-25} = 0b00;
1574 let Inst{24-23} = 0b01; // Increment After
1576 let Inst{21} = 1; // Writeback
1577 let Inst{20} = L_bit;
1578 let Inst{19-16} = Rn;
1579 let Inst{15-0} = regs;
1582 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1583 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1587 let Inst{31-27} = 0b11101;
1588 let Inst{26-25} = 0b00;
1589 let Inst{24-23} = 0b10; // Decrement Before
1591 let Inst{21} = 0; // No writeback
1592 let Inst{20} = L_bit;
1593 let Inst{19-16} = Rn;
1594 let Inst{15-0} = regs;
1597 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1598 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1602 let Inst{31-27} = 0b11101;
1603 let Inst{26-25} = 0b00;
1604 let Inst{24-23} = 0b10; // Decrement Before
1606 let Inst{21} = 1; // Writeback
1607 let Inst{20} = L_bit;
1608 let Inst{19-16} = Rn;
1609 let Inst{15-0} = regs;
1613 let neverHasSideEffects = 1 in {
1615 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1616 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1618 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1619 InstrItinClass itin_upd, bit L_bit> {
1621 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1622 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1626 let Inst{31-27} = 0b11101;
1627 let Inst{26-25} = 0b00;
1628 let Inst{24-23} = 0b01; // Increment After
1630 let Inst{21} = 0; // No writeback
1631 let Inst{20} = L_bit;
1632 let Inst{19-16} = Rn;
1634 let Inst{14} = regs{14};
1636 let Inst{12-0} = regs{12-0};
1639 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1640 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1644 let Inst{31-27} = 0b11101;
1645 let Inst{26-25} = 0b00;
1646 let Inst{24-23} = 0b01; // Increment After
1648 let Inst{21} = 1; // Writeback
1649 let Inst{20} = L_bit;
1650 let Inst{19-16} = Rn;
1652 let Inst{14} = regs{14};
1654 let Inst{12-0} = regs{12-0};
1657 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1658 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1662 let Inst{31-27} = 0b11101;
1663 let Inst{26-25} = 0b00;
1664 let Inst{24-23} = 0b10; // Decrement Before
1666 let Inst{21} = 0; // No writeback
1667 let Inst{20} = L_bit;
1668 let Inst{19-16} = Rn;
1670 let Inst{14} = regs{14};
1672 let Inst{12-0} = regs{12-0};
1675 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1676 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1680 let Inst{31-27} = 0b11101;
1681 let Inst{26-25} = 0b00;
1682 let Inst{24-23} = 0b10; // Decrement Before
1684 let Inst{21} = 1; // Writeback
1685 let Inst{20} = L_bit;
1686 let Inst{19-16} = Rn;
1688 let Inst{14} = regs{14};
1690 let Inst{12-0} = regs{12-0};
1695 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1696 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1698 } // neverHasSideEffects
1701 //===----------------------------------------------------------------------===//
1702 // Move Instructions.
1705 let neverHasSideEffects = 1 in
1706 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1707 "mov", ".w\t$Rd, $Rm", []> {
1708 let Inst{31-27} = 0b11101;
1709 let Inst{26-25} = 0b01;
1710 let Inst{24-21} = 0b0010;
1711 let Inst{19-16} = 0b1111; // Rn
1712 let Inst{14-12} = 0b000;
1713 let Inst{7-4} = 0b0000;
1715 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1716 pred:$p, zero_reg)>;
1717 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1719 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1722 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1723 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1724 AddedComplexity = 1 in
1725 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1726 "mov", ".w\t$Rd, $imm",
1727 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1728 let Inst{31-27} = 0b11110;
1730 let Inst{24-21} = 0b0010;
1731 let Inst{19-16} = 0b1111; // Rn
1735 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1736 // Use aliases to get that to play nice here.
1737 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1739 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1742 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1743 pred:$p, zero_reg)>;
1744 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1745 pred:$p, zero_reg)>;
1747 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1748 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1749 "movw", "\t$Rd, $imm",
1750 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1751 let Inst{31-27} = 0b11110;
1753 let Inst{24-21} = 0b0010;
1754 let Inst{20} = 0; // The S bit.
1760 let Inst{11-8} = Rd;
1761 let Inst{19-16} = imm{15-12};
1762 let Inst{26} = imm{11};
1763 let Inst{14-12} = imm{10-8};
1764 let Inst{7-0} = imm{7-0};
1765 let DecoderMethod = "DecodeT2MOVTWInstruction";
1768 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1769 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1771 let Constraints = "$src = $Rd" in {
1772 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1773 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1774 "movt", "\t$Rd, $imm",
1776 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1777 let Inst{31-27} = 0b11110;
1779 let Inst{24-21} = 0b0110;
1780 let Inst{20} = 0; // The S bit.
1786 let Inst{11-8} = Rd;
1787 let Inst{19-16} = imm{15-12};
1788 let Inst{26} = imm{11};
1789 let Inst{14-12} = imm{10-8};
1790 let Inst{7-0} = imm{7-0};
1791 let DecoderMethod = "DecodeT2MOVTWInstruction";
1794 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1795 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1798 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1800 //===----------------------------------------------------------------------===//
1801 // Extend Instructions.
1806 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1807 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1808 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1809 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1810 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1812 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1813 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1814 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1815 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1816 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1820 let AddedComplexity = 16 in {
1821 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1822 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1823 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1824 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1825 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1826 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1828 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1829 // The transformation should probably be done as a combiner action
1830 // instead so we can include a check for masking back in the upper
1831 // eight bits of the source into the lower eight bits of the result.
1832 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1833 // (t2UXTB16 rGPR:$Src, 3)>,
1834 // Requires<[HasT2ExtractPack, IsThumb2]>;
1835 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1836 (t2UXTB16 rGPR:$Src, 1)>,
1837 Requires<[HasT2ExtractPack, IsThumb2]>;
1839 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1840 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1841 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1842 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1843 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1846 //===----------------------------------------------------------------------===//
1847 // Arithmetic Instructions.
1850 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1851 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1852 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1853 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1855 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1857 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1858 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1859 // AdjustInstrPostInstrSelection where we determine whether or not to
1860 // set the "s" bit based on CPSR liveness.
1862 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1863 // support for an optional CPSR definition that corresponds to the DAG
1864 // node's second value. We can then eliminate the implicit def of CPSR.
1865 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1866 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1867 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1868 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1870 let hasPostISelHook = 1 in {
1871 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1872 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1873 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1874 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1878 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1879 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1881 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1882 // CPSR and the implicit def of CPSR is not needed.
1883 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1885 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1886 // The assume-no-carry-in form uses the negation of the input since add/sub
1887 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1888 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1890 // The AddedComplexity preferences the first variant over the others since
1891 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1892 let AddedComplexity = 1 in
1893 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1894 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1895 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1896 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1897 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1898 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1899 let AddedComplexity = 1 in
1900 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1901 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1902 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1903 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1904 // The with-carry-in form matches bitwise not instead of the negation.
1905 // Effectively, the inverse interpretation of the carry flag already accounts
1906 // for part of the negation.
1907 let AddedComplexity = 1 in
1908 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1909 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1910 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1911 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1913 // Select Bytes -- for disassembly only
1915 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1916 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1917 Requires<[IsThumb2, HasThumb2DSP]> {
1918 let Inst{31-27} = 0b11111;
1919 let Inst{26-24} = 0b010;
1921 let Inst{22-20} = 0b010;
1922 let Inst{15-12} = 0b1111;
1924 let Inst{6-4} = 0b000;
1927 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1928 // And Miscellaneous operations -- for disassembly only
1929 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1930 list<dag> pat = [/* For disassembly only; pattern left blank */],
1931 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1932 string asm = "\t$Rd, $Rn, $Rm">
1933 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1934 Requires<[IsThumb2, HasThumb2DSP]> {
1935 let Inst{31-27} = 0b11111;
1936 let Inst{26-23} = 0b0101;
1937 let Inst{22-20} = op22_20;
1938 let Inst{15-12} = 0b1111;
1939 let Inst{7-4} = op7_4;
1945 let Inst{11-8} = Rd;
1946 let Inst{19-16} = Rn;
1950 // Saturating add/subtract -- for disassembly only
1952 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1953 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1954 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1955 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1956 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1957 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1958 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1959 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1960 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1961 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1962 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1963 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1964 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1965 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1966 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1967 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1968 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1969 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1970 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1971 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1972 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1973 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1975 // Signed/Unsigned add/subtract -- for disassembly only
1977 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1978 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1979 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1980 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1981 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1982 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1983 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1984 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1985 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1986 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1987 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1988 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1990 // Signed/Unsigned halving add/subtract -- for disassembly only
1992 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1993 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1994 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1995 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1996 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1997 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1998 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1999 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2000 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2001 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2002 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2003 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2005 // Helper class for disassembly only
2006 // A6.3.16 & A6.3.17
2007 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2008 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2009 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2010 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2011 let Inst{31-27} = 0b11111;
2012 let Inst{26-24} = 0b011;
2013 let Inst{23} = long;
2014 let Inst{22-20} = op22_20;
2015 let Inst{7-4} = op7_4;
2018 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2019 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2020 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2021 let Inst{31-27} = 0b11111;
2022 let Inst{26-24} = 0b011;
2023 let Inst{23} = long;
2024 let Inst{22-20} = op22_20;
2025 let Inst{7-4} = op7_4;
2028 // Unsigned Sum of Absolute Differences [and Accumulate].
2029 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2030 (ins rGPR:$Rn, rGPR:$Rm),
2031 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2032 Requires<[IsThumb2, HasThumb2DSP]> {
2033 let Inst{15-12} = 0b1111;
2035 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2036 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2037 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2038 Requires<[IsThumb2, HasThumb2DSP]>;
2040 // Signed/Unsigned saturate.
2041 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2042 string opc, string asm, list<dag> pattern>
2043 : T2I<oops, iops, itin, opc, asm, pattern> {
2049 let Inst{11-8} = Rd;
2050 let Inst{19-16} = Rn;
2051 let Inst{4-0} = sat_imm;
2052 let Inst{21} = sh{5};
2053 let Inst{14-12} = sh{4-2};
2054 let Inst{7-6} = sh{1-0};
2059 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2060 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2061 let Inst{31-27} = 0b11110;
2062 let Inst{25-22} = 0b1100;
2068 def t2SSAT16: T2SatI<
2069 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2070 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2071 Requires<[IsThumb2, HasThumb2DSP]> {
2072 let Inst{31-27} = 0b11110;
2073 let Inst{25-22} = 0b1100;
2076 let Inst{21} = 1; // sh = '1'
2077 let Inst{14-12} = 0b000; // imm3 = '000'
2078 let Inst{7-6} = 0b00; // imm2 = '00'
2079 let Inst{5-4} = 0b00;
2084 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2085 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2086 let Inst{31-27} = 0b11110;
2087 let Inst{25-22} = 0b1110;
2092 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2094 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2095 Requires<[IsThumb2, HasThumb2DSP]> {
2096 let Inst{31-22} = 0b1111001110;
2099 let Inst{21} = 1; // sh = '1'
2100 let Inst{14-12} = 0b000; // imm3 = '000'
2101 let Inst{7-6} = 0b00; // imm2 = '00'
2102 let Inst{5-4} = 0b00;
2105 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2106 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2108 //===----------------------------------------------------------------------===//
2109 // Shift and rotate Instructions.
2112 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2113 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2114 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2115 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2116 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2117 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2118 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2119 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2121 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2122 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2123 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2125 let Uses = [CPSR] in {
2126 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2127 "rrx", "\t$Rd, $Rm",
2128 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2129 let Inst{31-27} = 0b11101;
2130 let Inst{26-25} = 0b01;
2131 let Inst{24-21} = 0b0010;
2132 let Inst{19-16} = 0b1111; // Rn
2133 let Inst{14-12} = 0b000;
2134 let Inst{7-4} = 0b0011;
2138 let isCodeGenOnly = 1, Defs = [CPSR] in {
2139 def t2MOVsrl_flag : T2TwoRegShiftImm<
2140 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2141 "lsrs", ".w\t$Rd, $Rm, #1",
2142 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2143 let Inst{31-27} = 0b11101;
2144 let Inst{26-25} = 0b01;
2145 let Inst{24-21} = 0b0010;
2146 let Inst{20} = 1; // The S bit.
2147 let Inst{19-16} = 0b1111; // Rn
2148 let Inst{5-4} = 0b01; // Shift type.
2149 // Shift amount = Inst{14-12:7-6} = 1.
2150 let Inst{14-12} = 0b000;
2151 let Inst{7-6} = 0b01;
2153 def t2MOVsra_flag : T2TwoRegShiftImm<
2154 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2155 "asrs", ".w\t$Rd, $Rm, #1",
2156 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2157 let Inst{31-27} = 0b11101;
2158 let Inst{26-25} = 0b01;
2159 let Inst{24-21} = 0b0010;
2160 let Inst{20} = 1; // The S bit.
2161 let Inst{19-16} = 0b1111; // Rn
2162 let Inst{5-4} = 0b10; // Shift type.
2163 // Shift amount = Inst{14-12:7-6} = 1.
2164 let Inst{14-12} = 0b000;
2165 let Inst{7-6} = 0b01;
2169 //===----------------------------------------------------------------------===//
2170 // Bitwise Instructions.
2173 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2174 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2175 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2176 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2177 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2178 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2179 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2180 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2181 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2183 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2184 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2185 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2188 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2189 string opc, string asm, list<dag> pattern>
2190 : T2I<oops, iops, itin, opc, asm, pattern> {
2195 let Inst{11-8} = Rd;
2196 let Inst{4-0} = msb{4-0};
2197 let Inst{14-12} = lsb{4-2};
2198 let Inst{7-6} = lsb{1-0};
2201 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2202 string opc, string asm, list<dag> pattern>
2203 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2206 let Inst{19-16} = Rn;
2209 let Constraints = "$src = $Rd" in
2210 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2211 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2212 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2213 let Inst{31-27} = 0b11110;
2214 let Inst{26} = 0; // should be 0.
2216 let Inst{24-20} = 0b10110;
2217 let Inst{19-16} = 0b1111; // Rn
2219 let Inst{5} = 0; // should be 0.
2222 let msb{4-0} = imm{9-5};
2223 let lsb{4-0} = imm{4-0};
2226 def t2SBFX: T2TwoRegBitFI<
2227 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2228 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2229 let Inst{31-27} = 0b11110;
2231 let Inst{24-20} = 0b10100;
2235 def t2UBFX: T2TwoRegBitFI<
2236 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2237 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2238 let Inst{31-27} = 0b11110;
2240 let Inst{24-20} = 0b11100;
2244 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2245 let Constraints = "$src = $Rd" in {
2246 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2247 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2248 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2249 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2250 bf_inv_mask_imm:$imm))]> {
2251 let Inst{31-27} = 0b11110;
2252 let Inst{26} = 0; // should be 0.
2254 let Inst{24-20} = 0b10110;
2256 let Inst{5} = 0; // should be 0.
2259 let msb{4-0} = imm{9-5};
2260 let lsb{4-0} = imm{4-0};
2264 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2265 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2266 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2269 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2270 /// unary operation that produces a value. These are predicable and can be
2271 /// changed to modify CPSR.
2272 multiclass T2I_un_irs<bits<4> opcod, string opc,
2273 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2274 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2276 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2278 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2279 let isAsCheapAsAMove = Cheap;
2280 let isReMaterializable = ReMat;
2281 let Inst{31-27} = 0b11110;
2283 let Inst{24-21} = opcod;
2284 let Inst{19-16} = 0b1111; // Rn
2288 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2289 opc, ".w\t$Rd, $Rm",
2290 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2291 let Inst{31-27} = 0b11101;
2292 let Inst{26-25} = 0b01;
2293 let Inst{24-21} = opcod;
2294 let Inst{19-16} = 0b1111; // Rn
2295 let Inst{14-12} = 0b000; // imm3
2296 let Inst{7-6} = 0b00; // imm2
2297 let Inst{5-4} = 0b00; // type
2300 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2301 opc, ".w\t$Rd, $ShiftedRm",
2302 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2303 let Inst{31-27} = 0b11101;
2304 let Inst{26-25} = 0b01;
2305 let Inst{24-21} = opcod;
2306 let Inst{19-16} = 0b1111; // Rn
2310 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2311 let AddedComplexity = 1 in
2312 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2313 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2314 UnOpFrag<(not node:$Src)>, 1, 1>;
2316 let AddedComplexity = 1 in
2317 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2318 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2320 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2321 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2322 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2323 Requires<[IsThumb2]>;
2325 def : T2Pat<(t2_so_imm_not:$src),
2326 (t2MVNi t2_so_imm_not:$src)>;
2328 //===----------------------------------------------------------------------===//
2329 // Multiply Instructions.
2331 let isCommutable = 1 in
2332 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2333 "mul", "\t$Rd, $Rn, $Rm",
2334 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2335 let Inst{31-27} = 0b11111;
2336 let Inst{26-23} = 0b0110;
2337 let Inst{22-20} = 0b000;
2338 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2339 let Inst{7-4} = 0b0000; // Multiply
2342 def t2MLA: T2FourReg<
2343 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2344 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2345 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2346 let Inst{31-27} = 0b11111;
2347 let Inst{26-23} = 0b0110;
2348 let Inst{22-20} = 0b000;
2349 let Inst{7-4} = 0b0000; // Multiply
2352 def t2MLS: T2FourReg<
2353 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2354 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2355 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2356 let Inst{31-27} = 0b11111;
2357 let Inst{26-23} = 0b0110;
2358 let Inst{22-20} = 0b000;
2359 let Inst{7-4} = 0b0001; // Multiply and Subtract
2362 // Extra precision multiplies with low / high results
2363 let neverHasSideEffects = 1 in {
2364 let isCommutable = 1 in {
2365 def t2SMULL : T2MulLong<0b000, 0b0000,
2366 (outs rGPR:$RdLo, rGPR:$RdHi),
2367 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2368 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2370 def t2UMULL : T2MulLong<0b010, 0b0000,
2371 (outs rGPR:$RdLo, rGPR:$RdHi),
2372 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2373 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2376 // Multiply + accumulate
2377 def t2SMLAL : T2MulLong<0b100, 0b0000,
2378 (outs rGPR:$RdLo, rGPR:$RdHi),
2379 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2380 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2382 def t2UMLAL : T2MulLong<0b110, 0b0000,
2383 (outs rGPR:$RdLo, rGPR:$RdHi),
2384 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2385 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2387 def t2UMAAL : T2MulLong<0b110, 0b0110,
2388 (outs rGPR:$RdLo, rGPR:$RdHi),
2389 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2390 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2391 Requires<[IsThumb2, HasThumb2DSP]>;
2392 } // neverHasSideEffects
2394 // Rounding variants of the below included for disassembly only
2396 // Most significant word multiply
2397 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2398 "smmul", "\t$Rd, $Rn, $Rm",
2399 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2400 Requires<[IsThumb2, HasThumb2DSP]> {
2401 let Inst{31-27} = 0b11111;
2402 let Inst{26-23} = 0b0110;
2403 let Inst{22-20} = 0b101;
2404 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2405 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2408 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2409 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2410 Requires<[IsThumb2, HasThumb2DSP]> {
2411 let Inst{31-27} = 0b11111;
2412 let Inst{26-23} = 0b0110;
2413 let Inst{22-20} = 0b101;
2414 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2415 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2418 def t2SMMLA : T2FourReg<
2419 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2420 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2421 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2422 Requires<[IsThumb2, HasThumb2DSP]> {
2423 let Inst{31-27} = 0b11111;
2424 let Inst{26-23} = 0b0110;
2425 let Inst{22-20} = 0b101;
2426 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2429 def t2SMMLAR: T2FourReg<
2430 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2431 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2432 Requires<[IsThumb2, HasThumb2DSP]> {
2433 let Inst{31-27} = 0b11111;
2434 let Inst{26-23} = 0b0110;
2435 let Inst{22-20} = 0b101;
2436 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2439 def t2SMMLS: T2FourReg<
2440 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2441 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2442 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2443 Requires<[IsThumb2, HasThumb2DSP]> {
2444 let Inst{31-27} = 0b11111;
2445 let Inst{26-23} = 0b0110;
2446 let Inst{22-20} = 0b110;
2447 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2450 def t2SMMLSR:T2FourReg<
2451 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2452 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2453 Requires<[IsThumb2, HasThumb2DSP]> {
2454 let Inst{31-27} = 0b11111;
2455 let Inst{26-23} = 0b0110;
2456 let Inst{22-20} = 0b110;
2457 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2460 multiclass T2I_smul<string opc, PatFrag opnode> {
2461 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2462 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2463 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2464 (sext_inreg rGPR:$Rm, i16)))]>,
2465 Requires<[IsThumb2, HasThumb2DSP]> {
2466 let Inst{31-27} = 0b11111;
2467 let Inst{26-23} = 0b0110;
2468 let Inst{22-20} = 0b001;
2469 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2470 let Inst{7-6} = 0b00;
2471 let Inst{5-4} = 0b00;
2474 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2475 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2476 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2477 (sra rGPR:$Rm, (i32 16))))]>,
2478 Requires<[IsThumb2, HasThumb2DSP]> {
2479 let Inst{31-27} = 0b11111;
2480 let Inst{26-23} = 0b0110;
2481 let Inst{22-20} = 0b001;
2482 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2483 let Inst{7-6} = 0b00;
2484 let Inst{5-4} = 0b01;
2487 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2488 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2489 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2490 (sext_inreg rGPR:$Rm, i16)))]>,
2491 Requires<[IsThumb2, HasThumb2DSP]> {
2492 let Inst{31-27} = 0b11111;
2493 let Inst{26-23} = 0b0110;
2494 let Inst{22-20} = 0b001;
2495 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2496 let Inst{7-6} = 0b00;
2497 let Inst{5-4} = 0b10;
2500 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2501 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2502 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2503 (sra rGPR:$Rm, (i32 16))))]>,
2504 Requires<[IsThumb2, HasThumb2DSP]> {
2505 let Inst{31-27} = 0b11111;
2506 let Inst{26-23} = 0b0110;
2507 let Inst{22-20} = 0b001;
2508 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2509 let Inst{7-6} = 0b00;
2510 let Inst{5-4} = 0b11;
2513 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2514 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2515 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2516 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2517 Requires<[IsThumb2, HasThumb2DSP]> {
2518 let Inst{31-27} = 0b11111;
2519 let Inst{26-23} = 0b0110;
2520 let Inst{22-20} = 0b011;
2521 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2522 let Inst{7-6} = 0b00;
2523 let Inst{5-4} = 0b00;
2526 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2527 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2528 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2529 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2530 Requires<[IsThumb2, HasThumb2DSP]> {
2531 let Inst{31-27} = 0b11111;
2532 let Inst{26-23} = 0b0110;
2533 let Inst{22-20} = 0b011;
2534 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2535 let Inst{7-6} = 0b00;
2536 let Inst{5-4} = 0b01;
2541 multiclass T2I_smla<string opc, PatFrag opnode> {
2543 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2544 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2545 [(set rGPR:$Rd, (add rGPR:$Ra,
2546 (opnode (sext_inreg rGPR:$Rn, i16),
2547 (sext_inreg rGPR:$Rm, i16))))]>,
2548 Requires<[IsThumb2, HasThumb2DSP]> {
2549 let Inst{31-27} = 0b11111;
2550 let Inst{26-23} = 0b0110;
2551 let Inst{22-20} = 0b001;
2552 let Inst{7-6} = 0b00;
2553 let Inst{5-4} = 0b00;
2557 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2558 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2559 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2560 (sra rGPR:$Rm, (i32 16)))))]>,
2561 Requires<[IsThumb2, HasThumb2DSP]> {
2562 let Inst{31-27} = 0b11111;
2563 let Inst{26-23} = 0b0110;
2564 let Inst{22-20} = 0b001;
2565 let Inst{7-6} = 0b00;
2566 let Inst{5-4} = 0b01;
2570 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2571 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2572 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2573 (sext_inreg rGPR:$Rm, i16))))]>,
2574 Requires<[IsThumb2, HasThumb2DSP]> {
2575 let Inst{31-27} = 0b11111;
2576 let Inst{26-23} = 0b0110;
2577 let Inst{22-20} = 0b001;
2578 let Inst{7-6} = 0b00;
2579 let Inst{5-4} = 0b10;
2583 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2584 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2585 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2586 (sra rGPR:$Rm, (i32 16)))))]>,
2587 Requires<[IsThumb2, HasThumb2DSP]> {
2588 let Inst{31-27} = 0b11111;
2589 let Inst{26-23} = 0b0110;
2590 let Inst{22-20} = 0b001;
2591 let Inst{7-6} = 0b00;
2592 let Inst{5-4} = 0b11;
2596 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2597 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2598 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2599 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2600 Requires<[IsThumb2, HasThumb2DSP]> {
2601 let Inst{31-27} = 0b11111;
2602 let Inst{26-23} = 0b0110;
2603 let Inst{22-20} = 0b011;
2604 let Inst{7-6} = 0b00;
2605 let Inst{5-4} = 0b00;
2609 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2610 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2611 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2612 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2613 Requires<[IsThumb2, HasThumb2DSP]> {
2614 let Inst{31-27} = 0b11111;
2615 let Inst{26-23} = 0b0110;
2616 let Inst{22-20} = 0b011;
2617 let Inst{7-6} = 0b00;
2618 let Inst{5-4} = 0b01;
2622 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2623 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2625 // Halfword multiple accumulate long: SMLAL<x><y>
2626 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2627 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2628 [/* For disassembly only; pattern left blank */]>,
2629 Requires<[IsThumb2, HasThumb2DSP]>;
2630 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2631 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2632 [/* For disassembly only; pattern left blank */]>,
2633 Requires<[IsThumb2, HasThumb2DSP]>;
2634 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2635 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2636 [/* For disassembly only; pattern left blank */]>,
2637 Requires<[IsThumb2, HasThumb2DSP]>;
2638 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2639 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2640 [/* For disassembly only; pattern left blank */]>,
2641 Requires<[IsThumb2, HasThumb2DSP]>;
2643 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2644 def t2SMUAD: T2ThreeReg_mac<
2645 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2646 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2647 Requires<[IsThumb2, HasThumb2DSP]> {
2648 let Inst{15-12} = 0b1111;
2650 def t2SMUADX:T2ThreeReg_mac<
2651 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2652 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2653 Requires<[IsThumb2, HasThumb2DSP]> {
2654 let Inst{15-12} = 0b1111;
2656 def t2SMUSD: T2ThreeReg_mac<
2657 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2658 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2659 Requires<[IsThumb2, HasThumb2DSP]> {
2660 let Inst{15-12} = 0b1111;
2662 def t2SMUSDX:T2ThreeReg_mac<
2663 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2664 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2665 Requires<[IsThumb2, HasThumb2DSP]> {
2666 let Inst{15-12} = 0b1111;
2668 def t2SMLAD : T2FourReg_mac<
2669 0, 0b010, 0b0000, (outs rGPR:$Rd),
2670 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2671 "\t$Rd, $Rn, $Rm, $Ra", []>,
2672 Requires<[IsThumb2, HasThumb2DSP]>;
2673 def t2SMLADX : T2FourReg_mac<
2674 0, 0b010, 0b0001, (outs rGPR:$Rd),
2675 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2676 "\t$Rd, $Rn, $Rm, $Ra", []>,
2677 Requires<[IsThumb2, HasThumb2DSP]>;
2678 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2679 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2680 "\t$Rd, $Rn, $Rm, $Ra", []>,
2681 Requires<[IsThumb2, HasThumb2DSP]>;
2682 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2683 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2684 "\t$Rd, $Rn, $Rm, $Ra", []>,
2685 Requires<[IsThumb2, HasThumb2DSP]>;
2686 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2687 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2688 "\t$Ra, $Rd, $Rn, $Rm", []>,
2689 Requires<[IsThumb2, HasThumb2DSP]>;
2690 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2691 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2692 "\t$Ra, $Rd, $Rn, $Rm", []>,
2693 Requires<[IsThumb2, HasThumb2DSP]>;
2694 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2695 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2696 "\t$Ra, $Rd, $Rn, $Rm", []>,
2697 Requires<[IsThumb2, HasThumb2DSP]>;
2698 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2699 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2700 "\t$Ra, $Rd, $Rn, $Rm", []>,
2701 Requires<[IsThumb2, HasThumb2DSP]>;
2703 //===----------------------------------------------------------------------===//
2704 // Division Instructions.
2705 // Signed and unsigned division on v7-M
2707 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2708 "sdiv", "\t$Rd, $Rn, $Rm",
2709 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2710 Requires<[HasDivide, IsThumb2]> {
2711 let Inst{31-27} = 0b11111;
2712 let Inst{26-21} = 0b011100;
2714 let Inst{15-12} = 0b1111;
2715 let Inst{7-4} = 0b1111;
2718 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2719 "udiv", "\t$Rd, $Rn, $Rm",
2720 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2721 Requires<[HasDivide, IsThumb2]> {
2722 let Inst{31-27} = 0b11111;
2723 let Inst{26-21} = 0b011101;
2725 let Inst{15-12} = 0b1111;
2726 let Inst{7-4} = 0b1111;
2729 //===----------------------------------------------------------------------===//
2730 // Misc. Arithmetic Instructions.
2733 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2734 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2735 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2736 let Inst{31-27} = 0b11111;
2737 let Inst{26-22} = 0b01010;
2738 let Inst{21-20} = op1;
2739 let Inst{15-12} = 0b1111;
2740 let Inst{7-6} = 0b10;
2741 let Inst{5-4} = op2;
2745 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2746 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2748 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2749 "rbit", "\t$Rd, $Rm",
2750 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2752 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2753 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2755 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2756 "rev16", ".w\t$Rd, $Rm",
2757 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2759 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2760 "revsh", ".w\t$Rd, $Rm",
2761 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2763 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2764 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2765 (t2REVSH rGPR:$Rm)>;
2767 def t2PKHBT : T2ThreeReg<
2768 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2769 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2770 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2771 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2773 Requires<[HasT2ExtractPack, IsThumb2]> {
2774 let Inst{31-27} = 0b11101;
2775 let Inst{26-25} = 0b01;
2776 let Inst{24-20} = 0b01100;
2777 let Inst{5} = 0; // BT form
2781 let Inst{14-12} = sh{4-2};
2782 let Inst{7-6} = sh{1-0};
2785 // Alternate cases for PKHBT where identities eliminate some nodes.
2786 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2787 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2788 Requires<[HasT2ExtractPack, IsThumb2]>;
2789 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2790 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2791 Requires<[HasT2ExtractPack, IsThumb2]>;
2793 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2794 // will match the pattern below.
2795 def t2PKHTB : T2ThreeReg<
2796 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2797 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2798 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2799 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2801 Requires<[HasT2ExtractPack, IsThumb2]> {
2802 let Inst{31-27} = 0b11101;
2803 let Inst{26-25} = 0b01;
2804 let Inst{24-20} = 0b01100;
2805 let Inst{5} = 1; // TB form
2809 let Inst{14-12} = sh{4-2};
2810 let Inst{7-6} = sh{1-0};
2813 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2814 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2815 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2816 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2817 Requires<[HasT2ExtractPack, IsThumb2]>;
2818 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2819 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2820 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2821 Requires<[HasT2ExtractPack, IsThumb2]>;
2823 //===----------------------------------------------------------------------===//
2824 // Comparison Instructions...
2826 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2827 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2828 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2830 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2831 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2832 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2833 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2834 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2835 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2837 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2838 // Compare-to-zero still works out, just not the relationals
2839 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2840 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2841 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2842 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2843 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2846 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2847 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2849 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2850 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2852 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2853 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2854 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2856 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2857 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2858 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2861 // Conditional moves
2862 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2863 // a two-value operand where a dag node expects two operands. :(
2864 let neverHasSideEffects = 1 in {
2865 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2866 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2868 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2869 RegConstraint<"$false = $Rd">;
2871 let isMoveImm = 1 in
2872 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2873 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2875 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2876 RegConstraint<"$false = $Rd">;
2878 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2879 let isCodeGenOnly = 1 in {
2880 let isMoveImm = 1 in
2881 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2883 "movw", "\t$Rd, $imm", []>,
2884 RegConstraint<"$false = $Rd"> {
2885 let Inst{31-27} = 0b11110;
2887 let Inst{24-21} = 0b0010;
2888 let Inst{20} = 0; // The S bit.
2894 let Inst{11-8} = Rd;
2895 let Inst{19-16} = imm{15-12};
2896 let Inst{26} = imm{11};
2897 let Inst{14-12} = imm{10-8};
2898 let Inst{7-0} = imm{7-0};
2901 let isMoveImm = 1 in
2902 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2903 (ins rGPR:$false, i32imm:$src, pred:$p),
2904 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2906 let isMoveImm = 1 in
2907 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2908 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
2909 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2910 imm:$cc, CCR:$ccr))*/]>,
2911 RegConstraint<"$false = $Rd"> {
2912 let Inst{31-27} = 0b11110;
2914 let Inst{24-21} = 0b0011;
2915 let Inst{20} = 0; // The S bit.
2916 let Inst{19-16} = 0b1111; // Rn
2920 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2921 string opc, string asm, list<dag> pattern>
2922 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2923 let Inst{31-27} = 0b11101;
2924 let Inst{26-25} = 0b01;
2925 let Inst{24-21} = 0b0010;
2926 let Inst{20} = 0; // The S bit.
2927 let Inst{19-16} = 0b1111; // Rn
2928 let Inst{5-4} = opcod; // Shift type.
2930 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2931 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2932 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2933 RegConstraint<"$false = $Rd">;
2934 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2935 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2936 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2937 RegConstraint<"$false = $Rd">;
2938 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2939 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2940 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2941 RegConstraint<"$false = $Rd">;
2942 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2943 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2944 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2945 RegConstraint<"$false = $Rd">;
2946 } // isCodeGenOnly = 1
2947 } // neverHasSideEffects
2949 //===----------------------------------------------------------------------===//
2950 // Atomic operations intrinsics
2953 // memory barriers protect the atomic sequences
2954 let hasSideEffects = 1 in {
2955 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2956 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2957 Requires<[IsThumb, HasDB]> {
2959 let Inst{31-4} = 0xf3bf8f5;
2960 let Inst{3-0} = opt;
2964 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2965 "dsb", "\t$opt", []>,
2966 Requires<[IsThumb, HasDB]> {
2968 let Inst{31-4} = 0xf3bf8f4;
2969 let Inst{3-0} = opt;
2972 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2974 []>, Requires<[IsThumb2, HasDB]> {
2976 let Inst{31-4} = 0xf3bf8f6;
2977 let Inst{3-0} = opt;
2980 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2981 InstrItinClass itin, string opc, string asm, string cstr,
2982 list<dag> pattern, bits<4> rt2 = 0b1111>
2983 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2984 let Inst{31-27} = 0b11101;
2985 let Inst{26-20} = 0b0001101;
2986 let Inst{11-8} = rt2;
2987 let Inst{7-6} = 0b01;
2988 let Inst{5-4} = opcod;
2989 let Inst{3-0} = 0b1111;
2993 let Inst{19-16} = addr;
2994 let Inst{15-12} = Rt;
2996 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2997 InstrItinClass itin, string opc, string asm, string cstr,
2998 list<dag> pattern, bits<4> rt2 = 0b1111>
2999 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3000 let Inst{31-27} = 0b11101;
3001 let Inst{26-20} = 0b0001100;
3002 let Inst{11-8} = rt2;
3003 let Inst{7-6} = 0b01;
3004 let Inst{5-4} = opcod;
3010 let Inst{19-16} = addr;
3011 let Inst{15-12} = Rt;
3014 let mayLoad = 1 in {
3015 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3016 AddrModeNone, 4, NoItinerary,
3017 "ldrexb", "\t$Rt, $addr", "", []>;
3018 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3019 AddrModeNone, 4, NoItinerary,
3020 "ldrexh", "\t$Rt, $addr", "", []>;
3021 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3022 AddrModeNone, 4, NoItinerary,
3023 "ldrex", "\t$Rt, $addr", "", []> {
3026 let Inst{31-27} = 0b11101;
3027 let Inst{26-20} = 0b0000101;
3028 let Inst{19-16} = addr{11-8};
3029 let Inst{15-12} = Rt;
3030 let Inst{11-8} = 0b1111;
3031 let Inst{7-0} = addr{7-0};
3033 let hasExtraDefRegAllocReq = 1 in
3034 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3035 (ins addr_offset_none:$addr),
3036 AddrModeNone, 4, NoItinerary,
3037 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3040 let Inst{11-8} = Rt2;
3044 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3045 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3046 (ins rGPR:$Rt, addr_offset_none:$addr),
3047 AddrModeNone, 4, NoItinerary,
3048 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3049 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3050 (ins rGPR:$Rt, addr_offset_none:$addr),
3051 AddrModeNone, 4, NoItinerary,
3052 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3053 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3054 t2addrmode_imm0_1020s4:$addr),
3055 AddrModeNone, 4, NoItinerary,
3056 "strex", "\t$Rd, $Rt, $addr", "",
3061 let Inst{31-27} = 0b11101;
3062 let Inst{26-20} = 0b0000100;
3063 let Inst{19-16} = addr{11-8};
3064 let Inst{15-12} = Rt;
3065 let Inst{11-8} = Rd;
3066 let Inst{7-0} = addr{7-0};
3068 let hasExtraSrcRegAllocReq = 1 in
3069 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3070 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3071 AddrModeNone, 4, NoItinerary,
3072 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3075 let Inst{11-8} = Rt2;
3079 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3080 Requires<[IsThumb2, HasV7]> {
3081 let Inst{31-16} = 0xf3bf;
3082 let Inst{15-14} = 0b10;
3085 let Inst{11-8} = 0b1111;
3086 let Inst{7-4} = 0b0010;
3087 let Inst{3-0} = 0b1111;
3090 //===----------------------------------------------------------------------===//
3091 // SJLJ Exception handling intrinsics
3092 // eh_sjlj_setjmp() is an instruction sequence to store the return
3093 // address and save #0 in R0 for the non-longjmp case.
3094 // Since by its nature we may be coming from some other function to get
3095 // here, and we're using the stack frame for the containing function to
3096 // save/restore registers, we can't keep anything live in regs across
3097 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3098 // when we get here from a longjmp(). We force everything out of registers
3099 // except for our own input by listing the relevant registers in Defs. By
3100 // doing so, we also cause the prologue/epilogue code to actively preserve
3101 // all of the callee-saved resgisters, which is exactly what we want.
3102 // $val is a scratch register for our use.
3104 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3105 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3106 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3107 usesCustomInserter = 1 in {
3108 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3109 AddrModeNone, 0, NoItinerary, "", "",
3110 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3111 Requires<[IsThumb2, HasVFP2]>;
3115 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3116 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3117 usesCustomInserter = 1 in {
3118 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3119 AddrModeNone, 0, NoItinerary, "", "",
3120 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3121 Requires<[IsThumb2, NoVFP]>;
3125 //===----------------------------------------------------------------------===//
3126 // Control-Flow Instructions
3129 // FIXME: remove when we have a way to marking a MI with these properties.
3130 // FIXME: Should pc be an implicit operand like PICADD, etc?
3131 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3132 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3133 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3134 reglist:$regs, variable_ops),
3135 4, IIC_iLoad_mBr, [],
3136 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3137 RegConstraint<"$Rn = $wb">;
3139 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3140 let isPredicable = 1 in
3141 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3143 [(br bb:$target)]> {
3144 let Inst{31-27} = 0b11110;
3145 let Inst{15-14} = 0b10;
3149 let Inst{26} = target{19};
3150 let Inst{11} = target{18};
3151 let Inst{13} = target{17};
3152 let Inst{21-16} = target{16-11};
3153 let Inst{10-0} = target{10-0};
3156 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3157 def t2BR_JT : t2PseudoInst<(outs),
3158 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3160 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3162 // FIXME: Add a non-pc based case that can be predicated.
3163 def t2TBB_JT : t2PseudoInst<(outs),
3164 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3166 def t2TBH_JT : t2PseudoInst<(outs),
3167 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3169 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3170 "tbb", "\t$addr", []> {
3173 let Inst{31-20} = 0b111010001101;
3174 let Inst{19-16} = Rn;
3175 let Inst{15-5} = 0b11110000000;
3176 let Inst{4} = 0; // B form
3179 let DecoderMethod = "DecodeThumbTableBranch";
3182 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3183 "tbh", "\t$addr", []> {
3186 let Inst{31-20} = 0b111010001101;
3187 let Inst{19-16} = Rn;
3188 let Inst{15-5} = 0b11110000000;
3189 let Inst{4} = 1; // H form
3192 let DecoderMethod = "DecodeThumbTableBranch";
3194 } // isNotDuplicable, isIndirectBranch
3196 } // isBranch, isTerminator, isBarrier
3198 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3199 // a two-value operand where a dag node expects ", "two operands. :(
3200 let isBranch = 1, isTerminator = 1 in
3201 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3203 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3204 let Inst{31-27} = 0b11110;
3205 let Inst{15-14} = 0b10;
3209 let Inst{25-22} = p;
3212 let Inst{26} = target{20};
3213 let Inst{11} = target{19};
3214 let Inst{13} = target{18};
3215 let Inst{21-16} = target{17-12};
3216 let Inst{10-0} = target{11-1};
3218 let DecoderMethod = "DecodeThumb2BCCInstruction";
3221 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3223 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3225 let Defs = [R0, R1, R2, R3, R9, R12, PC,
3226 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3228 def tTAILJMPd: tPseudoExpand<(outs),
3229 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3231 (t2B uncondbrtarget:$dst, pred:$p)>,
3232 Requires<[IsThumb2, IsIOS]>;
3236 let Defs = [ITSTATE] in
3237 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3238 AddrModeNone, 2, IIC_iALUx,
3239 "it$mask\t$cc", "", []> {
3240 // 16-bit instruction.
3241 let Inst{31-16} = 0x0000;
3242 let Inst{15-8} = 0b10111111;
3247 let Inst{3-0} = mask;
3249 let DecoderMethod = "DecodeIT";
3252 // Branch and Exchange Jazelle -- for disassembly only
3254 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3256 let Inst{31-27} = 0b11110;
3258 let Inst{25-20} = 0b111100;
3259 let Inst{19-16} = func;
3260 let Inst{15-0} = 0b1000111100000000;
3263 // Compare and branch on zero / non-zero
3264 let isBranch = 1, isTerminator = 1 in {
3265 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3266 "cbz\t$Rn, $target", []>,
3267 T1Misc<{0,0,?,1,?,?,?}>,
3268 Requires<[IsThumb2]> {
3272 let Inst{9} = target{5};
3273 let Inst{7-3} = target{4-0};
3277 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3278 "cbnz\t$Rn, $target", []>,
3279 T1Misc<{1,0,?,1,?,?,?}>,
3280 Requires<[IsThumb2]> {
3284 let Inst{9} = target{5};
3285 let Inst{7-3} = target{4-0};
3291 // Change Processor State is a system instruction.
3292 // FIXME: Since the asm parser has currently no clean way to handle optional
3293 // operands, create 3 versions of the same instruction. Once there's a clean
3294 // framework to represent optional operands, change this behavior.
3295 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3296 !strconcat("cps", asm_op), []> {
3302 let Inst{31-27} = 0b11110;
3304 let Inst{25-20} = 0b111010;
3305 let Inst{19-16} = 0b1111;
3306 let Inst{15-14} = 0b10;
3308 let Inst{10-9} = imod;
3310 let Inst{7-5} = iflags;
3311 let Inst{4-0} = mode;
3312 let DecoderMethod = "DecodeT2CPSInstruction";
3316 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3317 "$imod.w\t$iflags, $mode">;
3318 let mode = 0, M = 0 in
3319 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3320 "$imod.w\t$iflags">;
3321 let imod = 0, iflags = 0, M = 1 in
3322 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3324 // A6.3.4 Branches and miscellaneous control
3325 // Table A6-14 Change Processor State, and hint instructions
3326 class T2I_hint<bits<8> op7_0, string opc, string asm>
3327 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3328 let Inst{31-20} = 0xf3a;
3329 let Inst{19-16} = 0b1111;
3330 let Inst{15-14} = 0b10;
3332 let Inst{10-8} = 0b000;
3333 let Inst{7-0} = op7_0;
3336 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3337 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3338 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3339 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3340 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3342 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3344 let Inst{31-20} = 0b111100111010;
3345 let Inst{19-16} = 0b1111;
3346 let Inst{15-8} = 0b10000000;
3347 let Inst{7-4} = 0b1111;
3348 let Inst{3-0} = opt;
3351 // Secure Monitor Call is a system instruction.
3352 // Option = Inst{19-16}
3353 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3354 let Inst{31-27} = 0b11110;
3355 let Inst{26-20} = 0b1111111;
3356 let Inst{15-12} = 0b1000;
3359 let Inst{19-16} = opt;
3362 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3363 string opc, string asm, list<dag> pattern>
3364 : T2I<oops, iops, itin, opc, asm, pattern> {
3366 let Inst{31-25} = 0b1110100;
3367 let Inst{24-23} = Op;
3370 let Inst{20-16} = 0b01101;
3371 let Inst{15-5} = 0b11000000000;
3372 let Inst{4-0} = mode{4-0};
3375 // Store Return State is a system instruction.
3376 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3377 "srsdb", "\tsp!, $mode", []>;
3378 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3379 "srsdb","\tsp, $mode", []>;
3380 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3381 "srsia","\tsp!, $mode", []>;
3382 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3383 "srsia","\tsp, $mode", []>;
3385 // Return From Exception is a system instruction.
3386 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3387 string opc, string asm, list<dag> pattern>
3388 : T2I<oops, iops, itin, opc, asm, pattern> {
3389 let Inst{31-20} = op31_20{11-0};
3392 let Inst{19-16} = Rn;
3393 let Inst{15-0} = 0xc000;
3396 def t2RFEDBW : T2RFE<0b111010000011,
3397 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3398 [/* For disassembly only; pattern left blank */]>;
3399 def t2RFEDB : T2RFE<0b111010000001,
3400 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3401 [/* For disassembly only; pattern left blank */]>;
3402 def t2RFEIAW : T2RFE<0b111010011011,
3403 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3404 [/* For disassembly only; pattern left blank */]>;
3405 def t2RFEIA : T2RFE<0b111010011001,
3406 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3407 [/* For disassembly only; pattern left blank */]>;
3409 //===----------------------------------------------------------------------===//
3410 // Non-Instruction Patterns
3413 // 32-bit immediate using movw + movt.
3414 // This is a single pseudo instruction to make it re-materializable.
3415 // FIXME: Remove this when we can do generalized remat.
3416 let isReMaterializable = 1, isMoveImm = 1 in
3417 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3418 [(set rGPR:$dst, (i32 imm:$src))]>,
3419 Requires<[IsThumb, HasV6T2]>;
3421 // Pseudo instruction that combines movw + movt + add pc (if pic).
3422 // It also makes it possible to rematerialize the instructions.
3423 // FIXME: Remove this when we can do generalized remat and when machine licm
3424 // can properly the instructions.
3425 let isReMaterializable = 1 in {
3426 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3428 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3429 Requires<[IsThumb2, UseMovt]>;
3431 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3433 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3434 Requires<[IsThumb2, UseMovt]>;
3437 // ConstantPool, GlobalAddress, and JumpTable
3438 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3439 Requires<[IsThumb2, DontUseMovt]>;
3440 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3441 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3442 Requires<[IsThumb2, UseMovt]>;
3444 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3445 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3447 // Pseudo instruction that combines ldr from constpool and add pc. This should
3448 // be expanded into two instructions late to allow if-conversion and
3450 let canFoldAsLoad = 1, isReMaterializable = 1 in
3451 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3453 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3455 Requires<[IsThumb2]>;
3457 // Pseudo isntruction that combines movs + predicated rsbmi
3458 // to implement integer ABS
3459 let usesCustomInserter = 1, Defs = [CPSR] in {
3460 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3461 NoItinerary, []>, Requires<[IsThumb2]>;
3464 //===----------------------------------------------------------------------===//
3465 // Coprocessor load/store -- for disassembly only
3467 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3468 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3469 let Inst{31-28} = op31_28;
3470 let Inst{27-25} = 0b110;
3473 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3474 def _OFFSET : T2CI<op31_28,
3475 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3476 asm, "\t$cop, $CRd, $addr"> {
3480 let Inst{24} = 1; // P = 1
3481 let Inst{23} = addr{8};
3482 let Inst{22} = Dbit;
3483 let Inst{21} = 0; // W = 0
3484 let Inst{20} = load;
3485 let Inst{19-16} = addr{12-9};
3486 let Inst{15-12} = CRd;
3487 let Inst{11-8} = cop;
3488 let Inst{7-0} = addr{7-0};
3489 let DecoderMethod = "DecodeCopMemInstruction";
3491 def _PRE : T2CI<op31_28,
3492 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3493 asm, "\t$cop, $CRd, $addr!"> {
3497 let Inst{24} = 1; // P = 1
3498 let Inst{23} = addr{8};
3499 let Inst{22} = Dbit;
3500 let Inst{21} = 1; // W = 1
3501 let Inst{20} = load;
3502 let Inst{19-16} = addr{12-9};
3503 let Inst{15-12} = CRd;
3504 let Inst{11-8} = cop;
3505 let Inst{7-0} = addr{7-0};
3506 let DecoderMethod = "DecodeCopMemInstruction";
3508 def _POST: T2CI<op31_28,
3509 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3510 postidx_imm8s4:$offset),
3511 asm, "\t$cop, $CRd, $addr, $offset"> {
3516 let Inst{24} = 0; // P = 0
3517 let Inst{23} = offset{8};
3518 let Inst{22} = Dbit;
3519 let Inst{21} = 1; // W = 1
3520 let Inst{20} = load;
3521 let Inst{19-16} = addr;
3522 let Inst{15-12} = CRd;
3523 let Inst{11-8} = cop;
3524 let Inst{7-0} = offset{7-0};
3525 let DecoderMethod = "DecodeCopMemInstruction";
3527 def _OPTION : T2CI<op31_28, (outs),
3528 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3529 coproc_option_imm:$option),
3530 asm, "\t$cop, $CRd, $addr, $option"> {
3535 let Inst{24} = 0; // P = 0
3536 let Inst{23} = 1; // U = 1
3537 let Inst{22} = Dbit;
3538 let Inst{21} = 0; // W = 0
3539 let Inst{20} = load;
3540 let Inst{19-16} = addr;
3541 let Inst{15-12} = CRd;
3542 let Inst{11-8} = cop;
3543 let Inst{7-0} = option;
3544 let DecoderMethod = "DecodeCopMemInstruction";
3548 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3549 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3550 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3551 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3552 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3553 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3554 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3555 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3558 //===----------------------------------------------------------------------===//
3559 // Move between special register and ARM core register -- for disassembly only
3561 // Move to ARM core register from Special Register
3565 // A/R class can only move from CPSR or SPSR.
3566 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>,
3567 Requires<[IsThumb2,IsARClass]> {
3569 let Inst{31-12} = 0b11110011111011111000;
3570 let Inst{11-8} = Rd;
3571 let Inst{7-0} = 0b0000;
3574 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3576 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>,
3577 Requires<[IsThumb2,IsARClass]> {
3579 let Inst{31-12} = 0b11110011111111111000;
3580 let Inst{11-8} = Rd;
3581 let Inst{7-0} = 0b0000;
3586 // This MRS has a mask field in bits 7-0 and can take more values than
3587 // the A/R class (a full msr_mask).
3588 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3589 "mrs", "\t$Rd, $mask", []>,
3590 Requires<[IsThumb2,IsMClass]> {
3593 let Inst{31-12} = 0b11110011111011111000;
3594 let Inst{11-8} = Rd;
3595 let Inst{19-16} = 0b1111;
3596 let Inst{7-0} = mask;
3600 // Move from ARM core register to Special Register
3604 // No need to have both system and application versions, the encodings are the
3605 // same and the assembly parser has no way to distinguish between them. The mask
3606 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3607 // the mask with the fields to be accessed in the special register.
3608 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3609 NoItinerary, "msr", "\t$mask, $Rn", []>,
3610 Requires<[IsThumb2,IsARClass]> {
3613 let Inst{31-21} = 0b11110011100;
3614 let Inst{20} = mask{4}; // R Bit
3615 let Inst{19-16} = Rn;
3616 let Inst{15-12} = 0b1000;
3617 let Inst{11-8} = mask{3-0};
3623 // Move from ARM core register to Special Register
3624 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3625 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3626 Requires<[IsThumb2,IsMClass]> {
3629 let Inst{31-21} = 0b11110011100;
3631 let Inst{19-16} = Rn;
3632 let Inst{15-12} = 0b1000;
3633 let Inst{7-0} = SYSm;
3637 //===----------------------------------------------------------------------===//
3638 // Move between coprocessor and ARM core register
3641 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3643 : T2Cop<Op, oops, iops,
3644 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3646 let Inst{27-24} = 0b1110;
3647 let Inst{20} = direction;
3657 let Inst{15-12} = Rt;
3658 let Inst{11-8} = cop;
3659 let Inst{23-21} = opc1;
3660 let Inst{7-5} = opc2;
3661 let Inst{3-0} = CRm;
3662 let Inst{19-16} = CRn;
3665 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3666 list<dag> pattern = []>
3668 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3669 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3670 let Inst{27-24} = 0b1100;
3671 let Inst{23-21} = 0b010;
3672 let Inst{20} = direction;
3680 let Inst{15-12} = Rt;
3681 let Inst{19-16} = Rt2;
3682 let Inst{11-8} = cop;
3683 let Inst{7-4} = opc1;
3684 let Inst{3-0} = CRm;
3687 /* from ARM core register to coprocessor */
3688 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3690 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3691 c_imm:$CRm, imm0_7:$opc2),
3692 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3693 imm:$CRm, imm:$opc2)]>;
3694 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3695 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3696 c_imm:$CRm, imm0_7:$opc2),
3697 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3698 imm:$CRm, imm:$opc2)]>;
3700 /* from coprocessor to ARM core register */
3701 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3702 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3703 c_imm:$CRm, imm0_7:$opc2), []>;
3705 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3706 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3707 c_imm:$CRm, imm0_7:$opc2), []>;
3709 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3710 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3712 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3713 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3716 /* from ARM core register to coprocessor */
3717 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3718 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3720 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3721 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3722 GPR:$Rt2, imm:$CRm)]>;
3723 /* from coprocessor to ARM core register */
3724 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3726 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3728 //===----------------------------------------------------------------------===//
3729 // Other Coprocessor Instructions.
3732 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3733 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3734 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3735 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3736 imm:$CRm, imm:$opc2)]> {
3737 let Inst{27-24} = 0b1110;
3746 let Inst{3-0} = CRm;
3748 let Inst{7-5} = opc2;
3749 let Inst{11-8} = cop;
3750 let Inst{15-12} = CRd;
3751 let Inst{19-16} = CRn;
3752 let Inst{23-20} = opc1;
3755 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3756 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3757 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3758 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3759 imm:$CRm, imm:$opc2)]> {
3760 let Inst{27-24} = 0b1110;
3769 let Inst{3-0} = CRm;
3771 let Inst{7-5} = opc2;
3772 let Inst{11-8} = cop;
3773 let Inst{15-12} = CRd;
3774 let Inst{19-16} = CRn;
3775 let Inst{23-20} = opc1;
3780 //===----------------------------------------------------------------------===//
3781 // Non-Instruction Patterns
3784 // SXT/UXT with no rotate
3785 let AddedComplexity = 16 in {
3786 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3787 Requires<[IsThumb2]>;
3788 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3789 Requires<[IsThumb2]>;
3790 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3791 Requires<[HasT2ExtractPack, IsThumb2]>;
3792 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3793 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3794 Requires<[HasT2ExtractPack, IsThumb2]>;
3795 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3796 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3797 Requires<[HasT2ExtractPack, IsThumb2]>;
3800 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3801 Requires<[IsThumb2]>;
3802 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3803 Requires<[IsThumb2]>;
3804 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3805 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3806 Requires<[HasT2ExtractPack, IsThumb2]>;
3807 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3808 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3809 Requires<[HasT2ExtractPack, IsThumb2]>;
3811 // Atomic load/store patterns
3812 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3813 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3814 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3815 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3816 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3817 (t2LDRBs t2addrmode_so_reg:$addr)>;
3818 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3819 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3820 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3821 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3822 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3823 (t2LDRHs t2addrmode_so_reg:$addr)>;
3824 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3825 (t2LDRi12 t2addrmode_imm12:$addr)>;
3826 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3827 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3828 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3829 (t2LDRs t2addrmode_so_reg:$addr)>;
3830 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3831 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3832 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3833 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3834 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3835 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3836 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3837 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3838 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3839 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3840 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3841 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3842 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3843 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3844 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3845 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3846 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3847 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3850 //===----------------------------------------------------------------------===//
3851 // Assembler aliases
3854 // Aliases for ADC without the ".w" optional width specifier.
3855 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3856 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3857 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3858 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3859 pred:$p, cc_out:$s)>;
3861 // Aliases for SBC without the ".w" optional width specifier.
3862 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3863 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3864 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3865 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3866 pred:$p, cc_out:$s)>;
3868 // Aliases for ADD without the ".w" optional width specifier.
3869 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3870 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3871 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3872 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3873 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3874 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3875 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3876 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3877 pred:$p, cc_out:$s)>;
3878 // ... and with the destination and source register combined.
3879 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
3880 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3881 def : t2InstAlias<"add${p} $Rdn, $imm",
3882 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3883 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
3884 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3885 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
3886 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
3887 pred:$p, cc_out:$s)>;
3889 // Aliases for SUB without the ".w" optional width specifier.
3890 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3891 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3892 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3893 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3894 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3895 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3896 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3897 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3898 pred:$p, cc_out:$s)>;
3899 // ... and with the destination and source register combined.
3900 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
3901 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3902 def : t2InstAlias<"sub${p} $Rdn, $imm",
3903 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3904 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
3905 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3906 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
3907 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
3908 pred:$p, cc_out:$s)>;
3911 // Alias for compares without the ".w" optional width specifier.
3912 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3913 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3914 def : t2InstAlias<"teq${p} $Rn, $Rm",
3915 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3916 def : t2InstAlias<"tst${p} $Rn, $Rm",
3917 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3920 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3921 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3922 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3924 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3926 def : t2InstAlias<"ldr${p} $Rt, $addr",
3927 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3928 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3929 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3930 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3931 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3932 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3933 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3934 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3935 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3937 def : t2InstAlias<"ldr${p} $Rt, $addr",
3938 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3939 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3940 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3941 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3942 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3943 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3944 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3945 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3946 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3948 def : t2InstAlias<"ldr${p} $Rt, $addr",
3949 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3950 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3951 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3952 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3953 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3954 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3955 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3956 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3957 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3959 // Alias for MVN with(out) the ".w" optional width specifier.
3960 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
3961 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3962 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
3963 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
3964 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
3965 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
3967 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
3968 // shift amount is zero (i.e., unspecified).
3969 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
3970 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3971 Requires<[HasT2ExtractPack, IsThumb2]>;
3972 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
3973 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3974 Requires<[HasT2ExtractPack, IsThumb2]>;
3976 // PUSH/POP aliases for STM/LDM
3977 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3978 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3979 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3980 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3982 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
3983 def : t2InstAlias<"stm${p} $Rn, $regs",
3984 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
3985 def : t2InstAlias<"stm${p} $Rn!, $regs",
3986 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
3988 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
3989 def : t2InstAlias<"ldm${p} $Rn, $regs",
3990 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
3991 def : t2InstAlias<"ldm${p} $Rn!, $regs",
3992 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
3994 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
3995 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
3996 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
3997 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
3998 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4000 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4001 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4002 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4003 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4004 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4006 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4007 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4008 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4009 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4012 // Alias for RSB without the ".w" optional width specifier, and with optional
4013 // implied destination register.
4014 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4015 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4016 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4017 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4018 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4019 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4020 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4021 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4024 // SSAT/USAT optional shift operand.
4025 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4026 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4027 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4028 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4030 // STM w/o the .w suffix.
4031 def : t2InstAlias<"stm${p} $Rn, $regs",
4032 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4034 // Alias for STR, STRB, and STRH without the ".w" optional
4036 def : t2InstAlias<"str${p} $Rt, $addr",
4037 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4038 def : t2InstAlias<"strb${p} $Rt, $addr",
4039 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4040 def : t2InstAlias<"strh${p} $Rt, $addr",
4041 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4043 def : t2InstAlias<"str${p} $Rt, $addr",
4044 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4045 def : t2InstAlias<"strb${p} $Rt, $addr",
4046 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4047 def : t2InstAlias<"strh${p} $Rt, $addr",
4048 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4050 // Extend instruction optional rotate operand.
4051 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4052 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4053 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4054 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4055 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4056 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4058 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4059 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4060 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4061 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4062 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4063 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4064 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4065 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4066 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4067 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4069 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4070 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4071 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4072 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4073 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4074 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4075 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4076 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4077 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4078 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4079 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4080 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4082 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4083 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4084 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4085 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4087 // Extend instruction w/o the ".w" optional width specifier.
4088 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4089 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4090 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4091 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4092 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4093 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4095 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4096 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4097 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4098 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4099 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4100 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4103 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4105 def : t2InstAlias<"mov${p} $Rd, $imm",
4106 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4107 def : t2InstAlias<"mvn${p} $Rd, $imm",
4108 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4109 // Same for AND <--> BIC
4110 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4111 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4112 pred:$p, cc_out:$s)>;
4113 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4114 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4115 pred:$p, cc_out:$s)>;
4116 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4117 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4118 pred:$p, cc_out:$s)>;
4119 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4120 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4121 pred:$p, cc_out:$s)>;
4122 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4123 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4124 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4125 pred:$p, cc_out:$s)>;
4126 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4127 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4128 pred:$p, cc_out:$s)>;
4129 // Same for CMP <--> CMN via t2_so_imm_neg
4130 def : t2InstAlias<"cmp${p} $Rd, $imm",
4131 (t2CMNzri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4132 def : t2InstAlias<"cmn${p} $Rd, $imm",
4133 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4136 // Wide 'mul' encoding can be specified with only two operands.
4137 def : t2InstAlias<"mul${p} $Rn, $Rm",
4138 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4140 // "neg" is and alias for "rsb rd, rn, #0"
4141 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4142 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4144 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4145 // these, unfortunately.
4146 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4147 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4148 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4149 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4151 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4152 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4153 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4154 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4156 // ADR w/o the .w suffix
4157 def : t2InstAlias<"adr${p} $Rd, $addr",
4158 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4160 // LDR(literal) w/ alternate [pc, #imm] syntax.
4161 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4162 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4163 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4164 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4165 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4166 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4167 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4168 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4169 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4170 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4171 // Version w/ the .w suffix.
4172 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4173 (t2LDRpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4174 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4175 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4176 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4177 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4178 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4179 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4180 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4181 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4183 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4184 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;