1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
66 // described for so_imm_notSext def below, with sign extension from 16
68 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
69 APInt apIntN = N->getAPIntValue();
70 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
71 return CurDAG->getTargetConstant(~N16bitSignExt, MVT::i32);
74 // t2_so_imm - Match a 32-bit immediate operand, which is an
75 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
76 // immediate splatted into multiple bytes of the word.
77 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
78 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
79 return ARM_AM::getT2SOImmVal(Imm) != -1;
81 let ParserMatchClass = t2_so_imm_asmoperand;
82 let EncoderMethod = "getT2SOImmOpValue";
83 let DecoderMethod = "DecodeT2SOImm";
86 // t2_so_imm_not - Match an immediate that is a complement
88 // Note: this pattern doesn't require an encoder method and such, as it's
89 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
90 // is handled by the destination instructions, which use t2_so_imm.
91 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
92 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
93 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
94 }], t2_so_imm_not_XFORM> {
95 let ParserMatchClass = t2_so_imm_not_asmoperand;
98 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
99 // if the upper 16 bits are zero.
100 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
101 APInt apIntN = N->getAPIntValue();
102 if (!apIntN.isIntN(16)) return false;
103 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
104 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
105 }], t2_so_imm_notSext16_XFORM> {
106 let ParserMatchClass = t2_so_imm_not_asmoperand;
109 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
110 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
111 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
112 int64_t Value = -(int)N->getZExtValue();
113 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
114 }], t2_so_imm_neg_XFORM> {
115 let ParserMatchClass = t2_so_imm_neg_asmoperand;
118 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
119 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
120 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
121 return Imm >= 0 && Imm < 4096;
123 let ParserMatchClass = imm0_4095_asmoperand;
126 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
127 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
128 return (uint32_t)(-N->getZExtValue()) < 4096;
130 let ParserMatchClass = imm0_4095_neg_asmoperand;
133 def imm1_255_neg : PatLeaf<(i32 imm), [{
134 uint32_t Val = -N->getZExtValue();
135 return (Val > 0 && Val < 255);
138 def imm0_255_not : PatLeaf<(i32 imm), [{
139 return (uint32_t)(~N->getZExtValue()) < 255;
142 def lo5AllOne : PatLeaf<(i32 imm), [{
143 // Returns true if all low 5-bits are 1.
144 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
147 // Define Thumb2 specific addressing modes.
149 // t2addrmode_imm12 := reg + imm12
150 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
151 def t2addrmode_imm12 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
153 let PrintMethod = "printAddrModeImm12Operand<false>";
154 let EncoderMethod = "getAddrModeImm12OpValue";
155 let DecoderMethod = "DecodeT2AddrModeImm12";
156 let ParserMatchClass = t2addrmode_imm12_asmoperand;
157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
160 // t2ldrlabel := imm12
161 def t2ldrlabel : Operand<i32> {
162 let EncoderMethod = "getAddrModeImm12OpValue";
163 let PrintMethod = "printThumbLdrLabelOperand";
166 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
167 def t2ldr_pcrel_imm12 : Operand<i32> {
168 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
169 // used for assembler pseudo instruction and maps to t2ldrlabel, so
170 // doesn't need encoder or print methods of its own.
173 // ADR instruction labels.
174 def t2adrlabel : Operand<i32> {
175 let EncoderMethod = "getT2AdrLabelOpValue";
176 let PrintMethod = "printAdrLabelOperand<0>";
179 // t2addrmode_posimm8 := reg + imm8
180 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
181 def t2addrmode_posimm8 : Operand<i32> {
182 let PrintMethod = "printT2AddrModeImm8Operand<false>";
183 let EncoderMethod = "getT2AddrModeImm8OpValue";
184 let DecoderMethod = "DecodeT2AddrModeImm8";
185 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
189 // t2addrmode_negimm8 := reg - imm8
190 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
191 def t2addrmode_negimm8 : Operand<i32>,
192 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
193 let PrintMethod = "printT2AddrModeImm8Operand<false>";
194 let EncoderMethod = "getT2AddrModeImm8OpValue";
195 let DecoderMethod = "DecodeT2AddrModeImm8";
196 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
197 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
200 // t2addrmode_imm8 := reg +/- imm8
201 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
202 class T2AddrMode_Imm8 : Operand<i32>,
203 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
204 let EncoderMethod = "getT2AddrModeImm8OpValue";
205 let DecoderMethod = "DecodeT2AddrModeImm8";
206 let ParserMatchClass = MemImm8OffsetAsmOperand;
207 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
210 def t2addrmode_imm8 : T2AddrMode_Imm8 {
211 let PrintMethod = "printT2AddrModeImm8Operand<false>";
214 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
215 let PrintMethod = "printT2AddrModeImm8Operand<true>";
218 def t2am_imm8_offset : Operand<i32>,
219 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
220 [], [SDNPWantRoot]> {
221 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
222 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
223 let DecoderMethod = "DecodeT2Imm8";
226 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
227 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
228 class T2AddrMode_Imm8s4 : Operand<i32> {
229 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
230 let DecoderMethod = "DecodeT2AddrModeImm8s4";
231 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
232 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
235 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
236 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
239 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
240 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
243 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
244 def t2am_imm8s4_offset : Operand<i32> {
245 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
246 let EncoderMethod = "getT2Imm8s4OpValue";
247 let DecoderMethod = "DecodeT2Imm8S4";
250 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
251 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
252 let Name = "MemImm0_1020s4Offset";
254 def t2addrmode_imm0_1020s4 : Operand<i32>,
255 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
256 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
257 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
258 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
259 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
260 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
263 // t2addrmode_so_reg := reg + (reg << imm2)
264 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
265 def t2addrmode_so_reg : Operand<i32>,
266 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
267 let PrintMethod = "printT2AddrModeSoRegOperand";
268 let EncoderMethod = "getT2AddrModeSORegOpValue";
269 let DecoderMethod = "DecodeT2AddrModeSOReg";
270 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
271 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
274 // Addresses for the TBB/TBH instructions.
275 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
276 def addrmode_tbb : Operand<i32> {
277 let PrintMethod = "printAddrModeTBB";
278 let ParserMatchClass = addrmode_tbb_asmoperand;
279 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
281 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
282 def addrmode_tbh : Operand<i32> {
283 let PrintMethod = "printAddrModeTBH";
284 let ParserMatchClass = addrmode_tbh_asmoperand;
285 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
288 //===----------------------------------------------------------------------===//
289 // Multiclass helpers...
293 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
294 string opc, string asm, list<dag> pattern>
295 : T2I<oops, iops, itin, opc, asm, pattern> {
300 let Inst{26} = imm{11};
301 let Inst{14-12} = imm{10-8};
302 let Inst{7-0} = imm{7-0};
306 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
307 string opc, string asm, list<dag> pattern>
308 : T2sI<oops, iops, itin, opc, asm, pattern> {
314 let Inst{26} = imm{11};
315 let Inst{14-12} = imm{10-8};
316 let Inst{7-0} = imm{7-0};
319 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
320 string opc, string asm, list<dag> pattern>
321 : T2I<oops, iops, itin, opc, asm, pattern> {
325 let Inst{19-16} = Rn;
326 let Inst{26} = imm{11};
327 let Inst{14-12} = imm{10-8};
328 let Inst{7-0} = imm{7-0};
332 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
333 string opc, string asm, list<dag> pattern>
334 : T2I<oops, iops, itin, opc, asm, pattern> {
339 let Inst{3-0} = ShiftedRm{3-0};
340 let Inst{5-4} = ShiftedRm{6-5};
341 let Inst{14-12} = ShiftedRm{11-9};
342 let Inst{7-6} = ShiftedRm{8-7};
345 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
346 string opc, string asm, list<dag> pattern>
347 : T2sI<oops, iops, itin, opc, asm, pattern> {
352 let Inst{3-0} = ShiftedRm{3-0};
353 let Inst{5-4} = ShiftedRm{6-5};
354 let Inst{14-12} = ShiftedRm{11-9};
355 let Inst{7-6} = ShiftedRm{8-7};
358 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
359 string opc, string asm, list<dag> pattern>
360 : T2I<oops, iops, itin, opc, asm, pattern> {
364 let Inst{19-16} = Rn;
365 let Inst{3-0} = ShiftedRm{3-0};
366 let Inst{5-4} = ShiftedRm{6-5};
367 let Inst{14-12} = ShiftedRm{11-9};
368 let Inst{7-6} = ShiftedRm{8-7};
371 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
372 string opc, string asm, list<dag> pattern>
373 : T2I<oops, iops, itin, opc, asm, pattern> {
381 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
382 string opc, string asm, list<dag> pattern>
383 : T2sI<oops, iops, itin, opc, asm, pattern> {
391 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
392 string opc, string asm, list<dag> pattern>
393 : T2I<oops, iops, itin, opc, asm, pattern> {
397 let Inst{19-16} = Rn;
402 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : T2I<oops, iops, itin, opc, asm, pattern> {
410 let Inst{19-16} = Rn;
411 let Inst{26} = imm{11};
412 let Inst{14-12} = imm{10-8};
413 let Inst{7-0} = imm{7-0};
416 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
417 string opc, string asm, list<dag> pattern>
418 : T2sI<oops, iops, itin, opc, asm, pattern> {
424 let Inst{19-16} = Rn;
425 let Inst{26} = imm{11};
426 let Inst{14-12} = imm{10-8};
427 let Inst{7-0} = imm{7-0};
430 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
431 string opc, string asm, list<dag> pattern>
432 : T2I<oops, iops, itin, opc, asm, pattern> {
439 let Inst{14-12} = imm{4-2};
440 let Inst{7-6} = imm{1-0};
443 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
444 string opc, string asm, list<dag> pattern>
445 : T2sI<oops, iops, itin, opc, asm, pattern> {
452 let Inst{14-12} = imm{4-2};
453 let Inst{7-6} = imm{1-0};
456 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
457 string opc, string asm, list<dag> pattern>
458 : T2I<oops, iops, itin, opc, asm, pattern> {
464 let Inst{19-16} = Rn;
468 class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin,
469 string asm, list<dag> pattern>
470 : T2XI<oops, iops, itin, asm, pattern> {
476 let Inst{19-16} = Rn;
480 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
481 string opc, string asm, list<dag> pattern>
482 : T2sI<oops, iops, itin, opc, asm, pattern> {
488 let Inst{19-16} = Rn;
492 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
493 string opc, string asm, list<dag> pattern>
494 : T2I<oops, iops, itin, opc, asm, pattern> {
500 let Inst{19-16} = Rn;
501 let Inst{3-0} = ShiftedRm{3-0};
502 let Inst{5-4} = ShiftedRm{6-5};
503 let Inst{14-12} = ShiftedRm{11-9};
504 let Inst{7-6} = ShiftedRm{8-7};
507 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
508 string opc, string asm, list<dag> pattern>
509 : T2sI<oops, iops, itin, opc, asm, pattern> {
515 let Inst{19-16} = Rn;
516 let Inst{3-0} = ShiftedRm{3-0};
517 let Inst{5-4} = ShiftedRm{6-5};
518 let Inst{14-12} = ShiftedRm{11-9};
519 let Inst{7-6} = ShiftedRm{8-7};
522 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
523 string opc, string asm, list<dag> pattern>
524 : T2I<oops, iops, itin, opc, asm, pattern> {
530 let Inst{19-16} = Rn;
531 let Inst{15-12} = Ra;
536 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
537 dag oops, dag iops, InstrItinClass itin,
538 string opc, string asm, list<dag> pattern>
539 : T2I<oops, iops, itin, opc, asm, pattern> {
545 let Inst{31-23} = 0b111110111;
546 let Inst{22-20} = opc22_20;
547 let Inst{19-16} = Rn;
548 let Inst{15-12} = RdLo;
549 let Inst{11-8} = RdHi;
550 let Inst{7-4} = opc7_4;
553 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
554 dag oops, dag iops, InstrItinClass itin,
555 string opc, string asm, list<dag> pattern>
556 : T2I<oops, iops, itin, opc, asm, pattern> {
562 let Inst{31-23} = 0b111110111;
563 let Inst{22-20} = opc22_20;
564 let Inst{19-16} = Rn;
565 let Inst{15-12} = RdLo;
566 let Inst{11-8} = RdHi;
567 let Inst{7-4} = opc7_4;
572 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
573 /// binary operation that produces a value. These are predicable and can be
574 /// changed to modify CPSR.
575 multiclass T2I_bin_irs<bits<4> opcod, string opc,
576 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
577 PatFrag opnode, bit Commutable = 0,
580 def ri : T2sTwoRegImm<
581 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
582 opc, "\t$Rd, $Rn, $imm",
583 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
584 Sched<[WriteALU, ReadALU]> {
585 let Inst{31-27} = 0b11110;
587 let Inst{24-21} = opcod;
591 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
592 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
593 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
594 Sched<[WriteALU, ReadALU, ReadALU]> {
595 let isCommutable = Commutable;
596 let Inst{31-27} = 0b11101;
597 let Inst{26-25} = 0b01;
598 let Inst{24-21} = opcod;
599 let Inst{14-12} = 0b000; // imm3
600 let Inst{7-6} = 0b00; // imm2
601 let Inst{5-4} = 0b00; // type
604 def rs : T2sTwoRegShiftedReg<
605 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
606 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
607 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
608 Sched<[WriteALUsi, ReadALU]> {
609 let Inst{31-27} = 0b11101;
610 let Inst{26-25} = 0b01;
611 let Inst{24-21} = opcod;
613 // Assembly aliases for optional destination operand when it's the same
614 // as the source operand.
615 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
616 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
617 t2_so_imm:$imm, pred:$p,
619 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
620 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
623 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
624 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
625 t2_so_reg:$shift, pred:$p,
629 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
630 // the ".w" suffix to indicate that they are wide.
631 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
632 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
633 PatFrag opnode, bit Commutable = 0> :
634 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
635 // Assembler aliases w/ the ".w" suffix.
636 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
637 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
639 // Assembler aliases w/o the ".w" suffix.
640 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
641 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
643 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
644 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
645 pred:$p, cc_out:$s)>;
647 // and with the optional destination operand, too.
648 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
649 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
650 pred:$p, cc_out:$s)>;
651 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
652 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
654 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
655 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
656 pred:$p, cc_out:$s)>;
659 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
660 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
661 /// it is equivalent to the T2I_bin_irs counterpart.
662 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
664 def ri : T2sTwoRegImm<
665 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
666 opc, ".w\t$Rd, $Rn, $imm",
667 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
668 Sched<[WriteALU, ReadALU]> {
669 let Inst{31-27} = 0b11110;
671 let Inst{24-21} = opcod;
675 def rr : T2sThreeReg<
676 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
677 opc, "\t$Rd, $Rn, $Rm",
678 [/* For disassembly only; pattern left blank */]>,
679 Sched<[WriteALU, ReadALU, ReadALU]> {
680 let Inst{31-27} = 0b11101;
681 let Inst{26-25} = 0b01;
682 let Inst{24-21} = opcod;
683 let Inst{14-12} = 0b000; // imm3
684 let Inst{7-6} = 0b00; // imm2
685 let Inst{5-4} = 0b00; // type
688 def rs : T2sTwoRegShiftedReg<
689 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
690 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
691 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
692 Sched<[WriteALUsi, ReadALU]> {
693 let Inst{31-27} = 0b11101;
694 let Inst{26-25} = 0b01;
695 let Inst{24-21} = opcod;
699 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
700 /// instruction modifies the CPSR register.
702 /// These opcodes will be converted to the real non-S opcodes by
703 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
704 let hasPostISelHook = 1, Defs = [CPSR] in {
705 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
706 InstrItinClass iis, PatFrag opnode,
707 bit Commutable = 0> {
709 def ri : t2PseudoInst<(outs rGPR:$Rd),
710 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
712 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
714 Sched<[WriteALU, ReadALU]>;
716 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
718 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
720 Sched<[WriteALU, ReadALU, ReadALU]> {
721 let isCommutable = Commutable;
724 def rs : t2PseudoInst<(outs rGPR:$Rd),
725 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
727 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
728 t2_so_reg:$ShiftedRm))]>,
729 Sched<[WriteALUsi, ReadALUsr]>;
733 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
734 /// operands are reversed.
735 let hasPostISelHook = 1, Defs = [CPSR] in {
736 multiclass T2I_rbin_s_is<PatFrag opnode> {
738 def ri : t2PseudoInst<(outs rGPR:$Rd),
739 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
741 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
743 Sched<[WriteALU, ReadALU]>;
745 def rs : t2PseudoInst<(outs rGPR:$Rd),
746 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
748 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
750 Sched<[WriteALUsi, ReadALU]>;
754 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
755 /// patterns for a binary operation that produces a value.
756 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
757 bit Commutable = 0> {
759 // The register-immediate version is re-materializable. This is useful
760 // in particular for taking the address of a local.
761 let isReMaterializable = 1 in {
762 def ri : T2sTwoRegImm<
763 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
764 opc, ".w\t$Rd, $Rn, $imm",
765 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
766 Sched<[WriteALU, ReadALU]> {
767 let Inst{31-27} = 0b11110;
770 let Inst{23-21} = op23_21;
776 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
777 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
778 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
779 Sched<[WriteALU, ReadALU]> {
783 let Inst{31-27} = 0b11110;
784 let Inst{26} = imm{11};
785 let Inst{25-24} = 0b10;
786 let Inst{23-21} = op23_21;
787 let Inst{20} = 0; // The S bit.
788 let Inst{19-16} = Rn;
790 let Inst{14-12} = imm{10-8};
792 let Inst{7-0} = imm{7-0};
795 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
796 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
797 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
798 Sched<[WriteALU, ReadALU, ReadALU]> {
799 let isCommutable = Commutable;
800 let Inst{31-27} = 0b11101;
801 let Inst{26-25} = 0b01;
803 let Inst{23-21} = op23_21;
804 let Inst{14-12} = 0b000; // imm3
805 let Inst{7-6} = 0b00; // imm2
806 let Inst{5-4} = 0b00; // type
809 def rs : T2sTwoRegShiftedReg<
810 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
811 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
812 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
813 Sched<[WriteALUsi, ReadALU]> {
814 let Inst{31-27} = 0b11101;
815 let Inst{26-25} = 0b01;
817 let Inst{23-21} = op23_21;
821 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
822 /// for a binary operation that produces a value and use the carry
823 /// bit. It's not predicable.
824 let Defs = [CPSR], Uses = [CPSR] in {
825 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
826 bit Commutable = 0> {
828 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
829 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
830 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
831 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
832 let Inst{31-27} = 0b11110;
834 let Inst{24-21} = opcod;
838 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
839 opc, ".w\t$Rd, $Rn, $Rm",
840 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
841 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
842 let isCommutable = Commutable;
843 let Inst{31-27} = 0b11101;
844 let Inst{26-25} = 0b01;
845 let Inst{24-21} = opcod;
846 let Inst{14-12} = 0b000; // imm3
847 let Inst{7-6} = 0b00; // imm2
848 let Inst{5-4} = 0b00; // type
851 def rs : T2sTwoRegShiftedReg<
852 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
853 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
854 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
855 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
856 let Inst{31-27} = 0b11101;
857 let Inst{26-25} = 0b01;
858 let Inst{24-21} = opcod;
863 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
864 // rotate operation that produces a value.
865 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
867 def ri : T2sTwoRegShiftImm<
868 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
869 opc, ".w\t$Rd, $Rm, $imm",
870 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
872 let Inst{31-27} = 0b11101;
873 let Inst{26-21} = 0b010010;
874 let Inst{19-16} = 0b1111; // Rn
875 let Inst{5-4} = opcod;
878 def rr : T2sThreeReg<
879 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
880 opc, ".w\t$Rd, $Rn, $Rm",
881 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
883 let Inst{31-27} = 0b11111;
884 let Inst{26-23} = 0b0100;
885 let Inst{22-21} = opcod;
886 let Inst{15-12} = 0b1111;
887 let Inst{7-4} = 0b0000;
890 // Optional destination register
891 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
892 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
894 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
895 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
898 // Assembler aliases w/o the ".w" suffix.
899 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
900 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
902 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
903 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
906 // and with the optional destination operand, too.
907 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
908 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
910 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
911 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
915 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
916 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
917 /// a explicit result, only implicitly set CPSR.
918 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
919 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
921 let isCompare = 1, Defs = [CPSR] in {
923 def ri : T2OneRegCmpImm<
924 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
925 opc, ".w\t$Rn, $imm",
926 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
927 let Inst{31-27} = 0b11110;
929 let Inst{24-21} = opcod;
930 let Inst{20} = 1; // The S bit.
932 let Inst{11-8} = 0b1111; // Rd
935 def rr : T2TwoRegCmp<
936 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
938 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
939 let Inst{31-27} = 0b11101;
940 let Inst{26-25} = 0b01;
941 let Inst{24-21} = opcod;
942 let Inst{20} = 1; // The S bit.
943 let Inst{14-12} = 0b000; // imm3
944 let Inst{11-8} = 0b1111; // Rd
945 let Inst{7-6} = 0b00; // imm2
946 let Inst{5-4} = 0b00; // type
949 def rs : T2OneRegCmpShiftedReg<
950 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
951 opc, ".w\t$Rn, $ShiftedRm",
952 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
953 Sched<[WriteCMPsi]> {
954 let Inst{31-27} = 0b11101;
955 let Inst{26-25} = 0b01;
956 let Inst{24-21} = opcod;
957 let Inst{20} = 1; // The S bit.
958 let Inst{11-8} = 0b1111; // Rd
962 // Assembler aliases w/o the ".w" suffix.
963 // No alias here for 'rr' version as not all instantiations of this
964 // multiclass want one (CMP in particular, does not).
965 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
966 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
967 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
968 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
971 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
972 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
973 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
975 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
976 opc, ".w\t$Rt, $addr",
977 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
980 let Inst{31-25} = 0b1111100;
981 let Inst{24} = signed;
983 let Inst{22-21} = opcod;
984 let Inst{20} = 1; // load
985 let Inst{19-16} = addr{16-13}; // Rn
986 let Inst{15-12} = Rt;
987 let Inst{11-0} = addr{11-0}; // imm
989 let DecoderMethod = "DecodeT2LoadImm12";
991 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
993 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
996 let Inst{31-27} = 0b11111;
997 let Inst{26-25} = 0b00;
998 let Inst{24} = signed;
1000 let Inst{22-21} = opcod;
1001 let Inst{20} = 1; // load
1002 let Inst{19-16} = addr{12-9}; // Rn
1003 let Inst{15-12} = Rt;
1005 // Offset: index==TRUE, wback==FALSE
1006 let Inst{10} = 1; // The P bit.
1007 let Inst{9} = addr{8}; // U
1008 let Inst{8} = 0; // The W bit.
1009 let Inst{7-0} = addr{7-0}; // imm
1011 let DecoderMethod = "DecodeT2LoadImm8";
1013 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1014 opc, ".w\t$Rt, $addr",
1015 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
1016 let Inst{31-27} = 0b11111;
1017 let Inst{26-25} = 0b00;
1018 let Inst{24} = signed;
1020 let Inst{22-21} = opcod;
1021 let Inst{20} = 1; // load
1022 let Inst{11-6} = 0b000000;
1025 let Inst{15-12} = Rt;
1028 let Inst{19-16} = addr{9-6}; // Rn
1029 let Inst{3-0} = addr{5-2}; // Rm
1030 let Inst{5-4} = addr{1-0}; // imm
1032 let DecoderMethod = "DecodeT2LoadShift";
1035 // pci variant is very similar to i12, but supports negative offsets
1037 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1038 opc, ".w\t$Rt, $addr",
1039 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
1040 let isReMaterializable = 1;
1041 let Inst{31-27} = 0b11111;
1042 let Inst{26-25} = 0b00;
1043 let Inst{24} = signed;
1044 let Inst{22-21} = opcod;
1045 let Inst{20} = 1; // load
1046 let Inst{19-16} = 0b1111; // Rn
1049 let Inst{15-12} = Rt{3-0};
1052 let Inst{23} = addr{12}; // add = (U == '1')
1053 let Inst{11-0} = addr{11-0};
1055 let DecoderMethod = "DecodeT2LoadLabel";
1059 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1060 multiclass T2I_st<bits<2> opcod, string opc,
1061 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1063 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1064 opc, ".w\t$Rt, $addr",
1065 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1066 let Inst{31-27} = 0b11111;
1067 let Inst{26-23} = 0b0001;
1068 let Inst{22-21} = opcod;
1069 let Inst{20} = 0; // !load
1072 let Inst{15-12} = Rt;
1075 let addr{12} = 1; // add = TRUE
1076 let Inst{19-16} = addr{16-13}; // Rn
1077 let Inst{23} = addr{12}; // U
1078 let Inst{11-0} = addr{11-0}; // imm
1080 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1081 opc, "\t$Rt, $addr",
1082 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1083 let Inst{31-27} = 0b11111;
1084 let Inst{26-23} = 0b0000;
1085 let Inst{22-21} = opcod;
1086 let Inst{20} = 0; // !load
1088 // Offset: index==TRUE, wback==FALSE
1089 let Inst{10} = 1; // The P bit.
1090 let Inst{8} = 0; // The W bit.
1093 let Inst{15-12} = Rt;
1096 let Inst{19-16} = addr{12-9}; // Rn
1097 let Inst{9} = addr{8}; // U
1098 let Inst{7-0} = addr{7-0}; // imm
1100 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1101 opc, ".w\t$Rt, $addr",
1102 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1103 let Inst{31-27} = 0b11111;
1104 let Inst{26-23} = 0b0000;
1105 let Inst{22-21} = opcod;
1106 let Inst{20} = 0; // !load
1107 let Inst{11-6} = 0b000000;
1110 let Inst{15-12} = Rt;
1113 let Inst{19-16} = addr{9-6}; // Rn
1114 let Inst{3-0} = addr{5-2}; // Rm
1115 let Inst{5-4} = addr{1-0}; // imm
1119 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1120 /// register and one whose operand is a register rotated by 8/16/24.
1121 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1122 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1123 opc, ".w\t$Rd, $Rm$rot",
1124 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1125 Requires<[IsThumb2]> {
1126 let Inst{31-27} = 0b11111;
1127 let Inst{26-23} = 0b0100;
1128 let Inst{22-20} = opcod;
1129 let Inst{19-16} = 0b1111; // Rn
1130 let Inst{15-12} = 0b1111;
1134 let Inst{5-4} = rot{1-0}; // rotate
1137 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1138 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1139 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1140 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1141 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1142 Requires<[HasT2ExtractPack, IsThumb2]> {
1144 let Inst{31-27} = 0b11111;
1145 let Inst{26-23} = 0b0100;
1146 let Inst{22-20} = opcod;
1147 let Inst{19-16} = 0b1111; // Rn
1148 let Inst{15-12} = 0b1111;
1150 let Inst{5-4} = rot;
1153 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1155 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1156 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1157 opc, "\t$Rd, $Rm$rot", []>,
1158 Requires<[IsThumb2, HasT2ExtractPack]> {
1160 let Inst{31-27} = 0b11111;
1161 let Inst{26-23} = 0b0100;
1162 let Inst{22-20} = opcod;
1163 let Inst{19-16} = 0b1111; // Rn
1164 let Inst{15-12} = 0b1111;
1166 let Inst{5-4} = rot;
1169 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1170 /// register and one whose operand is a register rotated by 8/16/24.
1171 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1172 : T2ThreeReg<(outs rGPR:$Rd),
1173 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1174 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1175 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1176 Requires<[HasT2ExtractPack, IsThumb2]> {
1178 let Inst{31-27} = 0b11111;
1179 let Inst{26-23} = 0b0100;
1180 let Inst{22-20} = opcod;
1181 let Inst{15-12} = 0b1111;
1183 let Inst{5-4} = rot;
1186 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1187 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1188 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1190 let Inst{31-27} = 0b11111;
1191 let Inst{26-23} = 0b0100;
1192 let Inst{22-20} = opcod;
1193 let Inst{15-12} = 0b1111;
1195 let Inst{5-4} = rot;
1198 //===----------------------------------------------------------------------===//
1200 //===----------------------------------------------------------------------===//
1202 //===----------------------------------------------------------------------===//
1203 // Miscellaneous Instructions.
1206 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1207 string asm, list<dag> pattern>
1208 : T2XI<oops, iops, itin, asm, pattern> {
1212 let Inst{11-8} = Rd;
1213 let Inst{26} = label{11};
1214 let Inst{14-12} = label{10-8};
1215 let Inst{7-0} = label{7-0};
1218 // LEApcrel - Load a pc-relative address into a register without offending the
1220 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1221 (ins t2adrlabel:$addr, pred:$p),
1222 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1223 Sched<[WriteALU, ReadALU]> {
1224 let Inst{31-27} = 0b11110;
1225 let Inst{25-24} = 0b10;
1226 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1229 let Inst{19-16} = 0b1111; // Rn
1234 let Inst{11-8} = Rd;
1235 let Inst{23} = addr{12};
1236 let Inst{21} = addr{12};
1237 let Inst{26} = addr{11};
1238 let Inst{14-12} = addr{10-8};
1239 let Inst{7-0} = addr{7-0};
1241 let DecoderMethod = "DecodeT2Adr";
1244 let neverHasSideEffects = 1, isReMaterializable = 1 in
1245 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1246 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1247 let hasSideEffects = 1 in
1248 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1249 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1251 []>, Sched<[WriteALU, ReadALU]>;
1254 //===----------------------------------------------------------------------===//
1255 // Load / store Instructions.
1259 let canFoldAsLoad = 1, isReMaterializable = 1 in
1260 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1261 UnOpFrag<(load node:$Src)>>;
1263 // Loads with zero extension
1264 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1265 GPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1266 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1267 GPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1269 // Loads with sign extension
1270 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1271 GPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1272 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1273 GPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1275 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1277 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1278 (ins t2addrmode_imm8s4:$addr),
1279 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1280 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1282 // zextload i1 -> zextload i8
1283 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1284 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1285 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1286 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1287 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1288 (t2LDRBs t2addrmode_so_reg:$addr)>;
1289 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1290 (t2LDRBpci tconstpool:$addr)>;
1292 // extload -> zextload
1293 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1295 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1296 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1297 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1298 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1299 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1300 (t2LDRBs t2addrmode_so_reg:$addr)>;
1301 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1302 (t2LDRBpci tconstpool:$addr)>;
1304 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1305 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1306 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1307 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1308 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1309 (t2LDRBs t2addrmode_so_reg:$addr)>;
1310 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1311 (t2LDRBpci tconstpool:$addr)>;
1313 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1314 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1315 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1316 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1317 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1318 (t2LDRHs t2addrmode_so_reg:$addr)>;
1319 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1320 (t2LDRHpci tconstpool:$addr)>;
1322 // FIXME: The destination register of the loads and stores can't be PC, but
1323 // can be SP. We need another regclass (similar to rGPR) to represent
1324 // that. Not a pressing issue since these are selected manually,
1329 let mayLoad = 1, neverHasSideEffects = 1 in {
1330 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1331 (ins t2addrmode_imm8_pre:$addr),
1332 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1333 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1335 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1336 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1337 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1338 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1340 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1341 (ins t2addrmode_imm8_pre:$addr),
1342 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1343 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1345 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1346 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1347 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1348 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1350 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1351 (ins t2addrmode_imm8_pre:$addr),
1352 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1353 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1355 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1356 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1357 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1358 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1360 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1361 (ins t2addrmode_imm8_pre:$addr),
1362 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1363 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1366 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1367 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1368 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1369 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1371 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1372 (ins t2addrmode_imm8_pre:$addr),
1373 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1374 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1377 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1378 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1379 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1380 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1381 } // mayLoad = 1, neverHasSideEffects = 1
1383 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1384 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1385 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1386 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1387 "\t$Rt, $addr", []> {
1390 let Inst{31-27} = 0b11111;
1391 let Inst{26-25} = 0b00;
1392 let Inst{24} = signed;
1394 let Inst{22-21} = type;
1395 let Inst{20} = 1; // load
1396 let Inst{19-16} = addr{12-9};
1397 let Inst{15-12} = Rt;
1399 let Inst{10-8} = 0b110; // PUW.
1400 let Inst{7-0} = addr{7-0};
1402 let DecoderMethod = "DecodeT2LoadT";
1405 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1406 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1407 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1408 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1409 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1411 class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
1412 string opc, string asm, list<dag> pattern>
1413 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
1414 opc, asm, "", pattern>, Requires<[IsThumb, HasV8]> {
1418 let Inst{31-27} = 0b11101;
1419 let Inst{26-24} = 0b000;
1420 let Inst{23-20} = bits23_20;
1421 let Inst{11-6} = 0b111110;
1422 let Inst{5-4} = bit54;
1423 let Inst{3-0} = 0b1111;
1425 // Encode instruction operands
1426 let Inst{19-16} = addr;
1427 let Inst{15-12} = Rt;
1430 def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
1431 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>;
1432 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1433 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>;
1434 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1435 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>;
1438 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1439 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1440 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1441 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1442 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1443 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1446 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1447 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1448 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1449 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1453 let mayStore = 1, neverHasSideEffects = 1 in {
1454 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1455 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1456 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1457 "str", "\t$Rt, $addr!",
1458 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1460 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1461 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1462 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1463 "strh", "\t$Rt, $addr!",
1464 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1466 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1467 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1468 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1469 "strb", "\t$Rt, $addr!",
1470 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1471 } // mayStore = 1, neverHasSideEffects = 1
1473 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1474 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1475 t2am_imm8_offset:$offset),
1476 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1477 "str", "\t$Rt, $Rn$offset",
1478 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1479 [(set GPRnopc:$Rn_wb,
1480 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1481 t2am_imm8_offset:$offset))]>;
1483 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1484 (ins rGPR:$Rt, addr_offset_none:$Rn,
1485 t2am_imm8_offset:$offset),
1486 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1487 "strh", "\t$Rt, $Rn$offset",
1488 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1489 [(set GPRnopc:$Rn_wb,
1490 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1491 t2am_imm8_offset:$offset))]>;
1493 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1494 (ins rGPR:$Rt, addr_offset_none:$Rn,
1495 t2am_imm8_offset:$offset),
1496 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1497 "strb", "\t$Rt, $Rn$offset",
1498 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1499 [(set GPRnopc:$Rn_wb,
1500 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1501 t2am_imm8_offset:$offset))]>;
1503 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1504 // put the patterns on the instruction definitions directly as ISel wants
1505 // the address base and offset to be separate operands, not a single
1506 // complex operand like we represent the instructions themselves. The
1507 // pseudos map between the two.
1508 let usesCustomInserter = 1,
1509 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1510 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1511 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1513 [(set GPRnopc:$Rn_wb,
1514 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1515 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1516 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1518 [(set GPRnopc:$Rn_wb,
1519 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1520 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1521 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1523 [(set GPRnopc:$Rn_wb,
1524 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1527 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1529 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1530 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1531 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1532 "\t$Rt, $addr", []> {
1533 let Inst{31-27} = 0b11111;
1534 let Inst{26-25} = 0b00;
1535 let Inst{24} = 0; // not signed
1537 let Inst{22-21} = type;
1538 let Inst{20} = 0; // store
1540 let Inst{10-8} = 0b110; // PUW
1544 let Inst{15-12} = Rt;
1545 let Inst{19-16} = addr{12-9};
1546 let Inst{7-0} = addr{7-0};
1549 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1550 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1551 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1553 // ldrd / strd pre / post variants
1554 // For disassembly only.
1556 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1557 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1558 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1559 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1562 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1563 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1564 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1565 "$addr.base = $wb", []>;
1567 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1568 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1569 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1570 "$addr.base = $wb", []> {
1571 let DecoderMethod = "DecodeT2STRDPreInstruction";
1574 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1575 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1576 t2am_imm8s4_offset:$imm),
1577 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1578 "$addr.base = $wb", []>;
1580 class T2Istrrel<bits<2> bit54, dag oops, dag iops,
1581 string opc, string asm, list<dag> pattern>
1582 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
1583 asm, "", pattern>, Requires<[IsThumb, HasV8]> {
1587 let Inst{31-27} = 0b11101;
1588 let Inst{26-20} = 0b0001100;
1589 let Inst{11-6} = 0b111110;
1590 let Inst{5-4} = bit54;
1591 let Inst{3-0} = 0b1111;
1593 // Encode instruction operands
1594 let Inst{19-16} = addr;
1595 let Inst{15-12} = Rt;
1598 def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1599 "stl", "\t$Rt, $addr", []>;
1600 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1601 "stlb", "\t$Rt, $addr", []>;
1602 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1603 "stlh", "\t$Rt, $addr", []>;
1605 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1606 // data/instruction access.
1607 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1608 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1609 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1611 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1613 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1614 Sched<[WritePreLd]> {
1615 let Inst{31-25} = 0b1111100;
1616 let Inst{24} = instr;
1619 let Inst{21} = write;
1621 let Inst{15-12} = 0b1111;
1624 let Inst{19-16} = addr{16-13}; // Rn
1625 let Inst{11-0} = addr{11-0}; // imm12
1627 let DecoderMethod = "DecodeT2LoadImm12";
1630 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1632 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1633 Sched<[WritePreLd]> {
1634 let Inst{31-25} = 0b1111100;
1635 let Inst{24} = instr;
1636 let Inst{23} = 0; // U = 0
1638 let Inst{21} = write;
1640 let Inst{15-12} = 0b1111;
1641 let Inst{11-8} = 0b1100;
1644 let Inst{19-16} = addr{12-9}; // Rn
1645 let Inst{7-0} = addr{7-0}; // imm8
1647 let DecoderMethod = "DecodeT2LoadImm8";
1650 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1652 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1653 Sched<[WritePreLd]> {
1654 let Inst{31-25} = 0b1111100;
1655 let Inst{24} = instr;
1656 let Inst{23} = 0; // add = TRUE for T1
1658 let Inst{21} = write;
1660 let Inst{15-12} = 0b1111;
1661 let Inst{11-6} = 0b000000;
1664 let Inst{19-16} = addr{9-6}; // Rn
1665 let Inst{3-0} = addr{5-2}; // Rm
1666 let Inst{5-4} = addr{1-0}; // imm2
1668 let DecoderMethod = "DecodeT2LoadShift";
1672 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1673 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1674 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1676 // pci variant is very similar to i12, but supports negative offsets
1677 // from the PC. Only PLD and PLI have pci variants (not PLDW)
1678 class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
1679 IIC_Preload, opc, "\t$addr",
1680 [(ARMPreload (ARMWrapper tconstpool:$addr),
1681 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
1682 let Inst{31-25} = 0b1111100;
1683 let Inst{24} = inst;
1684 let Inst{22-20} = 0b001;
1685 let Inst{19-16} = 0b1111;
1686 let Inst{15-12} = 0b1111;
1689 let Inst{23} = addr{12}; // add = (U == '1')
1690 let Inst{11-0} = addr{11-0}; // imm12
1692 let DecoderMethod = "DecodeT2LoadLabel";
1695 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1696 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1698 //===----------------------------------------------------------------------===//
1699 // Load / store multiple Instructions.
1702 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1703 InstrItinClass itin_upd, bit L_bit> {
1705 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1706 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1710 let Inst{31-27} = 0b11101;
1711 let Inst{26-25} = 0b00;
1712 let Inst{24-23} = 0b01; // Increment After
1714 let Inst{21} = 0; // No writeback
1715 let Inst{20} = L_bit;
1716 let Inst{19-16} = Rn;
1717 let Inst{15-0} = regs;
1720 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1721 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1725 let Inst{31-27} = 0b11101;
1726 let Inst{26-25} = 0b00;
1727 let Inst{24-23} = 0b01; // Increment After
1729 let Inst{21} = 1; // Writeback
1730 let Inst{20} = L_bit;
1731 let Inst{19-16} = Rn;
1732 let Inst{15-0} = regs;
1735 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1736 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1740 let Inst{31-27} = 0b11101;
1741 let Inst{26-25} = 0b00;
1742 let Inst{24-23} = 0b10; // Decrement Before
1744 let Inst{21} = 0; // No writeback
1745 let Inst{20} = L_bit;
1746 let Inst{19-16} = Rn;
1747 let Inst{15-0} = regs;
1750 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1751 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1755 let Inst{31-27} = 0b11101;
1756 let Inst{26-25} = 0b00;
1757 let Inst{24-23} = 0b10; // Decrement Before
1759 let Inst{21} = 1; // Writeback
1760 let Inst{20} = L_bit;
1761 let Inst{19-16} = Rn;
1762 let Inst{15-0} = regs;
1766 let neverHasSideEffects = 1 in {
1768 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1769 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1771 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1772 InstrItinClass itin_upd, bit L_bit> {
1774 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1775 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1779 let Inst{31-27} = 0b11101;
1780 let Inst{26-25} = 0b00;
1781 let Inst{24-23} = 0b01; // Increment After
1783 let Inst{21} = 0; // No writeback
1784 let Inst{20} = L_bit;
1785 let Inst{19-16} = Rn;
1787 let Inst{14} = regs{14};
1789 let Inst{12-0} = regs{12-0};
1792 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1793 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1797 let Inst{31-27} = 0b11101;
1798 let Inst{26-25} = 0b00;
1799 let Inst{24-23} = 0b01; // Increment After
1801 let Inst{21} = 1; // Writeback
1802 let Inst{20} = L_bit;
1803 let Inst{19-16} = Rn;
1805 let Inst{14} = regs{14};
1807 let Inst{12-0} = regs{12-0};
1810 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1811 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1815 let Inst{31-27} = 0b11101;
1816 let Inst{26-25} = 0b00;
1817 let Inst{24-23} = 0b10; // Decrement Before
1819 let Inst{21} = 0; // No writeback
1820 let Inst{20} = L_bit;
1821 let Inst{19-16} = Rn;
1823 let Inst{14} = regs{14};
1825 let Inst{12-0} = regs{12-0};
1828 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1829 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1833 let Inst{31-27} = 0b11101;
1834 let Inst{26-25} = 0b00;
1835 let Inst{24-23} = 0b10; // Decrement Before
1837 let Inst{21} = 1; // Writeback
1838 let Inst{20} = L_bit;
1839 let Inst{19-16} = Rn;
1841 let Inst{14} = regs{14};
1843 let Inst{12-0} = regs{12-0};
1848 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1849 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1851 } // neverHasSideEffects
1854 //===----------------------------------------------------------------------===//
1855 // Move Instructions.
1858 let neverHasSideEffects = 1 in
1859 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1860 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1861 let Inst{31-27} = 0b11101;
1862 let Inst{26-25} = 0b01;
1863 let Inst{24-21} = 0b0010;
1864 let Inst{19-16} = 0b1111; // Rn
1865 let Inst{14-12} = 0b000;
1866 let Inst{7-4} = 0b0000;
1868 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1869 pred:$p, zero_reg)>;
1870 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1872 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1875 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1876 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1877 AddedComplexity = 1 in
1878 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1879 "mov", ".w\t$Rd, $imm",
1880 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1881 let Inst{31-27} = 0b11110;
1883 let Inst{24-21} = 0b0010;
1884 let Inst{19-16} = 0b1111; // Rn
1888 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1889 // Use aliases to get that to play nice here.
1890 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1892 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1895 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1896 pred:$p, zero_reg)>;
1897 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1898 pred:$p, zero_reg)>;
1900 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1901 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1902 "movw", "\t$Rd, $imm",
1903 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> {
1904 let Inst{31-27} = 0b11110;
1906 let Inst{24-21} = 0b0010;
1907 let Inst{20} = 0; // The S bit.
1913 let Inst{11-8} = Rd;
1914 let Inst{19-16} = imm{15-12};
1915 let Inst{26} = imm{11};
1916 let Inst{14-12} = imm{10-8};
1917 let Inst{7-0} = imm{7-0};
1918 let DecoderMethod = "DecodeT2MOVTWInstruction";
1921 def : t2InstAlias<"mov${p} $Rd, $imm",
1922 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>;
1924 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1925 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1927 let Constraints = "$src = $Rd" in {
1928 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1929 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1930 "movt", "\t$Rd, $imm",
1932 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1934 let Inst{31-27} = 0b11110;
1936 let Inst{24-21} = 0b0110;
1937 let Inst{20} = 0; // The S bit.
1943 let Inst{11-8} = Rd;
1944 let Inst{19-16} = imm{15-12};
1945 let Inst{26} = imm{11};
1946 let Inst{14-12} = imm{10-8};
1947 let Inst{7-0} = imm{7-0};
1948 let DecoderMethod = "DecodeT2MOVTWInstruction";
1951 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1952 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1956 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1958 //===----------------------------------------------------------------------===//
1959 // Extend Instructions.
1964 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1965 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1966 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1967 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1968 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1970 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1971 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1972 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1973 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1974 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1976 // A simple right-shift can also be used in most cases (the exception is the
1977 // SXTH operations with a rotate of 24: there the non-contiguous bits are
1979 def : Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)),
1980 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
1981 Requires<[HasT2ExtractPack, IsThumb2]>;
1982 def : Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), i16)),
1983 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
1984 Requires<[HasT2ExtractPack, IsThumb2]>;
1988 let AddedComplexity = 16 in {
1989 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1990 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1991 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1992 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1993 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1994 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1996 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1997 // The transformation should probably be done as a combiner action
1998 // instead so we can include a check for masking back in the upper
1999 // eight bits of the source into the lower eight bits of the result.
2000 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
2001 // (t2UXTB16 rGPR:$Src, 3)>,
2002 // Requires<[HasT2ExtractPack, IsThumb2]>;
2003 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
2004 (t2UXTB16 rGPR:$Src, 1)>,
2005 Requires<[HasT2ExtractPack, IsThumb2]>;
2007 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
2008 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2009 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
2010 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2011 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
2013 def : Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)),
2014 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
2015 Requires<[HasT2ExtractPack, IsThumb2]>;
2016 def : Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)),
2017 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
2018 Requires<[HasT2ExtractPack, IsThumb2]>;
2022 //===----------------------------------------------------------------------===//
2023 // Arithmetic Instructions.
2026 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
2027 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2028 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
2029 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2031 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
2033 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
2034 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
2035 // AdjustInstrPostInstrSelection where we determine whether or not to
2036 // set the "s" bit based on CPSR liveness.
2038 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
2039 // support for an optional CPSR definition that corresponds to the DAG
2040 // node's second value. We can then eliminate the implicit def of CPSR.
2041 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
2042 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
2043 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
2044 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
2046 let hasPostISelHook = 1 in {
2047 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
2048 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
2049 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
2050 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
2054 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
2055 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2057 // FIXME: Eliminate them if we can write def : Pat patterns which defines
2058 // CPSR and the implicit def of CPSR is not needed.
2059 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
2061 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2062 // The assume-no-carry-in form uses the negation of the input since add/sub
2063 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2064 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2066 // The AddedComplexity preferences the first variant over the others since
2067 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2068 let AddedComplexity = 1 in
2069 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2070 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2071 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2072 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2073 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2074 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2075 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2076 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2078 let AddedComplexity = 1 in
2079 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2080 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2081 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2082 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2083 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2084 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2085 // The with-carry-in form matches bitwise not instead of the negation.
2086 // Effectively, the inverse interpretation of the carry flag already accounts
2087 // for part of the negation.
2088 let AddedComplexity = 1 in
2089 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2090 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2091 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2092 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2093 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2094 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2096 // Select Bytes -- for disassembly only
2098 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2099 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
2100 Requires<[IsThumb2, HasThumb2DSP]> {
2101 let Inst{31-27} = 0b11111;
2102 let Inst{26-24} = 0b010;
2104 let Inst{22-20} = 0b010;
2105 let Inst{15-12} = 0b1111;
2107 let Inst{6-4} = 0b000;
2110 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2111 // And Miscellaneous operations -- for disassembly only
2112 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2113 list<dag> pat = [/* For disassembly only; pattern left blank */],
2114 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
2115 string asm = "\t$Rd, $Rn, $Rm">
2116 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2117 Requires<[IsThumb2, HasThumb2DSP]> {
2118 let Inst{31-27} = 0b11111;
2119 let Inst{26-23} = 0b0101;
2120 let Inst{22-20} = op22_20;
2121 let Inst{15-12} = 0b1111;
2122 let Inst{7-4} = op7_4;
2128 let Inst{11-8} = Rd;
2129 let Inst{19-16} = Rn;
2133 // Saturating add/subtract -- for disassembly only
2135 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2136 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
2137 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2138 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2139 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2140 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2141 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2142 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2143 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2144 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2145 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2146 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2147 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2148 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2149 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2150 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2151 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2152 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2153 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2154 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2155 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2156 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2158 // Signed/Unsigned add/subtract -- for disassembly only
2160 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2161 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2162 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2163 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2164 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2165 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2166 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2167 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2168 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2169 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2170 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2171 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2173 // Signed/Unsigned halving add/subtract -- for disassembly only
2175 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2176 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2177 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2178 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2179 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2180 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2181 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2182 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2183 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2184 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2185 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2186 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2188 // Helper class for disassembly only
2189 // A6.3.16 & A6.3.17
2190 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2191 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2192 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2193 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2194 let Inst{31-27} = 0b11111;
2195 let Inst{26-24} = 0b011;
2196 let Inst{23} = long;
2197 let Inst{22-20} = op22_20;
2198 let Inst{7-4} = op7_4;
2201 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2202 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2203 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2204 let Inst{31-27} = 0b11111;
2205 let Inst{26-24} = 0b011;
2206 let Inst{23} = long;
2207 let Inst{22-20} = op22_20;
2208 let Inst{7-4} = op7_4;
2211 // Unsigned Sum of Absolute Differences [and Accumulate].
2212 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2213 (ins rGPR:$Rn, rGPR:$Rm),
2214 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2215 Requires<[IsThumb2, HasThumb2DSP]> {
2216 let Inst{15-12} = 0b1111;
2218 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2219 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2220 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2221 Requires<[IsThumb2, HasThumb2DSP]>;
2223 // Signed/Unsigned saturate.
2224 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2225 string opc, string asm, list<dag> pattern>
2226 : T2I<oops, iops, itin, opc, asm, pattern> {
2232 let Inst{11-8} = Rd;
2233 let Inst{19-16} = Rn;
2234 let Inst{4-0} = sat_imm;
2235 let Inst{21} = sh{5};
2236 let Inst{14-12} = sh{4-2};
2237 let Inst{7-6} = sh{1-0};
2242 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2243 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2244 let Inst{31-27} = 0b11110;
2245 let Inst{25-22} = 0b1100;
2251 def t2SSAT16: T2SatI<
2252 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2253 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2254 Requires<[IsThumb2, HasThumb2DSP]> {
2255 let Inst{31-27} = 0b11110;
2256 let Inst{25-22} = 0b1100;
2259 let Inst{21} = 1; // sh = '1'
2260 let Inst{14-12} = 0b000; // imm3 = '000'
2261 let Inst{7-6} = 0b00; // imm2 = '00'
2262 let Inst{5-4} = 0b00;
2267 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2268 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2269 let Inst{31-27} = 0b11110;
2270 let Inst{25-22} = 0b1110;
2275 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2277 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2278 Requires<[IsThumb2, HasThumb2DSP]> {
2279 let Inst{31-22} = 0b1111001110;
2282 let Inst{21} = 1; // sh = '1'
2283 let Inst{14-12} = 0b000; // imm3 = '000'
2284 let Inst{7-6} = 0b00; // imm2 = '00'
2285 let Inst{5-4} = 0b00;
2288 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2289 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2291 //===----------------------------------------------------------------------===//
2292 // Shift and rotate Instructions.
2295 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2296 BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2297 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2298 BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2299 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2300 BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2301 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2302 BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2304 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2305 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2306 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2308 let Uses = [CPSR] in {
2309 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2310 "rrx", "\t$Rd, $Rm",
2311 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2312 let Inst{31-27} = 0b11101;
2313 let Inst{26-25} = 0b01;
2314 let Inst{24-21} = 0b0010;
2315 let Inst{19-16} = 0b1111; // Rn
2316 let Inst{14-12} = 0b000;
2317 let Inst{7-4} = 0b0011;
2321 let isCodeGenOnly = 1, Defs = [CPSR] in {
2322 def t2MOVsrl_flag : T2TwoRegShiftImm<
2323 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2324 "lsrs", ".w\t$Rd, $Rm, #1",
2325 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2327 let Inst{31-27} = 0b11101;
2328 let Inst{26-25} = 0b01;
2329 let Inst{24-21} = 0b0010;
2330 let Inst{20} = 1; // The S bit.
2331 let Inst{19-16} = 0b1111; // Rn
2332 let Inst{5-4} = 0b01; // Shift type.
2333 // Shift amount = Inst{14-12:7-6} = 1.
2334 let Inst{14-12} = 0b000;
2335 let Inst{7-6} = 0b01;
2337 def t2MOVsra_flag : T2TwoRegShiftImm<
2338 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2339 "asrs", ".w\t$Rd, $Rm, #1",
2340 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2342 let Inst{31-27} = 0b11101;
2343 let Inst{26-25} = 0b01;
2344 let Inst{24-21} = 0b0010;
2345 let Inst{20} = 1; // The S bit.
2346 let Inst{19-16} = 0b1111; // Rn
2347 let Inst{5-4} = 0b10; // Shift type.
2348 // Shift amount = Inst{14-12:7-6} = 1.
2349 let Inst{14-12} = 0b000;
2350 let Inst{7-6} = 0b01;
2354 //===----------------------------------------------------------------------===//
2355 // Bitwise Instructions.
2358 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2359 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2360 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2361 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2362 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2363 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2364 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2365 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2366 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2368 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2369 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2370 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2372 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2373 string opc, string asm, list<dag> pattern>
2374 : T2I<oops, iops, itin, opc, asm, pattern> {
2379 let Inst{11-8} = Rd;
2380 let Inst{4-0} = msb{4-0};
2381 let Inst{14-12} = lsb{4-2};
2382 let Inst{7-6} = lsb{1-0};
2385 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2386 string opc, string asm, list<dag> pattern>
2387 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2390 let Inst{19-16} = Rn;
2393 let Constraints = "$src = $Rd" in
2394 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2395 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2396 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2397 let Inst{31-27} = 0b11110;
2398 let Inst{26} = 0; // should be 0.
2400 let Inst{24-20} = 0b10110;
2401 let Inst{19-16} = 0b1111; // Rn
2403 let Inst{5} = 0; // should be 0.
2406 let msb{4-0} = imm{9-5};
2407 let lsb{4-0} = imm{4-0};
2410 def t2SBFX: T2TwoRegBitFI<
2411 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2412 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2413 let Inst{31-27} = 0b11110;
2415 let Inst{24-20} = 0b10100;
2419 def t2UBFX: T2TwoRegBitFI<
2420 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2421 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2422 let Inst{31-27} = 0b11110;
2424 let Inst{24-20} = 0b11100;
2428 // A8.8.247 UDF - Undefined (Encoding T2)
2429 def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
2430 [(int_arm_undefined imm0_65535:$imm16)]> {
2432 let Inst{31-29} = 0b111;
2433 let Inst{28-27} = 0b10;
2434 let Inst{26-20} = 0b1111111;
2435 let Inst{19-16} = imm16{15-12};
2437 let Inst{14-12} = 0b010;
2438 let Inst{11-0} = imm16{11-0};
2441 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2442 let Constraints = "$src = $Rd" in {
2443 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2444 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2445 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2446 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2447 bf_inv_mask_imm:$imm))]> {
2448 let Inst{31-27} = 0b11110;
2449 let Inst{26} = 0; // should be 0.
2451 let Inst{24-20} = 0b10110;
2453 let Inst{5} = 0; // should be 0.
2456 let msb{4-0} = imm{9-5};
2457 let lsb{4-0} = imm{4-0};
2461 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2462 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2463 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2465 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2466 /// unary operation that produces a value. These are predicable and can be
2467 /// changed to modify CPSR.
2468 multiclass T2I_un_irs<bits<4> opcod, string opc,
2469 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2471 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2473 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2475 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2476 let isAsCheapAsAMove = Cheap;
2477 let isReMaterializable = ReMat;
2478 let isMoveImm = MoveImm;
2479 let Inst{31-27} = 0b11110;
2481 let Inst{24-21} = opcod;
2482 let Inst{19-16} = 0b1111; // Rn
2486 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2487 opc, ".w\t$Rd, $Rm",
2488 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2489 let Inst{31-27} = 0b11101;
2490 let Inst{26-25} = 0b01;
2491 let Inst{24-21} = opcod;
2492 let Inst{19-16} = 0b1111; // Rn
2493 let Inst{14-12} = 0b000; // imm3
2494 let Inst{7-6} = 0b00; // imm2
2495 let Inst{5-4} = 0b00; // type
2498 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2499 opc, ".w\t$Rd, $ShiftedRm",
2500 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2502 let Inst{31-27} = 0b11101;
2503 let Inst{26-25} = 0b01;
2504 let Inst{24-21} = opcod;
2505 let Inst{19-16} = 0b1111; // Rn
2509 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2510 let AddedComplexity = 1 in
2511 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2512 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2513 UnOpFrag<(not node:$Src)>, 1, 1, 1>;
2515 let AddedComplexity = 1 in
2516 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2517 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2519 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2520 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2521 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2524 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2525 // will match the extended, not the original bitWidth for $src.
2526 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2527 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2530 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2531 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2532 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2533 Requires<[IsThumb2]>;
2535 def : T2Pat<(t2_so_imm_not:$src),
2536 (t2MVNi t2_so_imm_not:$src)>;
2538 //===----------------------------------------------------------------------===//
2539 // Multiply Instructions.
2541 let isCommutable = 1 in
2542 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2543 "mul", "\t$Rd, $Rn, $Rm",
2544 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2545 let Inst{31-27} = 0b11111;
2546 let Inst{26-23} = 0b0110;
2547 let Inst{22-20} = 0b000;
2548 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2549 let Inst{7-4} = 0b0000; // Multiply
2552 def t2MLA: T2FourReg<
2553 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2554 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2555 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
2556 Requires<[IsThumb2, UseMulOps]> {
2557 let Inst{31-27} = 0b11111;
2558 let Inst{26-23} = 0b0110;
2559 let Inst{22-20} = 0b000;
2560 let Inst{7-4} = 0b0000; // Multiply
2563 def t2MLS: T2FourReg<
2564 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2565 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2566 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
2567 Requires<[IsThumb2, UseMulOps]> {
2568 let Inst{31-27} = 0b11111;
2569 let Inst{26-23} = 0b0110;
2570 let Inst{22-20} = 0b000;
2571 let Inst{7-4} = 0b0001; // Multiply and Subtract
2574 // Extra precision multiplies with low / high results
2575 let neverHasSideEffects = 1 in {
2576 let isCommutable = 1 in {
2577 def t2SMULL : T2MulLong<0b000, 0b0000,
2578 (outs rGPR:$RdLo, rGPR:$RdHi),
2579 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2580 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2582 def t2UMULL : T2MulLong<0b010, 0b0000,
2583 (outs rGPR:$RdLo, rGPR:$RdHi),
2584 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2585 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2588 // Multiply + accumulate
2589 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2590 (outs rGPR:$RdLo, rGPR:$RdHi),
2591 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2592 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2593 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2595 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2596 (outs rGPR:$RdLo, rGPR:$RdHi),
2597 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2598 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2599 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2601 def t2UMAAL : T2MulLong<0b110, 0b0110,
2602 (outs rGPR:$RdLo, rGPR:$RdHi),
2603 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2604 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2605 Requires<[IsThumb2, HasThumb2DSP]>;
2606 } // neverHasSideEffects
2608 // Rounding variants of the below included for disassembly only
2610 // Most significant word multiply
2611 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2612 "smmul", "\t$Rd, $Rn, $Rm",
2613 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2614 Requires<[IsThumb2, HasThumb2DSP]> {
2615 let Inst{31-27} = 0b11111;
2616 let Inst{26-23} = 0b0110;
2617 let Inst{22-20} = 0b101;
2618 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2619 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2622 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2623 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2624 Requires<[IsThumb2, HasThumb2DSP]> {
2625 let Inst{31-27} = 0b11111;
2626 let Inst{26-23} = 0b0110;
2627 let Inst{22-20} = 0b101;
2628 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2629 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2632 def t2SMMLA : T2FourReg<
2633 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2634 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2635 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2636 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2637 let Inst{31-27} = 0b11111;
2638 let Inst{26-23} = 0b0110;
2639 let Inst{22-20} = 0b101;
2640 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2643 def t2SMMLAR: T2FourReg<
2644 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2645 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2646 Requires<[IsThumb2, HasThumb2DSP]> {
2647 let Inst{31-27} = 0b11111;
2648 let Inst{26-23} = 0b0110;
2649 let Inst{22-20} = 0b101;
2650 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2653 def t2SMMLS: T2FourReg<
2654 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2655 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2656 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2657 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2658 let Inst{31-27} = 0b11111;
2659 let Inst{26-23} = 0b0110;
2660 let Inst{22-20} = 0b110;
2661 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2664 def t2SMMLSR:T2FourReg<
2665 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2666 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2667 Requires<[IsThumb2, HasThumb2DSP]> {
2668 let Inst{31-27} = 0b11111;
2669 let Inst{26-23} = 0b0110;
2670 let Inst{22-20} = 0b110;
2671 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2674 multiclass T2I_smul<string opc, PatFrag opnode> {
2675 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2676 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2677 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2678 (sext_inreg rGPR:$Rm, i16)))]>,
2679 Requires<[IsThumb2, HasThumb2DSP]> {
2680 let Inst{31-27} = 0b11111;
2681 let Inst{26-23} = 0b0110;
2682 let Inst{22-20} = 0b001;
2683 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2684 let Inst{7-6} = 0b00;
2685 let Inst{5-4} = 0b00;
2688 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2689 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2690 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2691 (sra rGPR:$Rm, (i32 16))))]>,
2692 Requires<[IsThumb2, HasThumb2DSP]> {
2693 let Inst{31-27} = 0b11111;
2694 let Inst{26-23} = 0b0110;
2695 let Inst{22-20} = 0b001;
2696 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2697 let Inst{7-6} = 0b00;
2698 let Inst{5-4} = 0b01;
2701 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2702 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2703 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2704 (sext_inreg rGPR:$Rm, i16)))]>,
2705 Requires<[IsThumb2, HasThumb2DSP]> {
2706 let Inst{31-27} = 0b11111;
2707 let Inst{26-23} = 0b0110;
2708 let Inst{22-20} = 0b001;
2709 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2710 let Inst{7-6} = 0b00;
2711 let Inst{5-4} = 0b10;
2714 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2715 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2716 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2717 (sra rGPR:$Rm, (i32 16))))]>,
2718 Requires<[IsThumb2, HasThumb2DSP]> {
2719 let Inst{31-27} = 0b11111;
2720 let Inst{26-23} = 0b0110;
2721 let Inst{22-20} = 0b001;
2722 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2723 let Inst{7-6} = 0b00;
2724 let Inst{5-4} = 0b11;
2727 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2728 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2729 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2730 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2731 Requires<[IsThumb2, HasThumb2DSP]> {
2732 let Inst{31-27} = 0b11111;
2733 let Inst{26-23} = 0b0110;
2734 let Inst{22-20} = 0b011;
2735 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2736 let Inst{7-6} = 0b00;
2737 let Inst{5-4} = 0b00;
2740 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2741 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2742 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2743 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2744 Requires<[IsThumb2, HasThumb2DSP]> {
2745 let Inst{31-27} = 0b11111;
2746 let Inst{26-23} = 0b0110;
2747 let Inst{22-20} = 0b011;
2748 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2749 let Inst{7-6} = 0b00;
2750 let Inst{5-4} = 0b01;
2755 multiclass T2I_smla<string opc, PatFrag opnode> {
2757 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2758 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2759 [(set rGPR:$Rd, (add rGPR:$Ra,
2760 (opnode (sext_inreg rGPR:$Rn, i16),
2761 (sext_inreg rGPR:$Rm, i16))))]>,
2762 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2763 let Inst{31-27} = 0b11111;
2764 let Inst{26-23} = 0b0110;
2765 let Inst{22-20} = 0b001;
2766 let Inst{7-6} = 0b00;
2767 let Inst{5-4} = 0b00;
2771 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2772 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2773 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2774 (sra rGPR:$Rm, (i32 16)))))]>,
2775 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2776 let Inst{31-27} = 0b11111;
2777 let Inst{26-23} = 0b0110;
2778 let Inst{22-20} = 0b001;
2779 let Inst{7-6} = 0b00;
2780 let Inst{5-4} = 0b01;
2784 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2785 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2786 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2787 (sext_inreg rGPR:$Rm, i16))))]>,
2788 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2789 let Inst{31-27} = 0b11111;
2790 let Inst{26-23} = 0b0110;
2791 let Inst{22-20} = 0b001;
2792 let Inst{7-6} = 0b00;
2793 let Inst{5-4} = 0b10;
2797 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2798 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2799 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2800 (sra rGPR:$Rm, (i32 16)))))]>,
2801 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2802 let Inst{31-27} = 0b11111;
2803 let Inst{26-23} = 0b0110;
2804 let Inst{22-20} = 0b001;
2805 let Inst{7-6} = 0b00;
2806 let Inst{5-4} = 0b11;
2810 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2811 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2812 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2813 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2814 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2815 let Inst{31-27} = 0b11111;
2816 let Inst{26-23} = 0b0110;
2817 let Inst{22-20} = 0b011;
2818 let Inst{7-6} = 0b00;
2819 let Inst{5-4} = 0b00;
2823 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2824 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2825 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2826 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2827 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2828 let Inst{31-27} = 0b11111;
2829 let Inst{26-23} = 0b0110;
2830 let Inst{22-20} = 0b011;
2831 let Inst{7-6} = 0b00;
2832 let Inst{5-4} = 0b01;
2836 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2837 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2839 // Halfword multiple accumulate long: SMLAL<x><y>
2840 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2841 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2842 [/* For disassembly only; pattern left blank */]>,
2843 Requires<[IsThumb2, HasThumb2DSP]>;
2844 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2845 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2846 [/* For disassembly only; pattern left blank */]>,
2847 Requires<[IsThumb2, HasThumb2DSP]>;
2848 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2849 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2850 [/* For disassembly only; pattern left blank */]>,
2851 Requires<[IsThumb2, HasThumb2DSP]>;
2852 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2853 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2854 [/* For disassembly only; pattern left blank */]>,
2855 Requires<[IsThumb2, HasThumb2DSP]>;
2857 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2858 def t2SMUAD: T2ThreeReg_mac<
2859 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2860 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2861 Requires<[IsThumb2, HasThumb2DSP]> {
2862 let Inst{15-12} = 0b1111;
2864 def t2SMUADX:T2ThreeReg_mac<
2865 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2866 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2867 Requires<[IsThumb2, HasThumb2DSP]> {
2868 let Inst{15-12} = 0b1111;
2870 def t2SMUSD: T2ThreeReg_mac<
2871 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2872 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2873 Requires<[IsThumb2, HasThumb2DSP]> {
2874 let Inst{15-12} = 0b1111;
2876 def t2SMUSDX:T2ThreeReg_mac<
2877 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2878 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2879 Requires<[IsThumb2, HasThumb2DSP]> {
2880 let Inst{15-12} = 0b1111;
2882 def t2SMLAD : T2FourReg_mac<
2883 0, 0b010, 0b0000, (outs rGPR:$Rd),
2884 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2885 "\t$Rd, $Rn, $Rm, $Ra", []>,
2886 Requires<[IsThumb2, HasThumb2DSP]>;
2887 def t2SMLADX : T2FourReg_mac<
2888 0, 0b010, 0b0001, (outs rGPR:$Rd),
2889 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2890 "\t$Rd, $Rn, $Rm, $Ra", []>,
2891 Requires<[IsThumb2, HasThumb2DSP]>;
2892 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2893 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2894 "\t$Rd, $Rn, $Rm, $Ra", []>,
2895 Requires<[IsThumb2, HasThumb2DSP]>;
2896 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2897 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2898 "\t$Rd, $Rn, $Rm, $Ra", []>,
2899 Requires<[IsThumb2, HasThumb2DSP]>;
2900 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2901 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2902 "\t$Ra, $Rd, $Rn, $Rm", []>,
2903 Requires<[IsThumb2, HasThumb2DSP]>;
2904 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2905 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2906 "\t$Ra, $Rd, $Rn, $Rm", []>,
2907 Requires<[IsThumb2, HasThumb2DSP]>;
2908 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2909 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2910 "\t$Ra, $Rd, $Rn, $Rm", []>,
2911 Requires<[IsThumb2, HasThumb2DSP]>;
2912 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2913 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2914 "\t$Ra, $Rd, $Rn, $Rm", []>,
2915 Requires<[IsThumb2, HasThumb2DSP]>;
2917 //===----------------------------------------------------------------------===//
2918 // Division Instructions.
2919 // Signed and unsigned division on v7-M
2921 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2922 "sdiv", "\t$Rd, $Rn, $Rm",
2923 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2924 Requires<[HasDivide, IsThumb2]> {
2925 let Inst{31-27} = 0b11111;
2926 let Inst{26-21} = 0b011100;
2928 let Inst{15-12} = 0b1111;
2929 let Inst{7-4} = 0b1111;
2932 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2933 "udiv", "\t$Rd, $Rn, $Rm",
2934 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2935 Requires<[HasDivide, IsThumb2]> {
2936 let Inst{31-27} = 0b11111;
2937 let Inst{26-21} = 0b011101;
2939 let Inst{15-12} = 0b1111;
2940 let Inst{7-4} = 0b1111;
2943 //===----------------------------------------------------------------------===//
2944 // Misc. Arithmetic Instructions.
2947 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2948 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2949 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2950 let Inst{31-27} = 0b11111;
2951 let Inst{26-22} = 0b01010;
2952 let Inst{21-20} = op1;
2953 let Inst{15-12} = 0b1111;
2954 let Inst{7-6} = 0b10;
2955 let Inst{5-4} = op2;
2959 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2960 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2963 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2964 "rbit", "\t$Rd, $Rm",
2965 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>,
2968 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2969 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2972 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2973 "rev16", ".w\t$Rd, $Rm",
2974 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2977 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2978 "revsh", ".w\t$Rd, $Rm",
2979 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2982 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2983 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2984 (t2REVSH rGPR:$Rm)>;
2986 def t2PKHBT : T2ThreeReg<
2987 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2988 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2989 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2990 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2992 Requires<[HasT2ExtractPack, IsThumb2]>,
2993 Sched<[WriteALUsi, ReadALU]> {
2994 let Inst{31-27} = 0b11101;
2995 let Inst{26-25} = 0b01;
2996 let Inst{24-20} = 0b01100;
2997 let Inst{5} = 0; // BT form
3001 let Inst{14-12} = sh{4-2};
3002 let Inst{7-6} = sh{1-0};
3005 // Alternate cases for PKHBT where identities eliminate some nodes.
3006 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
3007 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
3008 Requires<[HasT2ExtractPack, IsThumb2]>;
3009 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
3010 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
3011 Requires<[HasT2ExtractPack, IsThumb2]>;
3013 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3014 // will match the pattern below.
3015 def t2PKHTB : T2ThreeReg<
3016 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
3017 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3018 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
3019 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
3021 Requires<[HasT2ExtractPack, IsThumb2]>,
3022 Sched<[WriteALUsi, ReadALU]> {
3023 let Inst{31-27} = 0b11101;
3024 let Inst{26-25} = 0b01;
3025 let Inst{24-20} = 0b01100;
3026 let Inst{5} = 1; // TB form
3030 let Inst{14-12} = sh{4-2};
3031 let Inst{7-6} = sh{1-0};
3034 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3035 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3036 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
3037 // pkhtb src1, src2, asr (17..31).
3038 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
3039 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
3040 Requires<[HasT2ExtractPack, IsThumb2]>;
3041 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
3042 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
3043 Requires<[HasT2ExtractPack, IsThumb2]>;
3044 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
3045 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
3046 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
3047 Requires<[HasT2ExtractPack, IsThumb2]>;
3049 //===----------------------------------------------------------------------===//
3050 // CRC32 Instructions
3053 // + CRC32{B,H,W} 0x04C11DB7
3054 // + CRC32C{B,H,W} 0x1EDC6F41
3057 class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
3058 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
3059 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
3060 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
3061 Requires<[IsThumb2, HasV8, HasCRC]> {
3062 let Inst{31-27} = 0b11111;
3063 let Inst{26-21} = 0b010110;
3065 let Inst{15-12} = 0b1111;
3066 let Inst{7-6} = 0b10;
3070 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3071 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3072 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
3073 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
3074 def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;
3075 def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;
3077 //===----------------------------------------------------------------------===//
3078 // Comparison Instructions...
3080 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
3081 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
3082 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3084 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
3085 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
3086 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
3087 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
3088 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
3089 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
3091 let isCompare = 1, Defs = [CPSR] in {
3093 def t2CMNri : T2OneRegCmpImm<
3094 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
3095 "cmn", ".w\t$Rn, $imm",
3096 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
3097 Sched<[WriteCMP, ReadALU]> {
3098 let Inst{31-27} = 0b11110;
3100 let Inst{24-21} = 0b1000;
3101 let Inst{20} = 1; // The S bit.
3103 let Inst{11-8} = 0b1111; // Rd
3106 def t2CMNzrr : T2TwoRegCmp<
3107 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
3108 "cmn", ".w\t$Rn, $Rm",
3109 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3110 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
3111 let Inst{31-27} = 0b11101;
3112 let Inst{26-25} = 0b01;
3113 let Inst{24-21} = 0b1000;
3114 let Inst{20} = 1; // The S bit.
3115 let Inst{14-12} = 0b000; // imm3
3116 let Inst{11-8} = 0b1111; // Rd
3117 let Inst{7-6} = 0b00; // imm2
3118 let Inst{5-4} = 0b00; // type
3121 def t2CMNzrs : T2OneRegCmpShiftedReg<
3122 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
3123 "cmn", ".w\t$Rn, $ShiftedRm",
3124 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3125 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
3126 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3127 let Inst{31-27} = 0b11101;
3128 let Inst{26-25} = 0b01;
3129 let Inst{24-21} = 0b1000;
3130 let Inst{20} = 1; // The S bit.
3131 let Inst{11-8} = 0b1111; // Rd
3135 // Assembler aliases w/o the ".w" suffix.
3136 // No alias here for 'rr' version as not all instantiations of this multiclass
3137 // want one (CMP in particular, does not).
3138 def : t2InstAlias<"cmn${p} $Rn, $imm",
3139 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
3140 def : t2InstAlias<"cmn${p} $Rn, $shift",
3141 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
3143 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
3144 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
3146 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
3147 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
3149 defm t2TST : T2I_cmp_irs<0b0000, "tst",
3150 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3151 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3152 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
3153 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3154 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3156 // Conditional moves
3157 let neverHasSideEffects = 1 in {
3159 let isCommutable = 1, isSelect = 1 in
3160 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3161 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p),
3163 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
3165 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3167 let isMoveImm = 1 in
3169 : t2PseudoInst<(outs rGPR:$Rd),
3170 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3172 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3174 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3176 let isCodeGenOnly = 1 in {
3177 let isMoveImm = 1 in
3179 : t2PseudoInst<(outs rGPR:$Rd),
3180 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
3182 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3184 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3186 let isMoveImm = 1 in
3188 : t2PseudoInst<(outs rGPR:$Rd),
3189 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3192 (ARMcmov rGPR:$false, t2_so_imm_not:$imm,
3194 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3196 class MOVCCShPseudo<SDPatternOperator opnode, Operand ty>
3197 : t2PseudoInst<(outs rGPR:$Rd),
3198 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p),
3200 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3201 (opnode rGPR:$Rm, (i32 ty:$imm)),
3203 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3205 def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>;
3206 def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>;
3207 def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>;
3208 def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>;
3210 let isMoveImm = 1 in
3212 : t2PseudoInst<(outs rGPR:$dst),
3213 (ins rGPR:$false, i32imm:$src, cmovpred:$p),
3215 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src,
3217 RegConstraint<"$false = $dst">;
3218 } // isCodeGenOnly = 1
3220 } // neverHasSideEffects
3222 //===----------------------------------------------------------------------===//
3223 // Atomic operations intrinsics
3226 // memory barriers protect the atomic sequences
3227 let hasSideEffects = 1 in {
3228 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3229 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
3230 Requires<[IsThumb, HasDB]> {
3232 let Inst{31-4} = 0xf3bf8f5;
3233 let Inst{3-0} = opt;
3236 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3237 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
3238 Requires<[IsThumb, HasDB]> {
3240 let Inst{31-4} = 0xf3bf8f4;
3241 let Inst{3-0} = opt;
3244 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3245 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
3246 Requires<[IsThumb, HasDB]> {
3248 let Inst{31-4} = 0xf3bf8f6;
3249 let Inst{3-0} = opt;
3253 class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3254 InstrItinClass itin, string opc, string asm, string cstr,
3255 list<dag> pattern, bits<4> rt2 = 0b1111>
3256 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3257 let Inst{31-27} = 0b11101;
3258 let Inst{26-20} = 0b0001101;
3259 let Inst{11-8} = rt2;
3260 let Inst{7-4} = opcod;
3261 let Inst{3-0} = 0b1111;
3265 let Inst{19-16} = addr;
3266 let Inst{15-12} = Rt;
3268 class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3269 InstrItinClass itin, string opc, string asm, string cstr,
3270 list<dag> pattern, bits<4> rt2 = 0b1111>
3271 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3272 let Inst{31-27} = 0b11101;
3273 let Inst{26-20} = 0b0001100;
3274 let Inst{11-8} = rt2;
3275 let Inst{7-4} = opcod;
3281 let Inst{19-16} = addr;
3282 let Inst{15-12} = Rt;
3285 let mayLoad = 1 in {
3286 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3287 AddrModeNone, 4, NoItinerary,
3288 "ldrexb", "\t$Rt, $addr", "",
3289 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
3290 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3291 AddrModeNone, 4, NoItinerary,
3292 "ldrexh", "\t$Rt, $addr", "",
3293 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
3294 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3295 AddrModeNone, 4, NoItinerary,
3296 "ldrex", "\t$Rt, $addr", "",
3297 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]> {
3300 let Inst{31-27} = 0b11101;
3301 let Inst{26-20} = 0b0000101;
3302 let Inst{19-16} = addr{11-8};
3303 let Inst{15-12} = Rt;
3304 let Inst{11-8} = 0b1111;
3305 let Inst{7-0} = addr{7-0};
3307 let hasExtraDefRegAllocReq = 1 in
3308 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3309 (ins addr_offset_none:$addr),
3310 AddrModeNone, 4, NoItinerary,
3311 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3314 let Inst{11-8} = Rt2;
3316 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3317 AddrModeNone, 4, NoItinerary,
3318 "ldaexb", "\t$Rt, $addr", "",
3319 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
3320 Requires<[IsThumb, HasV8]>;
3321 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3322 AddrModeNone, 4, NoItinerary,
3323 "ldaexh", "\t$Rt, $addr", "",
3324 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,
3325 Requires<[IsThumb, HasV8]>;
3326 def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
3327 AddrModeNone, 4, NoItinerary,
3328 "ldaex", "\t$Rt, $addr", "",
3329 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,
3330 Requires<[IsThumb, HasV8]> {
3333 let Inst{31-27} = 0b11101;
3334 let Inst{26-20} = 0b0001101;
3335 let Inst{19-16} = addr;
3336 let Inst{15-12} = Rt;
3337 let Inst{11-8} = 0b1111;
3338 let Inst{7-0} = 0b11101111;
3340 let hasExtraDefRegAllocReq = 1 in
3341 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3342 (ins addr_offset_none:$addr),
3343 AddrModeNone, 4, NoItinerary,
3344 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3345 [], {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> {
3347 let Inst{11-8} = Rt2;
3353 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3354 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3355 (ins rGPR:$Rt, addr_offset_none:$addr),
3356 AddrModeNone, 4, NoItinerary,
3357 "strexb", "\t$Rd, $Rt, $addr", "",
3359 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>;
3360 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3361 (ins rGPR:$Rt, addr_offset_none:$addr),
3362 AddrModeNone, 4, NoItinerary,
3363 "strexh", "\t$Rd, $Rt, $addr", "",
3365 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>;
3367 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3368 t2addrmode_imm0_1020s4:$addr),
3369 AddrModeNone, 4, NoItinerary,
3370 "strex", "\t$Rd, $Rt, $addr", "",
3372 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]> {
3376 let Inst{31-27} = 0b11101;
3377 let Inst{26-20} = 0b0000100;
3378 let Inst{19-16} = addr{11-8};
3379 let Inst{15-12} = Rt;
3380 let Inst{11-8} = Rd;
3381 let Inst{7-0} = addr{7-0};
3383 let hasExtraSrcRegAllocReq = 1 in
3384 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3385 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3386 AddrModeNone, 4, NoItinerary,
3387 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3390 let Inst{11-8} = Rt2;
3392 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3393 (ins rGPR:$Rt, addr_offset_none:$addr),
3394 AddrModeNone, 4, NoItinerary,
3395 "stlexb", "\t$Rd, $Rt, $addr", "",
3397 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3398 Requires<[IsThumb, HasV8]>;
3400 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3401 (ins rGPR:$Rt, addr_offset_none:$addr),
3402 AddrModeNone, 4, NoItinerary,
3403 "stlexh", "\t$Rd, $Rt, $addr", "",
3405 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3406 Requires<[IsThumb, HasV8]>;
3408 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3409 addr_offset_none:$addr),
3410 AddrModeNone, 4, NoItinerary,
3411 "stlex", "\t$Rd, $Rt, $addr", "",
3413 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,
3414 Requires<[IsThumb, HasV8]> {
3418 let Inst{31-27} = 0b11101;
3419 let Inst{26-20} = 0b0001100;
3420 let Inst{19-16} = addr;
3421 let Inst{15-12} = Rt;
3422 let Inst{11-4} = 0b11111110;
3425 let hasExtraSrcRegAllocReq = 1 in
3426 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3427 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3428 AddrModeNone, 4, NoItinerary,
3429 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3430 {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> {
3432 let Inst{11-8} = Rt2;
3436 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
3437 Requires<[IsThumb2, HasV7]> {
3438 let Inst{31-16} = 0xf3bf;
3439 let Inst{15-14} = 0b10;
3442 let Inst{11-8} = 0b1111;
3443 let Inst{7-4} = 0b0010;
3444 let Inst{3-0} = 0b1111;
3447 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3448 (t2LDREXB addr_offset_none:$addr)>;
3449 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3450 (t2LDREXH addr_offset_none:$addr)>;
3451 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3452 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>;
3453 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3454 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>;
3456 def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),
3457 (t2LDAEXB addr_offset_none:$addr)>;
3458 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
3459 (t2LDAEXH addr_offset_none:$addr)>;
3460 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3461 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>;
3462 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3463 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>;
3465 //===----------------------------------------------------------------------===//
3466 // SJLJ Exception handling intrinsics
3467 // eh_sjlj_setjmp() is an instruction sequence to store the return
3468 // address and save #0 in R0 for the non-longjmp case.
3469 // Since by its nature we may be coming from some other function to get
3470 // here, and we're using the stack frame for the containing function to
3471 // save/restore registers, we can't keep anything live in regs across
3472 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3473 // when we get here from a longjmp(). We force everything out of registers
3474 // except for our own input by listing the relevant registers in Defs. By
3475 // doing so, we also cause the prologue/epilogue code to actively preserve
3476 // all of the callee-saved resgisters, which is exactly what we want.
3477 // $val is a scratch register for our use.
3479 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3480 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3481 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3482 usesCustomInserter = 1 in {
3483 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3484 AddrModeNone, 0, NoItinerary, "", "",
3485 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3486 Requires<[IsThumb2, HasVFP2]>;
3490 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3491 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3492 usesCustomInserter = 1 in {
3493 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3494 AddrModeNone, 0, NoItinerary, "", "",
3495 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3496 Requires<[IsThumb2, NoVFP]>;
3500 //===----------------------------------------------------------------------===//
3501 // Control-Flow Instructions
3504 // FIXME: remove when we have a way to marking a MI with these properties.
3505 // FIXME: Should pc be an implicit operand like PICADD, etc?
3506 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3507 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3508 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3509 reglist:$regs, variable_ops),
3510 4, IIC_iLoad_mBr, [],
3511 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3512 RegConstraint<"$Rn = $wb">;
3514 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3515 let isPredicable = 1 in
3516 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3518 [(br bb:$target)]>, Sched<[WriteBr]> {
3519 let Inst{31-27} = 0b11110;
3520 let Inst{15-14} = 0b10;
3524 let Inst{26} = target{23};
3525 let Inst{13} = target{22};
3526 let Inst{11} = target{21};
3527 let Inst{25-16} = target{20-11};
3528 let Inst{10-0} = target{10-0};
3529 let DecoderMethod = "DecodeT2BInstruction";
3530 let AsmMatchConverter = "cvtThumbBranches";
3533 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3534 def t2BR_JT : t2PseudoInst<(outs),
3535 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3537 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>,
3540 // FIXME: Add a non-pc based case that can be predicated.
3541 def t2TBB_JT : t2PseudoInst<(outs),
3542 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3545 def t2TBH_JT : t2PseudoInst<(outs),
3546 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3549 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3550 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3553 let Inst{31-20} = 0b111010001101;
3554 let Inst{19-16} = Rn;
3555 let Inst{15-5} = 0b11110000000;
3556 let Inst{4} = 0; // B form
3559 let DecoderMethod = "DecodeThumbTableBranch";
3562 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3563 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3566 let Inst{31-20} = 0b111010001101;
3567 let Inst{19-16} = Rn;
3568 let Inst{15-5} = 0b11110000000;
3569 let Inst{4} = 1; // H form
3572 let DecoderMethod = "DecodeThumbTableBranch";
3574 } // isNotDuplicable, isIndirectBranch
3576 } // isBranch, isTerminator, isBarrier
3578 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3579 // a two-value operand where a dag node expects ", "two operands. :(
3580 let isBranch = 1, isTerminator = 1 in
3581 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3583 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3584 let Inst{31-27} = 0b11110;
3585 let Inst{15-14} = 0b10;
3589 let Inst{25-22} = p;
3592 let Inst{26} = target{20};
3593 let Inst{11} = target{19};
3594 let Inst{13} = target{18};
3595 let Inst{21-16} = target{17-12};
3596 let Inst{10-0} = target{11-1};
3598 let DecoderMethod = "DecodeThumb2BCCInstruction";
3599 let AsmMatchConverter = "cvtThumbBranches";
3602 // Tail calls. The MachO version of thumb tail calls uses a t2 branch, so
3604 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3607 def tTAILJMPd: tPseudoExpand<(outs),
3608 (ins uncondbrtarget:$dst, pred:$p),
3610 (t2B uncondbrtarget:$dst, pred:$p)>,
3611 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>;
3615 let Defs = [ITSTATE] in
3616 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3617 AddrModeNone, 2, IIC_iALUx,
3618 "it$mask\t$cc", "", []>,
3619 ComplexDeprecationPredicate<"IT"> {
3620 // 16-bit instruction.
3621 let Inst{31-16} = 0x0000;
3622 let Inst{15-8} = 0b10111111;
3627 let Inst{3-0} = mask;
3629 let DecoderMethod = "DecodeIT";
3632 // Branch and Exchange Jazelle -- for disassembly only
3634 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []>,
3637 let Inst{31-27} = 0b11110;
3639 let Inst{25-20} = 0b111100;
3640 let Inst{19-16} = func;
3641 let Inst{15-0} = 0b1000111100000000;
3644 // Compare and branch on zero / non-zero
3645 let isBranch = 1, isTerminator = 1 in {
3646 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3647 "cbz\t$Rn, $target", []>,
3648 T1Misc<{0,0,?,1,?,?,?}>,
3649 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3653 let Inst{9} = target{5};
3654 let Inst{7-3} = target{4-0};
3658 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3659 "cbnz\t$Rn, $target", []>,
3660 T1Misc<{1,0,?,1,?,?,?}>,
3661 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3665 let Inst{9} = target{5};
3666 let Inst{7-3} = target{4-0};
3672 // Change Processor State is a system instruction.
3673 // FIXME: Since the asm parser has currently no clean way to handle optional
3674 // operands, create 3 versions of the same instruction. Once there's a clean
3675 // framework to represent optional operands, change this behavior.
3676 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3677 !strconcat("cps", asm_op), []>,
3678 Requires<[IsThumb2, IsNotMClass]> {
3684 let Inst{31-11} = 0b111100111010111110000;
3685 let Inst{10-9} = imod;
3687 let Inst{7-5} = iflags;
3688 let Inst{4-0} = mode;
3689 let DecoderMethod = "DecodeT2CPSInstruction";
3693 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3694 "$imod\t$iflags, $mode">;
3695 let mode = 0, M = 0 in
3696 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3697 "$imod.w\t$iflags">;
3698 let imod = 0, iflags = 0, M = 1 in
3699 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3701 def : t2InstAlias<"cps$imod.w $iflags, $mode",
3702 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
3703 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
3705 // A6.3.4 Branches and miscellaneous control
3706 // Table A6-14 Change Processor State, and hint instructions
3707 def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
3708 [(int_arm_hint imm0_239:$imm)]> {
3710 let Inst{31-3} = 0b11110011101011111000000000000;
3711 let Inst{7-0} = imm;
3714 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p)>;
3715 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3716 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3717 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3718 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3719 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3720 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p)> {
3721 let Predicates = [IsThumb2, HasV8];
3724 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
3725 [(int_arm_dbg imm0_15:$opt)]> {
3727 let Inst{31-20} = 0b111100111010;
3728 let Inst{19-16} = 0b1111;
3729 let Inst{15-8} = 0b10000000;
3730 let Inst{7-4} = 0b1111;
3731 let Inst{3-0} = opt;
3734 // Secure Monitor Call is a system instruction.
3735 // Option = Inst{19-16}
3736 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3737 []>, Requires<[IsThumb2, HasTrustZone]> {
3738 let Inst{31-27} = 0b11110;
3739 let Inst{26-20} = 0b1111111;
3740 let Inst{15-12} = 0b1000;
3743 let Inst{19-16} = opt;
3746 class T2DCPS<bits<2> opt, string opc>
3747 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
3748 let Inst{31-27} = 0b11110;
3749 let Inst{26-20} = 0b1111000;
3750 let Inst{19-16} = 0b1111;
3751 let Inst{15-12} = 0b1000;
3752 let Inst{11-2} = 0b0000000000;
3753 let Inst{1-0} = opt;
3756 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
3757 def t2DCPS2 : T2DCPS<0b10, "dcps2">;
3758 def t2DCPS3 : T2DCPS<0b11, "dcps3">;
3760 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3761 string opc, string asm, list<dag> pattern>
3762 : T2I<oops, iops, itin, opc, asm, pattern> {
3764 let Inst{31-25} = 0b1110100;
3765 let Inst{24-23} = Op;
3768 let Inst{20-16} = 0b01101;
3769 let Inst{15-5} = 0b11000000000;
3770 let Inst{4-0} = mode{4-0};
3773 // Store Return State is a system instruction.
3774 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3775 "srsdb", "\tsp!, $mode", []>;
3776 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3777 "srsdb","\tsp, $mode", []>;
3778 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3779 "srsia","\tsp!, $mode", []>;
3780 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3781 "srsia","\tsp, $mode", []>;
3784 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3785 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3787 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3788 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3790 // Return From Exception is a system instruction.
3791 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3792 string opc, string asm, list<dag> pattern>
3793 : T2I<oops, iops, itin, opc, asm, pattern> {
3794 let Inst{31-20} = op31_20{11-0};
3797 let Inst{19-16} = Rn;
3798 let Inst{15-0} = 0xc000;
3801 def t2RFEDBW : T2RFE<0b111010000011,
3802 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3803 [/* For disassembly only; pattern left blank */]>;
3804 def t2RFEDB : T2RFE<0b111010000001,
3805 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3806 [/* For disassembly only; pattern left blank */]>;
3807 def t2RFEIAW : T2RFE<0b111010011011,
3808 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3809 [/* For disassembly only; pattern left blank */]>;
3810 def t2RFEIA : T2RFE<0b111010011001,
3811 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3812 [/* For disassembly only; pattern left blank */]>;
3814 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
3815 // Exception return instruction is "subs pc, lr, #imm".
3816 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3817 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
3818 "subs", "\tpc, lr, $imm",
3819 [(ARMintretflag imm0_255:$imm)]>,
3820 Requires<[IsThumb2]> {
3821 let Inst{31-8} = 0b111100111101111010001111;
3824 let Inst{7-0} = imm;
3827 //===----------------------------------------------------------------------===//
3828 // Non-Instruction Patterns
3831 // 32-bit immediate using movw + movt.
3832 // This is a single pseudo instruction to make it re-materializable.
3833 // FIXME: Remove this when we can do generalized remat.
3834 let isReMaterializable = 1, isMoveImm = 1 in
3835 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3836 [(set rGPR:$dst, (i32 imm:$src))]>,
3837 Requires<[IsThumb, UseMovt]>;
3839 // Pseudo instruction that combines movw + movt + add pc (if pic).
3840 // It also makes it possible to rematerialize the instructions.
3841 // FIXME: Remove this when we can do generalized remat and when machine licm
3842 // can properly the instructions.
3843 let isReMaterializable = 1 in {
3844 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3846 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3847 Requires<[IsThumb2, UseMovt]>;
3851 // ConstantPool, GlobalAddress, and JumpTable
3852 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3853 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3854 Requires<[IsThumb2, UseMovt]>;
3856 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3857 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3859 // Pseudo instruction that combines ldr from constpool and add pc. This should
3860 // be expanded into two instructions late to allow if-conversion and
3862 let canFoldAsLoad = 1, isReMaterializable = 1 in
3863 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3865 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3867 Requires<[IsThumb2]>;
3869 // Pseudo isntruction that combines movs + predicated rsbmi
3870 // to implement integer ABS
3871 let usesCustomInserter = 1, Defs = [CPSR] in {
3872 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3873 NoItinerary, []>, Requires<[IsThumb2]>;
3876 //===----------------------------------------------------------------------===//
3877 // Coprocessor load/store -- for disassembly only
3879 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3880 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3881 let Inst{31-28} = op31_28;
3882 let Inst{27-25} = 0b110;
3885 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3886 def _OFFSET : T2CI<op31_28,
3887 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3888 asm, "\t$cop, $CRd, $addr"> {
3892 let Inst{24} = 1; // P = 1
3893 let Inst{23} = addr{8};
3894 let Inst{22} = Dbit;
3895 let Inst{21} = 0; // W = 0
3896 let Inst{20} = load;
3897 let Inst{19-16} = addr{12-9};
3898 let Inst{15-12} = CRd;
3899 let Inst{11-8} = cop;
3900 let Inst{7-0} = addr{7-0};
3901 let DecoderMethod = "DecodeCopMemInstruction";
3903 def _PRE : T2CI<op31_28,
3904 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3905 asm, "\t$cop, $CRd, $addr!"> {
3909 let Inst{24} = 1; // P = 1
3910 let Inst{23} = addr{8};
3911 let Inst{22} = Dbit;
3912 let Inst{21} = 1; // W = 1
3913 let Inst{20} = load;
3914 let Inst{19-16} = addr{12-9};
3915 let Inst{15-12} = CRd;
3916 let Inst{11-8} = cop;
3917 let Inst{7-0} = addr{7-0};
3918 let DecoderMethod = "DecodeCopMemInstruction";
3920 def _POST: T2CI<op31_28,
3921 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3922 postidx_imm8s4:$offset),
3923 asm, "\t$cop, $CRd, $addr, $offset"> {
3928 let Inst{24} = 0; // P = 0
3929 let Inst{23} = offset{8};
3930 let Inst{22} = Dbit;
3931 let Inst{21} = 1; // W = 1
3932 let Inst{20} = load;
3933 let Inst{19-16} = addr;
3934 let Inst{15-12} = CRd;
3935 let Inst{11-8} = cop;
3936 let Inst{7-0} = offset{7-0};
3937 let DecoderMethod = "DecodeCopMemInstruction";
3939 def _OPTION : T2CI<op31_28, (outs),
3940 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3941 coproc_option_imm:$option),
3942 asm, "\t$cop, $CRd, $addr, $option"> {
3947 let Inst{24} = 0; // P = 0
3948 let Inst{23} = 1; // U = 1
3949 let Inst{22} = Dbit;
3950 let Inst{21} = 0; // W = 0
3951 let Inst{20} = load;
3952 let Inst{19-16} = addr;
3953 let Inst{15-12} = CRd;
3954 let Inst{11-8} = cop;
3955 let Inst{7-0} = option;
3956 let DecoderMethod = "DecodeCopMemInstruction";
3960 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3961 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3962 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3963 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3964 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">, Requires<[PreV8,IsThumb2]>;
3965 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">, Requires<[PreV8,IsThumb2]>;
3966 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">, Requires<[PreV8,IsThumb2]>;
3967 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">, Requires<[PreV8,IsThumb2]>;
3970 //===----------------------------------------------------------------------===//
3971 // Move between special register and ARM core register -- for disassembly only
3973 // Move to ARM core register from Special Register
3977 // A/R class can only move from CPSR or SPSR.
3978 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3979 []>, Requires<[IsThumb2,IsNotMClass]> {
3981 let Inst{31-12} = 0b11110011111011111000;
3982 let Inst{11-8} = Rd;
3983 let Inst{7-0} = 0b00000000;
3986 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3988 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3989 []>, Requires<[IsThumb2,IsNotMClass]> {
3991 let Inst{31-12} = 0b11110011111111111000;
3992 let Inst{11-8} = Rd;
3993 let Inst{7-0} = 0b00000000;
3996 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
3997 NoItinerary, "mrs", "\t$Rd, $banked", []>,
3998 Requires<[IsThumb, HasVirtualization]> {
4002 let Inst{31-21} = 0b11110011111;
4003 let Inst{20} = banked{5}; // R bit
4004 let Inst{19-16} = banked{3-0};
4005 let Inst{15-12} = 0b1000;
4006 let Inst{11-8} = Rd;
4007 let Inst{7-5} = 0b001;
4008 let Inst{4} = banked{4};
4009 let Inst{3-0} = 0b0000;
4015 // This MRS has a mask field in bits 7-0 and can take more values than
4016 // the A/R class (a full msr_mask).
4017 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
4018 "mrs", "\t$Rd, $SYSm", []>,
4019 Requires<[IsThumb,IsMClass]> {
4022 let Inst{31-12} = 0b11110011111011111000;
4023 let Inst{11-8} = Rd;
4024 let Inst{7-0} = SYSm;
4026 let Unpredictable{20-16} = 0b11111;
4027 let Unpredictable{13} = 0b1;
4031 // Move from ARM core register to Special Register
4035 // No need to have both system and application versions, the encodings are the
4036 // same and the assembly parser has no way to distinguish between them. The mask
4037 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4038 // the mask with the fields to be accessed in the special register.
4039 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
4040 NoItinerary, "msr", "\t$mask, $Rn", []>,
4041 Requires<[IsThumb2,IsNotMClass]> {
4044 let Inst{31-21} = 0b11110011100;
4045 let Inst{20} = mask{4}; // R Bit
4046 let Inst{19-16} = Rn;
4047 let Inst{15-12} = 0b1000;
4048 let Inst{11-8} = mask{3-0};
4052 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
4053 // separate encoding (distinguished by bit 5.
4054 def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn),
4055 NoItinerary, "msr", "\t$banked, $Rn", []>,
4056 Requires<[IsThumb, HasVirtualization]> {
4060 let Inst{31-21} = 0b11110011100;
4061 let Inst{20} = banked{5}; // R bit
4062 let Inst{19-16} = Rn;
4063 let Inst{15-12} = 0b1000;
4064 let Inst{11-8} = banked{3-0};
4065 let Inst{7-5} = 0b001;
4066 let Inst{4} = banked{4};
4067 let Inst{3-0} = 0b0000;
4073 // Move from ARM core register to Special Register
4074 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
4075 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
4076 Requires<[IsThumb,IsMClass]> {
4079 let Inst{31-21} = 0b11110011100;
4081 let Inst{19-16} = Rn;
4082 let Inst{15-12} = 0b1000;
4083 let Inst{11-10} = SYSm{11-10};
4084 let Inst{9-8} = 0b00;
4085 let Inst{7-0} = SYSm{7-0};
4087 let Unpredictable{20} = 0b1;
4088 let Unpredictable{13} = 0b1;
4089 let Unpredictable{9-8} = 0b11;
4093 //===----------------------------------------------------------------------===//
4094 // Move between coprocessor and ARM core register
4097 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4099 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4101 let Inst{27-24} = 0b1110;
4102 let Inst{20} = direction;
4112 let Inst{15-12} = Rt;
4113 let Inst{11-8} = cop;
4114 let Inst{23-21} = opc1;
4115 let Inst{7-5} = opc2;
4116 let Inst{3-0} = CRm;
4117 let Inst{19-16} = CRn;
4120 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
4121 list<dag> pattern = []>
4123 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4124 opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4125 let Inst{27-24} = 0b1100;
4126 let Inst{23-21} = 0b010;
4127 let Inst{20} = direction;
4135 let Inst{15-12} = Rt;
4136 let Inst{19-16} = Rt2;
4137 let Inst{11-8} = cop;
4138 let Inst{7-4} = opc1;
4139 let Inst{3-0} = CRm;
4142 /* from ARM core register to coprocessor */
4143 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
4145 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4146 c_imm:$CRm, imm0_7:$opc2),
4147 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4148 imm:$CRm, imm:$opc2)]>,
4149 ComplexDeprecationPredicate<"MCR">;
4150 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4151 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4152 c_imm:$CRm, 0, pred:$p)>;
4153 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
4154 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4155 c_imm:$CRm, imm0_7:$opc2),
4156 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4157 imm:$CRm, imm:$opc2)]> {
4158 let Predicates = [IsThumb2, PreV8];
4160 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4161 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4162 c_imm:$CRm, 0, pred:$p)>;
4164 /* from coprocessor to ARM core register */
4165 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
4166 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4167 c_imm:$CRm, imm0_7:$opc2), []>;
4168 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4169 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4170 c_imm:$CRm, 0, pred:$p)>;
4172 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4173 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4174 c_imm:$CRm, imm0_7:$opc2), []> {
4175 let Predicates = [IsThumb2, PreV8];
4177 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4178 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4179 c_imm:$CRm, 0, pred:$p)>;
4181 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4182 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4184 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4185 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4188 /* from ARM core register to coprocessor */
4189 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
4190 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4192 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
4193 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
4194 GPR:$Rt2, imm:$CRm)]> {
4195 let Predicates = [IsThumb2, PreV8];
4198 /* from coprocessor to ARM core register */
4199 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
4201 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1> {
4202 let Predicates = [IsThumb2, PreV8];
4205 //===----------------------------------------------------------------------===//
4206 // Other Coprocessor Instructions.
4209 def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4210 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4211 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4212 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4213 imm:$CRm, imm:$opc2)]> {
4214 let Inst{27-24} = 0b1110;
4223 let Inst{3-0} = CRm;
4225 let Inst{7-5} = opc2;
4226 let Inst{11-8} = cop;
4227 let Inst{15-12} = CRd;
4228 let Inst{19-16} = CRn;
4229 let Inst{23-20} = opc1;
4231 let Predicates = [IsThumb2, PreV8];
4234 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4235 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4236 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4237 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4238 imm:$CRm, imm:$opc2)]> {
4239 let Inst{27-24} = 0b1110;
4248 let Inst{3-0} = CRm;
4250 let Inst{7-5} = opc2;
4251 let Inst{11-8} = cop;
4252 let Inst{15-12} = CRd;
4253 let Inst{19-16} = CRn;
4254 let Inst{23-20} = opc1;
4256 let Predicates = [IsThumb2, PreV8];
4261 //===----------------------------------------------------------------------===//
4262 // Non-Instruction Patterns
4265 // SXT/UXT with no rotate
4266 let AddedComplexity = 16 in {
4267 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4268 Requires<[IsThumb2]>;
4269 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4270 Requires<[IsThumb2]>;
4271 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4272 Requires<[HasT2ExtractPack, IsThumb2]>;
4273 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4274 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4275 Requires<[HasT2ExtractPack, IsThumb2]>;
4276 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4277 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4278 Requires<[HasT2ExtractPack, IsThumb2]>;
4281 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4282 Requires<[IsThumb2]>;
4283 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4284 Requires<[IsThumb2]>;
4285 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4286 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4287 Requires<[HasT2ExtractPack, IsThumb2]>;
4288 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4289 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4290 Requires<[HasT2ExtractPack, IsThumb2]>;
4292 // Atomic load/store patterns
4293 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4294 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4295 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4296 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4297 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4298 (t2LDRBs t2addrmode_so_reg:$addr)>;
4299 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4300 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4301 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4302 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4303 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4304 (t2LDRHs t2addrmode_so_reg:$addr)>;
4305 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4306 (t2LDRi12 t2addrmode_imm12:$addr)>;
4307 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4308 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4309 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4310 (t2LDRs t2addrmode_so_reg:$addr)>;
4311 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4312 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4313 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4314 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4315 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4316 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4317 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4318 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4319 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4320 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4321 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4322 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4323 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4324 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4325 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4326 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4327 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4328 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4330 let AddedComplexity = 8 in {
4331 def : T2Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
4332 def : T2Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
4333 def : T2Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;
4334 def : T2Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;
4335 def : T2Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;
4336 def : T2Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>;
4340 //===----------------------------------------------------------------------===//
4341 // Assembler aliases
4344 // Aliases for ADC without the ".w" optional width specifier.
4345 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4346 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4347 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4348 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4349 pred:$p, cc_out:$s)>;
4351 // Aliases for SBC without the ".w" optional width specifier.
4352 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4353 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4354 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4355 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4356 pred:$p, cc_out:$s)>;
4358 // Aliases for ADD without the ".w" optional width specifier.
4359 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4360 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4362 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4363 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4364 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4365 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4366 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4367 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4368 pred:$p, cc_out:$s)>;
4369 // ... and with the destination and source register combined.
4370 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4371 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4372 def : t2InstAlias<"add${p} $Rdn, $imm",
4373 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4374 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4375 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4376 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4377 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4378 pred:$p, cc_out:$s)>;
4380 // add w/ negative immediates is just a sub.
4381 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4382 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4384 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4385 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4386 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4387 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4389 def : t2InstAlias<"add${p} $Rdn, $imm",
4390 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4392 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4393 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4395 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4396 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4397 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4398 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4400 def : t2InstAlias<"addw${p} $Rdn, $imm",
4401 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4404 // Aliases for SUB without the ".w" optional width specifier.
4405 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4406 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4407 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4408 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4409 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4410 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4411 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4412 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4413 pred:$p, cc_out:$s)>;
4414 // ... and with the destination and source register combined.
4415 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4416 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4417 def : t2InstAlias<"sub${p} $Rdn, $imm",
4418 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4419 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4420 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4421 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4422 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4423 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4424 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4425 pred:$p, cc_out:$s)>;
4427 // Alias for compares without the ".w" optional width specifier.
4428 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4429 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4430 def : t2InstAlias<"teq${p} $Rn, $Rm",
4431 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4432 def : t2InstAlias<"tst${p} $Rn, $Rm",
4433 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4436 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p)>, Requires<[HasDB]>;
4437 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p)>, Requires<[HasDB]>;
4438 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p)>, Requires<[HasDB]>;
4440 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4442 def : t2InstAlias<"ldr${p} $Rt, $addr",
4443 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4444 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4445 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4446 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4447 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4448 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4449 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4450 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4451 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4453 def : t2InstAlias<"ldr${p} $Rt, $addr",
4454 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4455 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4456 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4457 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4458 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4459 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4460 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4461 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4462 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4464 def : t2InstAlias<"ldr${p} $Rt, $addr",
4465 (t2LDRpci GPRnopc:$Rt, t2ldrlabel:$addr, pred:$p)>;
4466 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4467 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4468 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4469 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4470 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4471 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4472 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4473 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4475 // Alias for MVN with(out) the ".w" optional width specifier.
4476 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4477 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4478 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4479 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4480 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4481 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4483 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4484 // shift amount is zero (i.e., unspecified).
4485 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4486 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4487 Requires<[HasT2ExtractPack, IsThumb2]>;
4488 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4489 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4490 Requires<[HasT2ExtractPack, IsThumb2]>;
4492 // PUSH/POP aliases for STM/LDM
4493 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4494 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4495 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4496 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4498 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4499 def : t2InstAlias<"stm${p} $Rn, $regs",
4500 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4501 def : t2InstAlias<"stm${p} $Rn!, $regs",
4502 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4504 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4505 def : t2InstAlias<"ldm${p} $Rn, $regs",
4506 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4507 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4508 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4510 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4511 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4512 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4513 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4514 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4516 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4517 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4518 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4519 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4520 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4522 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4523 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4524 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4525 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4528 // Alias for RSB without the ".w" optional width specifier, and with optional
4529 // implied destination register.
4530 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4531 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4532 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4533 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4534 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4535 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4536 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4537 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4540 // SSAT/USAT optional shift operand.
4541 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4542 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4543 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4544 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4546 // STM w/o the .w suffix.
4547 def : t2InstAlias<"stm${p} $Rn, $regs",
4548 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4550 // Alias for STR, STRB, and STRH without the ".w" optional
4552 def : t2InstAlias<"str${p} $Rt, $addr",
4553 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4554 def : t2InstAlias<"strb${p} $Rt, $addr",
4555 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4556 def : t2InstAlias<"strh${p} $Rt, $addr",
4557 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4559 def : t2InstAlias<"str${p} $Rt, $addr",
4560 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4561 def : t2InstAlias<"strb${p} $Rt, $addr",
4562 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4563 def : t2InstAlias<"strh${p} $Rt, $addr",
4564 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4566 // Extend instruction optional rotate operand.
4567 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4568 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4569 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4570 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4571 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4572 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4574 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4575 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4576 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4577 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4578 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4579 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4580 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4581 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4582 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4583 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4585 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4586 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4587 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4588 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4589 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4590 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4591 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4592 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4593 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4594 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4595 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4596 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4598 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4599 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4600 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4601 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4603 // Extend instruction w/o the ".w" optional width specifier.
4604 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4605 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4606 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4607 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4608 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4609 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4611 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4612 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4613 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4614 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4615 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4616 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4619 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4621 def : t2InstAlias<"mov${p} $Rd, $imm",
4622 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4623 def : t2InstAlias<"mvn${p} $Rd, $imm",
4624 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4625 // Same for AND <--> BIC
4626 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4627 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4628 pred:$p, cc_out:$s)>;
4629 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4630 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4631 pred:$p, cc_out:$s)>;
4632 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4633 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4634 pred:$p, cc_out:$s)>;
4635 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4636 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4637 pred:$p, cc_out:$s)>;
4638 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4639 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4640 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4641 pred:$p, cc_out:$s)>;
4642 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4643 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4644 pred:$p, cc_out:$s)>;
4645 // Same for CMP <--> CMN via t2_so_imm_neg
4646 def : t2InstAlias<"cmp${p} $Rd, $imm",
4647 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4648 def : t2InstAlias<"cmn${p} $Rd, $imm",
4649 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4652 // Wide 'mul' encoding can be specified with only two operands.
4653 def : t2InstAlias<"mul${p} $Rn, $Rm",
4654 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4656 // "neg" is and alias for "rsb rd, rn, #0"
4657 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4658 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4660 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4661 // these, unfortunately.
4662 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4663 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4664 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4665 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4667 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4668 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4669 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4670 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4672 // ADR w/o the .w suffix
4673 def : t2InstAlias<"adr${p} $Rd, $addr",
4674 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4676 // LDR(literal) w/ alternate [pc, #imm] syntax.
4677 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4678 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4679 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4680 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4681 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4682 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4683 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4684 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4685 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4686 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4687 // Version w/ the .w suffix.
4688 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4689 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;
4690 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4691 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4692 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4693 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4694 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4695 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4696 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4697 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4699 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4700 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
4702 // PLD/PLDW/PLI with alternate literal form.
4703 def : t2InstAlias<"pld${p} $addr",
4704 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
4705 def : InstAlias<"pli${p} $addr",
4706 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p)>,
4707 Requires<[IsThumb2,HasV7]>;