1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // t2_so_imm - Match a 32-bit immediate operand, which is an
66 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
67 // immediate splatted into multiple bytes of the word.
68 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
69 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
70 return ARM_AM::getT2SOImmVal(Imm) != -1;
72 let ParserMatchClass = t2_so_imm_asmoperand;
73 let EncoderMethod = "getT2SOImmOpValue";
74 let DecoderMethod = "DecodeT2SOImm";
77 // t2_so_imm_not - Match an immediate that is a complement
79 def t2_so_imm_not : Operand<i32>,
81 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
82 }], t2_so_imm_not_XFORM>;
84 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
85 def t2_so_imm_neg : Operand<i32>,
87 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
88 }], t2_so_imm_neg_XFORM>;
90 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
91 def imm0_4095 : Operand<i32>,
93 return Imm >= 0 && Imm < 4096;
96 def imm0_4095_neg : PatLeaf<(i32 imm), [{
97 return (uint32_t)(-N->getZExtValue()) < 4096;
100 def imm0_255_neg : PatLeaf<(i32 imm), [{
101 return (uint32_t)(-N->getZExtValue()) < 255;
104 def imm0_255_not : PatLeaf<(i32 imm), [{
105 return (uint32_t)(~N->getZExtValue()) < 255;
108 def lo5AllOne : PatLeaf<(i32 imm), [{
109 // Returns true if all low 5-bits are 1.
110 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
113 // Define Thumb2 specific addressing modes.
115 // t2addrmode_imm12 := reg + imm12
116 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
117 def t2addrmode_imm12 : Operand<i32>,
118 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
119 let PrintMethod = "printAddrModeImm12Operand";
120 let EncoderMethod = "getAddrModeImm12OpValue";
121 let DecoderMethod = "DecodeT2AddrModeImm12";
122 let ParserMatchClass = t2addrmode_imm12_asmoperand;
123 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
126 // t2ldrlabel := imm12
127 def t2ldrlabel : Operand<i32> {
128 let EncoderMethod = "getAddrModeImm12OpValue";
129 let PrintMethod = "printT2LdrLabelOperand";
133 // ADR instruction labels.
134 def t2adrlabel : Operand<i32> {
135 let EncoderMethod = "getT2AdrLabelOpValue";
139 // t2addrmode_posimm8 := reg + imm8
140 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
141 def t2addrmode_posimm8 : Operand<i32> {
142 let PrintMethod = "printT2AddrModeImm8Operand";
143 let EncoderMethod = "getT2AddrModeImm8OpValue";
144 let DecoderMethod = "DecodeT2AddrModeImm8";
145 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
146 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
149 // t2addrmode_negimm8 := reg - imm8
150 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
151 def t2addrmode_negimm8 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
153 let PrintMethod = "printT2AddrModeImm8Operand";
154 let EncoderMethod = "getT2AddrModeImm8OpValue";
155 let DecoderMethod = "DecodeT2AddrModeImm8";
156 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
160 // t2addrmode_imm8 := reg +/- imm8
161 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
162 def t2addrmode_imm8 : Operand<i32>,
163 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
164 let PrintMethod = "printT2AddrModeImm8Operand";
165 let EncoderMethod = "getT2AddrModeImm8OpValue";
166 let DecoderMethod = "DecodeT2AddrModeImm8";
167 let ParserMatchClass = MemImm8OffsetAsmOperand;
168 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
171 def t2am_imm8_offset : Operand<i32>,
172 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
173 [], [SDNPWantRoot]> {
174 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
175 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
176 let DecoderMethod = "DecodeT2Imm8";
179 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
180 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
181 def t2addrmode_imm8s4 : Operand<i32> {
182 let PrintMethod = "printT2AddrModeImm8s4Operand";
183 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
184 let DecoderMethod = "DecodeT2AddrModeImm8s4";
185 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
189 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
190 def t2am_imm8s4_offset : Operand<i32> {
191 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
192 let EncoderMethod = "getT2Imm8s4OpValue";
193 let DecoderMethod = "DecodeT2Imm8S4";
196 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
197 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
198 let Name = "MemImm0_1020s4Offset";
200 def t2addrmode_imm0_1020s4 : Operand<i32> {
201 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
202 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
203 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
204 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
205 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
208 // t2addrmode_so_reg := reg + (reg << imm2)
209 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
210 def t2addrmode_so_reg : Operand<i32>,
211 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
212 let PrintMethod = "printT2AddrModeSoRegOperand";
213 let EncoderMethod = "getT2AddrModeSORegOpValue";
214 let DecoderMethod = "DecodeT2AddrModeSOReg";
215 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
216 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
219 // Addresses for the TBB/TBH instructions.
220 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
221 def addrmode_tbb : Operand<i32> {
222 let PrintMethod = "printAddrModeTBB";
223 let ParserMatchClass = addrmode_tbb_asmoperand;
224 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
226 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
227 def addrmode_tbh : Operand<i32> {
228 let PrintMethod = "printAddrModeTBH";
229 let ParserMatchClass = addrmode_tbh_asmoperand;
230 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
233 //===----------------------------------------------------------------------===//
234 // Multiclass helpers...
238 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
239 string opc, string asm, list<dag> pattern>
240 : T2I<oops, iops, itin, opc, asm, pattern> {
245 let Inst{26} = imm{11};
246 let Inst{14-12} = imm{10-8};
247 let Inst{7-0} = imm{7-0};
251 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
252 string opc, string asm, list<dag> pattern>
253 : T2sI<oops, iops, itin, opc, asm, pattern> {
259 let Inst{26} = imm{11};
260 let Inst{14-12} = imm{10-8};
261 let Inst{7-0} = imm{7-0};
264 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
265 string opc, string asm, list<dag> pattern>
266 : T2I<oops, iops, itin, opc, asm, pattern> {
270 let Inst{19-16} = Rn;
271 let Inst{26} = imm{11};
272 let Inst{14-12} = imm{10-8};
273 let Inst{7-0} = imm{7-0};
277 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
278 string opc, string asm, list<dag> pattern>
279 : T2I<oops, iops, itin, opc, asm, pattern> {
284 let Inst{3-0} = ShiftedRm{3-0};
285 let Inst{5-4} = ShiftedRm{6-5};
286 let Inst{14-12} = ShiftedRm{11-9};
287 let Inst{7-6} = ShiftedRm{8-7};
290 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
291 string opc, string asm, list<dag> pattern>
292 : T2sI<oops, iops, itin, opc, asm, pattern> {
297 let Inst{3-0} = ShiftedRm{3-0};
298 let Inst{5-4} = ShiftedRm{6-5};
299 let Inst{14-12} = ShiftedRm{11-9};
300 let Inst{7-6} = ShiftedRm{8-7};
303 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
304 string opc, string asm, list<dag> pattern>
305 : T2I<oops, iops, itin, opc, asm, pattern> {
309 let Inst{19-16} = Rn;
310 let Inst{3-0} = ShiftedRm{3-0};
311 let Inst{5-4} = ShiftedRm{6-5};
312 let Inst{14-12} = ShiftedRm{11-9};
313 let Inst{7-6} = ShiftedRm{8-7};
316 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
317 string opc, string asm, list<dag> pattern>
318 : T2I<oops, iops, itin, opc, asm, pattern> {
326 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
327 string opc, string asm, list<dag> pattern>
328 : T2sI<oops, iops, itin, opc, asm, pattern> {
336 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
337 string opc, string asm, list<dag> pattern>
338 : T2I<oops, iops, itin, opc, asm, pattern> {
342 let Inst{19-16} = Rn;
347 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
348 string opc, string asm, list<dag> pattern>
349 : T2I<oops, iops, itin, opc, asm, pattern> {
355 let Inst{19-16} = Rn;
356 let Inst{26} = imm{11};
357 let Inst{14-12} = imm{10-8};
358 let Inst{7-0} = imm{7-0};
361 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
362 string opc, string asm, list<dag> pattern>
363 : T2sI<oops, iops, itin, opc, asm, pattern> {
369 let Inst{19-16} = Rn;
370 let Inst{26} = imm{11};
371 let Inst{14-12} = imm{10-8};
372 let Inst{7-0} = imm{7-0};
375 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
376 string opc, string asm, list<dag> pattern>
377 : T2I<oops, iops, itin, opc, asm, pattern> {
384 let Inst{14-12} = imm{4-2};
385 let Inst{7-6} = imm{1-0};
388 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
389 string opc, string asm, list<dag> pattern>
390 : T2sI<oops, iops, itin, opc, asm, pattern> {
397 let Inst{14-12} = imm{4-2};
398 let Inst{7-6} = imm{1-0};
401 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
402 string opc, string asm, list<dag> pattern>
403 : T2I<oops, iops, itin, opc, asm, pattern> {
409 let Inst{19-16} = Rn;
413 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
414 string opc, string asm, list<dag> pattern>
415 : T2sI<oops, iops, itin, opc, asm, pattern> {
421 let Inst{19-16} = Rn;
425 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
426 string opc, string asm, list<dag> pattern>
427 : T2I<oops, iops, itin, opc, asm, pattern> {
433 let Inst{19-16} = Rn;
434 let Inst{3-0} = ShiftedRm{3-0};
435 let Inst{5-4} = ShiftedRm{6-5};
436 let Inst{14-12} = ShiftedRm{11-9};
437 let Inst{7-6} = ShiftedRm{8-7};
440 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
441 string opc, string asm, list<dag> pattern>
442 : T2sI<oops, iops, itin, opc, asm, pattern> {
448 let Inst{19-16} = Rn;
449 let Inst{3-0} = ShiftedRm{3-0};
450 let Inst{5-4} = ShiftedRm{6-5};
451 let Inst{14-12} = ShiftedRm{11-9};
452 let Inst{7-6} = ShiftedRm{8-7};
455 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
456 string opc, string asm, list<dag> pattern>
457 : T2I<oops, iops, itin, opc, asm, pattern> {
463 let Inst{19-16} = Rn;
464 let Inst{15-12} = Ra;
469 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
470 dag oops, dag iops, InstrItinClass itin,
471 string opc, string asm, list<dag> pattern>
472 : T2I<oops, iops, itin, opc, asm, pattern> {
478 let Inst{31-23} = 0b111110111;
479 let Inst{22-20} = opc22_20;
480 let Inst{19-16} = Rn;
481 let Inst{15-12} = RdLo;
482 let Inst{11-8} = RdHi;
483 let Inst{7-4} = opc7_4;
488 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
489 /// binary operation that produces a value. These are predicable and can be
490 /// changed to modify CPSR.
491 multiclass T2I_bin_irs<bits<4> opcod, string opc,
492 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
493 PatFrag opnode, string baseOpc, bit Commutable = 0,
496 def ri : T2sTwoRegImm<
497 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
498 opc, "\t$Rd, $Rn, $imm",
499 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
500 let Inst{31-27} = 0b11110;
502 let Inst{24-21} = opcod;
506 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
507 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
508 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
509 let isCommutable = Commutable;
510 let Inst{31-27} = 0b11101;
511 let Inst{26-25} = 0b01;
512 let Inst{24-21} = opcod;
513 let Inst{14-12} = 0b000; // imm3
514 let Inst{7-6} = 0b00; // imm2
515 let Inst{5-4} = 0b00; // type
518 def rs : T2sTwoRegShiftedReg<
519 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
520 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
521 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
522 let Inst{31-27} = 0b11101;
523 let Inst{26-25} = 0b01;
524 let Inst{24-21} = opcod;
526 // Assembly aliases for optional destination operand when it's the same
527 // as the source operand.
528 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
529 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
530 t2_so_imm:$imm, pred:$p,
532 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
533 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
536 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
537 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
538 t2_so_reg:$shift, pred:$p,
542 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
543 // the ".w" suffix to indicate that they are wide.
544 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
545 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
546 PatFrag opnode, string baseOpc, bit Commutable = 0> :
547 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
548 // Assembler aliases w/o the ".w" suffix.
549 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
550 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
553 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
554 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
555 t2_so_reg:$shift, pred:$p,
558 // and with the optional destination operand, too.
559 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
560 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
563 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
564 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
565 t2_so_reg:$shift, pred:$p,
569 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
570 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
571 /// it is equivalent to the T2I_bin_irs counterpart.
572 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
574 def ri : T2sTwoRegImm<
575 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
576 opc, ".w\t$Rd, $Rn, $imm",
577 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
578 let Inst{31-27} = 0b11110;
580 let Inst{24-21} = opcod;
584 def rr : T2sThreeReg<
585 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
586 opc, "\t$Rd, $Rn, $Rm",
587 [/* For disassembly only; pattern left blank */]> {
588 let Inst{31-27} = 0b11101;
589 let Inst{26-25} = 0b01;
590 let Inst{24-21} = opcod;
591 let Inst{14-12} = 0b000; // imm3
592 let Inst{7-6} = 0b00; // imm2
593 let Inst{5-4} = 0b00; // type
596 def rs : T2sTwoRegShiftedReg<
597 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
598 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
599 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
600 let Inst{31-27} = 0b11101;
601 let Inst{26-25} = 0b01;
602 let Inst{24-21} = opcod;
606 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
607 /// instruction modifies the CPSR register.
609 /// These opcodes will be converted to the real non-S opcodes by
610 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
611 let hasPostISelHook = 1, Defs = [CPSR] in {
612 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
613 InstrItinClass iis, PatFrag opnode,
614 bit Commutable = 0> {
616 def ri : t2PseudoInst<(outs rGPR:$Rd),
617 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
619 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
622 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
624 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
626 let isCommutable = Commutable;
629 def rs : t2PseudoInst<(outs rGPR:$Rd),
630 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
632 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
633 t2_so_reg:$ShiftedRm))]>;
637 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
638 /// operands are reversed.
639 let hasPostISelHook = 1, Defs = [CPSR] in {
640 multiclass T2I_rbin_s_is<PatFrag opnode> {
642 def ri : t2PseudoInst<(outs rGPR:$Rd),
643 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
645 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
648 def rs : t2PseudoInst<(outs rGPR:$Rd),
649 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
651 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
656 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
657 /// patterns for a binary operation that produces a value.
658 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
659 bit Commutable = 0> {
661 // The register-immediate version is re-materializable. This is useful
662 // in particular for taking the address of a local.
663 let isReMaterializable = 1 in {
664 def ri : T2sTwoRegImm<
665 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
666 opc, ".w\t$Rd, $Rn, $imm",
667 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
668 let Inst{31-27} = 0b11110;
671 let Inst{23-21} = op23_21;
677 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
678 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
679 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
683 let Inst{31-27} = 0b11110;
684 let Inst{26} = imm{11};
685 let Inst{25-24} = 0b10;
686 let Inst{23-21} = op23_21;
687 let Inst{20} = 0; // The S bit.
688 let Inst{19-16} = Rn;
690 let Inst{14-12} = imm{10-8};
692 let Inst{7-0} = imm{7-0};
695 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
696 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
697 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
698 let isCommutable = Commutable;
699 let Inst{31-27} = 0b11101;
700 let Inst{26-25} = 0b01;
702 let Inst{23-21} = op23_21;
703 let Inst{14-12} = 0b000; // imm3
704 let Inst{7-6} = 0b00; // imm2
705 let Inst{5-4} = 0b00; // type
708 def rs : T2sTwoRegShiftedReg<
709 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
710 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
711 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
712 let Inst{31-27} = 0b11101;
713 let Inst{26-25} = 0b01;
715 let Inst{23-21} = op23_21;
719 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
720 /// for a binary operation that produces a value and use the carry
721 /// bit. It's not predicable.
722 let Defs = [CPSR], Uses = [CPSR] in {
723 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
724 bit Commutable = 0> {
726 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
727 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
728 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
729 Requires<[IsThumb2]> {
730 let Inst{31-27} = 0b11110;
732 let Inst{24-21} = opcod;
736 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
737 opc, ".w\t$Rd, $Rn, $Rm",
738 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
739 Requires<[IsThumb2]> {
740 let isCommutable = Commutable;
741 let Inst{31-27} = 0b11101;
742 let Inst{26-25} = 0b01;
743 let Inst{24-21} = opcod;
744 let Inst{14-12} = 0b000; // imm3
745 let Inst{7-6} = 0b00; // imm2
746 let Inst{5-4} = 0b00; // type
749 def rs : T2sTwoRegShiftedReg<
750 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
751 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
752 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
753 Requires<[IsThumb2]> {
754 let Inst{31-27} = 0b11101;
755 let Inst{26-25} = 0b01;
756 let Inst{24-21} = opcod;
761 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
762 // rotate operation that produces a value.
763 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
766 def ri : T2sTwoRegShiftImm<
767 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
768 opc, ".w\t$Rd, $Rm, $imm",
769 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
770 let Inst{31-27} = 0b11101;
771 let Inst{26-21} = 0b010010;
772 let Inst{19-16} = 0b1111; // Rn
773 let Inst{5-4} = opcod;
776 def rr : T2sThreeReg<
777 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
778 opc, ".w\t$Rd, $Rn, $Rm",
779 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
780 let Inst{31-27} = 0b11111;
781 let Inst{26-23} = 0b0100;
782 let Inst{22-21} = opcod;
783 let Inst{15-12} = 0b1111;
784 let Inst{7-4} = 0b0000;
787 // Optional destination register
788 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
789 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
792 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
793 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
797 // Assembler aliases w/o the ".w" suffix.
798 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
799 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
802 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
803 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
807 // and with the optional destination operand, too.
808 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
809 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
812 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
813 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
818 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
819 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
820 /// a explicit result, only implicitly set CPSR.
821 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
822 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
823 PatFrag opnode, string baseOpc> {
824 let isCompare = 1, Defs = [CPSR] in {
826 def ri : T2OneRegCmpImm<
827 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
828 opc, ".w\t$Rn, $imm",
829 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
830 let Inst{31-27} = 0b11110;
832 let Inst{24-21} = opcod;
833 let Inst{20} = 1; // The S bit.
835 let Inst{11-8} = 0b1111; // Rd
838 def rr : T2TwoRegCmp<
839 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
841 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
842 let Inst{31-27} = 0b11101;
843 let Inst{26-25} = 0b01;
844 let Inst{24-21} = opcod;
845 let Inst{20} = 1; // The S bit.
846 let Inst{14-12} = 0b000; // imm3
847 let Inst{11-8} = 0b1111; // Rd
848 let Inst{7-6} = 0b00; // imm2
849 let Inst{5-4} = 0b00; // type
852 def rs : T2OneRegCmpShiftedReg<
853 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
854 opc, ".w\t$Rn, $ShiftedRm",
855 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
856 let Inst{31-27} = 0b11101;
857 let Inst{26-25} = 0b01;
858 let Inst{24-21} = opcod;
859 let Inst{20} = 1; // The S bit.
860 let Inst{11-8} = 0b1111; // Rd
864 // Assembler aliases w/o the ".w" suffix.
865 // No alias here for 'rr' version as not all instantiations of this
866 // multiclass want one (CMP in particular, does not).
867 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
868 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
869 t2_so_imm:$imm, pred:$p)>;
870 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
871 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
876 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
877 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
878 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
880 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
881 opc, ".w\t$Rt, $addr",
882 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
885 let Inst{31-25} = 0b1111100;
886 let Inst{24} = signed;
888 let Inst{22-21} = opcod;
889 let Inst{20} = 1; // load
890 let Inst{19-16} = addr{16-13}; // Rn
891 let Inst{15-12} = Rt;
892 let Inst{11-0} = addr{11-0}; // imm
894 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
896 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
899 let Inst{31-27} = 0b11111;
900 let Inst{26-25} = 0b00;
901 let Inst{24} = signed;
903 let Inst{22-21} = opcod;
904 let Inst{20} = 1; // load
905 let Inst{19-16} = addr{12-9}; // Rn
906 let Inst{15-12} = Rt;
908 // Offset: index==TRUE, wback==FALSE
909 let Inst{10} = 1; // The P bit.
910 let Inst{9} = addr{8}; // U
911 let Inst{8} = 0; // The W bit.
912 let Inst{7-0} = addr{7-0}; // imm
914 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
915 opc, ".w\t$Rt, $addr",
916 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
917 let Inst{31-27} = 0b11111;
918 let Inst{26-25} = 0b00;
919 let Inst{24} = signed;
921 let Inst{22-21} = opcod;
922 let Inst{20} = 1; // load
923 let Inst{11-6} = 0b000000;
926 let Inst{15-12} = Rt;
929 let Inst{19-16} = addr{9-6}; // Rn
930 let Inst{3-0} = addr{5-2}; // Rm
931 let Inst{5-4} = addr{1-0}; // imm
933 let DecoderMethod = "DecodeT2LoadShift";
936 // FIXME: Is the pci variant actually needed?
937 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
938 opc, ".w\t$Rt, $addr",
939 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
940 let isReMaterializable = 1;
941 let Inst{31-27} = 0b11111;
942 let Inst{26-25} = 0b00;
943 let Inst{24} = signed;
944 let Inst{23} = ?; // add = (U == '1')
945 let Inst{22-21} = opcod;
946 let Inst{20} = 1; // load
947 let Inst{19-16} = 0b1111; // Rn
950 let Inst{15-12} = Rt{3-0};
951 let Inst{11-0} = addr{11-0};
955 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
956 multiclass T2I_st<bits<2> opcod, string opc,
957 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
959 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
960 opc, ".w\t$Rt, $addr",
961 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
962 let Inst{31-27} = 0b11111;
963 let Inst{26-23} = 0b0001;
964 let Inst{22-21} = opcod;
965 let Inst{20} = 0; // !load
968 let Inst{15-12} = Rt;
971 let addr{12} = 1; // add = TRUE
972 let Inst{19-16} = addr{16-13}; // Rn
973 let Inst{23} = addr{12}; // U
974 let Inst{11-0} = addr{11-0}; // imm
976 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
978 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
979 let Inst{31-27} = 0b11111;
980 let Inst{26-23} = 0b0000;
981 let Inst{22-21} = opcod;
982 let Inst{20} = 0; // !load
984 // Offset: index==TRUE, wback==FALSE
985 let Inst{10} = 1; // The P bit.
986 let Inst{8} = 0; // The W bit.
989 let Inst{15-12} = Rt;
992 let Inst{19-16} = addr{12-9}; // Rn
993 let Inst{9} = addr{8}; // U
994 let Inst{7-0} = addr{7-0}; // imm
996 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
997 opc, ".w\t$Rt, $addr",
998 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
999 let Inst{31-27} = 0b11111;
1000 let Inst{26-23} = 0b0000;
1001 let Inst{22-21} = opcod;
1002 let Inst{20} = 0; // !load
1003 let Inst{11-6} = 0b000000;
1006 let Inst{15-12} = Rt;
1009 let Inst{19-16} = addr{9-6}; // Rn
1010 let Inst{3-0} = addr{5-2}; // Rm
1011 let Inst{5-4} = addr{1-0}; // imm
1015 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1016 /// register and one whose operand is a register rotated by 8/16/24.
1017 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1018 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1019 opc, ".w\t$Rd, $Rm$rot",
1020 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1021 Requires<[IsThumb2]> {
1022 let Inst{31-27} = 0b11111;
1023 let Inst{26-23} = 0b0100;
1024 let Inst{22-20} = opcod;
1025 let Inst{19-16} = 0b1111; // Rn
1026 let Inst{15-12} = 0b1111;
1030 let Inst{5-4} = rot{1-0}; // rotate
1033 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1034 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1035 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1036 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1037 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1038 Requires<[HasT2ExtractPack, IsThumb2]> {
1040 let Inst{31-27} = 0b11111;
1041 let Inst{26-23} = 0b0100;
1042 let Inst{22-20} = opcod;
1043 let Inst{19-16} = 0b1111; // Rn
1044 let Inst{15-12} = 0b1111;
1046 let Inst{5-4} = rot;
1049 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1051 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1052 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1053 opc, "\t$Rd, $Rm$rot", []>,
1054 Requires<[IsThumb2, HasT2ExtractPack]> {
1056 let Inst{31-27} = 0b11111;
1057 let Inst{26-23} = 0b0100;
1058 let Inst{22-20} = opcod;
1059 let Inst{19-16} = 0b1111; // Rn
1060 let Inst{15-12} = 0b1111;
1062 let Inst{5-4} = rot;
1065 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1066 /// register and one whose operand is a register rotated by 8/16/24.
1067 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1068 : T2ThreeReg<(outs rGPR:$Rd),
1069 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1070 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1071 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1072 Requires<[HasT2ExtractPack, IsThumb2]> {
1074 let Inst{31-27} = 0b11111;
1075 let Inst{26-23} = 0b0100;
1076 let Inst{22-20} = opcod;
1077 let Inst{15-12} = 0b1111;
1079 let Inst{5-4} = rot;
1082 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1083 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1084 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1086 let Inst{31-27} = 0b11111;
1087 let Inst{26-23} = 0b0100;
1088 let Inst{22-20} = opcod;
1089 let Inst{15-12} = 0b1111;
1091 let Inst{5-4} = rot;
1094 //===----------------------------------------------------------------------===//
1096 //===----------------------------------------------------------------------===//
1098 //===----------------------------------------------------------------------===//
1099 // Miscellaneous Instructions.
1102 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1103 string asm, list<dag> pattern>
1104 : T2XI<oops, iops, itin, asm, pattern> {
1108 let Inst{11-8} = Rd;
1109 let Inst{26} = label{11};
1110 let Inst{14-12} = label{10-8};
1111 let Inst{7-0} = label{7-0};
1114 // LEApcrel - Load a pc-relative address into a register without offending the
1116 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1117 (ins t2adrlabel:$addr, pred:$p),
1118 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1119 let Inst{31-27} = 0b11110;
1120 let Inst{25-24} = 0b10;
1121 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1124 let Inst{19-16} = 0b1111; // Rn
1129 let Inst{11-8} = Rd;
1130 let Inst{23} = addr{12};
1131 let Inst{21} = addr{12};
1132 let Inst{26} = addr{11};
1133 let Inst{14-12} = addr{10-8};
1134 let Inst{7-0} = addr{7-0};
1136 let DecoderMethod = "DecodeT2Adr";
1139 let neverHasSideEffects = 1, isReMaterializable = 1 in
1140 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1142 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1143 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1148 //===----------------------------------------------------------------------===//
1149 // Load / store Instructions.
1153 let canFoldAsLoad = 1, isReMaterializable = 1 in
1154 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1155 UnOpFrag<(load node:$Src)>>;
1157 // Loads with zero extension
1158 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1159 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1160 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1161 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1163 // Loads with sign extension
1164 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1165 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1166 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1167 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1169 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1171 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1172 (ins t2addrmode_imm8s4:$addr),
1173 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1174 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1176 // zextload i1 -> zextload i8
1177 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1178 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1179 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1180 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1181 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1182 (t2LDRBs t2addrmode_so_reg:$addr)>;
1183 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1184 (t2LDRBpci tconstpool:$addr)>;
1186 // extload -> zextload
1187 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1189 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1190 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1191 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1192 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1193 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1194 (t2LDRBs t2addrmode_so_reg:$addr)>;
1195 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1196 (t2LDRBpci tconstpool:$addr)>;
1198 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1199 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1200 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1201 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1202 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1203 (t2LDRBs t2addrmode_so_reg:$addr)>;
1204 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1205 (t2LDRBpci tconstpool:$addr)>;
1207 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1208 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1209 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1210 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1211 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1212 (t2LDRHs t2addrmode_so_reg:$addr)>;
1213 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1214 (t2LDRHpci tconstpool:$addr)>;
1216 // FIXME: The destination register of the loads and stores can't be PC, but
1217 // can be SP. We need another regclass (similar to rGPR) to represent
1218 // that. Not a pressing issue since these are selected manually,
1223 let mayLoad = 1, neverHasSideEffects = 1 in {
1224 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1225 (ins t2addrmode_imm8:$addr),
1226 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1227 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1229 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1232 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1233 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1234 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1235 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1237 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1238 (ins t2addrmode_imm8:$addr),
1239 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1240 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1242 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1244 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1245 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1246 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1247 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1249 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1250 (ins t2addrmode_imm8:$addr),
1251 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1252 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1254 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1256 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1257 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1258 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1259 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1261 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1262 (ins t2addrmode_imm8:$addr),
1263 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1264 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1266 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1268 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1269 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1270 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1271 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1273 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1274 (ins t2addrmode_imm8:$addr),
1275 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1276 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1278 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1280 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1281 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1282 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1283 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1284 } // mayLoad = 1, neverHasSideEffects = 1
1286 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1287 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1288 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1289 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1290 "\t$Rt, $addr", []> {
1293 let Inst{31-27} = 0b11111;
1294 let Inst{26-25} = 0b00;
1295 let Inst{24} = signed;
1297 let Inst{22-21} = type;
1298 let Inst{20} = 1; // load
1299 let Inst{19-16} = addr{12-9};
1300 let Inst{15-12} = Rt;
1302 let Inst{10-8} = 0b110; // PUW.
1303 let Inst{7-0} = addr{7-0};
1306 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1307 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1308 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1309 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1310 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1313 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1314 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1315 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1316 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1317 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1318 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1321 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1322 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1323 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1324 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1328 let mayStore = 1, neverHasSideEffects = 1 in {
1329 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1330 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1331 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1332 "str", "\t$Rt, $addr!",
1333 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1334 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1336 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1337 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1338 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1339 "strh", "\t$Rt, $addr!",
1340 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1341 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1344 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1345 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1346 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1347 "strb", "\t$Rt, $addr!",
1348 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1349 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1351 } // mayStore = 1, neverHasSideEffects = 1
1353 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1354 (ins rGPR:$Rt, addr_offset_none:$Rn,
1355 t2am_imm8_offset:$offset),
1356 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1357 "str", "\t$Rt, $Rn$offset",
1358 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1359 [(set GPRnopc:$Rn_wb,
1360 (post_store rGPR:$Rt, addr_offset_none:$Rn,
1361 t2am_imm8_offset:$offset))]>;
1363 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1364 (ins rGPR:$Rt, addr_offset_none:$Rn,
1365 t2am_imm8_offset:$offset),
1366 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1367 "strh", "\t$Rt, $Rn$offset",
1368 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1369 [(set GPRnopc:$Rn_wb,
1370 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1371 t2am_imm8_offset:$offset))]>;
1373 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1374 (ins rGPR:$Rt, addr_offset_none:$Rn,
1375 t2am_imm8_offset:$offset),
1376 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1377 "strb", "\t$Rt, $Rn$offset",
1378 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1379 [(set GPRnopc:$Rn_wb,
1380 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1381 t2am_imm8_offset:$offset))]>;
1383 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1384 // put the patterns on the instruction definitions directly as ISel wants
1385 // the address base and offset to be separate operands, not a single
1386 // complex operand like we represent the instructions themselves. The
1387 // pseudos map between the two.
1388 let usesCustomInserter = 1,
1389 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1390 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1391 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1393 [(set GPRnopc:$Rn_wb,
1394 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1395 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1396 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1398 [(set GPRnopc:$Rn_wb,
1399 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1400 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1401 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1403 [(set GPRnopc:$Rn_wb,
1404 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1407 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1409 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1410 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1411 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1412 "\t$Rt, $addr", []> {
1413 let Inst{31-27} = 0b11111;
1414 let Inst{26-25} = 0b00;
1415 let Inst{24} = 0; // not signed
1417 let Inst{22-21} = type;
1418 let Inst{20} = 0; // store
1420 let Inst{10-8} = 0b110; // PUW
1424 let Inst{15-12} = Rt;
1425 let Inst{19-16} = addr{12-9};
1426 let Inst{7-0} = addr{7-0};
1429 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1430 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1431 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1433 // ldrd / strd pre / post variants
1434 // For disassembly only.
1436 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1437 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1438 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1439 let AsmMatchConverter = "cvtT2LdrdPre";
1440 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1443 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1444 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1445 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1446 "$addr.base = $wb", []>;
1448 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1449 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1450 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1451 "$addr.base = $wb", []> {
1452 let AsmMatchConverter = "cvtT2StrdPre";
1453 let DecoderMethod = "DecodeT2STRDPreInstruction";
1456 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1457 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1458 t2am_imm8s4_offset:$imm),
1459 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1460 "$addr.base = $wb", []>;
1462 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1463 // data/instruction access. These are for disassembly only.
1464 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1465 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1466 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1468 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1470 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1471 let Inst{31-25} = 0b1111100;
1472 let Inst{24} = instr;
1474 let Inst{21} = write;
1476 let Inst{15-12} = 0b1111;
1479 let addr{12} = 1; // add = TRUE
1480 let Inst{19-16} = addr{16-13}; // Rn
1481 let Inst{23} = addr{12}; // U
1482 let Inst{11-0} = addr{11-0}; // imm12
1485 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1487 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1488 let Inst{31-25} = 0b1111100;
1489 let Inst{24} = instr;
1490 let Inst{23} = 0; // U = 0
1492 let Inst{21} = write;
1494 let Inst{15-12} = 0b1111;
1495 let Inst{11-8} = 0b1100;
1498 let Inst{19-16} = addr{12-9}; // Rn
1499 let Inst{7-0} = addr{7-0}; // imm8
1502 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1504 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1505 let Inst{31-25} = 0b1111100;
1506 let Inst{24} = instr;
1507 let Inst{23} = 0; // add = TRUE for T1
1509 let Inst{21} = write;
1511 let Inst{15-12} = 0b1111;
1512 let Inst{11-6} = 0000000;
1515 let Inst{19-16} = addr{9-6}; // Rn
1516 let Inst{3-0} = addr{5-2}; // Rm
1517 let Inst{5-4} = addr{1-0}; // imm2
1519 let DecoderMethod = "DecodeT2LoadShift";
1523 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1524 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1525 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1527 //===----------------------------------------------------------------------===//
1528 // Load / store multiple Instructions.
1531 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1532 InstrItinClass itin_upd, bit L_bit> {
1534 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1535 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1539 let Inst{31-27} = 0b11101;
1540 let Inst{26-25} = 0b00;
1541 let Inst{24-23} = 0b01; // Increment After
1543 let Inst{21} = 0; // No writeback
1544 let Inst{20} = L_bit;
1545 let Inst{19-16} = Rn;
1547 let Inst{14-0} = regs{14-0};
1550 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1551 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1555 let Inst{31-27} = 0b11101;
1556 let Inst{26-25} = 0b00;
1557 let Inst{24-23} = 0b01; // Increment After
1559 let Inst{21} = 1; // Writeback
1560 let Inst{20} = L_bit;
1561 let Inst{19-16} = Rn;
1563 let Inst{14-0} = regs{14-0};
1566 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1567 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1571 let Inst{31-27} = 0b11101;
1572 let Inst{26-25} = 0b00;
1573 let Inst{24-23} = 0b10; // Decrement Before
1575 let Inst{21} = 0; // No writeback
1576 let Inst{20} = L_bit;
1577 let Inst{19-16} = Rn;
1579 let Inst{14-0} = regs{14-0};
1582 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1583 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1587 let Inst{31-27} = 0b11101;
1588 let Inst{26-25} = 0b00;
1589 let Inst{24-23} = 0b10; // Decrement Before
1591 let Inst{21} = 1; // Writeback
1592 let Inst{20} = L_bit;
1593 let Inst{19-16} = Rn;
1595 let Inst{14-0} = regs{14-0};
1599 let neverHasSideEffects = 1 in {
1601 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1602 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1604 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1605 InstrItinClass itin_upd, bit L_bit> {
1607 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1608 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1612 let Inst{31-27} = 0b11101;
1613 let Inst{26-25} = 0b00;
1614 let Inst{24-23} = 0b01; // Increment After
1616 let Inst{21} = 0; // No writeback
1617 let Inst{20} = L_bit;
1618 let Inst{19-16} = Rn;
1620 let Inst{14} = regs{14};
1622 let Inst{12-0} = regs{12-0};
1625 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1626 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1630 let Inst{31-27} = 0b11101;
1631 let Inst{26-25} = 0b00;
1632 let Inst{24-23} = 0b01; // Increment After
1634 let Inst{21} = 1; // Writeback
1635 let Inst{20} = L_bit;
1636 let Inst{19-16} = Rn;
1638 let Inst{14} = regs{14};
1640 let Inst{12-0} = regs{12-0};
1643 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1644 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1648 let Inst{31-27} = 0b11101;
1649 let Inst{26-25} = 0b00;
1650 let Inst{24-23} = 0b10; // Decrement Before
1652 let Inst{21} = 0; // No writeback
1653 let Inst{20} = L_bit;
1654 let Inst{19-16} = Rn;
1656 let Inst{14} = regs{14};
1658 let Inst{12-0} = regs{12-0};
1661 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1662 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1666 let Inst{31-27} = 0b11101;
1667 let Inst{26-25} = 0b00;
1668 let Inst{24-23} = 0b10; // Decrement Before
1670 let Inst{21} = 1; // Writeback
1671 let Inst{20} = L_bit;
1672 let Inst{19-16} = Rn;
1674 let Inst{14} = regs{14};
1676 let Inst{12-0} = regs{12-0};
1681 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1682 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1684 } // neverHasSideEffects
1687 //===----------------------------------------------------------------------===//
1688 // Move Instructions.
1691 let neverHasSideEffects = 1 in
1692 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1693 "mov", ".w\t$Rd, $Rm", []> {
1694 let Inst{31-27} = 0b11101;
1695 let Inst{26-25} = 0b01;
1696 let Inst{24-21} = 0b0010;
1697 let Inst{19-16} = 0b1111; // Rn
1698 let Inst{14-12} = 0b000;
1699 let Inst{7-4} = 0b0000;
1701 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1702 pred:$p, zero_reg)>;
1703 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1705 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1708 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1709 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1710 AddedComplexity = 1 in
1711 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1712 "mov", ".w\t$Rd, $imm",
1713 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1714 let Inst{31-27} = 0b11110;
1716 let Inst{24-21} = 0b0010;
1717 let Inst{19-16} = 0b1111; // Rn
1721 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1722 // Use aliases to get that to play nice here.
1723 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1725 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1728 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1729 pred:$p, zero_reg)>;
1730 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1731 pred:$p, zero_reg)>;
1733 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1734 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1735 "movw", "\t$Rd, $imm",
1736 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1737 let Inst{31-27} = 0b11110;
1739 let Inst{24-21} = 0b0010;
1740 let Inst{20} = 0; // The S bit.
1746 let Inst{11-8} = Rd;
1747 let Inst{19-16} = imm{15-12};
1748 let Inst{26} = imm{11};
1749 let Inst{14-12} = imm{10-8};
1750 let Inst{7-0} = imm{7-0};
1751 let DecoderMethod = "DecodeT2MOVTWInstruction";
1754 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1755 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1757 let Constraints = "$src = $Rd" in {
1758 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1759 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1760 "movt", "\t$Rd, $imm",
1762 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1763 let Inst{31-27} = 0b11110;
1765 let Inst{24-21} = 0b0110;
1766 let Inst{20} = 0; // The S bit.
1772 let Inst{11-8} = Rd;
1773 let Inst{19-16} = imm{15-12};
1774 let Inst{26} = imm{11};
1775 let Inst{14-12} = imm{10-8};
1776 let Inst{7-0} = imm{7-0};
1777 let DecoderMethod = "DecodeT2MOVTWInstruction";
1780 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1781 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1784 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1786 //===----------------------------------------------------------------------===//
1787 // Extend Instructions.
1792 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1793 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1794 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1795 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1796 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1798 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1799 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1800 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1801 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1802 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1806 let AddedComplexity = 16 in {
1807 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1808 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1809 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1810 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1811 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1812 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1814 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1815 // The transformation should probably be done as a combiner action
1816 // instead so we can include a check for masking back in the upper
1817 // eight bits of the source into the lower eight bits of the result.
1818 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1819 // (t2UXTB16 rGPR:$Src, 3)>,
1820 // Requires<[HasT2ExtractPack, IsThumb2]>;
1821 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1822 (t2UXTB16 rGPR:$Src, 1)>,
1823 Requires<[HasT2ExtractPack, IsThumb2]>;
1825 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1826 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1827 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1828 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1829 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1832 //===----------------------------------------------------------------------===//
1833 // Arithmetic Instructions.
1836 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1837 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1838 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1839 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1841 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1843 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1844 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1845 // AdjustInstrPostInstrSelection where we determine whether or not to
1846 // set the "s" bit based on CPSR liveness.
1848 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1849 // support for an optional CPSR definition that corresponds to the DAG
1850 // node's second value. We can then eliminate the implicit def of CPSR.
1851 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1852 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1853 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1854 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1856 let hasPostISelHook = 1 in {
1857 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1858 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1859 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1860 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1864 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1865 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1867 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1868 // CPSR and the implicit def of CPSR is not needed.
1869 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1871 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1872 // The assume-no-carry-in form uses the negation of the input since add/sub
1873 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1874 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1876 // The AddedComplexity preferences the first variant over the others since
1877 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1878 let AddedComplexity = 1 in
1879 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1880 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1881 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1882 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1883 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1884 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1885 let AddedComplexity = 1 in
1886 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1887 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1888 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1889 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1890 // The with-carry-in form matches bitwise not instead of the negation.
1891 // Effectively, the inverse interpretation of the carry flag already accounts
1892 // for part of the negation.
1893 let AddedComplexity = 1 in
1894 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1895 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1896 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1897 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1899 // Select Bytes -- for disassembly only
1901 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1902 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1903 Requires<[IsThumb2, HasThumb2DSP]> {
1904 let Inst{31-27} = 0b11111;
1905 let Inst{26-24} = 0b010;
1907 let Inst{22-20} = 0b010;
1908 let Inst{15-12} = 0b1111;
1910 let Inst{6-4} = 0b000;
1913 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1914 // And Miscellaneous operations -- for disassembly only
1915 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1916 list<dag> pat = [/* For disassembly only; pattern left blank */],
1917 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1918 string asm = "\t$Rd, $Rn, $Rm">
1919 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1920 Requires<[IsThumb2, HasThumb2DSP]> {
1921 let Inst{31-27} = 0b11111;
1922 let Inst{26-23} = 0b0101;
1923 let Inst{22-20} = op22_20;
1924 let Inst{15-12} = 0b1111;
1925 let Inst{7-4} = op7_4;
1931 let Inst{11-8} = Rd;
1932 let Inst{19-16} = Rn;
1936 // Saturating add/subtract -- for disassembly only
1938 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1939 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1940 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1941 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1942 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1943 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1944 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1945 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1946 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1947 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1948 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1949 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1950 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1951 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1952 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1953 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1954 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1955 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1956 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1957 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1958 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1959 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1961 // Signed/Unsigned add/subtract -- for disassembly only
1963 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1964 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1965 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1966 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1967 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1968 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1969 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1970 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1971 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1972 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1973 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1974 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1976 // Signed/Unsigned halving add/subtract -- for disassembly only
1978 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1979 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1980 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1981 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1982 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1983 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1984 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1985 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1986 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1987 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1988 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1989 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1991 // Helper class for disassembly only
1992 // A6.3.16 & A6.3.17
1993 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1994 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1995 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1996 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1997 let Inst{31-27} = 0b11111;
1998 let Inst{26-24} = 0b011;
1999 let Inst{23} = long;
2000 let Inst{22-20} = op22_20;
2001 let Inst{7-4} = op7_4;
2004 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2005 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2006 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2007 let Inst{31-27} = 0b11111;
2008 let Inst{26-24} = 0b011;
2009 let Inst{23} = long;
2010 let Inst{22-20} = op22_20;
2011 let Inst{7-4} = op7_4;
2014 // Unsigned Sum of Absolute Differences [and Accumulate].
2015 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2016 (ins rGPR:$Rn, rGPR:$Rm),
2017 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2018 Requires<[IsThumb2, HasThumb2DSP]> {
2019 let Inst{15-12} = 0b1111;
2021 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2022 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2023 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2024 Requires<[IsThumb2, HasThumb2DSP]>;
2026 // Signed/Unsigned saturate.
2027 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2028 string opc, string asm, list<dag> pattern>
2029 : T2I<oops, iops, itin, opc, asm, pattern> {
2035 let Inst{11-8} = Rd;
2036 let Inst{19-16} = Rn;
2037 let Inst{4-0} = sat_imm;
2038 let Inst{21} = sh{5};
2039 let Inst{14-12} = sh{4-2};
2040 let Inst{7-6} = sh{1-0};
2045 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2046 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2047 let Inst{31-27} = 0b11110;
2048 let Inst{25-22} = 0b1100;
2054 def t2SSAT16: T2SatI<
2055 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2056 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2057 Requires<[IsThumb2, HasThumb2DSP]> {
2058 let Inst{31-27} = 0b11110;
2059 let Inst{25-22} = 0b1100;
2062 let Inst{21} = 1; // sh = '1'
2063 let Inst{14-12} = 0b000; // imm3 = '000'
2064 let Inst{7-6} = 0b00; // imm2 = '00'
2065 let Inst{5-4} = 0b00;
2070 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2071 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2072 let Inst{31-27} = 0b11110;
2073 let Inst{25-22} = 0b1110;
2078 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2080 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2081 Requires<[IsThumb2, HasThumb2DSP]> {
2082 let Inst{31-22} = 0b1111001110;
2085 let Inst{21} = 1; // sh = '1'
2086 let Inst{14-12} = 0b000; // imm3 = '000'
2087 let Inst{7-6} = 0b00; // imm2 = '00'
2088 let Inst{5-4} = 0b00;
2091 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2092 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2094 //===----------------------------------------------------------------------===//
2095 // Shift and rotate Instructions.
2098 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2099 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2100 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2101 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2102 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2103 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2104 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2105 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2107 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2108 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2109 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2111 let Uses = [CPSR] in {
2112 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2113 "rrx", "\t$Rd, $Rm",
2114 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2115 let Inst{31-27} = 0b11101;
2116 let Inst{26-25} = 0b01;
2117 let Inst{24-21} = 0b0010;
2118 let Inst{19-16} = 0b1111; // Rn
2119 let Inst{14-12} = 0b000;
2120 let Inst{7-4} = 0b0011;
2124 let isCodeGenOnly = 1, Defs = [CPSR] in {
2125 def t2MOVsrl_flag : T2TwoRegShiftImm<
2126 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2127 "lsrs", ".w\t$Rd, $Rm, #1",
2128 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2129 let Inst{31-27} = 0b11101;
2130 let Inst{26-25} = 0b01;
2131 let Inst{24-21} = 0b0010;
2132 let Inst{20} = 1; // The S bit.
2133 let Inst{19-16} = 0b1111; // Rn
2134 let Inst{5-4} = 0b01; // Shift type.
2135 // Shift amount = Inst{14-12:7-6} = 1.
2136 let Inst{14-12} = 0b000;
2137 let Inst{7-6} = 0b01;
2139 def t2MOVsra_flag : T2TwoRegShiftImm<
2140 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2141 "asrs", ".w\t$Rd, $Rm, #1",
2142 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2143 let Inst{31-27} = 0b11101;
2144 let Inst{26-25} = 0b01;
2145 let Inst{24-21} = 0b0010;
2146 let Inst{20} = 1; // The S bit.
2147 let Inst{19-16} = 0b1111; // Rn
2148 let Inst{5-4} = 0b10; // Shift type.
2149 // Shift amount = Inst{14-12:7-6} = 1.
2150 let Inst{14-12} = 0b000;
2151 let Inst{7-6} = 0b01;
2155 //===----------------------------------------------------------------------===//
2156 // Bitwise Instructions.
2159 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2160 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2161 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2162 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2163 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2164 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2165 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2166 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2167 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2169 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2170 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2171 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2174 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2175 string opc, string asm, list<dag> pattern>
2176 : T2I<oops, iops, itin, opc, asm, pattern> {
2181 let Inst{11-8} = Rd;
2182 let Inst{4-0} = msb{4-0};
2183 let Inst{14-12} = lsb{4-2};
2184 let Inst{7-6} = lsb{1-0};
2187 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2188 string opc, string asm, list<dag> pattern>
2189 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2192 let Inst{19-16} = Rn;
2195 let Constraints = "$src = $Rd" in
2196 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2197 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2198 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2199 let Inst{31-27} = 0b11110;
2200 let Inst{26} = 0; // should be 0.
2202 let Inst{24-20} = 0b10110;
2203 let Inst{19-16} = 0b1111; // Rn
2205 let Inst{5} = 0; // should be 0.
2208 let msb{4-0} = imm{9-5};
2209 let lsb{4-0} = imm{4-0};
2212 def t2SBFX: T2TwoRegBitFI<
2213 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2214 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2215 let Inst{31-27} = 0b11110;
2217 let Inst{24-20} = 0b10100;
2221 def t2UBFX: T2TwoRegBitFI<
2222 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2223 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2224 let Inst{31-27} = 0b11110;
2226 let Inst{24-20} = 0b11100;
2230 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2231 let Constraints = "$src = $Rd" in {
2232 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2233 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2234 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2235 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2236 bf_inv_mask_imm:$imm))]> {
2237 let Inst{31-27} = 0b11110;
2238 let Inst{26} = 0; // should be 0.
2240 let Inst{24-20} = 0b10110;
2242 let Inst{5} = 0; // should be 0.
2245 let msb{4-0} = imm{9-5};
2246 let lsb{4-0} = imm{4-0};
2250 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2251 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2252 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2255 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2256 /// unary operation that produces a value. These are predicable and can be
2257 /// changed to modify CPSR.
2258 multiclass T2I_un_irs<bits<4> opcod, string opc,
2259 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2260 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2262 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2264 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2265 let isAsCheapAsAMove = Cheap;
2266 let isReMaterializable = ReMat;
2267 let Inst{31-27} = 0b11110;
2269 let Inst{24-21} = opcod;
2270 let Inst{19-16} = 0b1111; // Rn
2274 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2275 opc, ".w\t$Rd, $Rm",
2276 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2277 let Inst{31-27} = 0b11101;
2278 let Inst{26-25} = 0b01;
2279 let Inst{24-21} = opcod;
2280 let Inst{19-16} = 0b1111; // Rn
2281 let Inst{14-12} = 0b000; // imm3
2282 let Inst{7-6} = 0b00; // imm2
2283 let Inst{5-4} = 0b00; // type
2286 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2287 opc, ".w\t$Rd, $ShiftedRm",
2288 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2289 let Inst{31-27} = 0b11101;
2290 let Inst{26-25} = 0b01;
2291 let Inst{24-21} = opcod;
2292 let Inst{19-16} = 0b1111; // Rn
2296 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2297 let AddedComplexity = 1 in
2298 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2299 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2300 UnOpFrag<(not node:$Src)>, 1, 1>;
2302 let AddedComplexity = 1 in
2303 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2304 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2306 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2307 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2308 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2309 Requires<[IsThumb2]>;
2311 def : T2Pat<(t2_so_imm_not:$src),
2312 (t2MVNi t2_so_imm_not:$src)>;
2314 //===----------------------------------------------------------------------===//
2315 // Multiply Instructions.
2317 let isCommutable = 1 in
2318 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2319 "mul", "\t$Rd, $Rn, $Rm",
2320 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2321 let Inst{31-27} = 0b11111;
2322 let Inst{26-23} = 0b0110;
2323 let Inst{22-20} = 0b000;
2324 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2325 let Inst{7-4} = 0b0000; // Multiply
2328 def t2MLA: T2FourReg<
2329 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2330 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2331 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2332 let Inst{31-27} = 0b11111;
2333 let Inst{26-23} = 0b0110;
2334 let Inst{22-20} = 0b000;
2335 let Inst{7-4} = 0b0000; // Multiply
2338 def t2MLS: T2FourReg<
2339 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2340 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2341 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2342 let Inst{31-27} = 0b11111;
2343 let Inst{26-23} = 0b0110;
2344 let Inst{22-20} = 0b000;
2345 let Inst{7-4} = 0b0001; // Multiply and Subtract
2348 // Extra precision multiplies with low / high results
2349 let neverHasSideEffects = 1 in {
2350 let isCommutable = 1 in {
2351 def t2SMULL : T2MulLong<0b000, 0b0000,
2352 (outs rGPR:$RdLo, rGPR:$RdHi),
2353 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2354 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2356 def t2UMULL : T2MulLong<0b010, 0b0000,
2357 (outs rGPR:$RdLo, rGPR:$RdHi),
2358 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2359 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2362 // Multiply + accumulate
2363 def t2SMLAL : T2MulLong<0b100, 0b0000,
2364 (outs rGPR:$RdLo, rGPR:$RdHi),
2365 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2366 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2368 def t2UMLAL : T2MulLong<0b110, 0b0000,
2369 (outs rGPR:$RdLo, rGPR:$RdHi),
2370 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2371 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2373 def t2UMAAL : T2MulLong<0b110, 0b0110,
2374 (outs rGPR:$RdLo, rGPR:$RdHi),
2375 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2376 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2377 Requires<[IsThumb2, HasThumb2DSP]>;
2378 } // neverHasSideEffects
2380 // Rounding variants of the below included for disassembly only
2382 // Most significant word multiply
2383 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2384 "smmul", "\t$Rd, $Rn, $Rm",
2385 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2386 Requires<[IsThumb2, HasThumb2DSP]> {
2387 let Inst{31-27} = 0b11111;
2388 let Inst{26-23} = 0b0110;
2389 let Inst{22-20} = 0b101;
2390 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2391 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2394 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2395 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2396 Requires<[IsThumb2, HasThumb2DSP]> {
2397 let Inst{31-27} = 0b11111;
2398 let Inst{26-23} = 0b0110;
2399 let Inst{22-20} = 0b101;
2400 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2401 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2404 def t2SMMLA : T2FourReg<
2405 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2406 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2407 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2408 Requires<[IsThumb2, HasThumb2DSP]> {
2409 let Inst{31-27} = 0b11111;
2410 let Inst{26-23} = 0b0110;
2411 let Inst{22-20} = 0b101;
2412 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2415 def t2SMMLAR: T2FourReg<
2416 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2417 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2418 Requires<[IsThumb2, HasThumb2DSP]> {
2419 let Inst{31-27} = 0b11111;
2420 let Inst{26-23} = 0b0110;
2421 let Inst{22-20} = 0b101;
2422 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2425 def t2SMMLS: T2FourReg<
2426 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2427 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2428 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2429 Requires<[IsThumb2, HasThumb2DSP]> {
2430 let Inst{31-27} = 0b11111;
2431 let Inst{26-23} = 0b0110;
2432 let Inst{22-20} = 0b110;
2433 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2436 def t2SMMLSR:T2FourReg<
2437 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2438 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2439 Requires<[IsThumb2, HasThumb2DSP]> {
2440 let Inst{31-27} = 0b11111;
2441 let Inst{26-23} = 0b0110;
2442 let Inst{22-20} = 0b110;
2443 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2446 multiclass T2I_smul<string opc, PatFrag opnode> {
2447 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2448 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2449 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2450 (sext_inreg rGPR:$Rm, i16)))]>,
2451 Requires<[IsThumb2, HasThumb2DSP]> {
2452 let Inst{31-27} = 0b11111;
2453 let Inst{26-23} = 0b0110;
2454 let Inst{22-20} = 0b001;
2455 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2456 let Inst{7-6} = 0b00;
2457 let Inst{5-4} = 0b00;
2460 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2461 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2462 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2463 (sra rGPR:$Rm, (i32 16))))]>,
2464 Requires<[IsThumb2, HasThumb2DSP]> {
2465 let Inst{31-27} = 0b11111;
2466 let Inst{26-23} = 0b0110;
2467 let Inst{22-20} = 0b001;
2468 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2469 let Inst{7-6} = 0b00;
2470 let Inst{5-4} = 0b01;
2473 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2474 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2475 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2476 (sext_inreg rGPR:$Rm, i16)))]>,
2477 Requires<[IsThumb2, HasThumb2DSP]> {
2478 let Inst{31-27} = 0b11111;
2479 let Inst{26-23} = 0b0110;
2480 let Inst{22-20} = 0b001;
2481 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2482 let Inst{7-6} = 0b00;
2483 let Inst{5-4} = 0b10;
2486 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2487 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2488 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2489 (sra rGPR:$Rm, (i32 16))))]>,
2490 Requires<[IsThumb2, HasThumb2DSP]> {
2491 let Inst{31-27} = 0b11111;
2492 let Inst{26-23} = 0b0110;
2493 let Inst{22-20} = 0b001;
2494 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2495 let Inst{7-6} = 0b00;
2496 let Inst{5-4} = 0b11;
2499 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2500 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2501 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2502 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2503 Requires<[IsThumb2, HasThumb2DSP]> {
2504 let Inst{31-27} = 0b11111;
2505 let Inst{26-23} = 0b0110;
2506 let Inst{22-20} = 0b011;
2507 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2508 let Inst{7-6} = 0b00;
2509 let Inst{5-4} = 0b00;
2512 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2513 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2514 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2515 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2516 Requires<[IsThumb2, HasThumb2DSP]> {
2517 let Inst{31-27} = 0b11111;
2518 let Inst{26-23} = 0b0110;
2519 let Inst{22-20} = 0b011;
2520 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2521 let Inst{7-6} = 0b00;
2522 let Inst{5-4} = 0b01;
2527 multiclass T2I_smla<string opc, PatFrag opnode> {
2529 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2530 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2531 [(set rGPR:$Rd, (add rGPR:$Ra,
2532 (opnode (sext_inreg rGPR:$Rn, i16),
2533 (sext_inreg rGPR:$Rm, i16))))]>,
2534 Requires<[IsThumb2, HasThumb2DSP]> {
2535 let Inst{31-27} = 0b11111;
2536 let Inst{26-23} = 0b0110;
2537 let Inst{22-20} = 0b001;
2538 let Inst{7-6} = 0b00;
2539 let Inst{5-4} = 0b00;
2543 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2544 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2545 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2546 (sra rGPR:$Rm, (i32 16)))))]>,
2547 Requires<[IsThumb2, HasThumb2DSP]> {
2548 let Inst{31-27} = 0b11111;
2549 let Inst{26-23} = 0b0110;
2550 let Inst{22-20} = 0b001;
2551 let Inst{7-6} = 0b00;
2552 let Inst{5-4} = 0b01;
2556 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2557 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2558 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2559 (sext_inreg rGPR:$Rm, i16))))]>,
2560 Requires<[IsThumb2, HasThumb2DSP]> {
2561 let Inst{31-27} = 0b11111;
2562 let Inst{26-23} = 0b0110;
2563 let Inst{22-20} = 0b001;
2564 let Inst{7-6} = 0b00;
2565 let Inst{5-4} = 0b10;
2569 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2570 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2571 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2572 (sra rGPR:$Rm, (i32 16)))))]>,
2573 Requires<[IsThumb2, HasThumb2DSP]> {
2574 let Inst{31-27} = 0b11111;
2575 let Inst{26-23} = 0b0110;
2576 let Inst{22-20} = 0b001;
2577 let Inst{7-6} = 0b00;
2578 let Inst{5-4} = 0b11;
2582 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2583 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2584 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2585 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2586 Requires<[IsThumb2, HasThumb2DSP]> {
2587 let Inst{31-27} = 0b11111;
2588 let Inst{26-23} = 0b0110;
2589 let Inst{22-20} = 0b011;
2590 let Inst{7-6} = 0b00;
2591 let Inst{5-4} = 0b00;
2595 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2596 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2597 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2598 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2599 Requires<[IsThumb2, HasThumb2DSP]> {
2600 let Inst{31-27} = 0b11111;
2601 let Inst{26-23} = 0b0110;
2602 let Inst{22-20} = 0b011;
2603 let Inst{7-6} = 0b00;
2604 let Inst{5-4} = 0b01;
2608 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2609 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2611 // Halfword multiple accumulate long: SMLAL<x><y>
2612 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2613 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2614 [/* For disassembly only; pattern left blank */]>,
2615 Requires<[IsThumb2, HasThumb2DSP]>;
2616 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2617 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2618 [/* For disassembly only; pattern left blank */]>,
2619 Requires<[IsThumb2, HasThumb2DSP]>;
2620 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2621 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2622 [/* For disassembly only; pattern left blank */]>,
2623 Requires<[IsThumb2, HasThumb2DSP]>;
2624 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2625 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2626 [/* For disassembly only; pattern left blank */]>,
2627 Requires<[IsThumb2, HasThumb2DSP]>;
2629 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2630 def t2SMUAD: T2ThreeReg_mac<
2631 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2632 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2633 Requires<[IsThumb2, HasThumb2DSP]> {
2634 let Inst{15-12} = 0b1111;
2636 def t2SMUADX:T2ThreeReg_mac<
2637 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2638 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2639 Requires<[IsThumb2, HasThumb2DSP]> {
2640 let Inst{15-12} = 0b1111;
2642 def t2SMUSD: T2ThreeReg_mac<
2643 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2644 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2645 Requires<[IsThumb2, HasThumb2DSP]> {
2646 let Inst{15-12} = 0b1111;
2648 def t2SMUSDX:T2ThreeReg_mac<
2649 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2650 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2651 Requires<[IsThumb2, HasThumb2DSP]> {
2652 let Inst{15-12} = 0b1111;
2654 def t2SMLAD : T2FourReg_mac<
2655 0, 0b010, 0b0000, (outs rGPR:$Rd),
2656 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2657 "\t$Rd, $Rn, $Rm, $Ra", []>,
2658 Requires<[IsThumb2, HasThumb2DSP]>;
2659 def t2SMLADX : T2FourReg_mac<
2660 0, 0b010, 0b0001, (outs rGPR:$Rd),
2661 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2662 "\t$Rd, $Rn, $Rm, $Ra", []>,
2663 Requires<[IsThumb2, HasThumb2DSP]>;
2664 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2665 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2666 "\t$Rd, $Rn, $Rm, $Ra", []>,
2667 Requires<[IsThumb2, HasThumb2DSP]>;
2668 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2669 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2670 "\t$Rd, $Rn, $Rm, $Ra", []>,
2671 Requires<[IsThumb2, HasThumb2DSP]>;
2672 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2673 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2674 "\t$Ra, $Rd, $Rn, $Rm", []>,
2675 Requires<[IsThumb2, HasThumb2DSP]>;
2676 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2677 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2678 "\t$Ra, $Rd, $Rn, $Rm", []>,
2679 Requires<[IsThumb2, HasThumb2DSP]>;
2680 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2681 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2682 "\t$Ra, $Rd, $Rn, $Rm", []>,
2683 Requires<[IsThumb2, HasThumb2DSP]>;
2684 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2685 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2686 "\t$Ra, $Rd, $Rn, $Rm", []>,
2687 Requires<[IsThumb2, HasThumb2DSP]>;
2689 //===----------------------------------------------------------------------===//
2690 // Division Instructions.
2691 // Signed and unsigned division on v7-M
2693 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2694 "sdiv", "\t$Rd, $Rn, $Rm",
2695 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2696 Requires<[HasDivide, IsThumb2]> {
2697 let Inst{31-27} = 0b11111;
2698 let Inst{26-21} = 0b011100;
2700 let Inst{15-12} = 0b1111;
2701 let Inst{7-4} = 0b1111;
2704 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2705 "udiv", "\t$Rd, $Rn, $Rm",
2706 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2707 Requires<[HasDivide, IsThumb2]> {
2708 let Inst{31-27} = 0b11111;
2709 let Inst{26-21} = 0b011101;
2711 let Inst{15-12} = 0b1111;
2712 let Inst{7-4} = 0b1111;
2715 //===----------------------------------------------------------------------===//
2716 // Misc. Arithmetic Instructions.
2719 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2720 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2721 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2722 let Inst{31-27} = 0b11111;
2723 let Inst{26-22} = 0b01010;
2724 let Inst{21-20} = op1;
2725 let Inst{15-12} = 0b1111;
2726 let Inst{7-6} = 0b10;
2727 let Inst{5-4} = op2;
2731 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2732 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2734 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2735 "rbit", "\t$Rd, $Rm",
2736 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2738 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2739 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2741 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2742 "rev16", ".w\t$Rd, $Rm",
2743 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2745 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2746 "revsh", ".w\t$Rd, $Rm",
2747 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2749 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2750 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2751 (t2REVSH rGPR:$Rm)>;
2753 def t2PKHBT : T2ThreeReg<
2754 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2755 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2756 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2757 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2759 Requires<[HasT2ExtractPack, IsThumb2]> {
2760 let Inst{31-27} = 0b11101;
2761 let Inst{26-25} = 0b01;
2762 let Inst{24-20} = 0b01100;
2763 let Inst{5} = 0; // BT form
2767 let Inst{14-12} = sh{4-2};
2768 let Inst{7-6} = sh{1-0};
2771 // Alternate cases for PKHBT where identities eliminate some nodes.
2772 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2773 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2774 Requires<[HasT2ExtractPack, IsThumb2]>;
2775 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2776 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2777 Requires<[HasT2ExtractPack, IsThumb2]>;
2779 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2780 // will match the pattern below.
2781 def t2PKHTB : T2ThreeReg<
2782 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2783 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2784 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2785 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2787 Requires<[HasT2ExtractPack, IsThumb2]> {
2788 let Inst{31-27} = 0b11101;
2789 let Inst{26-25} = 0b01;
2790 let Inst{24-20} = 0b01100;
2791 let Inst{5} = 1; // TB form
2795 let Inst{14-12} = sh{4-2};
2796 let Inst{7-6} = sh{1-0};
2799 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2800 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2801 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2802 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2803 Requires<[HasT2ExtractPack, IsThumb2]>;
2804 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2805 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2806 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2807 Requires<[HasT2ExtractPack, IsThumb2]>;
2809 //===----------------------------------------------------------------------===//
2810 // Comparison Instructions...
2812 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2813 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2814 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2816 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2817 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2818 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2819 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2820 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2821 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2823 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2824 // Compare-to-zero still works out, just not the relationals
2825 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2826 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2827 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2828 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2829 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2832 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2833 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2835 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2836 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2838 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2839 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2840 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2842 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2843 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2844 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2847 // Conditional moves
2848 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2849 // a two-value operand where a dag node expects two operands. :(
2850 let neverHasSideEffects = 1 in {
2851 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2852 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2854 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2855 RegConstraint<"$false = $Rd">;
2857 let isMoveImm = 1 in
2858 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2859 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2861 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2862 RegConstraint<"$false = $Rd">;
2864 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2865 let isCodeGenOnly = 1 in {
2866 let isMoveImm = 1 in
2867 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2869 "movw", "\t$Rd, $imm", []>,
2870 RegConstraint<"$false = $Rd"> {
2871 let Inst{31-27} = 0b11110;
2873 let Inst{24-21} = 0b0010;
2874 let Inst{20} = 0; // The S bit.
2880 let Inst{11-8} = Rd;
2881 let Inst{19-16} = imm{15-12};
2882 let Inst{26} = imm{11};
2883 let Inst{14-12} = imm{10-8};
2884 let Inst{7-0} = imm{7-0};
2887 let isMoveImm = 1 in
2888 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2889 (ins rGPR:$false, i32imm:$src, pred:$p),
2890 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2892 let isMoveImm = 1 in
2893 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2894 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2895 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2896 imm:$cc, CCR:$ccr))*/]>,
2897 RegConstraint<"$false = $Rd"> {
2898 let Inst{31-27} = 0b11110;
2900 let Inst{24-21} = 0b0011;
2901 let Inst{20} = 0; // The S bit.
2902 let Inst{19-16} = 0b1111; // Rn
2906 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2907 string opc, string asm, list<dag> pattern>
2908 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2909 let Inst{31-27} = 0b11101;
2910 let Inst{26-25} = 0b01;
2911 let Inst{24-21} = 0b0010;
2912 let Inst{20} = 0; // The S bit.
2913 let Inst{19-16} = 0b1111; // Rn
2914 let Inst{5-4} = opcod; // Shift type.
2916 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2917 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2918 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2919 RegConstraint<"$false = $Rd">;
2920 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2921 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2922 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2923 RegConstraint<"$false = $Rd">;
2924 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2925 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2926 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2927 RegConstraint<"$false = $Rd">;
2928 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2929 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2930 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2931 RegConstraint<"$false = $Rd">;
2932 } // isCodeGenOnly = 1
2933 } // neverHasSideEffects
2935 //===----------------------------------------------------------------------===//
2936 // Atomic operations intrinsics
2939 // memory barriers protect the atomic sequences
2940 let hasSideEffects = 1 in {
2941 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2942 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2943 Requires<[IsThumb, HasDB]> {
2945 let Inst{31-4} = 0xf3bf8f5;
2946 let Inst{3-0} = opt;
2950 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2951 "dsb", "\t$opt", []>,
2952 Requires<[IsThumb, HasDB]> {
2954 let Inst{31-4} = 0xf3bf8f4;
2955 let Inst{3-0} = opt;
2958 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2960 []>, Requires<[IsThumb2, HasDB]> {
2962 let Inst{31-4} = 0xf3bf8f6;
2963 let Inst{3-0} = opt;
2966 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2967 InstrItinClass itin, string opc, string asm, string cstr,
2968 list<dag> pattern, bits<4> rt2 = 0b1111>
2969 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2970 let Inst{31-27} = 0b11101;
2971 let Inst{26-20} = 0b0001101;
2972 let Inst{11-8} = rt2;
2973 let Inst{7-6} = 0b01;
2974 let Inst{5-4} = opcod;
2975 let Inst{3-0} = 0b1111;
2979 let Inst{19-16} = addr;
2980 let Inst{15-12} = Rt;
2982 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2983 InstrItinClass itin, string opc, string asm, string cstr,
2984 list<dag> pattern, bits<4> rt2 = 0b1111>
2985 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2986 let Inst{31-27} = 0b11101;
2987 let Inst{26-20} = 0b0001100;
2988 let Inst{11-8} = rt2;
2989 let Inst{7-6} = 0b01;
2990 let Inst{5-4} = opcod;
2996 let Inst{19-16} = addr;
2997 let Inst{15-12} = Rt;
3000 let mayLoad = 1 in {
3001 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3002 AddrModeNone, 4, NoItinerary,
3003 "ldrexb", "\t$Rt, $addr", "", []>;
3004 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3005 AddrModeNone, 4, NoItinerary,
3006 "ldrexh", "\t$Rt, $addr", "", []>;
3007 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3008 AddrModeNone, 4, NoItinerary,
3009 "ldrex", "\t$Rt, $addr", "", []> {
3012 let Inst{31-27} = 0b11101;
3013 let Inst{26-20} = 0b0000101;
3014 let Inst{19-16} = addr{11-8};
3015 let Inst{15-12} = Rt;
3016 let Inst{11-8} = 0b1111;
3017 let Inst{7-0} = addr{7-0};
3019 let hasExtraDefRegAllocReq = 1 in
3020 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3021 (ins addr_offset_none:$addr),
3022 AddrModeNone, 4, NoItinerary,
3023 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3026 let Inst{11-8} = Rt2;
3030 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3031 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3032 (ins rGPR:$Rt, addr_offset_none:$addr),
3033 AddrModeNone, 4, NoItinerary,
3034 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3035 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3036 (ins rGPR:$Rt, addr_offset_none:$addr),
3037 AddrModeNone, 4, NoItinerary,
3038 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3039 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3040 t2addrmode_imm0_1020s4:$addr),
3041 AddrModeNone, 4, NoItinerary,
3042 "strex", "\t$Rd, $Rt, $addr", "",
3047 let Inst{31-27} = 0b11101;
3048 let Inst{26-20} = 0b0000100;
3049 let Inst{19-16} = addr{11-8};
3050 let Inst{15-12} = Rt;
3051 let Inst{11-8} = Rd;
3052 let Inst{7-0} = addr{7-0};
3056 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3057 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3058 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3059 AddrModeNone, 4, NoItinerary,
3060 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3063 let Inst{11-8} = Rt2;
3066 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3067 Requires<[IsThumb2, HasV7]> {
3068 let Inst{31-16} = 0xf3bf;
3069 let Inst{15-14} = 0b10;
3072 let Inst{11-8} = 0b1111;
3073 let Inst{7-4} = 0b0010;
3074 let Inst{3-0} = 0b1111;
3077 //===----------------------------------------------------------------------===//
3078 // SJLJ Exception handling intrinsics
3079 // eh_sjlj_setjmp() is an instruction sequence to store the return
3080 // address and save #0 in R0 for the non-longjmp case.
3081 // Since by its nature we may be coming from some other function to get
3082 // here, and we're using the stack frame for the containing function to
3083 // save/restore registers, we can't keep anything live in regs across
3084 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3085 // when we get here from a longjmp(). We force everything out of registers
3086 // except for our own input by listing the relevant registers in Defs. By
3087 // doing so, we also cause the prologue/epilogue code to actively preserve
3088 // all of the callee-saved resgisters, which is exactly what we want.
3089 // $val is a scratch register for our use.
3091 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3092 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
3093 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3094 usesCustomInserter = 1 in {
3095 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3096 AddrModeNone, 0, NoItinerary, "", "",
3097 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3098 Requires<[IsThumb2, HasVFP2]>;
3102 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3103 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3104 usesCustomInserter = 1 in {
3105 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3106 AddrModeNone, 0, NoItinerary, "", "",
3107 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3108 Requires<[IsThumb2, NoVFP]>;
3112 //===----------------------------------------------------------------------===//
3113 // Control-Flow Instructions
3116 // FIXME: remove when we have a way to marking a MI with these properties.
3117 // FIXME: Should pc be an implicit operand like PICADD, etc?
3118 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3119 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3120 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3121 reglist:$regs, variable_ops),
3122 4, IIC_iLoad_mBr, [],
3123 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3124 RegConstraint<"$Rn = $wb">;
3126 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3127 let isPredicable = 1 in
3128 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3130 [(br bb:$target)]> {
3131 let Inst{31-27} = 0b11110;
3132 let Inst{15-14} = 0b10;
3136 let Inst{26} = target{19};
3137 let Inst{11} = target{18};
3138 let Inst{13} = target{17};
3139 let Inst{21-16} = target{16-11};
3140 let Inst{10-0} = target{10-0};
3143 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3144 def t2BR_JT : t2PseudoInst<(outs),
3145 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3147 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3149 // FIXME: Add a non-pc based case that can be predicated.
3150 def t2TBB_JT : t2PseudoInst<(outs),
3151 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3153 def t2TBH_JT : t2PseudoInst<(outs),
3154 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3156 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3157 "tbb", "\t$addr", []> {
3160 let Inst{31-20} = 0b111010001101;
3161 let Inst{19-16} = Rn;
3162 let Inst{15-5} = 0b11110000000;
3163 let Inst{4} = 0; // B form
3166 let DecoderMethod = "DecodeThumbTableBranch";
3169 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3170 "tbh", "\t$addr", []> {
3173 let Inst{31-20} = 0b111010001101;
3174 let Inst{19-16} = Rn;
3175 let Inst{15-5} = 0b11110000000;
3176 let Inst{4} = 1; // H form
3179 let DecoderMethod = "DecodeThumbTableBranch";
3181 } // isNotDuplicable, isIndirectBranch
3183 } // isBranch, isTerminator, isBarrier
3185 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3186 // a two-value operand where a dag node expects ", "two operands. :(
3187 let isBranch = 1, isTerminator = 1 in
3188 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3190 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3191 let Inst{31-27} = 0b11110;
3192 let Inst{15-14} = 0b10;
3196 let Inst{25-22} = p;
3199 let Inst{26} = target{20};
3200 let Inst{11} = target{19};
3201 let Inst{13} = target{18};
3202 let Inst{21-16} = target{17-12};
3203 let Inst{10-0} = target{11-1};
3205 let DecoderMethod = "DecodeThumb2BCCInstruction";
3208 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3210 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3212 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3214 def tTAILJMPd: tPseudoExpand<(outs),
3215 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3217 (t2B uncondbrtarget:$dst, pred:$p)>,
3218 Requires<[IsThumb2, IsDarwin]>;
3222 let Defs = [ITSTATE] in
3223 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3224 AddrModeNone, 2, IIC_iALUx,
3225 "it$mask\t$cc", "", []> {
3226 // 16-bit instruction.
3227 let Inst{31-16} = 0x0000;
3228 let Inst{15-8} = 0b10111111;
3233 let Inst{3-0} = mask;
3235 let DecoderMethod = "DecodeIT";
3238 // Branch and Exchange Jazelle -- for disassembly only
3240 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3242 let Inst{31-27} = 0b11110;
3244 let Inst{25-20} = 0b111100;
3245 let Inst{19-16} = func;
3246 let Inst{15-0} = 0b1000111100000000;
3249 // Compare and branch on zero / non-zero
3250 let isBranch = 1, isTerminator = 1 in {
3251 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3252 "cbz\t$Rn, $target", []>,
3253 T1Misc<{0,0,?,1,?,?,?}>,
3254 Requires<[IsThumb2]> {
3258 let Inst{9} = target{5};
3259 let Inst{7-3} = target{4-0};
3263 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3264 "cbnz\t$Rn, $target", []>,
3265 T1Misc<{1,0,?,1,?,?,?}>,
3266 Requires<[IsThumb2]> {
3270 let Inst{9} = target{5};
3271 let Inst{7-3} = target{4-0};
3277 // Change Processor State is a system instruction.
3278 // FIXME: Since the asm parser has currently no clean way to handle optional
3279 // operands, create 3 versions of the same instruction. Once there's a clean
3280 // framework to represent optional operands, change this behavior.
3281 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3282 !strconcat("cps", asm_op), []> {
3288 let Inst{31-27} = 0b11110;
3290 let Inst{25-20} = 0b111010;
3291 let Inst{19-16} = 0b1111;
3292 let Inst{15-14} = 0b10;
3294 let Inst{10-9} = imod;
3296 let Inst{7-5} = iflags;
3297 let Inst{4-0} = mode;
3298 let DecoderMethod = "DecodeT2CPSInstruction";
3302 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3303 "$imod.w\t$iflags, $mode">;
3304 let mode = 0, M = 0 in
3305 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3306 "$imod.w\t$iflags">;
3307 let imod = 0, iflags = 0, M = 1 in
3308 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3310 // A6.3.4 Branches and miscellaneous control
3311 // Table A6-14 Change Processor State, and hint instructions
3312 class T2I_hint<bits<8> op7_0, string opc, string asm>
3313 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3314 let Inst{31-20} = 0xf3a;
3315 let Inst{19-16} = 0b1111;
3316 let Inst{15-14} = 0b10;
3318 let Inst{10-8} = 0b000;
3319 let Inst{7-0} = op7_0;
3322 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3323 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3324 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3325 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3326 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3328 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3330 let Inst{31-20} = 0b111100111010;
3331 let Inst{19-16} = 0b1111;
3332 let Inst{15-8} = 0b10000000;
3333 let Inst{7-4} = 0b1111;
3334 let Inst{3-0} = opt;
3337 // Secure Monitor Call is a system instruction.
3338 // Option = Inst{19-16}
3339 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3340 let Inst{31-27} = 0b11110;
3341 let Inst{26-20} = 0b1111111;
3342 let Inst{15-12} = 0b1000;
3345 let Inst{19-16} = opt;
3348 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3349 string opc, string asm, list<dag> pattern>
3350 : T2I<oops, iops, itin, opc, asm, pattern> {
3352 let Inst{31-25} = 0b1110100;
3353 let Inst{24-23} = Op;
3356 let Inst{20-16} = 0b01101;
3357 let Inst{15-5} = 0b11000000000;
3358 let Inst{4-0} = mode{4-0};
3361 // Store Return State is a system instruction.
3362 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3363 "srsdb", "\tsp!, $mode", []>;
3364 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3365 "srsdb","\tsp, $mode", []>;
3366 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3367 "srsia","\tsp!, $mode", []>;
3368 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3369 "srsia","\tsp, $mode", []>;
3371 // Return From Exception is a system instruction.
3372 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3373 string opc, string asm, list<dag> pattern>
3374 : T2I<oops, iops, itin, opc, asm, pattern> {
3375 let Inst{31-20} = op31_20{11-0};
3378 let Inst{19-16} = Rn;
3379 let Inst{15-0} = 0xc000;
3382 def t2RFEDBW : T2RFE<0b111010000011,
3383 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3384 [/* For disassembly only; pattern left blank */]>;
3385 def t2RFEDB : T2RFE<0b111010000001,
3386 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3387 [/* For disassembly only; pattern left blank */]>;
3388 def t2RFEIAW : T2RFE<0b111010011011,
3389 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3390 [/* For disassembly only; pattern left blank */]>;
3391 def t2RFEIA : T2RFE<0b111010011001,
3392 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3393 [/* For disassembly only; pattern left blank */]>;
3395 //===----------------------------------------------------------------------===//
3396 // Non-Instruction Patterns
3399 // 32-bit immediate using movw + movt.
3400 // This is a single pseudo instruction to make it re-materializable.
3401 // FIXME: Remove this when we can do generalized remat.
3402 let isReMaterializable = 1, isMoveImm = 1 in
3403 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3404 [(set rGPR:$dst, (i32 imm:$src))]>,
3405 Requires<[IsThumb, HasV6T2]>;
3407 // Pseudo instruction that combines movw + movt + add pc (if pic).
3408 // It also makes it possible to rematerialize the instructions.
3409 // FIXME: Remove this when we can do generalized remat and when machine licm
3410 // can properly the instructions.
3411 let isReMaterializable = 1 in {
3412 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3414 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3415 Requires<[IsThumb2, UseMovt]>;
3417 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3419 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3420 Requires<[IsThumb2, UseMovt]>;
3423 // ConstantPool, GlobalAddress, and JumpTable
3424 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3425 Requires<[IsThumb2, DontUseMovt]>;
3426 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3427 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3428 Requires<[IsThumb2, UseMovt]>;
3430 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3431 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3433 // Pseudo instruction that combines ldr from constpool and add pc. This should
3434 // be expanded into two instructions late to allow if-conversion and
3436 let canFoldAsLoad = 1, isReMaterializable = 1 in
3437 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3439 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3441 Requires<[IsThumb2]>;
3443 // Pseudo isntruction that combines movs + predicated rsbmi
3444 // to implement integer ABS
3445 let usesCustomInserter = 1, Defs = [CPSR] in {
3446 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3447 NoItinerary, []>, Requires<[IsThumb2]>;
3450 //===----------------------------------------------------------------------===//
3451 // Coprocessor load/store -- for disassembly only
3453 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3454 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3455 let Inst{31-28} = op31_28;
3456 let Inst{27-25} = 0b110;
3459 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3460 def _OFFSET : T2CI<op31_28,
3461 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3462 asm, "\t$cop, $CRd, $addr"> {
3466 let Inst{24} = 1; // P = 1
3467 let Inst{23} = addr{8};
3468 let Inst{22} = Dbit;
3469 let Inst{21} = 0; // W = 0
3470 let Inst{20} = load;
3471 let Inst{19-16} = addr{12-9};
3472 let Inst{15-12} = CRd;
3473 let Inst{11-8} = cop;
3474 let Inst{7-0} = addr{7-0};
3475 let DecoderMethod = "DecodeCopMemInstruction";
3477 def _PRE : T2CI<op31_28,
3478 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3479 asm, "\t$cop, $CRd, $addr!"> {
3483 let Inst{24} = 1; // P = 1
3484 let Inst{23} = addr{8};
3485 let Inst{22} = Dbit;
3486 let Inst{21} = 1; // W = 1
3487 let Inst{20} = load;
3488 let Inst{19-16} = addr{12-9};
3489 let Inst{15-12} = CRd;
3490 let Inst{11-8} = cop;
3491 let Inst{7-0} = addr{7-0};
3492 let DecoderMethod = "DecodeCopMemInstruction";
3494 def _POST: T2CI<op31_28,
3495 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3496 postidx_imm8s4:$offset),
3497 asm, "\t$cop, $CRd, $addr, $offset"> {
3502 let Inst{24} = 0; // P = 0
3503 let Inst{23} = offset{8};
3504 let Inst{22} = Dbit;
3505 let Inst{21} = 1; // W = 1
3506 let Inst{20} = load;
3507 let Inst{19-16} = addr;
3508 let Inst{15-12} = CRd;
3509 let Inst{11-8} = cop;
3510 let Inst{7-0} = offset{7-0};
3511 let DecoderMethod = "DecodeCopMemInstruction";
3513 def _OPTION : T2CI<op31_28, (outs),
3514 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3515 coproc_option_imm:$option),
3516 asm, "\t$cop, $CRd, $addr, $option"> {
3521 let Inst{24} = 0; // P = 0
3522 let Inst{23} = 1; // U = 1
3523 let Inst{22} = Dbit;
3524 let Inst{21} = 0; // W = 0
3525 let Inst{20} = load;
3526 let Inst{19-16} = addr;
3527 let Inst{15-12} = CRd;
3528 let Inst{11-8} = cop;
3529 let Inst{7-0} = option;
3530 let DecoderMethod = "DecodeCopMemInstruction";
3534 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3535 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3536 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3537 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3538 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3539 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3540 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3541 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3544 //===----------------------------------------------------------------------===//
3545 // Move between special register and ARM core register -- for disassembly only
3547 // Move to ARM core register from Special Register
3551 // A/R class can only move from CPSR or SPSR.
3552 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>,
3553 Requires<[IsThumb2,IsARClass]> {
3555 let Inst{31-12} = 0b11110011111011111000;
3556 let Inst{11-8} = Rd;
3557 let Inst{7-0} = 0b0000;
3560 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3562 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>,
3563 Requires<[IsThumb2,IsARClass]> {
3565 let Inst{31-12} = 0b11110011111111111000;
3566 let Inst{11-8} = Rd;
3567 let Inst{7-0} = 0b0000;
3572 // This MRS has a mask field in bits 7-0 and can take more values than
3573 // the A/R class (a full msr_mask).
3574 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3575 "mrs", "\t$Rd, $mask", []>,
3576 Requires<[IsThumb2,IsMClass]> {
3579 let Inst{31-12} = 0b11110011111011111000;
3580 let Inst{11-8} = Rd;
3581 let Inst{19-16} = 0b1111;
3582 let Inst{7-0} = mask;
3586 // Move from ARM core register to Special Register
3590 // No need to have both system and application versions, the encodings are the
3591 // same and the assembly parser has no way to distinguish between them. The mask
3592 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3593 // the mask with the fields to be accessed in the special register.
3594 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3595 NoItinerary, "msr", "\t$mask, $Rn", []>,
3596 Requires<[IsThumb2,IsARClass]> {
3599 let Inst{31-21} = 0b11110011100;
3600 let Inst{20} = mask{4}; // R Bit
3601 let Inst{19-16} = Rn;
3602 let Inst{15-12} = 0b1000;
3603 let Inst{11-8} = mask{3-0};
3609 // Move from ARM core register to Special Register
3610 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3611 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3612 Requires<[IsThumb2,IsMClass]> {
3615 let Inst{31-21} = 0b11110011100;
3617 let Inst{19-16} = Rn;
3618 let Inst{15-12} = 0b1000;
3619 let Inst{7-0} = SYSm;
3623 //===----------------------------------------------------------------------===//
3624 // Move between coprocessor and ARM core register
3627 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3629 : T2Cop<Op, oops, iops,
3630 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3632 let Inst{27-24} = 0b1110;
3633 let Inst{20} = direction;
3643 let Inst{15-12} = Rt;
3644 let Inst{11-8} = cop;
3645 let Inst{23-21} = opc1;
3646 let Inst{7-5} = opc2;
3647 let Inst{3-0} = CRm;
3648 let Inst{19-16} = CRn;
3651 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3652 list<dag> pattern = []>
3654 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3655 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3656 let Inst{27-24} = 0b1100;
3657 let Inst{23-21} = 0b010;
3658 let Inst{20} = direction;
3666 let Inst{15-12} = Rt;
3667 let Inst{19-16} = Rt2;
3668 let Inst{11-8} = cop;
3669 let Inst{7-4} = opc1;
3670 let Inst{3-0} = CRm;
3673 /* from ARM core register to coprocessor */
3674 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3676 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3677 c_imm:$CRm, imm0_7:$opc2),
3678 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3679 imm:$CRm, imm:$opc2)]>;
3680 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3681 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3682 c_imm:$CRm, imm0_7:$opc2),
3683 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3684 imm:$CRm, imm:$opc2)]>;
3686 /* from coprocessor to ARM core register */
3687 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3688 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3689 c_imm:$CRm, imm0_7:$opc2), []>;
3691 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3692 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3693 c_imm:$CRm, imm0_7:$opc2), []>;
3695 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3696 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3698 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3699 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3702 /* from ARM core register to coprocessor */
3703 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3704 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3706 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3707 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3708 GPR:$Rt2, imm:$CRm)]>;
3709 /* from coprocessor to ARM core register */
3710 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3712 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3714 //===----------------------------------------------------------------------===//
3715 // Other Coprocessor Instructions.
3718 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3719 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3720 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3721 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3722 imm:$CRm, imm:$opc2)]> {
3723 let Inst{27-24} = 0b1110;
3732 let Inst{3-0} = CRm;
3734 let Inst{7-5} = opc2;
3735 let Inst{11-8} = cop;
3736 let Inst{15-12} = CRd;
3737 let Inst{19-16} = CRn;
3738 let Inst{23-20} = opc1;
3741 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3742 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3743 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3744 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3745 imm:$CRm, imm:$opc2)]> {
3746 let Inst{27-24} = 0b1110;
3755 let Inst{3-0} = CRm;
3757 let Inst{7-5} = opc2;
3758 let Inst{11-8} = cop;
3759 let Inst{15-12} = CRd;
3760 let Inst{19-16} = CRn;
3761 let Inst{23-20} = opc1;
3766 //===----------------------------------------------------------------------===//
3767 // Non-Instruction Patterns
3770 // SXT/UXT with no rotate
3771 let AddedComplexity = 16 in {
3772 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3773 Requires<[IsThumb2]>;
3774 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3775 Requires<[IsThumb2]>;
3776 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3777 Requires<[HasT2ExtractPack, IsThumb2]>;
3778 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3779 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3780 Requires<[HasT2ExtractPack, IsThumb2]>;
3781 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3782 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3783 Requires<[HasT2ExtractPack, IsThumb2]>;
3786 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3787 Requires<[IsThumb2]>;
3788 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3789 Requires<[IsThumb2]>;
3790 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3791 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3792 Requires<[HasT2ExtractPack, IsThumb2]>;
3793 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3794 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3795 Requires<[HasT2ExtractPack, IsThumb2]>;
3797 // Atomic load/store patterns
3798 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3799 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3800 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3801 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3802 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3803 (t2LDRBs t2addrmode_so_reg:$addr)>;
3804 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3805 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3806 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3807 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3808 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3809 (t2LDRHs t2addrmode_so_reg:$addr)>;
3810 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3811 (t2LDRi12 t2addrmode_imm12:$addr)>;
3812 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3813 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3814 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3815 (t2LDRs t2addrmode_so_reg:$addr)>;
3816 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3817 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3818 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3819 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3820 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3821 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3822 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3823 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3824 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3825 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3826 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3827 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3828 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3829 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3830 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3831 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3832 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3833 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3836 //===----------------------------------------------------------------------===//
3837 // Assembler aliases
3840 // Aliases for ADC without the ".w" optional width specifier.
3841 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3842 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3843 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3844 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3845 pred:$p, cc_out:$s)>;
3847 // Aliases for SBC without the ".w" optional width specifier.
3848 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3849 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3850 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3851 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3852 pred:$p, cc_out:$s)>;
3854 // Aliases for ADD without the ".w" optional width specifier.
3855 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3856 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3857 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3858 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3859 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3860 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3861 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3862 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3863 pred:$p, cc_out:$s)>;
3865 // Aliases for SUB without the ".w" optional width specifier.
3866 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3867 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3868 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3869 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3870 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3871 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3872 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3873 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3874 pred:$p, cc_out:$s)>;
3876 // Alias for compares without the ".w" optional width specifier.
3877 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3878 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3879 def : t2InstAlias<"teq${p} $Rn, $Rm",
3880 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3881 def : t2InstAlias<"tst${p} $Rn, $Rm",
3882 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3885 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3886 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3887 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3889 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3891 def : t2InstAlias<"ldr${p} $Rt, $addr",
3892 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3893 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3894 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3895 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3896 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3897 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3898 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3899 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3900 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3902 def : t2InstAlias<"ldr${p} $Rt, $addr",
3903 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3904 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3905 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3906 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3907 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3908 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3909 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3910 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3911 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3913 // Alias for MVN without the ".w" optional width specifier.
3914 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
3915 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
3916 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
3917 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
3919 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
3920 // shift amount is zero (i.e., unspecified).
3921 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
3922 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3923 Requires<[HasT2ExtractPack, IsThumb2]>;
3924 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
3925 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3926 Requires<[HasT2ExtractPack, IsThumb2]>;
3928 // PUSH/POP aliases for STM/LDM
3929 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3930 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3931 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3932 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3934 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
3935 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3936 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3937 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3940 // Alias for RSB without the ".w" optional width specifier, and with optional
3941 // implied destination register.
3942 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
3943 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3944 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
3945 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3946 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
3947 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3948 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
3949 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
3952 // SSAT/USAT optional shift operand.
3953 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
3954 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3955 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
3956 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3958 // STM w/o the .w suffix.
3959 def : t2InstAlias<"stm${p} $Rn, $regs",
3960 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
3962 // Alias for STR, STRB, and STRH without the ".w" optional
3964 def : t2InstAlias<"str${p} $Rt, $addr",
3965 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3966 def : t2InstAlias<"strb${p} $Rt, $addr",
3967 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3968 def : t2InstAlias<"strh${p} $Rt, $addr",
3969 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3971 def : t2InstAlias<"str${p} $Rt, $addr",
3972 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3973 def : t2InstAlias<"strb${p} $Rt, $addr",
3974 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3975 def : t2InstAlias<"strh${p} $Rt, $addr",
3976 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3978 // Extend instruction optional rotate operand.
3979 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
3980 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3981 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
3982 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3983 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
3984 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3986 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
3987 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3988 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
3989 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3990 def : t2InstAlias<"sxth${p} $Rd, $Rm",
3991 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3992 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
3993 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3994 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
3995 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3997 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
3998 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3999 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4000 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4001 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4002 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4003 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4004 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4005 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4006 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4007 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4008 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4010 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4011 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4012 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4013 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4015 // Extend instruction w/o the ".w" optional width specifier.
4016 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4017 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4018 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4019 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4020 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4021 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4023 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4024 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4025 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4026 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4027 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4028 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;