1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // Shifted operands. No register controlled shifts for Thumb2.
32 // Note: We do not support rrx shifted operands yet.
33 def t2_so_reg : Operand<i32>, // reg imm
34 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
36 let EncoderMethod = "getT2SORegOpValue";
37 let PrintMethod = "printT2SOOperand";
38 let DecoderMethod = "DecodeSORegImmOperand";
39 let ParserMatchClass = ShiftedImmAsmOperand;
40 let MIOperandInfo = (ops rGPR, i32imm);
43 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
44 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
48 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
49 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
50 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
53 // t2_so_imm - Match a 32-bit immediate operand, which is an
54 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
55 // immediate splatted into multiple bytes of the word.
56 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
57 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
58 return ARM_AM::getT2SOImmVal(Imm) != -1;
60 let ParserMatchClass = t2_so_imm_asmoperand;
61 let EncoderMethod = "getT2SOImmOpValue";
62 let DecoderMethod = "DecodeT2SOImm";
65 // t2_so_imm_not - Match an immediate that is a complement
67 def t2_so_imm_not : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
70 }], t2_so_imm_not_XFORM>;
72 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
73 def t2_so_imm_neg : Operand<i32>,
75 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
76 }], t2_so_imm_neg_XFORM>;
78 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
79 def imm0_4095 : Operand<i32>,
81 return Imm >= 0 && Imm < 4096;
84 def imm0_4095_neg : PatLeaf<(i32 imm), [{
85 return (uint32_t)(-N->getZExtValue()) < 4096;
88 def imm0_255_neg : PatLeaf<(i32 imm), [{
89 return (uint32_t)(-N->getZExtValue()) < 255;
92 def imm0_255_not : PatLeaf<(i32 imm), [{
93 return (uint32_t)(~N->getZExtValue()) < 255;
96 def lo5AllOne : PatLeaf<(i32 imm), [{
97 // Returns true if all low 5-bits are 1.
98 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
101 // Define Thumb2 specific addressing modes.
103 // t2addrmode_imm12 := reg + imm12
104 def t2addrmode_imm12 : Operand<i32>,
105 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
106 let PrintMethod = "printAddrModeImm12Operand";
107 let EncoderMethod = "getAddrModeImm12OpValue";
108 let DecoderMethod = "DecodeT2AddrModeImm12";
109 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
112 // t2ldrlabel := imm12
113 def t2ldrlabel : Operand<i32> {
114 let EncoderMethod = "getAddrModeImm12OpValue";
118 // ADR instruction labels.
119 def t2adrlabel : Operand<i32> {
120 let EncoderMethod = "getT2AdrLabelOpValue";
124 // t2addrmode_imm8 := reg +/- imm8
125 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
126 def t2addrmode_imm8 : Operand<i32>,
127 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
128 let PrintMethod = "printT2AddrModeImm8Operand";
129 let EncoderMethod = "getT2AddrModeImm8OpValue";
130 let DecoderMethod = "DecodeT2AddrModeImm8";
131 let ParserMatchClass = MemImm8OffsetAsmOperand;
132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
135 def t2am_imm8_offset : Operand<i32>,
136 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
137 [], [SDNPWantRoot]> {
138 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
139 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
140 let DecoderMethod = "DecodeT2Imm8";
143 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
144 def t2addrmode_imm8s4 : Operand<i32> {
145 let PrintMethod = "printT2AddrModeImm8s4Operand";
146 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
147 let DecoderMethod = "DecodeT2AddrModeImm8s4";
148 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
151 def t2am_imm8s4_offset : Operand<i32> {
152 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
153 let DecoderMethod = "DecodeT2Imm8S4";
156 // t2addrmode_so_reg := reg + (reg << imm2)
157 def t2addrmode_so_reg : Operand<i32>,
158 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
159 let PrintMethod = "printT2AddrModeSoRegOperand";
160 let EncoderMethod = "getT2AddrModeSORegOpValue";
161 let DecoderMethod = "DecodeT2AddrModeSOReg";
162 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
165 // t2addrmode_reg := reg
166 // Used by load/store exclusive instructions. Useful to enable right assembly
167 // parsing and printing. Not used for any codegen matching.
169 def t2addrmode_reg : Operand<i32> {
170 let PrintMethod = "printAddrMode7Operand";
171 let DecoderMethod = "DecodeGPRRegisterClass";
172 let MIOperandInfo = (ops GPR);
175 //===----------------------------------------------------------------------===//
176 // Multiclass helpers...
180 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
181 string opc, string asm, list<dag> pattern>
182 : T2I<oops, iops, itin, opc, asm, pattern> {
187 let Inst{26} = imm{11};
188 let Inst{14-12} = imm{10-8};
189 let Inst{7-0} = imm{7-0};
193 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
194 string opc, string asm, list<dag> pattern>
195 : T2sI<oops, iops, itin, opc, asm, pattern> {
201 let Inst{26} = imm{11};
202 let Inst{14-12} = imm{10-8};
203 let Inst{7-0} = imm{7-0};
206 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
207 string opc, string asm, list<dag> pattern>
208 : T2I<oops, iops, itin, opc, asm, pattern> {
212 let Inst{19-16} = Rn;
213 let Inst{26} = imm{11};
214 let Inst{14-12} = imm{10-8};
215 let Inst{7-0} = imm{7-0};
219 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
220 string opc, string asm, list<dag> pattern>
221 : T2I<oops, iops, itin, opc, asm, pattern> {
226 let Inst{3-0} = ShiftedRm{3-0};
227 let Inst{5-4} = ShiftedRm{6-5};
228 let Inst{14-12} = ShiftedRm{11-9};
229 let Inst{7-6} = ShiftedRm{8-7};
232 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
233 string opc, string asm, list<dag> pattern>
234 : T2sI<oops, iops, itin, opc, asm, pattern> {
239 let Inst{3-0} = ShiftedRm{3-0};
240 let Inst{5-4} = ShiftedRm{6-5};
241 let Inst{14-12} = ShiftedRm{11-9};
242 let Inst{7-6} = ShiftedRm{8-7};
245 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
246 string opc, string asm, list<dag> pattern>
247 : T2I<oops, iops, itin, opc, asm, pattern> {
251 let Inst{19-16} = Rn;
252 let Inst{3-0} = ShiftedRm{3-0};
253 let Inst{5-4} = ShiftedRm{6-5};
254 let Inst{14-12} = ShiftedRm{11-9};
255 let Inst{7-6} = ShiftedRm{8-7};
258 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
259 string opc, string asm, list<dag> pattern>
260 : T2I<oops, iops, itin, opc, asm, pattern> {
268 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
269 string opc, string asm, list<dag> pattern>
270 : T2sI<oops, iops, itin, opc, asm, pattern> {
278 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
279 string opc, string asm, list<dag> pattern>
280 : T2I<oops, iops, itin, opc, asm, pattern> {
284 let Inst{19-16} = Rn;
289 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
290 string opc, string asm, list<dag> pattern>
291 : T2I<oops, iops, itin, opc, asm, pattern> {
297 let Inst{19-16} = Rn;
298 let Inst{26} = imm{11};
299 let Inst{14-12} = imm{10-8};
300 let Inst{7-0} = imm{7-0};
303 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
304 string opc, string asm, list<dag> pattern>
305 : T2sI<oops, iops, itin, opc, asm, pattern> {
311 let Inst{19-16} = Rn;
312 let Inst{26} = imm{11};
313 let Inst{14-12} = imm{10-8};
314 let Inst{7-0} = imm{7-0};
317 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
318 string opc, string asm, list<dag> pattern>
319 : T2I<oops, iops, itin, opc, asm, pattern> {
326 let Inst{14-12} = imm{4-2};
327 let Inst{7-6} = imm{1-0};
330 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
331 string opc, string asm, list<dag> pattern>
332 : T2sI<oops, iops, itin, opc, asm, pattern> {
339 let Inst{14-12} = imm{4-2};
340 let Inst{7-6} = imm{1-0};
343 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
344 string opc, string asm, list<dag> pattern>
345 : T2I<oops, iops, itin, opc, asm, pattern> {
351 let Inst{19-16} = Rn;
355 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
356 string opc, string asm, list<dag> pattern>
357 : T2sI<oops, iops, itin, opc, asm, pattern> {
363 let Inst{19-16} = Rn;
367 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
368 string opc, string asm, list<dag> pattern>
369 : T2I<oops, iops, itin, opc, asm, pattern> {
375 let Inst{19-16} = Rn;
376 let Inst{3-0} = ShiftedRm{3-0};
377 let Inst{5-4} = ShiftedRm{6-5};
378 let Inst{14-12} = ShiftedRm{11-9};
379 let Inst{7-6} = ShiftedRm{8-7};
382 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
383 string opc, string asm, list<dag> pattern>
384 : T2sI<oops, iops, itin, opc, asm, pattern> {
390 let Inst{19-16} = Rn;
391 let Inst{3-0} = ShiftedRm{3-0};
392 let Inst{5-4} = ShiftedRm{6-5};
393 let Inst{14-12} = ShiftedRm{11-9};
394 let Inst{7-6} = ShiftedRm{8-7};
397 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
398 string opc, string asm, list<dag> pattern>
399 : T2I<oops, iops, itin, opc, asm, pattern> {
405 let Inst{19-16} = Rn;
406 let Inst{15-12} = Ra;
411 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
412 dag oops, dag iops, InstrItinClass itin,
413 string opc, string asm, list<dag> pattern>
414 : T2I<oops, iops, itin, opc, asm, pattern> {
420 let Inst{31-23} = 0b111110111;
421 let Inst{22-20} = opc22_20;
422 let Inst{19-16} = Rn;
423 let Inst{15-12} = RdLo;
424 let Inst{11-8} = RdHi;
425 let Inst{7-4} = opc7_4;
430 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
431 /// unary operation that produces a value. These are predicable and can be
432 /// changed to modify CPSR.
433 multiclass T2I_un_irs<bits<4> opcod, string opc,
434 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
435 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
437 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
439 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
440 let isAsCheapAsAMove = Cheap;
441 let isReMaterializable = ReMat;
442 let Inst{31-27} = 0b11110;
444 let Inst{24-21} = opcod;
445 let Inst{19-16} = 0b1111; // Rn
449 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
451 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
452 let Inst{31-27} = 0b11101;
453 let Inst{26-25} = 0b01;
454 let Inst{24-21} = opcod;
455 let Inst{19-16} = 0b1111; // Rn
456 let Inst{14-12} = 0b000; // imm3
457 let Inst{7-6} = 0b00; // imm2
458 let Inst{5-4} = 0b00; // type
461 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
462 opc, ".w\t$Rd, $ShiftedRm",
463 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
464 let Inst{31-27} = 0b11101;
465 let Inst{26-25} = 0b01;
466 let Inst{24-21} = opcod;
467 let Inst{19-16} = 0b1111; // Rn
471 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
472 /// binary operation that produces a value. These are predicable and can be
473 /// changed to modify CPSR.
474 multiclass T2I_bin_irs<bits<4> opcod, string opc,
475 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
476 PatFrag opnode, string baseOpc, bit Commutable = 0,
479 def ri : T2sTwoRegImm<
480 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
481 opc, "\t$Rd, $Rn, $imm",
482 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
483 let Inst{31-27} = 0b11110;
485 let Inst{24-21} = opcod;
489 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
490 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
491 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
492 let isCommutable = Commutable;
493 let Inst{31-27} = 0b11101;
494 let Inst{26-25} = 0b01;
495 let Inst{24-21} = opcod;
496 let Inst{14-12} = 0b000; // imm3
497 let Inst{7-6} = 0b00; // imm2
498 let Inst{5-4} = 0b00; // type
501 def rs : T2sTwoRegShiftedReg<
502 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
503 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
504 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
505 let Inst{31-27} = 0b11101;
506 let Inst{26-25} = 0b01;
507 let Inst{24-21} = opcod;
509 // Assembly aliases for optional destination operand when it's the same
510 // as the source operand.
511 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
512 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
513 t2_so_imm:$imm, pred:$p,
515 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
516 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
519 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
520 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
521 t2_so_reg:$shift, pred:$p,
525 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
526 // the ".w" suffix to indicate that they are wide.
527 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
528 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
529 PatFrag opnode, string baseOpc, bit Commutable = 0> :
530 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
531 // Assembler aliases w/o the ".w" suffix.
532 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
533 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
536 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
537 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
538 t2_so_reg:$shift, pred:$p,
541 // and with the optional destination operand, too.
542 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
543 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
546 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
547 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
548 t2_so_reg:$shift, pred:$p,
552 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
553 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
554 /// it is equivalent to the T2I_bin_irs counterpart.
555 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
557 def ri : T2sTwoRegImm<
558 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
559 opc, ".w\t$Rd, $Rn, $imm",
560 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
561 let Inst{31-27} = 0b11110;
563 let Inst{24-21} = opcod;
567 def rr : T2sThreeReg<
568 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
569 opc, "\t$Rd, $Rn, $Rm",
570 [/* For disassembly only; pattern left blank */]> {
571 let Inst{31-27} = 0b11101;
572 let Inst{26-25} = 0b01;
573 let Inst{24-21} = opcod;
574 let Inst{14-12} = 0b000; // imm3
575 let Inst{7-6} = 0b00; // imm2
576 let Inst{5-4} = 0b00; // type
579 def rs : T2sTwoRegShiftedReg<
580 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
581 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
582 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
583 let Inst{31-27} = 0b11101;
584 let Inst{26-25} = 0b01;
585 let Inst{24-21} = opcod;
589 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
590 /// instruction modifies the CPSR register.
591 let isCodeGenOnly = 1, Defs = [CPSR] in {
592 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
593 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
594 PatFrag opnode, bit Commutable = 0> {
596 def ri : T2TwoRegImm<
597 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
598 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
599 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
600 let Inst{31-27} = 0b11110;
602 let Inst{24-21} = opcod;
603 let Inst{20} = 1; // The S bit.
608 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
609 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
610 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
611 let isCommutable = Commutable;
612 let Inst{31-27} = 0b11101;
613 let Inst{26-25} = 0b01;
614 let Inst{24-21} = opcod;
615 let Inst{20} = 1; // The S bit.
616 let Inst{14-12} = 0b000; // imm3
617 let Inst{7-6} = 0b00; // imm2
618 let Inst{5-4} = 0b00; // type
621 def rs : T2TwoRegShiftedReg<
622 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
623 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
624 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
625 let Inst{31-27} = 0b11101;
626 let Inst{26-25} = 0b01;
627 let Inst{24-21} = opcod;
628 let Inst{20} = 1; // The S bit.
633 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
634 /// patterns for a binary operation that produces a value.
635 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
636 bit Commutable = 0> {
638 // The register-immediate version is re-materializable. This is useful
639 // in particular for taking the address of a local.
640 let isReMaterializable = 1 in {
641 def ri : T2sTwoRegImm<
642 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
643 opc, ".w\t$Rd, $Rn, $imm",
644 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
645 let Inst{31-27} = 0b11110;
648 let Inst{23-21} = op23_21;
654 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
655 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
656 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
660 let Inst{31-27} = 0b11110;
661 let Inst{26} = imm{11};
662 let Inst{25-24} = 0b10;
663 let Inst{23-21} = op23_21;
664 let Inst{20} = 0; // The S bit.
665 let Inst{19-16} = Rn;
667 let Inst{14-12} = imm{10-8};
669 let Inst{7-0} = imm{7-0};
672 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
673 opc, ".w\t$Rd, $Rn, $Rm",
674 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
675 let isCommutable = Commutable;
676 let Inst{31-27} = 0b11101;
677 let Inst{26-25} = 0b01;
679 let Inst{23-21} = op23_21;
680 let Inst{14-12} = 0b000; // imm3
681 let Inst{7-6} = 0b00; // imm2
682 let Inst{5-4} = 0b00; // type
685 def rs : T2sTwoRegShiftedReg<
686 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
687 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
688 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
689 let Inst{31-27} = 0b11101;
690 let Inst{26-25} = 0b01;
692 let Inst{23-21} = op23_21;
696 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
697 /// for a binary operation that produces a value and use the carry
698 /// bit. It's not predicable.
699 let Defs = [CPSR], Uses = [CPSR] in {
700 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
701 bit Commutable = 0> {
703 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
704 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
705 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
706 Requires<[IsThumb2]> {
707 let Inst{31-27} = 0b11110;
709 let Inst{24-21} = opcod;
713 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
714 opc, ".w\t$Rd, $Rn, $Rm",
715 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
716 Requires<[IsThumb2]> {
717 let isCommutable = Commutable;
718 let Inst{31-27} = 0b11101;
719 let Inst{26-25} = 0b01;
720 let Inst{24-21} = opcod;
721 let Inst{14-12} = 0b000; // imm3
722 let Inst{7-6} = 0b00; // imm2
723 let Inst{5-4} = 0b00; // type
726 def rs : T2sTwoRegShiftedReg<
727 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
728 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
729 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
730 Requires<[IsThumb2]> {
731 let Inst{31-27} = 0b11101;
732 let Inst{26-25} = 0b01;
733 let Inst{24-21} = opcod;
738 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
739 /// version is not needed since this is only for codegen.
740 let isCodeGenOnly = 1, Defs = [CPSR] in {
741 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
743 def ri : T2TwoRegImm<
744 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
745 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
746 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
747 let Inst{31-27} = 0b11110;
749 let Inst{24-21} = opcod;
750 let Inst{20} = 1; // The S bit.
754 def rs : T2TwoRegShiftedReg<
755 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
756 IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
757 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
758 let Inst{31-27} = 0b11101;
759 let Inst{26-25} = 0b01;
760 let Inst{24-21} = opcod;
761 let Inst{20} = 1; // The S bit.
766 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
767 // rotate operation that produces a value.
768 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
771 def ri : T2sTwoRegShiftImm<
772 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
773 opc, ".w\t$Rd, $Rm, $imm",
774 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
775 let Inst{31-27} = 0b11101;
776 let Inst{26-21} = 0b010010;
777 let Inst{19-16} = 0b1111; // Rn
778 let Inst{5-4} = opcod;
781 def rr : T2sThreeReg<
782 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
783 opc, ".w\t$Rd, $Rn, $Rm",
784 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
785 let Inst{31-27} = 0b11111;
786 let Inst{26-23} = 0b0100;
787 let Inst{22-21} = opcod;
788 let Inst{15-12} = 0b1111;
789 let Inst{7-4} = 0b0000;
792 // Optional destination register
793 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
794 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
797 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
798 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
802 // Assembler aliases w/o the ".w" suffix.
803 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
804 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
807 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
808 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
812 // and with the optional destination operand, too.
813 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
814 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
817 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
818 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
823 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
824 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
825 /// a explicit result, only implicitly set CPSR.
826 let isCompare = 1, Defs = [CPSR] in {
827 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
828 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
831 def ri : T2OneRegCmpImm<
832 (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
833 opc, ".w\t$Rn, $imm",
834 [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
835 let Inst{31-27} = 0b11110;
837 let Inst{24-21} = opcod;
838 let Inst{20} = 1; // The S bit.
840 let Inst{11-8} = 0b1111; // Rd
843 def rr : T2TwoRegCmp<
844 (outs), (ins GPR:$Rn, rGPR:$Rm), iir,
846 [(opnode GPR:$Rn, rGPR:$Rm)]> {
847 let Inst{31-27} = 0b11101;
848 let Inst{26-25} = 0b01;
849 let Inst{24-21} = opcod;
850 let Inst{20} = 1; // The S bit.
851 let Inst{14-12} = 0b000; // imm3
852 let Inst{11-8} = 0b1111; // Rd
853 let Inst{7-6} = 0b00; // imm2
854 let Inst{5-4} = 0b00; // type
857 def rs : T2OneRegCmpShiftedReg<
858 (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
859 opc, ".w\t$Rn, $ShiftedRm",
860 [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
861 let Inst{31-27} = 0b11101;
862 let Inst{26-25} = 0b01;
863 let Inst{24-21} = opcod;
864 let Inst{20} = 1; // The S bit.
865 let Inst{11-8} = 0b1111; // Rd
870 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
871 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
872 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
874 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
875 opc, ".w\t$Rt, $addr",
876 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
877 let Inst{31-27} = 0b11111;
878 let Inst{26-25} = 0b00;
879 let Inst{24} = signed;
881 let Inst{22-21} = opcod;
882 let Inst{20} = 1; // load
885 let Inst{15-12} = Rt;
888 let addr{12} = 1; // add = TRUE
889 let Inst{19-16} = addr{16-13}; // Rn
890 let Inst{23} = addr{12}; // U
891 let Inst{11-0} = addr{11-0}; // imm
893 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_imm8:$addr), iii,
895 [(set target:$Rt, (opnode t2addrmode_imm8:$addr))]> {
896 let Inst{31-27} = 0b11111;
897 let Inst{26-25} = 0b00;
898 let Inst{24} = signed;
900 let Inst{22-21} = opcod;
901 let Inst{20} = 1; // load
903 // Offset: index==TRUE, wback==FALSE
904 let Inst{10} = 1; // The P bit.
905 let Inst{8} = 0; // The W bit.
908 let Inst{15-12} = Rt;
911 let Inst{19-16} = addr{12-9}; // Rn
912 let Inst{9} = addr{8}; // U
913 let Inst{7-0} = addr{7-0}; // imm
915 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
916 opc, ".w\t$Rt, $addr",
917 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
918 let Inst{31-27} = 0b11111;
919 let Inst{26-25} = 0b00;
920 let Inst{24} = signed;
922 let Inst{22-21} = opcod;
923 let Inst{20} = 1; // load
924 let Inst{11-6} = 0b000000;
927 let Inst{15-12} = Rt;
930 let Inst{19-16} = addr{9-6}; // Rn
931 let Inst{3-0} = addr{5-2}; // Rm
932 let Inst{5-4} = addr{1-0}; // imm
934 let DecoderMethod = "DecodeT2LoadShift";
937 // FIXME: Is the pci variant actually needed?
938 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
939 opc, ".w\t$Rt, $addr",
940 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
941 let isReMaterializable = 1;
942 let Inst{31-27} = 0b11111;
943 let Inst{26-25} = 0b00;
944 let Inst{24} = signed;
945 let Inst{23} = ?; // add = (U == '1')
946 let Inst{22-21} = opcod;
947 let Inst{20} = 1; // load
948 let Inst{19-16} = 0b1111; // Rn
951 let Inst{15-12} = Rt{3-0};
952 let Inst{11-0} = addr{11-0};
956 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
957 multiclass T2I_st<bits<2> opcod, string opc,
958 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
960 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
961 opc, ".w\t$Rt, $addr",
962 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
963 let Inst{31-27} = 0b11111;
964 let Inst{26-23} = 0b0001;
965 let Inst{22-21} = opcod;
966 let Inst{20} = 0; // !load
969 let Inst{15-12} = Rt;
972 let addr{12} = 1; // add = TRUE
973 let Inst{19-16} = addr{16-13}; // Rn
974 let Inst{23} = addr{12}; // U
975 let Inst{11-0} = addr{11-0}; // imm
977 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_imm8:$addr), iii,
979 [(opnode target:$Rt, t2addrmode_imm8:$addr)]> {
980 let Inst{31-27} = 0b11111;
981 let Inst{26-23} = 0b0000;
982 let Inst{22-21} = opcod;
983 let Inst{20} = 0; // !load
985 // Offset: index==TRUE, wback==FALSE
986 let Inst{10} = 1; // The P bit.
987 let Inst{8} = 0; // The W bit.
990 let Inst{15-12} = Rt;
993 let Inst{19-16} = addr{12-9}; // Rn
994 let Inst{9} = addr{8}; // U
995 let Inst{7-0} = addr{7-0}; // imm
997 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
998 opc, ".w\t$Rt, $addr",
999 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1000 let Inst{31-27} = 0b11111;
1001 let Inst{26-23} = 0b0000;
1002 let Inst{22-21} = opcod;
1003 let Inst{20} = 0; // !load
1004 let Inst{11-6} = 0b000000;
1007 let Inst{15-12} = Rt;
1010 let Inst{19-16} = addr{9-6}; // Rn
1011 let Inst{3-0} = addr{5-2}; // Rm
1012 let Inst{5-4} = addr{1-0}; // imm
1016 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1017 /// register and one whose operand is a register rotated by 8/16/24.
1018 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1019 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1020 opc, ".w\t$Rd, $Rm$rot",
1021 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1022 Requires<[IsThumb2]> {
1023 let Inst{31-27} = 0b11111;
1024 let Inst{26-23} = 0b0100;
1025 let Inst{22-20} = opcod;
1026 let Inst{19-16} = 0b1111; // Rn
1027 let Inst{15-12} = 0b1111;
1031 let Inst{5-4} = rot{1-0}; // rotate
1034 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1035 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1036 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1037 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1038 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1039 Requires<[HasT2ExtractPack, IsThumb2]> {
1041 let Inst{31-27} = 0b11111;
1042 let Inst{26-23} = 0b0100;
1043 let Inst{22-20} = opcod;
1044 let Inst{19-16} = 0b1111; // Rn
1045 let Inst{15-12} = 0b1111;
1047 let Inst{5-4} = rot;
1050 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1052 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1053 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1054 opc, "\t$Rd, $Rm$rot", []>,
1055 Requires<[IsThumb2, HasT2ExtractPack]> {
1057 let Inst{31-27} = 0b11111;
1058 let Inst{26-23} = 0b0100;
1059 let Inst{22-20} = opcod;
1060 let Inst{19-16} = 0b1111; // Rn
1061 let Inst{15-12} = 0b1111;
1063 let Inst{5-4} = rot;
1066 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1067 /// register and one whose operand is a register rotated by 8/16/24.
1068 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1069 : T2ThreeReg<(outs rGPR:$Rd),
1070 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1071 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1072 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1073 Requires<[HasT2ExtractPack, IsThumb2]> {
1075 let Inst{31-27} = 0b11111;
1076 let Inst{26-23} = 0b0100;
1077 let Inst{22-20} = opcod;
1078 let Inst{15-12} = 0b1111;
1080 let Inst{5-4} = rot;
1083 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1084 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1085 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1087 let Inst{31-27} = 0b11111;
1088 let Inst{26-23} = 0b0100;
1089 let Inst{22-20} = opcod;
1090 let Inst{15-12} = 0b1111;
1092 let Inst{5-4} = rot;
1095 //===----------------------------------------------------------------------===//
1097 //===----------------------------------------------------------------------===//
1099 //===----------------------------------------------------------------------===//
1100 // Miscellaneous Instructions.
1103 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1104 string asm, list<dag> pattern>
1105 : T2XI<oops, iops, itin, asm, pattern> {
1109 let Inst{11-8} = Rd;
1110 let Inst{26} = label{11};
1111 let Inst{14-12} = label{10-8};
1112 let Inst{7-0} = label{7-0};
1115 // LEApcrel - Load a pc-relative address into a register without offending the
1117 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1118 (ins t2adrlabel:$addr, pred:$p),
1119 IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1120 let Inst{31-27} = 0b11110;
1121 let Inst{25-24} = 0b10;
1122 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1125 let Inst{19-16} = 0b1111; // Rn
1130 let Inst{11-8} = Rd;
1131 let Inst{23} = addr{12};
1132 let Inst{21} = addr{12};
1133 let Inst{26} = addr{11};
1134 let Inst{14-12} = addr{10-8};
1135 let Inst{7-0} = addr{7-0};
1138 let neverHasSideEffects = 1, isReMaterializable = 1 in
1139 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1141 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1142 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1147 //===----------------------------------------------------------------------===//
1148 // Load / store Instructions.
1152 let canFoldAsLoad = 1, isReMaterializable = 1 in
1153 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1154 UnOpFrag<(load node:$Src)>>;
1156 // Loads with zero extension
1157 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1158 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1159 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1160 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1162 // Loads with sign extension
1163 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1164 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1165 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1166 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1168 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1170 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1171 (ins t2addrmode_imm8s4:$addr),
1172 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1173 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1175 // zextload i1 -> zextload i8
1176 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1177 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1178 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1179 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1180 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1181 (t2LDRBs t2addrmode_so_reg:$addr)>;
1182 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1183 (t2LDRBpci tconstpool:$addr)>;
1185 // extload -> zextload
1186 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1188 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1189 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1190 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1191 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1192 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1193 (t2LDRBs t2addrmode_so_reg:$addr)>;
1194 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1195 (t2LDRBpci tconstpool:$addr)>;
1197 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1198 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1199 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1200 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1201 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1202 (t2LDRBs t2addrmode_so_reg:$addr)>;
1203 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1204 (t2LDRBpci tconstpool:$addr)>;
1206 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1207 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1208 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1209 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1210 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1211 (t2LDRHs t2addrmode_so_reg:$addr)>;
1212 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1213 (t2LDRHpci tconstpool:$addr)>;
1215 // FIXME: The destination register of the loads and stores can't be PC, but
1216 // can be SP. We need another regclass (similar to rGPR) to represent
1217 // that. Not a pressing issue since these are selected manually,
1222 let mayLoad = 1, neverHasSideEffects = 1 in {
1223 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1224 (ins t2addrmode_imm8:$addr),
1225 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1226 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1229 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1230 (ins GPR:$base, t2am_imm8_offset:$addr),
1231 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1232 "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1235 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1236 (ins t2addrmode_imm8:$addr),
1237 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1238 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1240 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1241 (ins GPR:$base, t2am_imm8_offset:$addr),
1242 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1243 "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1246 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1247 (ins t2addrmode_imm8:$addr),
1248 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1249 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1251 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1252 (ins GPR:$base, t2am_imm8_offset:$addr),
1253 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1254 "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1257 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1258 (ins t2addrmode_imm8:$addr),
1259 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1260 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1262 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1263 (ins GPR:$base, t2am_imm8_offset:$addr),
1264 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1265 "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1268 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1269 (ins t2addrmode_imm8:$addr),
1270 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1271 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1273 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1274 (ins GPR:$base, t2am_imm8_offset:$addr),
1275 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1276 "ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1278 } // mayLoad = 1, neverHasSideEffects = 1
1280 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1281 // for disassembly only.
1282 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1283 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1284 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1285 "\t$Rt, $addr", []> {
1286 let Inst{31-27} = 0b11111;
1287 let Inst{26-25} = 0b00;
1288 let Inst{24} = signed;
1290 let Inst{22-21} = type;
1291 let Inst{20} = 1; // load
1293 let Inst{10-8} = 0b110; // PUW.
1297 let Inst{15-12} = Rt;
1298 let Inst{19-16} = addr{12-9};
1299 let Inst{7-0} = addr{7-0};
1302 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1303 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1304 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1305 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1306 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1309 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1310 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1311 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1312 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1313 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1314 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1317 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1318 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1319 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1320 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1323 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPRnopc:$base_wb),
1324 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1325 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1326 "str", "\t$Rt, [$Rn, $addr]!",
1327 "$Rn = $base_wb,@earlyclobber $base_wb",
1328 [(set GPRnopc:$base_wb,
1329 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1331 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPRnopc:$base_wb),
1332 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1333 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1334 "str", "\t$Rt, [$Rn], $addr",
1335 "$Rn = $base_wb,@earlyclobber $base_wb",
1336 [(set GPRnopc:$base_wb,
1337 (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1339 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPRnopc:$base_wb),
1340 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1341 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1342 "strh", "\t$Rt, [$Rn, $addr]!",
1343 "$Rn = $base_wb,@earlyclobber $base_wb",
1344 [(set GPRnopc:$base_wb,
1345 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1347 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPRnopc:$base_wb),
1348 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1349 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1350 "strh", "\t$Rt, [$Rn], $addr",
1351 "$Rn = $base_wb,@earlyclobber $base_wb",
1352 [(set GPRnopc:$base_wb,
1353 (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1355 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPRnopc:$base_wb),
1356 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1357 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1358 "strb", "\t$Rt, [$Rn, $addr]!",
1359 "$Rn = $base_wb,@earlyclobber $base_wb",
1360 [(set GPRnopc:$base_wb,
1361 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1363 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPRnopc:$base_wb),
1364 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1365 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1366 "strb", "\t$Rt, [$Rn], $addr",
1367 "$Rn = $base_wb,@earlyclobber $base_wb",
1368 [(set GPRnopc:$base_wb,
1369 (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1371 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1373 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1374 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1375 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1376 "\t$Rt, $addr", []> {
1377 let Inst{31-27} = 0b11111;
1378 let Inst{26-25} = 0b00;
1379 let Inst{24} = 0; // not signed
1381 let Inst{22-21} = type;
1382 let Inst{20} = 0; // store
1384 let Inst{10-8} = 0b110; // PUW
1388 let Inst{15-12} = Rt;
1389 let Inst{19-16} = addr{12-9};
1390 let Inst{7-0} = addr{7-0};
1393 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1394 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1395 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1397 // ldrd / strd pre / post variants
1398 // For disassembly only.
1400 def t2LDRD_PRE : T2Ii8s4Tied<1, 1, 1,
1401 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1402 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1403 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1405 def t2LDRD_POST : T2Ii8s4Tied<0, 1, 1,
1406 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1407 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1408 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1410 def t2STRD_PRE : T2Ii8s4Tied<1, 1, 0, (outs GPR:$wb),
1411 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1412 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1414 def t2STRD_POST : T2Ii8s4Tied<0, 1, 0, (outs GPR:$wb),
1415 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1416 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1418 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1419 // data/instruction access. These are for disassembly only.
1420 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1421 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1422 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1424 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1426 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1427 let Inst{31-25} = 0b1111100;
1428 let Inst{24} = instr;
1430 let Inst{21} = write;
1432 let Inst{15-12} = 0b1111;
1435 let addr{12} = 1; // add = TRUE
1436 let Inst{19-16} = addr{16-13}; // Rn
1437 let Inst{23} = addr{12}; // U
1438 let Inst{11-0} = addr{11-0}; // imm12
1441 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1443 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1444 let Inst{31-25} = 0b1111100;
1445 let Inst{24} = instr;
1446 let Inst{23} = 0; // U = 0
1448 let Inst{21} = write;
1450 let Inst{15-12} = 0b1111;
1451 let Inst{11-8} = 0b1100;
1454 let Inst{19-16} = addr{12-9}; // Rn
1455 let Inst{7-0} = addr{7-0}; // imm8
1458 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1460 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1461 let Inst{31-25} = 0b1111100;
1462 let Inst{24} = instr;
1463 let Inst{23} = 0; // add = TRUE for T1
1465 let Inst{21} = write;
1467 let Inst{15-12} = 0b1111;
1468 let Inst{11-6} = 0000000;
1471 let Inst{19-16} = addr{9-6}; // Rn
1472 let Inst{3-0} = addr{5-2}; // Rm
1473 let Inst{5-4} = addr{1-0}; // imm2
1475 let DecoderMethod = "DecodeT2LoadShift";
1479 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1480 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1481 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1483 //===----------------------------------------------------------------------===//
1484 // Load / store multiple Instructions.
1487 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1488 InstrItinClass itin_upd, bit L_bit> {
1490 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1491 itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1495 let Inst{31-27} = 0b11101;
1496 let Inst{26-25} = 0b00;
1497 let Inst{24-23} = 0b01; // Increment After
1499 let Inst{21} = 0; // No writeback
1500 let Inst{20} = L_bit;
1501 let Inst{19-16} = Rn;
1502 let Inst{15-0} = regs;
1505 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1506 itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1510 let Inst{31-27} = 0b11101;
1511 let Inst{26-25} = 0b00;
1512 let Inst{24-23} = 0b01; // Increment After
1514 let Inst{21} = 1; // Writeback
1515 let Inst{20} = L_bit;
1516 let Inst{19-16} = Rn;
1517 let Inst{15-0} = regs;
1520 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1521 itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1525 let Inst{31-27} = 0b11101;
1526 let Inst{26-25} = 0b00;
1527 let Inst{24-23} = 0b10; // Decrement Before
1529 let Inst{21} = 0; // No writeback
1530 let Inst{20} = L_bit;
1531 let Inst{19-16} = Rn;
1532 let Inst{15-0} = regs;
1535 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1536 itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1540 let Inst{31-27} = 0b11101;
1541 let Inst{26-25} = 0b00;
1542 let Inst{24-23} = 0b10; // Decrement Before
1544 let Inst{21} = 1; // Writeback
1545 let Inst{20} = L_bit;
1546 let Inst{19-16} = Rn;
1547 let Inst{15-0} = regs;
1551 let neverHasSideEffects = 1 in {
1553 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1554 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1556 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1557 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1559 } // neverHasSideEffects
1562 //===----------------------------------------------------------------------===//
1563 // Move Instructions.
1566 let neverHasSideEffects = 1 in
1567 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1568 "mov", ".w\t$Rd, $Rm", []> {
1569 let Inst{31-27} = 0b11101;
1570 let Inst{26-25} = 0b01;
1571 let Inst{24-21} = 0b0010;
1572 let Inst{19-16} = 0b1111; // Rn
1573 let Inst{14-12} = 0b000;
1574 let Inst{7-4} = 0b0000;
1577 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1578 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1579 AddedComplexity = 1 in
1580 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1581 "mov", ".w\t$Rd, $imm",
1582 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1583 let Inst{31-27} = 0b11110;
1585 let Inst{24-21} = 0b0010;
1586 let Inst{19-16} = 0b1111; // Rn
1590 def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1591 pred:$p, cc_out:$s)>;
1593 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1594 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1595 "movw", "\t$Rd, $imm",
1596 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1597 let Inst{31-27} = 0b11110;
1599 let Inst{24-21} = 0b0010;
1600 let Inst{20} = 0; // The S bit.
1606 let Inst{11-8} = Rd;
1607 let Inst{19-16} = imm{15-12};
1608 let Inst{26} = imm{11};
1609 let Inst{14-12} = imm{10-8};
1610 let Inst{7-0} = imm{7-0};
1613 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1614 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1616 let Constraints = "$src = $Rd" in {
1617 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1618 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1619 "movt", "\t$Rd, $imm",
1621 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1622 let Inst{31-27} = 0b11110;
1624 let Inst{24-21} = 0b0110;
1625 let Inst{20} = 0; // The S bit.
1631 let Inst{11-8} = Rd;
1632 let Inst{19-16} = imm{15-12};
1633 let Inst{26} = imm{11};
1634 let Inst{14-12} = imm{10-8};
1635 let Inst{7-0} = imm{7-0};
1638 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1639 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1642 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1644 //===----------------------------------------------------------------------===//
1645 // Extend Instructions.
1650 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1651 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1652 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1653 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1654 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1656 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1657 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1658 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1659 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1660 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1662 // TODO: SXT(A){B|H}16
1666 let AddedComplexity = 16 in {
1667 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1668 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1669 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1670 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1671 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1672 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1674 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1675 // The transformation should probably be done as a combiner action
1676 // instead so we can include a check for masking back in the upper
1677 // eight bits of the source into the lower eight bits of the result.
1678 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1679 // (t2UXTB16 rGPR:$Src, 3)>,
1680 // Requires<[HasT2ExtractPack, IsThumb2]>;
1681 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1682 (t2UXTB16 rGPR:$Src, 1)>,
1683 Requires<[HasT2ExtractPack, IsThumb2]>;
1685 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1686 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1687 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1688 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1689 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1692 //===----------------------------------------------------------------------===//
1693 // Arithmetic Instructions.
1696 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1697 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1698 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1699 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1701 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1702 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1703 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1704 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1705 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1706 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1707 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1709 let hasPostISelHook = 1 in {
1710 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1711 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1712 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1713 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1717 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1718 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1719 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1720 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1722 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1723 // The assume-no-carry-in form uses the negation of the input since add/sub
1724 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1725 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1727 // The AddedComplexity preferences the first variant over the others since
1728 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1729 let AddedComplexity = 1 in
1730 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1731 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1732 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1733 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1734 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1735 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1736 let AddedComplexity = 1 in
1737 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1738 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1739 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1740 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1741 // The with-carry-in form matches bitwise not instead of the negation.
1742 // Effectively, the inverse interpretation of the carry flag already accounts
1743 // for part of the negation.
1744 let AddedComplexity = 1 in
1745 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1746 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1747 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1748 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1750 // Select Bytes -- for disassembly only
1752 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1753 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1754 Requires<[IsThumb2, HasThumb2DSP]> {
1755 let Inst{31-27} = 0b11111;
1756 let Inst{26-24} = 0b010;
1758 let Inst{22-20} = 0b010;
1759 let Inst{15-12} = 0b1111;
1761 let Inst{6-4} = 0b000;
1764 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1765 // And Miscellaneous operations -- for disassembly only
1766 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1767 list<dag> pat = [/* For disassembly only; pattern left blank */],
1768 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1769 string asm = "\t$Rd, $Rn, $Rm">
1770 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1771 Requires<[IsThumb2, HasThumb2DSP]> {
1772 let Inst{31-27} = 0b11111;
1773 let Inst{26-23} = 0b0101;
1774 let Inst{22-20} = op22_20;
1775 let Inst{15-12} = 0b1111;
1776 let Inst{7-4} = op7_4;
1782 let Inst{11-8} = Rd;
1783 let Inst{19-16} = Rn;
1787 // Saturating add/subtract -- for disassembly only
1789 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1790 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1791 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1792 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1793 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1794 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1795 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1796 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1797 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1798 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1799 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1800 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1801 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1802 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1803 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1804 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1805 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1806 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1807 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1808 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1809 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1810 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1812 // Signed/Unsigned add/subtract -- for disassembly only
1814 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1815 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1816 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1817 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1818 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1819 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1820 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1821 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1822 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1823 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1824 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1825 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1827 // Signed/Unsigned halving add/subtract -- for disassembly only
1829 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1830 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1831 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1832 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1833 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1834 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1835 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1836 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1837 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1838 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1839 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1840 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1842 // Helper class for disassembly only
1843 // A6.3.16 & A6.3.17
1844 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1845 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1846 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1847 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1848 let Inst{31-27} = 0b11111;
1849 let Inst{26-24} = 0b011;
1850 let Inst{23} = long;
1851 let Inst{22-20} = op22_20;
1852 let Inst{7-4} = op7_4;
1855 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1856 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1857 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1858 let Inst{31-27} = 0b11111;
1859 let Inst{26-24} = 0b011;
1860 let Inst{23} = long;
1861 let Inst{22-20} = op22_20;
1862 let Inst{7-4} = op7_4;
1865 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1867 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1868 (ins rGPR:$Rn, rGPR:$Rm),
1869 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1870 Requires<[IsThumb2, HasThumb2DSP]> {
1871 let Inst{15-12} = 0b1111;
1873 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1874 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1875 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1876 Requires<[IsThumb2, HasThumb2DSP]>;
1878 // Signed/Unsigned saturate -- for disassembly only
1880 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1881 string opc, string asm, list<dag> pattern>
1882 : T2I<oops, iops, itin, opc, asm, pattern> {
1888 let Inst{11-8} = Rd;
1889 let Inst{19-16} = Rn;
1890 let Inst{4-0} = sat_imm;
1891 let Inst{21} = sh{5};
1892 let Inst{14-12} = sh{4-2};
1893 let Inst{7-6} = sh{1-0};
1897 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1898 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1899 [/* For disassembly only; pattern left blank */]> {
1900 let Inst{31-27} = 0b11110;
1901 let Inst{25-22} = 0b1100;
1906 def t2SSAT16: T2SatI<
1907 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
1908 "ssat16", "\t$Rd, $sat_imm, $Rn",
1909 [/* For disassembly only; pattern left blank */]>,
1910 Requires<[IsThumb2, HasThumb2DSP]> {
1911 let Inst{31-27} = 0b11110;
1912 let Inst{25-22} = 0b1100;
1915 let Inst{21} = 1; // sh = '1'
1916 let Inst{14-12} = 0b000; // imm3 = '000'
1917 let Inst{7-6} = 0b00; // imm2 = '00'
1921 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1922 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1923 [/* For disassembly only; pattern left blank */]> {
1924 let Inst{31-27} = 0b11110;
1925 let Inst{25-22} = 0b1110;
1930 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn),
1932 "usat16", "\t$Rd, $sat_imm, $Rn",
1933 [/* For disassembly only; pattern left blank */]>,
1934 Requires<[IsThumb2, HasThumb2DSP]> {
1935 let Inst{31-27} = 0b11110;
1936 let Inst{25-22} = 0b1110;
1939 let Inst{21} = 1; // sh = '1'
1940 let Inst{14-12} = 0b000; // imm3 = '000'
1941 let Inst{7-6} = 0b00; // imm2 = '00'
1944 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1945 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1947 //===----------------------------------------------------------------------===//
1948 // Shift and rotate Instructions.
1951 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
1952 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
1953 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
1954 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
1955 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
1956 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
1957 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
1958 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
1960 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
1961 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
1962 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
1964 let Uses = [CPSR] in {
1965 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1966 "rrx", "\t$Rd, $Rm",
1967 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
1968 let Inst{31-27} = 0b11101;
1969 let Inst{26-25} = 0b01;
1970 let Inst{24-21} = 0b0010;
1971 let Inst{19-16} = 0b1111; // Rn
1972 let Inst{14-12} = 0b000;
1973 let Inst{7-4} = 0b0011;
1977 let isCodeGenOnly = 1, Defs = [CPSR] in {
1978 def t2MOVsrl_flag : T2TwoRegShiftImm<
1979 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1980 "lsrs", ".w\t$Rd, $Rm, #1",
1981 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
1982 let Inst{31-27} = 0b11101;
1983 let Inst{26-25} = 0b01;
1984 let Inst{24-21} = 0b0010;
1985 let Inst{20} = 1; // The S bit.
1986 let Inst{19-16} = 0b1111; // Rn
1987 let Inst{5-4} = 0b01; // Shift type.
1988 // Shift amount = Inst{14-12:7-6} = 1.
1989 let Inst{14-12} = 0b000;
1990 let Inst{7-6} = 0b01;
1992 def t2MOVsra_flag : T2TwoRegShiftImm<
1993 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1994 "asrs", ".w\t$Rd, $Rm, #1",
1995 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
1996 let Inst{31-27} = 0b11101;
1997 let Inst{26-25} = 0b01;
1998 let Inst{24-21} = 0b0010;
1999 let Inst{20} = 1; // The S bit.
2000 let Inst{19-16} = 0b1111; // Rn
2001 let Inst{5-4} = 0b10; // Shift type.
2002 // Shift amount = Inst{14-12:7-6} = 1.
2003 let Inst{14-12} = 0b000;
2004 let Inst{7-6} = 0b01;
2008 //===----------------------------------------------------------------------===//
2009 // Bitwise Instructions.
2012 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2013 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2014 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2015 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2016 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2017 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2018 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2019 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2020 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2022 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2023 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2024 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2027 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2028 string opc, string asm, list<dag> pattern>
2029 : T2I<oops, iops, itin, opc, asm, pattern> {
2034 let Inst{11-8} = Rd;
2035 let Inst{4-0} = msb{4-0};
2036 let Inst{14-12} = lsb{4-2};
2037 let Inst{7-6} = lsb{1-0};
2040 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2041 string opc, string asm, list<dag> pattern>
2042 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2045 let Inst{19-16} = Rn;
2048 let Constraints = "$src = $Rd" in
2049 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2050 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2051 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2052 let Inst{31-27} = 0b11110;
2053 let Inst{26} = 0; // should be 0.
2055 let Inst{24-20} = 0b10110;
2056 let Inst{19-16} = 0b1111; // Rn
2058 let Inst{5} = 0; // should be 0.
2061 let msb{4-0} = imm{9-5};
2062 let lsb{4-0} = imm{4-0};
2065 def t2SBFX: T2TwoRegBitFI<
2066 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2067 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2068 let Inst{31-27} = 0b11110;
2070 let Inst{24-20} = 0b10100;
2074 def t2UBFX: T2TwoRegBitFI<
2075 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2076 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2077 let Inst{31-27} = 0b11110;
2079 let Inst{24-20} = 0b11100;
2083 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2084 let Constraints = "$src = $Rd" in {
2085 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2086 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2087 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2088 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2089 bf_inv_mask_imm:$imm))]> {
2090 let Inst{31-27} = 0b11110;
2091 let Inst{26} = 0; // should be 0.
2093 let Inst{24-20} = 0b10110;
2095 let Inst{5} = 0; // should be 0.
2098 let msb{4-0} = imm{9-5};
2099 let lsb{4-0} = imm{4-0};
2102 // GNU as only supports this form of bfi (w/ 4 arguments)
2103 let isAsmParserOnly = 1 in
2104 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2105 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2107 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2109 let Inst{31-27} = 0b11110;
2110 let Inst{26} = 0; // should be 0.
2112 let Inst{24-20} = 0b10110;
2114 let Inst{5} = 0; // should be 0.
2118 let msb{4-0} = width; // Custom encoder => lsb+width-1
2119 let lsb{4-0} = lsbit;
2123 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2124 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2125 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2128 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2129 let AddedComplexity = 1 in
2130 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2131 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2132 UnOpFrag<(not node:$Src)>, 1, 1>;
2135 let AddedComplexity = 1 in
2136 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2137 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2139 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2140 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2141 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2142 Requires<[IsThumb2]>;
2144 def : T2Pat<(t2_so_imm_not:$src),
2145 (t2MVNi t2_so_imm_not:$src)>;
2147 //===----------------------------------------------------------------------===//
2148 // Multiply Instructions.
2150 let isCommutable = 1 in
2151 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2152 "mul", "\t$Rd, $Rn, $Rm",
2153 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2154 let Inst{31-27} = 0b11111;
2155 let Inst{26-23} = 0b0110;
2156 let Inst{22-20} = 0b000;
2157 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2158 let Inst{7-4} = 0b0000; // Multiply
2161 def t2MLA: T2FourReg<
2162 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2163 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2164 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2165 let Inst{31-27} = 0b11111;
2166 let Inst{26-23} = 0b0110;
2167 let Inst{22-20} = 0b000;
2168 let Inst{7-4} = 0b0000; // Multiply
2171 def t2MLS: T2FourReg<
2172 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2173 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2174 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2175 let Inst{31-27} = 0b11111;
2176 let Inst{26-23} = 0b0110;
2177 let Inst{22-20} = 0b000;
2178 let Inst{7-4} = 0b0001; // Multiply and Subtract
2181 // Extra precision multiplies with low / high results
2182 let neverHasSideEffects = 1 in {
2183 let isCommutable = 1 in {
2184 def t2SMULL : T2MulLong<0b000, 0b0000,
2185 (outs rGPR:$RdLo, rGPR:$RdHi),
2186 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2187 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2189 def t2UMULL : T2MulLong<0b010, 0b0000,
2190 (outs rGPR:$RdLo, rGPR:$RdHi),
2191 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2192 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2195 // Multiply + accumulate
2196 def t2SMLAL : T2MulLong<0b100, 0b0000,
2197 (outs rGPR:$RdLo, rGPR:$RdHi),
2198 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2199 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2201 def t2UMLAL : T2MulLong<0b110, 0b0000,
2202 (outs rGPR:$RdLo, rGPR:$RdHi),
2203 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2204 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2206 def t2UMAAL : T2MulLong<0b110, 0b0110,
2207 (outs rGPR:$RdLo, rGPR:$RdHi),
2208 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2209 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2210 Requires<[IsThumb2, HasThumb2DSP]>;
2211 } // neverHasSideEffects
2213 // Rounding variants of the below included for disassembly only
2215 // Most significant word multiply
2216 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2217 "smmul", "\t$Rd, $Rn, $Rm",
2218 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2219 Requires<[IsThumb2, HasThumb2DSP]> {
2220 let Inst{31-27} = 0b11111;
2221 let Inst{26-23} = 0b0110;
2222 let Inst{22-20} = 0b101;
2223 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2224 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2227 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2228 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2229 Requires<[IsThumb2, HasThumb2DSP]> {
2230 let Inst{31-27} = 0b11111;
2231 let Inst{26-23} = 0b0110;
2232 let Inst{22-20} = 0b101;
2233 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2234 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2237 def t2SMMLA : T2FourReg<
2238 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2239 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2240 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2241 Requires<[IsThumb2, HasThumb2DSP]> {
2242 let Inst{31-27} = 0b11111;
2243 let Inst{26-23} = 0b0110;
2244 let Inst{22-20} = 0b101;
2245 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2248 def t2SMMLAR: T2FourReg<
2249 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2250 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2251 Requires<[IsThumb2, HasThumb2DSP]> {
2252 let Inst{31-27} = 0b11111;
2253 let Inst{26-23} = 0b0110;
2254 let Inst{22-20} = 0b101;
2255 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2258 def t2SMMLS: T2FourReg<
2259 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2260 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2261 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2262 Requires<[IsThumb2, HasThumb2DSP]> {
2263 let Inst{31-27} = 0b11111;
2264 let Inst{26-23} = 0b0110;
2265 let Inst{22-20} = 0b110;
2266 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2269 def t2SMMLSR:T2FourReg<
2270 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2271 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2272 Requires<[IsThumb2, HasThumb2DSP]> {
2273 let Inst{31-27} = 0b11111;
2274 let Inst{26-23} = 0b0110;
2275 let Inst{22-20} = 0b110;
2276 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2279 multiclass T2I_smul<string opc, PatFrag opnode> {
2280 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2281 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2282 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2283 (sext_inreg rGPR:$Rm, i16)))]>,
2284 Requires<[IsThumb2, HasThumb2DSP]> {
2285 let Inst{31-27} = 0b11111;
2286 let Inst{26-23} = 0b0110;
2287 let Inst{22-20} = 0b001;
2288 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2289 let Inst{7-6} = 0b00;
2290 let Inst{5-4} = 0b00;
2293 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2294 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2295 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2296 (sra rGPR:$Rm, (i32 16))))]>,
2297 Requires<[IsThumb2, HasThumb2DSP]> {
2298 let Inst{31-27} = 0b11111;
2299 let Inst{26-23} = 0b0110;
2300 let Inst{22-20} = 0b001;
2301 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2302 let Inst{7-6} = 0b00;
2303 let Inst{5-4} = 0b01;
2306 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2307 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2308 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2309 (sext_inreg rGPR:$Rm, i16)))]>,
2310 Requires<[IsThumb2, HasThumb2DSP]> {
2311 let Inst{31-27} = 0b11111;
2312 let Inst{26-23} = 0b0110;
2313 let Inst{22-20} = 0b001;
2314 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2315 let Inst{7-6} = 0b00;
2316 let Inst{5-4} = 0b10;
2319 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2320 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2321 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2322 (sra rGPR:$Rm, (i32 16))))]>,
2323 Requires<[IsThumb2, HasThumb2DSP]> {
2324 let Inst{31-27} = 0b11111;
2325 let Inst{26-23} = 0b0110;
2326 let Inst{22-20} = 0b001;
2327 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2328 let Inst{7-6} = 0b00;
2329 let Inst{5-4} = 0b11;
2332 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2333 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2334 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2335 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2336 Requires<[IsThumb2, HasThumb2DSP]> {
2337 let Inst{31-27} = 0b11111;
2338 let Inst{26-23} = 0b0110;
2339 let Inst{22-20} = 0b011;
2340 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2341 let Inst{7-6} = 0b00;
2342 let Inst{5-4} = 0b00;
2345 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2346 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2347 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2348 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2349 Requires<[IsThumb2, HasThumb2DSP]> {
2350 let Inst{31-27} = 0b11111;
2351 let Inst{26-23} = 0b0110;
2352 let Inst{22-20} = 0b011;
2353 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2354 let Inst{7-6} = 0b00;
2355 let Inst{5-4} = 0b01;
2360 multiclass T2I_smla<string opc, PatFrag opnode> {
2362 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2363 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2364 [(set rGPR:$Rd, (add rGPR:$Ra,
2365 (opnode (sext_inreg rGPR:$Rn, i16),
2366 (sext_inreg rGPR:$Rm, i16))))]>,
2367 Requires<[IsThumb2, HasThumb2DSP]> {
2368 let Inst{31-27} = 0b11111;
2369 let Inst{26-23} = 0b0110;
2370 let Inst{22-20} = 0b001;
2371 let Inst{7-6} = 0b00;
2372 let Inst{5-4} = 0b00;
2376 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2377 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2378 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2379 (sra rGPR:$Rm, (i32 16)))))]>,
2380 Requires<[IsThumb2, HasThumb2DSP]> {
2381 let Inst{31-27} = 0b11111;
2382 let Inst{26-23} = 0b0110;
2383 let Inst{22-20} = 0b001;
2384 let Inst{7-6} = 0b00;
2385 let Inst{5-4} = 0b01;
2389 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2390 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2391 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2392 (sext_inreg rGPR:$Rm, i16))))]>,
2393 Requires<[IsThumb2, HasThumb2DSP]> {
2394 let Inst{31-27} = 0b11111;
2395 let Inst{26-23} = 0b0110;
2396 let Inst{22-20} = 0b001;
2397 let Inst{7-6} = 0b00;
2398 let Inst{5-4} = 0b10;
2402 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2403 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2404 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2405 (sra rGPR:$Rm, (i32 16)))))]>,
2406 Requires<[IsThumb2, HasThumb2DSP]> {
2407 let Inst{31-27} = 0b11111;
2408 let Inst{26-23} = 0b0110;
2409 let Inst{22-20} = 0b001;
2410 let Inst{7-6} = 0b00;
2411 let Inst{5-4} = 0b11;
2415 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2416 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2417 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2418 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2419 Requires<[IsThumb2, HasThumb2DSP]> {
2420 let Inst{31-27} = 0b11111;
2421 let Inst{26-23} = 0b0110;
2422 let Inst{22-20} = 0b011;
2423 let Inst{7-6} = 0b00;
2424 let Inst{5-4} = 0b00;
2428 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2429 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2430 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2431 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2432 Requires<[IsThumb2, HasThumb2DSP]> {
2433 let Inst{31-27} = 0b11111;
2434 let Inst{26-23} = 0b0110;
2435 let Inst{22-20} = 0b011;
2436 let Inst{7-6} = 0b00;
2437 let Inst{5-4} = 0b01;
2441 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2442 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2444 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2445 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2446 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2447 [/* For disassembly only; pattern left blank */]>,
2448 Requires<[IsThumb2, HasThumb2DSP]>;
2449 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2450 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2451 [/* For disassembly only; pattern left blank */]>,
2452 Requires<[IsThumb2, HasThumb2DSP]>;
2453 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2454 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2455 [/* For disassembly only; pattern left blank */]>,
2456 Requires<[IsThumb2, HasThumb2DSP]>;
2457 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2458 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2459 [/* For disassembly only; pattern left blank */]>,
2460 Requires<[IsThumb2, HasThumb2DSP]>;
2462 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2463 // These are for disassembly only.
2465 def t2SMUAD: T2ThreeReg_mac<
2466 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2467 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2468 Requires<[IsThumb2, HasThumb2DSP]> {
2469 let Inst{15-12} = 0b1111;
2471 def t2SMUADX:T2ThreeReg_mac<
2472 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2473 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2474 Requires<[IsThumb2, HasThumb2DSP]> {
2475 let Inst{15-12} = 0b1111;
2477 def t2SMUSD: T2ThreeReg_mac<
2478 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2479 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2480 Requires<[IsThumb2, HasThumb2DSP]> {
2481 let Inst{15-12} = 0b1111;
2483 def t2SMUSDX:T2ThreeReg_mac<
2484 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2485 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2486 Requires<[IsThumb2, HasThumb2DSP]> {
2487 let Inst{15-12} = 0b1111;
2489 def t2SMLAD : T2FourReg_mac<
2490 0, 0b010, 0b0000, (outs rGPR:$Rd),
2491 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2492 "\t$Rd, $Rn, $Rm, $Ra", []>,
2493 Requires<[IsThumb2, HasThumb2DSP]>;
2494 def t2SMLADX : T2FourReg_mac<
2495 0, 0b010, 0b0001, (outs rGPR:$Rd),
2496 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2497 "\t$Rd, $Rn, $Rm, $Ra", []>,
2498 Requires<[IsThumb2, HasThumb2DSP]>;
2499 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2500 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2501 "\t$Rd, $Rn, $Rm, $Ra", []>,
2502 Requires<[IsThumb2, HasThumb2DSP]>;
2503 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2504 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2505 "\t$Rd, $Rn, $Rm, $Ra", []>,
2506 Requires<[IsThumb2, HasThumb2DSP]>;
2507 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2508 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2509 "\t$Ra, $Rd, $Rm, $Rn", []>,
2510 Requires<[IsThumb2, HasThumb2DSP]>;
2511 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2512 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2513 "\t$Ra, $Rd, $Rm, $Rn", []>,
2514 Requires<[IsThumb2, HasThumb2DSP]>;
2515 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2516 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2517 "\t$Ra, $Rd, $Rm, $Rn", []>,
2518 Requires<[IsThumb2, HasThumb2DSP]>;
2519 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2520 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2521 "\t$Ra, $Rd, $Rm, $Rn", []>,
2522 Requires<[IsThumb2, HasThumb2DSP]>;
2524 //===----------------------------------------------------------------------===//
2525 // Division Instructions.
2526 // Signed and unsigned division on v7-M
2528 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2529 "sdiv", "\t$Rd, $Rn, $Rm",
2530 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2531 Requires<[HasDivide, IsThumb2]> {
2532 let Inst{31-27} = 0b11111;
2533 let Inst{26-21} = 0b011100;
2535 let Inst{15-12} = 0b1111;
2536 let Inst{7-4} = 0b1111;
2539 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2540 "udiv", "\t$Rd, $Rn, $Rm",
2541 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2542 Requires<[HasDivide, IsThumb2]> {
2543 let Inst{31-27} = 0b11111;
2544 let Inst{26-21} = 0b011101;
2546 let Inst{15-12} = 0b1111;
2547 let Inst{7-4} = 0b1111;
2550 //===----------------------------------------------------------------------===//
2551 // Misc. Arithmetic Instructions.
2554 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2555 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2556 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2557 let Inst{31-27} = 0b11111;
2558 let Inst{26-22} = 0b01010;
2559 let Inst{21-20} = op1;
2560 let Inst{15-12} = 0b1111;
2561 let Inst{7-6} = 0b10;
2562 let Inst{5-4} = op2;
2566 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2567 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2569 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2570 "rbit", "\t$Rd, $Rm",
2571 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2573 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2574 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2576 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2577 "rev16", ".w\t$Rd, $Rm",
2578 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2580 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2581 "revsh", ".w\t$Rd, $Rm",
2582 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2584 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2585 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2586 (t2REVSH rGPR:$Rm)>;
2588 def t2PKHBT : T2ThreeReg<
2589 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2590 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
2591 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2592 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2594 Requires<[HasT2ExtractPack, IsThumb2]> {
2595 let Inst{31-27} = 0b11101;
2596 let Inst{26-25} = 0b01;
2597 let Inst{24-20} = 0b01100;
2598 let Inst{5} = 0; // BT form
2602 let Inst{14-12} = sh{4-2};
2603 let Inst{7-6} = sh{1-0};
2606 // Alternate cases for PKHBT where identities eliminate some nodes.
2607 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2608 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2609 Requires<[HasT2ExtractPack, IsThumb2]>;
2610 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2611 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2612 Requires<[HasT2ExtractPack, IsThumb2]>;
2614 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2615 // will match the pattern below.
2616 def t2PKHTB : T2ThreeReg<
2617 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2618 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
2619 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2620 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2622 Requires<[HasT2ExtractPack, IsThumb2]> {
2623 let Inst{31-27} = 0b11101;
2624 let Inst{26-25} = 0b01;
2625 let Inst{24-20} = 0b01100;
2626 let Inst{5} = 1; // TB form
2630 let Inst{14-12} = sh{4-2};
2631 let Inst{7-6} = sh{1-0};
2634 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2635 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2636 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2637 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2638 Requires<[HasT2ExtractPack, IsThumb2]>;
2639 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2640 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2641 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2642 Requires<[HasT2ExtractPack, IsThumb2]>;
2644 //===----------------------------------------------------------------------===//
2645 // Comparison Instructions...
2647 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2648 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2649 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2651 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
2652 (t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
2653 def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
2654 (t2CMPrr GPR:$lhs, rGPR:$rhs)>;
2655 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
2656 (t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
2658 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2659 // Compare-to-zero still works out, just not the relationals
2660 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2661 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2662 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2663 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2664 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2666 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2667 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2669 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2670 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2672 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2673 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2674 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2675 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2676 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2677 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2679 // Conditional moves
2680 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2681 // a two-value operand where a dag node expects two operands. :(
2682 let neverHasSideEffects = 1 in {
2683 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2684 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2686 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2687 RegConstraint<"$false = $Rd">;
2689 let isMoveImm = 1 in
2690 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2691 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2693 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2694 RegConstraint<"$false = $Rd">;
2696 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2697 let isCodeGenOnly = 1 in {
2698 let isMoveImm = 1 in
2699 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2701 "movw", "\t$Rd, $imm", []>,
2702 RegConstraint<"$false = $Rd"> {
2703 let Inst{31-27} = 0b11110;
2705 let Inst{24-21} = 0b0010;
2706 let Inst{20} = 0; // The S bit.
2712 let Inst{11-8} = Rd;
2713 let Inst{19-16} = imm{15-12};
2714 let Inst{26} = imm{11};
2715 let Inst{14-12} = imm{10-8};
2716 let Inst{7-0} = imm{7-0};
2719 let isMoveImm = 1 in
2720 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2721 (ins rGPR:$false, i32imm:$src, pred:$p),
2722 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2724 let isMoveImm = 1 in
2725 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2726 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2727 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2728 imm:$cc, CCR:$ccr))*/]>,
2729 RegConstraint<"$false = $Rd"> {
2730 let Inst{31-27} = 0b11110;
2732 let Inst{24-21} = 0b0011;
2733 let Inst{20} = 0; // The S bit.
2734 let Inst{19-16} = 0b1111; // Rn
2738 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2739 string opc, string asm, list<dag> pattern>
2740 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2741 let Inst{31-27} = 0b11101;
2742 let Inst{26-25} = 0b01;
2743 let Inst{24-21} = 0b0010;
2744 let Inst{20} = 0; // The S bit.
2745 let Inst{19-16} = 0b1111; // Rn
2746 let Inst{5-4} = opcod; // Shift type.
2748 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2749 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2750 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2751 RegConstraint<"$false = $Rd">;
2752 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2753 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2754 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2755 RegConstraint<"$false = $Rd">;
2756 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2757 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2758 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2759 RegConstraint<"$false = $Rd">;
2760 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2761 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2762 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2763 RegConstraint<"$false = $Rd">;
2764 } // isCodeGenOnly = 1
2765 } // neverHasSideEffects
2767 //===----------------------------------------------------------------------===//
2768 // Atomic operations intrinsics
2771 // memory barriers protect the atomic sequences
2772 let hasSideEffects = 1 in {
2773 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2774 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2775 Requires<[IsThumb, HasDB]> {
2777 let Inst{31-4} = 0xf3bf8f5;
2778 let Inst{3-0} = opt;
2782 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2784 [/* For disassembly only; pattern left blank */]>,
2785 Requires<[IsThumb, HasDB]> {
2787 let Inst{31-4} = 0xf3bf8f4;
2788 let Inst{3-0} = opt;
2791 // ISB has only full system option -- for disassembly only
2792 def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2793 [/* For disassembly only; pattern left blank */]>,
2794 Requires<[IsThumb2, HasV7]> {
2795 let Inst{31-4} = 0xf3bf8f6;
2796 let Inst{3-0} = 0b1111;
2799 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2800 InstrItinClass itin, string opc, string asm, string cstr,
2801 list<dag> pattern, bits<4> rt2 = 0b1111>
2802 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2803 let Inst{31-27} = 0b11101;
2804 let Inst{26-20} = 0b0001101;
2805 let Inst{11-8} = rt2;
2806 let Inst{7-6} = 0b01;
2807 let Inst{5-4} = opcod;
2808 let Inst{3-0} = 0b1111;
2812 let Inst{19-16} = addr;
2813 let Inst{15-12} = Rt;
2815 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2816 InstrItinClass itin, string opc, string asm, string cstr,
2817 list<dag> pattern, bits<4> rt2 = 0b1111>
2818 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2819 let Inst{31-27} = 0b11101;
2820 let Inst{26-20} = 0b0001100;
2821 let Inst{11-8} = rt2;
2822 let Inst{7-6} = 0b01;
2823 let Inst{5-4} = opcod;
2829 let Inst{19-16} = addr;
2830 let Inst{15-12} = Rt;
2833 let mayLoad = 1 in {
2834 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2835 AddrModeNone, 4, NoItinerary,
2836 "ldrexb", "\t$Rt, $addr", "", []>;
2837 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2838 AddrModeNone, 4, NoItinerary,
2839 "ldrexh", "\t$Rt, $addr", "", []>;
2840 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2841 AddrModeNone, 4, NoItinerary,
2842 "ldrex", "\t$Rt, $addr", "", []> {
2843 let Inst{31-27} = 0b11101;
2844 let Inst{26-20} = 0b0000101;
2845 let Inst{11-8} = 0b1111;
2846 let Inst{7-0} = 0b00000000; // imm8 = 0
2850 let Inst{19-16} = addr;
2851 let Inst{15-12} = Rt;
2853 let hasExtraDefRegAllocReq = 1 in
2854 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2855 (ins t2addrmode_reg:$addr),
2856 AddrModeNone, 4, NoItinerary,
2857 "ldrexd", "\t$Rt, $Rt2, $addr", "",
2860 let Inst{11-8} = Rt2;
2864 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2865 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2866 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2867 AddrModeNone, 4, NoItinerary,
2868 "strexb", "\t$Rd, $Rt, $addr", "", []>;
2869 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2870 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2871 AddrModeNone, 4, NoItinerary,
2872 "strexh", "\t$Rd, $Rt, $addr", "", []>;
2873 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2874 AddrModeNone, 4, NoItinerary,
2875 "strex", "\t$Rd, $Rt, $addr", "",
2877 let Inst{31-27} = 0b11101;
2878 let Inst{26-20} = 0b0000100;
2879 let Inst{7-0} = 0b00000000; // imm8 = 0
2884 let Inst{11-8} = Rd;
2885 let Inst{19-16} = addr;
2886 let Inst{15-12} = Rt;
2890 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2891 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2892 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2893 AddrModeNone, 4, NoItinerary,
2894 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2897 let Inst{11-8} = Rt2;
2900 // Clear-Exclusive is for disassembly only.
2901 def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
2902 [/* For disassembly only; pattern left blank */]>,
2903 Requires<[IsThumb2, HasV7]> {
2904 let Inst{31-16} = 0xf3bf;
2905 let Inst{15-14} = 0b10;
2908 let Inst{11-8} = 0b1111;
2909 let Inst{7-4} = 0b0010;
2910 let Inst{3-0} = 0b1111;
2913 //===----------------------------------------------------------------------===//
2914 // SJLJ Exception handling intrinsics
2915 // eh_sjlj_setjmp() is an instruction sequence to store the return
2916 // address and save #0 in R0 for the non-longjmp case.
2917 // Since by its nature we may be coming from some other function to get
2918 // here, and we're using the stack frame for the containing function to
2919 // save/restore registers, we can't keep anything live in regs across
2920 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2921 // when we get here from a longjmp(). We force everything out of registers
2922 // except for our own input by listing the relevant registers in Defs. By
2923 // doing so, we also cause the prologue/epilogue code to actively preserve
2924 // all of the callee-saved resgisters, which is exactly what we want.
2925 // $val is a scratch register for our use.
2927 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
2928 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2929 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2930 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2931 AddrModeNone, 0, NoItinerary, "", "",
2932 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2933 Requires<[IsThumb2, HasVFP2]>;
2937 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
2938 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2939 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2940 AddrModeNone, 0, NoItinerary, "", "",
2941 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2942 Requires<[IsThumb2, NoVFP]>;
2946 //===----------------------------------------------------------------------===//
2947 // Control-Flow Instructions
2950 // FIXME: remove when we have a way to marking a MI with these properties.
2951 // FIXME: Should pc be an implicit operand like PICADD, etc?
2952 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2953 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2954 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2955 reglist:$regs, variable_ops),
2956 4, IIC_iLoad_mBr, [],
2957 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2958 RegConstraint<"$Rn = $wb">;
2960 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2961 let isPredicable = 1 in
2962 def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
2964 [(br bb:$target)]> {
2965 let Inst{31-27} = 0b11110;
2966 let Inst{15-14} = 0b10;
2970 let Inst{26} = target{19};
2971 let Inst{11} = target{18};
2972 let Inst{13} = target{17};
2973 let Inst{21-16} = target{16-11};
2974 let Inst{10-0} = target{10-0};
2977 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2978 def t2BR_JT : t2PseudoInst<(outs),
2979 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
2981 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
2983 // FIXME: Add a non-pc based case that can be predicated.
2984 def t2TBB_JT : t2PseudoInst<(outs),
2985 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2988 def t2TBH_JT : t2PseudoInst<(outs),
2989 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2992 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2993 "tbb", "\t[$Rn, $Rm]", []> {
2996 let Inst{31-20} = 0b111010001101;
2997 let Inst{19-16} = Rn;
2998 let Inst{15-5} = 0b11110000000;
2999 let Inst{4} = 0; // B form
3003 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3004 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3007 let Inst{31-20} = 0b111010001101;
3008 let Inst{19-16} = Rn;
3009 let Inst{15-5} = 0b11110000000;
3010 let Inst{4} = 1; // H form
3013 } // isNotDuplicable, isIndirectBranch
3015 } // isBranch, isTerminator, isBarrier
3017 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3018 // a two-value operand where a dag node expects two operands. :(
3019 let isBranch = 1, isTerminator = 1 in
3020 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3022 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3023 let Inst{31-27} = 0b11110;
3024 let Inst{15-14} = 0b10;
3028 let Inst{25-22} = p;
3031 let Inst{26} = target{20};
3032 let Inst{11} = target{19};
3033 let Inst{13} = target{18};
3034 let Inst{21-16} = target{17-12};
3035 let Inst{10-0} = target{11-1};
3037 let DecoderMethod = "DecodeThumb2BCCInstruction";
3040 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3042 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3044 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3046 def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
3048 (t2B uncondbrtarget:$dst)>,
3049 Requires<[IsThumb2, IsDarwin]>;
3053 let Defs = [ITSTATE] in
3054 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3055 AddrModeNone, 2, IIC_iALUx,
3056 "it$mask\t$cc", "", []> {
3057 // 16-bit instruction.
3058 let Inst{31-16} = 0x0000;
3059 let Inst{15-8} = 0b10111111;
3064 let Inst{3-0} = mask;
3066 let DecoderMethod = "DecodeIT";
3069 // Branch and Exchange Jazelle -- for disassembly only
3071 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3072 [/* For disassembly only; pattern left blank */]> {
3073 let Inst{31-27} = 0b11110;
3075 let Inst{25-20} = 0b111100;
3076 let Inst{15-14} = 0b10;
3080 let Inst{19-16} = func;
3083 // Compare and branch on zero / non-zero
3084 let isBranch = 1, isTerminator = 1 in {
3085 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3086 "cbz\t$Rn, $target", []>,
3087 T1Misc<{0,0,?,1,?,?,?}>,
3088 Requires<[IsThumb2]> {
3092 let Inst{9} = target{5};
3093 let Inst{7-3} = target{4-0};
3097 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3098 "cbnz\t$Rn, $target", []>,
3099 T1Misc<{1,0,?,1,?,?,?}>,
3100 Requires<[IsThumb2]> {
3104 let Inst{9} = target{5};
3105 let Inst{7-3} = target{4-0};
3111 // Change Processor State is a system instruction -- for disassembly and
3113 // FIXME: Since the asm parser has currently no clean way to handle optional
3114 // operands, create 3 versions of the same instruction. Once there's a clean
3115 // framework to represent optional operands, change this behavior.
3116 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3117 !strconcat("cps", asm_op),
3118 [/* For disassembly only; pattern left blank */]> {
3124 let Inst{31-27} = 0b11110;
3126 let Inst{25-20} = 0b111010;
3127 let Inst{19-16} = 0b1111;
3128 let Inst{15-14} = 0b10;
3130 let Inst{10-9} = imod;
3132 let Inst{7-5} = iflags;
3133 let Inst{4-0} = mode;
3134 let DecoderMethod = "DecodeT2CPSInstruction";
3138 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3139 "$imod.w\t$iflags, $mode">;
3140 let mode = 0, M = 0 in
3141 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3142 "$imod.w\t$iflags">;
3143 let imod = 0, iflags = 0, M = 1 in
3144 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3146 // A6.3.4 Branches and miscellaneous control
3147 // Table A6-14 Change Processor State, and hint instructions
3148 // Helper class for disassembly only.
3149 class T2I_hint<bits<8> op7_0, string opc, string asm>
3150 : T2I<(outs), (ins), NoItinerary, opc, asm,
3151 [/* For disassembly only; pattern left blank */]> {
3152 let Inst{31-20} = 0xf3a;
3153 let Inst{19-16} = 0b1111;
3154 let Inst{15-14} = 0b10;
3156 let Inst{10-8} = 0b000;
3157 let Inst{7-0} = op7_0;
3160 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3161 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3162 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3163 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3164 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3166 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3167 let Inst{31-20} = 0xf3a;
3168 let Inst{15-14} = 0b10;
3170 let Inst{10-8} = 0b000;
3171 let Inst{7-4} = 0b1111;
3174 let Inst{3-0} = opt;
3177 // Secure Monitor Call is a system instruction -- for disassembly only
3178 // Option = Inst{19-16}
3179 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3180 [/* For disassembly only; pattern left blank */]> {
3181 let Inst{31-27} = 0b11110;
3182 let Inst{26-20} = 0b1111111;
3183 let Inst{15-12} = 0b1000;
3186 let Inst{19-16} = opt;
3189 class T2SRS<bits<12> op31_20,
3190 dag oops, dag iops, InstrItinClass itin,
3191 string opc, string asm, list<dag> pattern>
3192 : T2I<oops, iops, itin, opc, asm, pattern> {
3193 let Inst{31-20} = op31_20{11-0};
3196 let Inst{4-0} = mode{4-0};
3199 // Store Return State is a system instruction -- for disassembly only
3200 def t2SRSDBW : T2SRS<0b111010000010,
3201 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3202 [/* For disassembly only; pattern left blank */]>;
3203 def t2SRSDB : T2SRS<0b111010000000,
3204 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3205 [/* For disassembly only; pattern left blank */]>;
3206 def t2SRSIAW : T2SRS<0b111010011010,
3207 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3208 [/* For disassembly only; pattern left blank */]>;
3209 def t2SRSIA : T2SRS<0b111010011000,
3210 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3211 [/* For disassembly only; pattern left blank */]>;
3213 // Return From Exception is a system instruction -- for disassembly only
3215 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3216 string opc, string asm, list<dag> pattern>
3217 : T2I<oops, iops, itin, opc, asm, pattern> {
3218 let Inst{31-20} = op31_20{11-0};
3221 let Inst{19-16} = Rn;
3222 let Inst{15-0} = 0xc000;
3225 def t2RFEDBW : T2RFE<0b111010000011,
3226 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3227 [/* For disassembly only; pattern left blank */]>;
3228 def t2RFEDB : T2RFE<0b111010000001,
3229 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3230 [/* For disassembly only; pattern left blank */]>;
3231 def t2RFEIAW : T2RFE<0b111010011011,
3232 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3233 [/* For disassembly only; pattern left blank */]>;
3234 def t2RFEIA : T2RFE<0b111010011001,
3235 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3236 [/* For disassembly only; pattern left blank */]>;
3238 //===----------------------------------------------------------------------===//
3239 // Non-Instruction Patterns
3242 // 32-bit immediate using movw + movt.
3243 // This is a single pseudo instruction to make it re-materializable.
3244 // FIXME: Remove this when we can do generalized remat.
3245 let isReMaterializable = 1, isMoveImm = 1 in
3246 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3247 [(set rGPR:$dst, (i32 imm:$src))]>,
3248 Requires<[IsThumb, HasV6T2]>;
3250 // Pseudo instruction that combines movw + movt + add pc (if pic).
3251 // It also makes it possible to rematerialize the instructions.
3252 // FIXME: Remove this when we can do generalized remat and when machine licm
3253 // can properly the instructions.
3254 let isReMaterializable = 1 in {
3255 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3257 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3258 Requires<[IsThumb2, UseMovt]>;
3260 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3262 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3263 Requires<[IsThumb2, UseMovt]>;
3266 // ConstantPool, GlobalAddress, and JumpTable
3267 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3268 Requires<[IsThumb2, DontUseMovt]>;
3269 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3270 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3271 Requires<[IsThumb2, UseMovt]>;
3273 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3274 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3276 // Pseudo instruction that combines ldr from constpool and add pc. This should
3277 // be expanded into two instructions late to allow if-conversion and
3279 let canFoldAsLoad = 1, isReMaterializable = 1 in
3280 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3282 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3284 Requires<[IsThumb2]>;
3286 //===----------------------------------------------------------------------===//
3287 // Move between special register and ARM core register -- for disassembly only
3290 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3291 dag oops, dag iops, InstrItinClass itin,
3292 string opc, string asm, list<dag> pattern>
3293 : T2I<oops, iops, itin, opc, asm, pattern> {
3294 let Inst{31-20} = op31_20{11-0};
3295 let Inst{15-14} = op15_14{1-0};
3297 let Inst{12} = op12{0};
3301 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3302 dag oops, dag iops, InstrItinClass itin,
3303 string opc, string asm, list<dag> pattern>
3304 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3306 let Inst{11-8} = Rd;
3307 let Inst{19-16} = 0b1111;
3310 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3311 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3312 [/* For disassembly only; pattern left blank */]>;
3313 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3314 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3315 [/* For disassembly only; pattern left blank */]>;
3317 // Move from ARM core register to Special Register
3319 // No need to have both system and application versions, the encodings are the
3320 // same and the assembly parser has no way to distinguish between them. The mask
3321 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3322 // the mask with the fields to be accessed in the special register.
3323 def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3324 0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3325 NoItinerary, "msr", "\t$mask, $Rn",
3326 [/* For disassembly only; pattern left blank */]> {
3329 let Inst{19-16} = Rn;
3330 let Inst{20} = mask{4}; // R Bit
3331 let Inst{11-8} = mask{3-0};
3334 //===----------------------------------------------------------------------===//
3335 // Move between coprocessor and ARM core register
3338 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3340 : T2Cop<Op, oops, iops,
3341 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3343 let Inst{27-24} = 0b1110;
3344 let Inst{20} = direction;
3354 let Inst{15-12} = Rt;
3355 let Inst{11-8} = cop;
3356 let Inst{23-21} = opc1;
3357 let Inst{7-5} = opc2;
3358 let Inst{3-0} = CRm;
3359 let Inst{19-16} = CRn;
3362 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3363 list<dag> pattern = []>
3365 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3366 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3367 let Inst{27-24} = 0b1100;
3368 let Inst{23-21} = 0b010;
3369 let Inst{20} = direction;
3377 let Inst{15-12} = Rt;
3378 let Inst{19-16} = Rt2;
3379 let Inst{11-8} = cop;
3380 let Inst{7-4} = opc1;
3381 let Inst{3-0} = CRm;
3384 /* from ARM core register to coprocessor */
3385 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3387 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3388 c_imm:$CRm, imm0_7:$opc2),
3389 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3390 imm:$CRm, imm:$opc2)]>;
3391 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3392 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3393 c_imm:$CRm, imm0_7:$opc2),
3394 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3395 imm:$CRm, imm:$opc2)]>;
3397 /* from coprocessor to ARM core register */
3398 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3399 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3400 c_imm:$CRm, imm0_7:$opc2), []>;
3402 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3403 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3404 c_imm:$CRm, imm0_7:$opc2), []>;
3406 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3407 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3409 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3410 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3413 /* from ARM core register to coprocessor */
3414 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3415 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3417 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3418 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3419 GPR:$Rt2, imm:$CRm)]>;
3420 /* from coprocessor to ARM core register */
3421 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3423 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3425 //===----------------------------------------------------------------------===//
3426 // Other Coprocessor Instructions.
3429 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3430 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3431 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3432 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3433 imm:$CRm, imm:$opc2)]> {
3434 let Inst{27-24} = 0b1110;
3443 let Inst{3-0} = CRm;
3445 let Inst{7-5} = opc2;
3446 let Inst{11-8} = cop;
3447 let Inst{15-12} = CRd;
3448 let Inst{19-16} = CRn;
3449 let Inst{23-20} = opc1;
3452 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3453 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3454 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3455 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3456 imm:$CRm, imm:$opc2)]> {
3457 let Inst{27-24} = 0b1110;
3466 let Inst{3-0} = CRm;
3468 let Inst{7-5} = opc2;
3469 let Inst{11-8} = cop;
3470 let Inst{15-12} = CRd;
3471 let Inst{19-16} = CRn;
3472 let Inst{23-20} = opc1;
3477 //===----------------------------------------------------------------------===//
3478 // Non-Instruction Patterns
3481 // SXT/UXT with no rotate
3482 let AddedComplexity = 16 in {
3483 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3484 Requires<[IsThumb2]>;
3485 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3486 Requires<[IsThumb2]>;
3487 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3488 Requires<[HasT2ExtractPack, IsThumb2]>;
3489 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3490 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3491 Requires<[HasT2ExtractPack, IsThumb2]>;
3492 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3493 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3494 Requires<[HasT2ExtractPack, IsThumb2]>;
3497 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3498 Requires<[IsThumb2]>;
3499 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3500 Requires<[IsThumb2]>;
3501 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3502 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3503 Requires<[HasT2ExtractPack, IsThumb2]>;
3504 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3505 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3506 Requires<[HasT2ExtractPack, IsThumb2]>;
3508 // Atomic load/store patterns
3509 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3510 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3511 def : T2Pat<(atomic_load_8 t2addrmode_imm8:$addr),
3512 (t2LDRBi8 t2addrmode_imm8:$addr)>;
3513 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3514 (t2LDRBs t2addrmode_so_reg:$addr)>;
3515 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3516 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3517 def : T2Pat<(atomic_load_16 t2addrmode_imm8:$addr),
3518 (t2LDRHi8 t2addrmode_imm8:$addr)>;
3519 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3520 (t2LDRHs t2addrmode_so_reg:$addr)>;
3521 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3522 (t2LDRi12 t2addrmode_imm12:$addr)>;
3523 def : T2Pat<(atomic_load_32 t2addrmode_imm8:$addr),
3524 (t2LDRi8 t2addrmode_imm8:$addr)>;
3525 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3526 (t2LDRs t2addrmode_so_reg:$addr)>;
3527 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3528 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3529 def : T2Pat<(atomic_store_8 t2addrmode_imm8:$addr, GPR:$val),
3530 (t2STRBi8 GPR:$val, t2addrmode_imm8:$addr)>;
3531 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3532 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3533 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3534 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3535 def : T2Pat<(atomic_store_16 t2addrmode_imm8:$addr, GPR:$val),
3536 (t2STRHi8 GPR:$val, t2addrmode_imm8:$addr)>;
3537 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3538 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3539 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3540 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3541 def : T2Pat<(atomic_store_32 t2addrmode_imm8:$addr, GPR:$val),
3542 (t2STRi8 GPR:$val, t2addrmode_imm8:$addr)>;
3543 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3544 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3547 //===----------------------------------------------------------------------===//
3548 // Assembler aliases
3551 // Aliases for ADC without the ".w" optional width specifier.
3552 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3553 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3554 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3555 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3556 pred:$p, cc_out:$s)>;
3558 // Aliases for SBC without the ".w" optional width specifier.
3559 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3560 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3561 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3562 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3563 pred:$p, cc_out:$s)>;
3565 // Aliases for ADD without the ".w" optional width specifier.
3566 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3567 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3568 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3569 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3570 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3571 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3572 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3573 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3574 pred:$p, cc_out:$s)>;