1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
61 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
62 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
63 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
67 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
68 // described for so_imm_notSext def below, with sign extension from 16
70 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
71 APInt apIntN = N->getAPIntValue();
72 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
73 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
76 // t2_so_imm - Match a 32-bit immediate operand, which is an
77 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
78 // immediate splatted into multiple bytes of the word.
79 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
80 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
81 return ARM_AM::getT2SOImmVal(Imm) != -1;
83 let ParserMatchClass = t2_so_imm_asmoperand;
84 let EncoderMethod = "getT2SOImmOpValue";
85 let DecoderMethod = "DecodeT2SOImm";
88 // t2_so_imm_not - Match an immediate that is a complement
90 // Note: this pattern doesn't require an encoder method and such, as it's
91 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
92 // is handled by the destination instructions, which use t2_so_imm.
93 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
94 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
95 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
96 }], t2_so_imm_not_XFORM> {
97 let ParserMatchClass = t2_so_imm_not_asmoperand;
100 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
101 // if the upper 16 bits are zero.
102 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
103 APInt apIntN = N->getAPIntValue();
104 if (!apIntN.isIntN(16)) return false;
105 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
106 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
107 }], t2_so_imm_notSext16_XFORM> {
108 let ParserMatchClass = t2_so_imm_not_asmoperand;
111 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
112 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
113 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
114 int64_t Value = -(int)N->getZExtValue();
115 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
116 }], t2_so_imm_neg_XFORM> {
117 let ParserMatchClass = t2_so_imm_neg_asmoperand;
120 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
121 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
122 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
123 return Imm >= 0 && Imm < 4096;
125 let ParserMatchClass = imm0_4095_asmoperand;
128 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
129 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
130 return (uint32_t)(-N->getZExtValue()) < 4096;
132 let ParserMatchClass = imm0_4095_neg_asmoperand;
135 def imm1_255_neg : PatLeaf<(i32 imm), [{
136 uint32_t Val = -N->getZExtValue();
137 return (Val > 0 && Val < 255);
140 def imm0_255_not : PatLeaf<(i32 imm), [{
141 return (uint32_t)(~N->getZExtValue()) < 255;
144 def lo5AllOne : PatLeaf<(i32 imm), [{
145 // Returns true if all low 5-bits are 1.
146 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
149 // Define Thumb2 specific addressing modes.
151 // t2addrmode_imm12 := reg + imm12
152 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
153 def t2addrmode_imm12 : MemOperand,
154 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
155 let PrintMethod = "printAddrModeImm12Operand<false>";
156 let EncoderMethod = "getAddrModeImm12OpValue";
157 let DecoderMethod = "DecodeT2AddrModeImm12";
158 let ParserMatchClass = t2addrmode_imm12_asmoperand;
159 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
162 // t2ldrlabel := imm12
163 def t2ldrlabel : Operand<i32> {
164 let EncoderMethod = "getAddrModeImm12OpValue";
165 let PrintMethod = "printThumbLdrLabelOperand";
168 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
169 def t2ldr_pcrel_imm12 : Operand<i32> {
170 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
171 // used for assembler pseudo instruction and maps to t2ldrlabel, so
172 // doesn't need encoder or print methods of its own.
175 // ADR instruction labels.
176 def t2adrlabel : Operand<i32> {
177 let EncoderMethod = "getT2AdrLabelOpValue";
178 let PrintMethod = "printAdrLabelOperand<0>";
181 // t2addrmode_posimm8 := reg + imm8
182 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
183 def t2addrmode_posimm8 : MemOperand {
184 let PrintMethod = "printT2AddrModeImm8Operand<false>";
185 let EncoderMethod = "getT2AddrModeImm8OpValue";
186 let DecoderMethod = "DecodeT2AddrModeImm8";
187 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
188 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
191 // t2addrmode_negimm8 := reg - imm8
192 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
193 def t2addrmode_negimm8 : MemOperand,
194 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
195 let PrintMethod = "printT2AddrModeImm8Operand<false>";
196 let EncoderMethod = "getT2AddrModeImm8OpValue";
197 let DecoderMethod = "DecodeT2AddrModeImm8";
198 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
199 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
202 // t2addrmode_imm8 := reg +/- imm8
203 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
204 class T2AddrMode_Imm8 : MemOperand,
205 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
206 let EncoderMethod = "getT2AddrModeImm8OpValue";
207 let DecoderMethod = "DecodeT2AddrModeImm8";
208 let ParserMatchClass = MemImm8OffsetAsmOperand;
209 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
212 def t2addrmode_imm8 : T2AddrMode_Imm8 {
213 let PrintMethod = "printT2AddrModeImm8Operand<false>";
216 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
217 let PrintMethod = "printT2AddrModeImm8Operand<true>";
220 def t2am_imm8_offset : MemOperand,
221 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
222 [], [SDNPWantRoot]> {
223 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
224 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
225 let DecoderMethod = "DecodeT2Imm8";
228 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
229 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
230 class T2AddrMode_Imm8s4 : MemOperand {
231 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
232 let DecoderMethod = "DecodeT2AddrModeImm8s4";
233 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
234 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
237 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
238 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
241 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
242 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
245 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
246 def t2am_imm8s4_offset : MemOperand {
247 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
248 let EncoderMethod = "getT2Imm8s4OpValue";
249 let DecoderMethod = "DecodeT2Imm8S4";
252 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
253 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
254 let Name = "MemImm0_1020s4Offset";
256 def t2addrmode_imm0_1020s4 : MemOperand,
257 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
258 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
259 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
260 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
261 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
262 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
265 // t2addrmode_so_reg := reg + (reg << imm2)
266 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
267 def t2addrmode_so_reg : MemOperand,
268 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
269 let PrintMethod = "printT2AddrModeSoRegOperand";
270 let EncoderMethod = "getT2AddrModeSORegOpValue";
271 let DecoderMethod = "DecodeT2AddrModeSOReg";
272 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
273 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
276 // Addresses for the TBB/TBH instructions.
277 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
278 def addrmode_tbb : MemOperand {
279 let PrintMethod = "printAddrModeTBB";
280 let ParserMatchClass = addrmode_tbb_asmoperand;
281 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
283 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
284 def addrmode_tbh : MemOperand {
285 let PrintMethod = "printAddrModeTBH";
286 let ParserMatchClass = addrmode_tbh_asmoperand;
287 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
290 //===----------------------------------------------------------------------===//
291 // Multiclass helpers...
295 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
296 string opc, string asm, list<dag> pattern>
297 : T2I<oops, iops, itin, opc, asm, pattern> {
302 let Inst{26} = imm{11};
303 let Inst{14-12} = imm{10-8};
304 let Inst{7-0} = imm{7-0};
308 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
309 string opc, string asm, list<dag> pattern>
310 : T2sI<oops, iops, itin, opc, asm, pattern> {
316 let Inst{26} = imm{11};
317 let Inst{14-12} = imm{10-8};
318 let Inst{7-0} = imm{7-0};
321 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
322 string opc, string asm, list<dag> pattern>
323 : T2I<oops, iops, itin, opc, asm, pattern> {
327 let Inst{19-16} = Rn;
328 let Inst{26} = imm{11};
329 let Inst{14-12} = imm{10-8};
330 let Inst{7-0} = imm{7-0};
334 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
335 string opc, string asm, list<dag> pattern>
336 : T2I<oops, iops, itin, opc, asm, pattern> {
341 let Inst{3-0} = ShiftedRm{3-0};
342 let Inst{5-4} = ShiftedRm{6-5};
343 let Inst{14-12} = ShiftedRm{11-9};
344 let Inst{7-6} = ShiftedRm{8-7};
347 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
348 string opc, string asm, list<dag> pattern>
349 : T2sI<oops, iops, itin, opc, asm, pattern> {
354 let Inst{3-0} = ShiftedRm{3-0};
355 let Inst{5-4} = ShiftedRm{6-5};
356 let Inst{14-12} = ShiftedRm{11-9};
357 let Inst{7-6} = ShiftedRm{8-7};
360 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : T2I<oops, iops, itin, opc, asm, pattern> {
366 let Inst{19-16} = Rn;
367 let Inst{3-0} = ShiftedRm{3-0};
368 let Inst{5-4} = ShiftedRm{6-5};
369 let Inst{14-12} = ShiftedRm{11-9};
370 let Inst{7-6} = ShiftedRm{8-7};
373 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
374 string opc, string asm, list<dag> pattern>
375 : T2I<oops, iops, itin, opc, asm, pattern> {
383 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
384 string opc, string asm, list<dag> pattern>
385 : T2sI<oops, iops, itin, opc, asm, pattern> {
393 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
394 string opc, string asm, list<dag> pattern>
395 : T2I<oops, iops, itin, opc, asm, pattern> {
399 let Inst{19-16} = Rn;
404 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
405 string opc, string asm, list<dag> pattern>
406 : T2I<oops, iops, itin, opc, asm, pattern> {
412 let Inst{19-16} = Rn;
413 let Inst{26} = imm{11};
414 let Inst{14-12} = imm{10-8};
415 let Inst{7-0} = imm{7-0};
418 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
419 string opc, string asm, list<dag> pattern>
420 : T2sI<oops, iops, itin, opc, asm, pattern> {
426 let Inst{19-16} = Rn;
427 let Inst{26} = imm{11};
428 let Inst{14-12} = imm{10-8};
429 let Inst{7-0} = imm{7-0};
432 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
433 string opc, string asm, list<dag> pattern>
434 : T2I<oops, iops, itin, opc, asm, pattern> {
441 let Inst{14-12} = imm{4-2};
442 let Inst{7-6} = imm{1-0};
445 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
446 string opc, string asm, list<dag> pattern>
447 : T2sI<oops, iops, itin, opc, asm, pattern> {
454 let Inst{14-12} = imm{4-2};
455 let Inst{7-6} = imm{1-0};
458 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
459 string opc, string asm, list<dag> pattern>
460 : T2I<oops, iops, itin, opc, asm, pattern> {
466 let Inst{19-16} = Rn;
470 class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin,
471 string asm, list<dag> pattern>
472 : T2XI<oops, iops, itin, asm, pattern> {
478 let Inst{19-16} = Rn;
482 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
483 string opc, string asm, list<dag> pattern>
484 : T2sI<oops, iops, itin, opc, asm, pattern> {
490 let Inst{19-16} = Rn;
494 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : T2I<oops, iops, itin, opc, asm, pattern> {
502 let Inst{19-16} = Rn;
503 let Inst{3-0} = ShiftedRm{3-0};
504 let Inst{5-4} = ShiftedRm{6-5};
505 let Inst{14-12} = ShiftedRm{11-9};
506 let Inst{7-6} = ShiftedRm{8-7};
509 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
510 string opc, string asm, list<dag> pattern>
511 : T2sI<oops, iops, itin, opc, asm, pattern> {
517 let Inst{19-16} = Rn;
518 let Inst{3-0} = ShiftedRm{3-0};
519 let Inst{5-4} = ShiftedRm{6-5};
520 let Inst{14-12} = ShiftedRm{11-9};
521 let Inst{7-6} = ShiftedRm{8-7};
524 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
525 string opc, string asm, list<dag> pattern>
526 : T2I<oops, iops, itin, opc, asm, pattern> {
532 let Inst{19-16} = Rn;
533 let Inst{15-12} = Ra;
538 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
539 dag oops, dag iops, InstrItinClass itin,
540 string opc, string asm, list<dag> pattern>
541 : T2I<oops, iops, itin, opc, asm, pattern> {
547 let Inst{31-23} = 0b111110111;
548 let Inst{22-20} = opc22_20;
549 let Inst{19-16} = Rn;
550 let Inst{15-12} = RdLo;
551 let Inst{11-8} = RdHi;
552 let Inst{7-4} = opc7_4;
555 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
556 dag oops, dag iops, InstrItinClass itin,
557 string opc, string asm, list<dag> pattern>
558 : T2I<oops, iops, itin, opc, asm, pattern> {
564 let Inst{31-23} = 0b111110111;
565 let Inst{22-20} = opc22_20;
566 let Inst{19-16} = Rn;
567 let Inst{15-12} = RdLo;
568 let Inst{11-8} = RdHi;
569 let Inst{7-4} = opc7_4;
574 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
575 /// binary operation that produces a value. These are predicable and can be
576 /// changed to modify CPSR.
577 multiclass T2I_bin_irs<bits<4> opcod, string opc,
578 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
579 PatFrag opnode, bit Commutable = 0,
582 def ri : T2sTwoRegImm<
583 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
584 opc, "\t$Rd, $Rn, $imm",
585 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
586 Sched<[WriteALU, ReadALU]> {
587 let Inst{31-27} = 0b11110;
589 let Inst{24-21} = opcod;
593 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
594 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
595 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
596 Sched<[WriteALU, ReadALU, ReadALU]> {
597 let isCommutable = Commutable;
598 let Inst{31-27} = 0b11101;
599 let Inst{26-25} = 0b01;
600 let Inst{24-21} = opcod;
601 let Inst{14-12} = 0b000; // imm3
602 let Inst{7-6} = 0b00; // imm2
603 let Inst{5-4} = 0b00; // type
606 def rs : T2sTwoRegShiftedReg<
607 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
608 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
609 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
610 Sched<[WriteALUsi, ReadALU]> {
611 let Inst{31-27} = 0b11101;
612 let Inst{26-25} = 0b01;
613 let Inst{24-21} = opcod;
615 // Assembly aliases for optional destination operand when it's the same
616 // as the source operand.
617 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
618 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
619 t2_so_imm:$imm, pred:$p,
621 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
622 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
625 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
626 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
627 t2_so_reg:$shift, pred:$p,
631 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
632 // the ".w" suffix to indicate that they are wide.
633 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
634 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
635 PatFrag opnode, bit Commutable = 0> :
636 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
637 // Assembler aliases w/ the ".w" suffix.
638 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
639 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
641 // Assembler aliases w/o the ".w" suffix.
642 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
643 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
645 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
646 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
647 pred:$p, cc_out:$s)>;
649 // and with the optional destination operand, too.
650 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
651 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
652 pred:$p, cc_out:$s)>;
653 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
654 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
656 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
657 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
658 pred:$p, cc_out:$s)>;
661 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
662 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
663 /// it is equivalent to the T2I_bin_irs counterpart.
664 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
666 def ri : T2sTwoRegImm<
667 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
668 opc, ".w\t$Rd, $Rn, $imm",
669 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
670 Sched<[WriteALU, ReadALU]> {
671 let Inst{31-27} = 0b11110;
673 let Inst{24-21} = opcod;
677 def rr : T2sThreeReg<
678 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
679 opc, "\t$Rd, $Rn, $Rm",
680 [/* For disassembly only; pattern left blank */]>,
681 Sched<[WriteALU, ReadALU, ReadALU]> {
682 let Inst{31-27} = 0b11101;
683 let Inst{26-25} = 0b01;
684 let Inst{24-21} = opcod;
685 let Inst{14-12} = 0b000; // imm3
686 let Inst{7-6} = 0b00; // imm2
687 let Inst{5-4} = 0b00; // type
690 def rs : T2sTwoRegShiftedReg<
691 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
692 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
693 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
694 Sched<[WriteALUsi, ReadALU]> {
695 let Inst{31-27} = 0b11101;
696 let Inst{26-25} = 0b01;
697 let Inst{24-21} = opcod;
701 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
702 /// instruction modifies the CPSR register.
704 /// These opcodes will be converted to the real non-S opcodes by
705 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
706 let hasPostISelHook = 1, Defs = [CPSR] in {
707 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
708 InstrItinClass iis, PatFrag opnode,
709 bit Commutable = 0> {
711 def ri : t2PseudoInst<(outs rGPR:$Rd),
712 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
714 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
716 Sched<[WriteALU, ReadALU]>;
718 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
720 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
722 Sched<[WriteALU, ReadALU, ReadALU]> {
723 let isCommutable = Commutable;
726 def rs : t2PseudoInst<(outs rGPR:$Rd),
727 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
729 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
730 t2_so_reg:$ShiftedRm))]>,
731 Sched<[WriteALUsi, ReadALUsr]>;
735 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
736 /// operands are reversed.
737 let hasPostISelHook = 1, Defs = [CPSR] in {
738 multiclass T2I_rbin_s_is<PatFrag opnode> {
740 def ri : t2PseudoInst<(outs rGPR:$Rd),
741 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
743 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
745 Sched<[WriteALU, ReadALU]>;
747 def rs : t2PseudoInst<(outs rGPR:$Rd),
748 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
750 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
752 Sched<[WriteALUsi, ReadALU]>;
756 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
757 /// patterns for a binary operation that produces a value.
758 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
759 bit Commutable = 0> {
761 // The register-immediate version is re-materializable. This is useful
762 // in particular for taking the address of a local.
763 let isReMaterializable = 1 in {
764 def ri : T2sTwoRegImm<
765 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
766 opc, ".w\t$Rd, $Rn, $imm",
767 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
768 Sched<[WriteALU, ReadALU]> {
769 let Inst{31-27} = 0b11110;
772 let Inst{23-21} = op23_21;
778 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
779 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
780 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
781 Sched<[WriteALU, ReadALU]> {
785 let Inst{31-27} = 0b11110;
786 let Inst{26} = imm{11};
787 let Inst{25-24} = 0b10;
788 let Inst{23-21} = op23_21;
789 let Inst{20} = 0; // The S bit.
790 let Inst{19-16} = Rn;
792 let Inst{14-12} = imm{10-8};
794 let Inst{7-0} = imm{7-0};
797 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
798 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
799 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
800 Sched<[WriteALU, ReadALU, ReadALU]> {
801 let isCommutable = Commutable;
802 let Inst{31-27} = 0b11101;
803 let Inst{26-25} = 0b01;
805 let Inst{23-21} = op23_21;
806 let Inst{14-12} = 0b000; // imm3
807 let Inst{7-6} = 0b00; // imm2
808 let Inst{5-4} = 0b00; // type
811 def rs : T2sTwoRegShiftedReg<
812 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
813 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
814 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
815 Sched<[WriteALUsi, ReadALU]> {
816 let Inst{31-27} = 0b11101;
817 let Inst{26-25} = 0b01;
819 let Inst{23-21} = op23_21;
823 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
824 /// for a binary operation that produces a value and use the carry
825 /// bit. It's not predicable.
826 let Defs = [CPSR], Uses = [CPSR] in {
827 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
828 bit Commutable = 0> {
830 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
831 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
832 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
833 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
834 let Inst{31-27} = 0b11110;
836 let Inst{24-21} = opcod;
840 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
841 opc, ".w\t$Rd, $Rn, $Rm",
842 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
843 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
844 let isCommutable = Commutable;
845 let Inst{31-27} = 0b11101;
846 let Inst{26-25} = 0b01;
847 let Inst{24-21} = opcod;
848 let Inst{14-12} = 0b000; // imm3
849 let Inst{7-6} = 0b00; // imm2
850 let Inst{5-4} = 0b00; // type
853 def rs : T2sTwoRegShiftedReg<
854 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
855 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
856 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
857 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
858 let Inst{31-27} = 0b11101;
859 let Inst{26-25} = 0b01;
860 let Inst{24-21} = opcod;
865 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
866 // rotate operation that produces a value.
867 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
869 def ri : T2sTwoRegShiftImm<
870 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
871 opc, ".w\t$Rd, $Rm, $imm",
872 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
874 let Inst{31-27} = 0b11101;
875 let Inst{26-21} = 0b010010;
876 let Inst{19-16} = 0b1111; // Rn
877 let Inst{5-4} = opcod;
880 def rr : T2sThreeReg<
881 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
882 opc, ".w\t$Rd, $Rn, $Rm",
883 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
885 let Inst{31-27} = 0b11111;
886 let Inst{26-23} = 0b0100;
887 let Inst{22-21} = opcod;
888 let Inst{15-12} = 0b1111;
889 let Inst{7-4} = 0b0000;
892 // Optional destination register
893 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
894 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
896 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
897 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
900 // Assembler aliases w/o the ".w" suffix.
901 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
902 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
904 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
905 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
908 // and with the optional destination operand, too.
909 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
910 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
912 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
913 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
917 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
918 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
919 /// a explicit result, only implicitly set CPSR.
920 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
921 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
923 let isCompare = 1, Defs = [CPSR] in {
925 def ri : T2OneRegCmpImm<
926 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
927 opc, ".w\t$Rn, $imm",
928 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
929 let Inst{31-27} = 0b11110;
931 let Inst{24-21} = opcod;
932 let Inst{20} = 1; // The S bit.
934 let Inst{11-8} = 0b1111; // Rd
937 def rr : T2TwoRegCmp<
938 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
940 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
941 let Inst{31-27} = 0b11101;
942 let Inst{26-25} = 0b01;
943 let Inst{24-21} = opcod;
944 let Inst{20} = 1; // The S bit.
945 let Inst{14-12} = 0b000; // imm3
946 let Inst{11-8} = 0b1111; // Rd
947 let Inst{7-6} = 0b00; // imm2
948 let Inst{5-4} = 0b00; // type
951 def rs : T2OneRegCmpShiftedReg<
952 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
953 opc, ".w\t$Rn, $ShiftedRm",
954 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
955 Sched<[WriteCMPsi]> {
956 let Inst{31-27} = 0b11101;
957 let Inst{26-25} = 0b01;
958 let Inst{24-21} = opcod;
959 let Inst{20} = 1; // The S bit.
960 let Inst{11-8} = 0b1111; // Rd
964 // Assembler aliases w/o the ".w" suffix.
965 // No alias here for 'rr' version as not all instantiations of this
966 // multiclass want one (CMP in particular, does not).
967 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
968 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
969 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
970 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
973 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
974 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
975 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
977 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
978 opc, ".w\t$Rt, $addr",
979 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
982 let Inst{31-25} = 0b1111100;
983 let Inst{24} = signed;
985 let Inst{22-21} = opcod;
986 let Inst{20} = 1; // load
987 let Inst{19-16} = addr{16-13}; // Rn
988 let Inst{15-12} = Rt;
989 let Inst{11-0} = addr{11-0}; // imm
991 let DecoderMethod = "DecodeT2LoadImm12";
993 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
995 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
998 let Inst{31-27} = 0b11111;
999 let Inst{26-25} = 0b00;
1000 let Inst{24} = signed;
1002 let Inst{22-21} = opcod;
1003 let Inst{20} = 1; // load
1004 let Inst{19-16} = addr{12-9}; // Rn
1005 let Inst{15-12} = Rt;
1007 // Offset: index==TRUE, wback==FALSE
1008 let Inst{10} = 1; // The P bit.
1009 let Inst{9} = addr{8}; // U
1010 let Inst{8} = 0; // The W bit.
1011 let Inst{7-0} = addr{7-0}; // imm
1013 let DecoderMethod = "DecodeT2LoadImm8";
1015 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1016 opc, ".w\t$Rt, $addr",
1017 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
1018 let Inst{31-27} = 0b11111;
1019 let Inst{26-25} = 0b00;
1020 let Inst{24} = signed;
1022 let Inst{22-21} = opcod;
1023 let Inst{20} = 1; // load
1024 let Inst{11-6} = 0b000000;
1027 let Inst{15-12} = Rt;
1030 let Inst{19-16} = addr{9-6}; // Rn
1031 let Inst{3-0} = addr{5-2}; // Rm
1032 let Inst{5-4} = addr{1-0}; // imm
1034 let DecoderMethod = "DecodeT2LoadShift";
1037 // pci variant is very similar to i12, but supports negative offsets
1039 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1040 opc, ".w\t$Rt, $addr",
1041 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
1042 let isReMaterializable = 1;
1043 let Inst{31-27} = 0b11111;
1044 let Inst{26-25} = 0b00;
1045 let Inst{24} = signed;
1046 let Inst{22-21} = opcod;
1047 let Inst{20} = 1; // load
1048 let Inst{19-16} = 0b1111; // Rn
1051 let Inst{15-12} = Rt{3-0};
1054 let Inst{23} = addr{12}; // add = (U == '1')
1055 let Inst{11-0} = addr{11-0};
1057 let DecoderMethod = "DecodeT2LoadLabel";
1061 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1062 multiclass T2I_st<bits<2> opcod, string opc,
1063 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1065 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1066 opc, ".w\t$Rt, $addr",
1067 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1068 let Inst{31-27} = 0b11111;
1069 let Inst{26-23} = 0b0001;
1070 let Inst{22-21} = opcod;
1071 let Inst{20} = 0; // !load
1074 let Inst{15-12} = Rt;
1077 let addr{12} = 1; // add = TRUE
1078 let Inst{19-16} = addr{16-13}; // Rn
1079 let Inst{23} = addr{12}; // U
1080 let Inst{11-0} = addr{11-0}; // imm
1082 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1083 opc, "\t$Rt, $addr",
1084 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1085 let Inst{31-27} = 0b11111;
1086 let Inst{26-23} = 0b0000;
1087 let Inst{22-21} = opcod;
1088 let Inst{20} = 0; // !load
1090 // Offset: index==TRUE, wback==FALSE
1091 let Inst{10} = 1; // The P bit.
1092 let Inst{8} = 0; // The W bit.
1095 let Inst{15-12} = Rt;
1098 let Inst{19-16} = addr{12-9}; // Rn
1099 let Inst{9} = addr{8}; // U
1100 let Inst{7-0} = addr{7-0}; // imm
1102 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1103 opc, ".w\t$Rt, $addr",
1104 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1105 let Inst{31-27} = 0b11111;
1106 let Inst{26-23} = 0b0000;
1107 let Inst{22-21} = opcod;
1108 let Inst{20} = 0; // !load
1109 let Inst{11-6} = 0b000000;
1112 let Inst{15-12} = Rt;
1115 let Inst{19-16} = addr{9-6}; // Rn
1116 let Inst{3-0} = addr{5-2}; // Rm
1117 let Inst{5-4} = addr{1-0}; // imm
1121 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1122 /// register and one whose operand is a register rotated by 8/16/24.
1123 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1124 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1125 opc, ".w\t$Rd, $Rm$rot",
1126 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1127 Requires<[IsThumb2]> {
1128 let Inst{31-27} = 0b11111;
1129 let Inst{26-23} = 0b0100;
1130 let Inst{22-20} = opcod;
1131 let Inst{19-16} = 0b1111; // Rn
1132 let Inst{15-12} = 0b1111;
1136 let Inst{5-4} = rot{1-0}; // rotate
1139 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1140 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1141 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1142 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1143 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1144 Requires<[HasT2ExtractPack, IsThumb2]> {
1146 let Inst{31-27} = 0b11111;
1147 let Inst{26-23} = 0b0100;
1148 let Inst{22-20} = opcod;
1149 let Inst{19-16} = 0b1111; // Rn
1150 let Inst{15-12} = 0b1111;
1152 let Inst{5-4} = rot;
1155 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1157 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1158 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1159 opc, "\t$Rd, $Rm$rot", []>,
1160 Requires<[IsThumb2, HasT2ExtractPack]> {
1162 let Inst{31-27} = 0b11111;
1163 let Inst{26-23} = 0b0100;
1164 let Inst{22-20} = opcod;
1165 let Inst{19-16} = 0b1111; // Rn
1166 let Inst{15-12} = 0b1111;
1168 let Inst{5-4} = rot;
1171 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1172 /// register and one whose operand is a register rotated by 8/16/24.
1173 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1174 : T2ThreeReg<(outs rGPR:$Rd),
1175 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1176 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1177 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1178 Requires<[HasT2ExtractPack, IsThumb2]> {
1180 let Inst{31-27} = 0b11111;
1181 let Inst{26-23} = 0b0100;
1182 let Inst{22-20} = opcod;
1183 let Inst{15-12} = 0b1111;
1185 let Inst{5-4} = rot;
1188 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1189 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1190 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1191 Requires<[HasT2ExtractPack, IsThumb2]> {
1193 let Inst{31-27} = 0b11111;
1194 let Inst{26-23} = 0b0100;
1195 let Inst{22-20} = opcod;
1196 let Inst{15-12} = 0b1111;
1198 let Inst{5-4} = rot;
1201 //===----------------------------------------------------------------------===//
1203 //===----------------------------------------------------------------------===//
1205 //===----------------------------------------------------------------------===//
1206 // Miscellaneous Instructions.
1209 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1210 string asm, list<dag> pattern>
1211 : T2XI<oops, iops, itin, asm, pattern> {
1215 let Inst{11-8} = Rd;
1216 let Inst{26} = label{11};
1217 let Inst{14-12} = label{10-8};
1218 let Inst{7-0} = label{7-0};
1221 // LEApcrel - Load a pc-relative address into a register without offending the
1223 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1224 (ins t2adrlabel:$addr, pred:$p),
1225 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1226 Sched<[WriteALU, ReadALU]> {
1227 let Inst{31-27} = 0b11110;
1228 let Inst{25-24} = 0b10;
1229 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1232 let Inst{19-16} = 0b1111; // Rn
1237 let Inst{11-8} = Rd;
1238 let Inst{23} = addr{12};
1239 let Inst{21} = addr{12};
1240 let Inst{26} = addr{11};
1241 let Inst{14-12} = addr{10-8};
1242 let Inst{7-0} = addr{7-0};
1244 let DecoderMethod = "DecodeT2Adr";
1247 let hasSideEffects = 0, isReMaterializable = 1 in
1248 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1249 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1250 let hasSideEffects = 1 in
1251 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1252 (ins i32imm:$label, pred:$p),
1254 []>, Sched<[WriteALU, ReadALU]>;
1257 //===----------------------------------------------------------------------===//
1258 // Load / store Instructions.
1262 let canFoldAsLoad = 1, isReMaterializable = 1 in
1263 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1264 UnOpFrag<(load node:$Src)>>;
1266 // Loads with zero extension
1267 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1268 GPRnopc, UnOpFrag<(zextloadi16 node:$Src)>>;
1269 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1270 GPRnopc, UnOpFrag<(zextloadi8 node:$Src)>>;
1272 // Loads with sign extension
1273 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1274 GPRnopc, UnOpFrag<(sextloadi16 node:$Src)>>;
1275 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1276 GPRnopc, UnOpFrag<(sextloadi8 node:$Src)>>;
1278 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1280 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1281 (ins t2addrmode_imm8s4:$addr),
1282 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1283 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1285 // zextload i1 -> zextload i8
1286 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1287 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1288 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1289 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1290 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1291 (t2LDRBs t2addrmode_so_reg:$addr)>;
1292 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1293 (t2LDRBpci tconstpool:$addr)>;
1295 // extload -> zextload
1296 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1298 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1299 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1300 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1301 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1302 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1303 (t2LDRBs t2addrmode_so_reg:$addr)>;
1304 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1305 (t2LDRBpci tconstpool:$addr)>;
1307 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1308 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1309 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1310 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1311 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1312 (t2LDRBs t2addrmode_so_reg:$addr)>;
1313 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1314 (t2LDRBpci tconstpool:$addr)>;
1316 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1317 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1318 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1319 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1320 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1321 (t2LDRHs t2addrmode_so_reg:$addr)>;
1322 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1323 (t2LDRHpci tconstpool:$addr)>;
1325 // FIXME: The destination register of the loads and stores can't be PC, but
1326 // can be SP. We need another regclass (similar to rGPR) to represent
1327 // that. Not a pressing issue since these are selected manually,
1332 let mayLoad = 1, hasSideEffects = 0 in {
1333 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1334 (ins t2addrmode_imm8_pre:$addr),
1335 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1336 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1338 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1339 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1340 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1341 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1343 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1344 (ins t2addrmode_imm8_pre:$addr),
1345 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1346 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1348 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1349 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1350 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1351 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1353 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1354 (ins t2addrmode_imm8_pre:$addr),
1355 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1356 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1358 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1359 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1360 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1361 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1363 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1364 (ins t2addrmode_imm8_pre:$addr),
1365 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1366 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1369 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1370 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1371 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1372 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1374 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1375 (ins t2addrmode_imm8_pre:$addr),
1376 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1377 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1380 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1381 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1382 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1383 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1384 } // mayLoad = 1, hasSideEffects = 0
1386 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1387 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1388 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1389 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1390 "\t$Rt, $addr", []> {
1393 let Inst{31-27} = 0b11111;
1394 let Inst{26-25} = 0b00;
1395 let Inst{24} = signed;
1397 let Inst{22-21} = type;
1398 let Inst{20} = 1; // load
1399 let Inst{19-16} = addr{12-9};
1400 let Inst{15-12} = Rt;
1402 let Inst{10-8} = 0b110; // PUW.
1403 let Inst{7-0} = addr{7-0};
1405 let DecoderMethod = "DecodeT2LoadT";
1408 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1409 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1410 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1411 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1412 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1414 class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
1415 string opc, string asm, list<dag> pattern>
1416 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
1417 opc, asm, "", pattern>, Requires<[IsThumb, HasV8]> {
1421 let Inst{31-27} = 0b11101;
1422 let Inst{26-24} = 0b000;
1423 let Inst{23-20} = bits23_20;
1424 let Inst{11-6} = 0b111110;
1425 let Inst{5-4} = bit54;
1426 let Inst{3-0} = 0b1111;
1428 // Encode instruction operands
1429 let Inst{19-16} = addr;
1430 let Inst{15-12} = Rt;
1433 def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
1434 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>;
1435 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1436 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>;
1437 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1438 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>;
1441 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1442 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1443 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1444 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1445 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1446 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1449 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
1450 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1451 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1452 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1456 let mayStore = 1, hasSideEffects = 0 in {
1457 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1458 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1459 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1460 "str", "\t$Rt, $addr!",
1461 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1463 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1464 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1465 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1466 "strh", "\t$Rt, $addr!",
1467 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1469 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1470 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1471 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1472 "strb", "\t$Rt, $addr!",
1473 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
1474 } // mayStore = 1, hasSideEffects = 0
1476 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1477 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1478 t2am_imm8_offset:$offset),
1479 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1480 "str", "\t$Rt, $Rn$offset",
1481 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1482 [(set GPRnopc:$Rn_wb,
1483 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1484 t2am_imm8_offset:$offset))]>;
1486 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1487 (ins rGPR:$Rt, addr_offset_none:$Rn,
1488 t2am_imm8_offset:$offset),
1489 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1490 "strh", "\t$Rt, $Rn$offset",
1491 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1492 [(set GPRnopc:$Rn_wb,
1493 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1494 t2am_imm8_offset:$offset))]>;
1496 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1497 (ins rGPR:$Rt, addr_offset_none:$Rn,
1498 t2am_imm8_offset:$offset),
1499 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1500 "strb", "\t$Rt, $Rn$offset",
1501 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1502 [(set GPRnopc:$Rn_wb,
1503 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1504 t2am_imm8_offset:$offset))]>;
1506 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1507 // put the patterns on the instruction definitions directly as ISel wants
1508 // the address base and offset to be separate operands, not a single
1509 // complex operand like we represent the instructions themselves. The
1510 // pseudos map between the two.
1511 let usesCustomInserter = 1,
1512 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1513 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1514 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1516 [(set GPRnopc:$Rn_wb,
1517 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1518 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1519 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1521 [(set GPRnopc:$Rn_wb,
1522 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1523 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1524 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1526 [(set GPRnopc:$Rn_wb,
1527 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1530 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1532 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1533 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1534 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1535 "\t$Rt, $addr", []> {
1536 let Inst{31-27} = 0b11111;
1537 let Inst{26-25} = 0b00;
1538 let Inst{24} = 0; // not signed
1540 let Inst{22-21} = type;
1541 let Inst{20} = 0; // store
1543 let Inst{10-8} = 0b110; // PUW
1547 let Inst{15-12} = Rt;
1548 let Inst{19-16} = addr{12-9};
1549 let Inst{7-0} = addr{7-0};
1552 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1553 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1554 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1556 // ldrd / strd pre / post variants
1557 // For disassembly only.
1559 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1560 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1561 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1562 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1565 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1566 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1567 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1568 "$addr.base = $wb", []>;
1570 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1571 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1572 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1573 "$addr.base = $wb", []> {
1574 let DecoderMethod = "DecodeT2STRDPreInstruction";
1577 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1578 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1579 t2am_imm8s4_offset:$imm),
1580 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1581 "$addr.base = $wb", []>;
1583 class T2Istrrel<bits<2> bit54, dag oops, dag iops,
1584 string opc, string asm, list<dag> pattern>
1585 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
1586 asm, "", pattern>, Requires<[IsThumb, HasV8]> {
1590 let Inst{31-27} = 0b11101;
1591 let Inst{26-20} = 0b0001100;
1592 let Inst{11-6} = 0b111110;
1593 let Inst{5-4} = bit54;
1594 let Inst{3-0} = 0b1111;
1596 // Encode instruction operands
1597 let Inst{19-16} = addr;
1598 let Inst{15-12} = Rt;
1601 def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1602 "stl", "\t$Rt, $addr", []>;
1603 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1604 "stlb", "\t$Rt, $addr", []>;
1605 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1606 "stlh", "\t$Rt, $addr", []>;
1608 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1609 // data/instruction access.
1610 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1611 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1612 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1614 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1616 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1617 Sched<[WritePreLd]> {
1618 let Inst{31-25} = 0b1111100;
1619 let Inst{24} = instr;
1622 let Inst{21} = write;
1624 let Inst{15-12} = 0b1111;
1627 let Inst{19-16} = addr{16-13}; // Rn
1628 let Inst{11-0} = addr{11-0}; // imm12
1630 let DecoderMethod = "DecodeT2LoadImm12";
1633 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1635 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1636 Sched<[WritePreLd]> {
1637 let Inst{31-25} = 0b1111100;
1638 let Inst{24} = instr;
1639 let Inst{23} = 0; // U = 0
1641 let Inst{21} = write;
1643 let Inst{15-12} = 0b1111;
1644 let Inst{11-8} = 0b1100;
1647 let Inst{19-16} = addr{12-9}; // Rn
1648 let Inst{7-0} = addr{7-0}; // imm8
1650 let DecoderMethod = "DecodeT2LoadImm8";
1653 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1655 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1656 Sched<[WritePreLd]> {
1657 let Inst{31-25} = 0b1111100;
1658 let Inst{24} = instr;
1659 let Inst{23} = 0; // add = TRUE for T1
1661 let Inst{21} = write;
1663 let Inst{15-12} = 0b1111;
1664 let Inst{11-6} = 0b000000;
1667 let Inst{19-16} = addr{9-6}; // Rn
1668 let Inst{3-0} = addr{5-2}; // Rm
1669 let Inst{5-4} = addr{1-0}; // imm2
1671 let DecoderMethod = "DecodeT2LoadShift";
1675 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1676 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1677 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1679 // pci variant is very similar to i12, but supports negative offsets
1680 // from the PC. Only PLD and PLI have pci variants (not PLDW)
1681 class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
1682 IIC_Preload, opc, "\t$addr",
1683 [(ARMPreload (ARMWrapper tconstpool:$addr),
1684 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
1685 let Inst{31-25} = 0b1111100;
1686 let Inst{24} = inst;
1687 let Inst{22-20} = 0b001;
1688 let Inst{19-16} = 0b1111;
1689 let Inst{15-12} = 0b1111;
1692 let Inst{23} = addr{12}; // add = (U == '1')
1693 let Inst{11-0} = addr{11-0}; // imm12
1695 let DecoderMethod = "DecodeT2LoadLabel";
1698 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1699 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1701 //===----------------------------------------------------------------------===//
1702 // Load / store multiple Instructions.
1705 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1706 InstrItinClass itin_upd, bit L_bit> {
1708 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1709 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1713 let Inst{31-27} = 0b11101;
1714 let Inst{26-25} = 0b00;
1715 let Inst{24-23} = 0b01; // Increment After
1717 let Inst{21} = 0; // No writeback
1718 let Inst{20} = L_bit;
1719 let Inst{19-16} = Rn;
1720 let Inst{15-0} = regs;
1723 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1724 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1728 let Inst{31-27} = 0b11101;
1729 let Inst{26-25} = 0b00;
1730 let Inst{24-23} = 0b01; // Increment After
1732 let Inst{21} = 1; // Writeback
1733 let Inst{20} = L_bit;
1734 let Inst{19-16} = Rn;
1735 let Inst{15-0} = regs;
1738 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1739 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1743 let Inst{31-27} = 0b11101;
1744 let Inst{26-25} = 0b00;
1745 let Inst{24-23} = 0b10; // Decrement Before
1747 let Inst{21} = 0; // No writeback
1748 let Inst{20} = L_bit;
1749 let Inst{19-16} = Rn;
1750 let Inst{15-0} = regs;
1753 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1754 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1758 let Inst{31-27} = 0b11101;
1759 let Inst{26-25} = 0b00;
1760 let Inst{24-23} = 0b10; // Decrement Before
1762 let Inst{21} = 1; // Writeback
1763 let Inst{20} = L_bit;
1764 let Inst{19-16} = Rn;
1765 let Inst{15-0} = regs;
1769 let hasSideEffects = 0 in {
1771 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1772 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1774 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1775 InstrItinClass itin_upd, bit L_bit> {
1777 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1778 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1782 let Inst{31-27} = 0b11101;
1783 let Inst{26-25} = 0b00;
1784 let Inst{24-23} = 0b01; // Increment After
1786 let Inst{21} = 0; // No writeback
1787 let Inst{20} = L_bit;
1788 let Inst{19-16} = Rn;
1790 let Inst{14} = regs{14};
1792 let Inst{12-0} = regs{12-0};
1795 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1796 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1800 let Inst{31-27} = 0b11101;
1801 let Inst{26-25} = 0b00;
1802 let Inst{24-23} = 0b01; // Increment After
1804 let Inst{21} = 1; // Writeback
1805 let Inst{20} = L_bit;
1806 let Inst{19-16} = Rn;
1808 let Inst{14} = regs{14};
1810 let Inst{12-0} = regs{12-0};
1813 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1814 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1818 let Inst{31-27} = 0b11101;
1819 let Inst{26-25} = 0b00;
1820 let Inst{24-23} = 0b10; // Decrement Before
1822 let Inst{21} = 0; // No writeback
1823 let Inst{20} = L_bit;
1824 let Inst{19-16} = Rn;
1826 let Inst{14} = regs{14};
1828 let Inst{12-0} = regs{12-0};
1831 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1832 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1836 let Inst{31-27} = 0b11101;
1837 let Inst{26-25} = 0b00;
1838 let Inst{24-23} = 0b10; // Decrement Before
1840 let Inst{21} = 1; // Writeback
1841 let Inst{20} = L_bit;
1842 let Inst{19-16} = Rn;
1844 let Inst{14} = regs{14};
1846 let Inst{12-0} = regs{12-0};
1851 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1852 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1857 //===----------------------------------------------------------------------===//
1858 // Move Instructions.
1861 let hasSideEffects = 0 in
1862 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1863 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1864 let Inst{31-27} = 0b11101;
1865 let Inst{26-25} = 0b01;
1866 let Inst{24-21} = 0b0010;
1867 let Inst{19-16} = 0b1111; // Rn
1868 let Inst{14-12} = 0b000;
1869 let Inst{7-4} = 0b0000;
1871 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1872 pred:$p, zero_reg)>;
1873 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1875 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1878 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1879 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1880 AddedComplexity = 1 in
1881 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1882 "mov", ".w\t$Rd, $imm",
1883 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1884 let Inst{31-27} = 0b11110;
1886 let Inst{24-21} = 0b0010;
1887 let Inst{19-16} = 0b1111; // Rn
1891 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1892 // Use aliases to get that to play nice here.
1893 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1895 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1898 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1899 pred:$p, zero_reg)>;
1900 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1901 pred:$p, zero_reg)>;
1903 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1904 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1905 "movw", "\t$Rd, $imm",
1906 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> {
1907 let Inst{31-27} = 0b11110;
1909 let Inst{24-21} = 0b0010;
1910 let Inst{20} = 0; // The S bit.
1916 let Inst{11-8} = Rd;
1917 let Inst{19-16} = imm{15-12};
1918 let Inst{26} = imm{11};
1919 let Inst{14-12} = imm{10-8};
1920 let Inst{7-0} = imm{7-0};
1921 let DecoderMethod = "DecodeT2MOVTWInstruction";
1924 def : t2InstAlias<"mov${p} $Rd, $imm",
1925 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>;
1927 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1928 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1930 let Constraints = "$src = $Rd" in {
1931 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1932 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1933 "movt", "\t$Rd, $imm",
1935 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1937 let Inst{31-27} = 0b11110;
1939 let Inst{24-21} = 0b0110;
1940 let Inst{20} = 0; // The S bit.
1946 let Inst{11-8} = Rd;
1947 let Inst{19-16} = imm{15-12};
1948 let Inst{26} = imm{11};
1949 let Inst{14-12} = imm{10-8};
1950 let Inst{7-0} = imm{7-0};
1951 let DecoderMethod = "DecodeT2MOVTWInstruction";
1954 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1955 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1959 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1961 //===----------------------------------------------------------------------===//
1962 // Extend Instructions.
1967 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1968 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1969 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1970 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1971 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1973 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1974 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1975 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1976 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1977 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1979 // A simple right-shift can also be used in most cases (the exception is the
1980 // SXTH operations with a rotate of 24: there the non-contiguous bits are
1982 def : Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)),
1983 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
1984 Requires<[HasT2ExtractPack, IsThumb2]>;
1985 def : Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), i16)),
1986 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
1987 Requires<[HasT2ExtractPack, IsThumb2]>;
1991 let AddedComplexity = 16 in {
1992 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1993 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1994 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1995 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1996 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1997 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1999 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2000 // The transformation should probably be done as a combiner action
2001 // instead so we can include a check for masking back in the upper
2002 // eight bits of the source into the lower eight bits of the result.
2003 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
2004 // (t2UXTB16 rGPR:$Src, 3)>,
2005 // Requires<[HasT2ExtractPack, IsThumb2]>;
2006 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
2007 (t2UXTB16 rGPR:$Src, 1)>,
2008 Requires<[HasT2ExtractPack, IsThumb2]>;
2010 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
2011 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2012 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
2013 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2014 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
2016 def : Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)),
2017 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
2018 Requires<[HasT2ExtractPack, IsThumb2]>;
2019 def : Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)),
2020 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>,
2021 Requires<[HasT2ExtractPack, IsThumb2]>;
2025 //===----------------------------------------------------------------------===//
2026 // Arithmetic Instructions.
2029 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
2030 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2031 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
2032 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2034 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
2036 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
2037 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
2038 // AdjustInstrPostInstrSelection where we determine whether or not to
2039 // set the "s" bit based on CPSR liveness.
2041 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
2042 // support for an optional CPSR definition that corresponds to the DAG
2043 // node's second value. We can then eliminate the implicit def of CPSR.
2044 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
2045 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
2046 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
2047 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
2049 let hasPostISelHook = 1 in {
2050 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
2051 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
2052 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
2053 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
2057 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
2058 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2060 // FIXME: Eliminate them if we can write def : Pat patterns which defines
2061 // CPSR and the implicit def of CPSR is not needed.
2062 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
2064 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2065 // The assume-no-carry-in form uses the negation of the input since add/sub
2066 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2067 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2069 // The AddedComplexity preferences the first variant over the others since
2070 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2071 let AddedComplexity = 1 in
2072 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2073 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2074 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2075 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2076 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2077 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2078 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2079 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2081 let AddedComplexity = 1 in
2082 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2083 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2084 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2085 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2086 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2087 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2088 // The with-carry-in form matches bitwise not instead of the negation.
2089 // Effectively, the inverse interpretation of the carry flag already accounts
2090 // for part of the negation.
2091 let AddedComplexity = 1 in
2092 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2093 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2094 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2095 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2096 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2097 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2099 // Select Bytes -- for disassembly only
2101 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2102 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
2103 Requires<[IsThumb2, HasThumb2DSP]> {
2104 let Inst{31-27} = 0b11111;
2105 let Inst{26-24} = 0b010;
2107 let Inst{22-20} = 0b010;
2108 let Inst{15-12} = 0b1111;
2110 let Inst{6-4} = 0b000;
2113 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2114 // And Miscellaneous operations -- for disassembly only
2115 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2116 list<dag> pat = [/* For disassembly only; pattern left blank */],
2117 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
2118 string asm = "\t$Rd, $Rn, $Rm">
2119 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2120 Requires<[IsThumb2, HasThumb2DSP]> {
2121 let Inst{31-27} = 0b11111;
2122 let Inst{26-23} = 0b0101;
2123 let Inst{22-20} = op22_20;
2124 let Inst{15-12} = 0b1111;
2125 let Inst{7-4} = op7_4;
2131 let Inst{11-8} = Rd;
2132 let Inst{19-16} = Rn;
2136 // Saturating add/subtract -- for disassembly only
2138 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2139 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
2140 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2141 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2142 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2143 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2144 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2145 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2146 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2147 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2148 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2149 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2150 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2151 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2152 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2153 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2154 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2155 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2156 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2157 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2158 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2159 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2161 // Signed/Unsigned add/subtract -- for disassembly only
2163 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2164 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2165 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2166 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2167 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2168 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2169 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2170 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2171 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2172 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2173 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2174 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2176 // Signed/Unsigned halving add/subtract -- for disassembly only
2178 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2179 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2180 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2181 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2182 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2183 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2184 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2185 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2186 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2187 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2188 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2189 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2191 // Helper class for disassembly only
2192 // A6.3.16 & A6.3.17
2193 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2194 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2195 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2196 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2197 let Inst{31-27} = 0b11111;
2198 let Inst{26-24} = 0b011;
2199 let Inst{23} = long;
2200 let Inst{22-20} = op22_20;
2201 let Inst{7-4} = op7_4;
2204 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2205 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2206 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2207 let Inst{31-27} = 0b11111;
2208 let Inst{26-24} = 0b011;
2209 let Inst{23} = long;
2210 let Inst{22-20} = op22_20;
2211 let Inst{7-4} = op7_4;
2214 // Unsigned Sum of Absolute Differences [and Accumulate].
2215 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2216 (ins rGPR:$Rn, rGPR:$Rm),
2217 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2218 Requires<[IsThumb2, HasThumb2DSP]> {
2219 let Inst{15-12} = 0b1111;
2221 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2222 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2223 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2224 Requires<[IsThumb2, HasThumb2DSP]>;
2226 // Signed/Unsigned saturate.
2227 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2228 string opc, string asm, list<dag> pattern>
2229 : T2I<oops, iops, itin, opc, asm, pattern> {
2235 let Inst{11-8} = Rd;
2236 let Inst{19-16} = Rn;
2237 let Inst{4-0} = sat_imm;
2238 let Inst{21} = sh{5};
2239 let Inst{14-12} = sh{4-2};
2240 let Inst{7-6} = sh{1-0};
2245 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2246 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2247 let Inst{31-27} = 0b11110;
2248 let Inst{25-22} = 0b1100;
2254 def t2SSAT16: T2SatI<
2255 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2256 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2257 Requires<[IsThumb2, HasThumb2DSP]> {
2258 let Inst{31-27} = 0b11110;
2259 let Inst{25-22} = 0b1100;
2262 let Inst{21} = 1; // sh = '1'
2263 let Inst{14-12} = 0b000; // imm3 = '000'
2264 let Inst{7-6} = 0b00; // imm2 = '00'
2265 let Inst{5-4} = 0b00;
2270 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2271 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2272 let Inst{31-27} = 0b11110;
2273 let Inst{25-22} = 0b1110;
2278 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2280 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2281 Requires<[IsThumb2, HasThumb2DSP]> {
2282 let Inst{31-22} = 0b1111001110;
2285 let Inst{21} = 1; // sh = '1'
2286 let Inst{14-12} = 0b000; // imm3 = '000'
2287 let Inst{7-6} = 0b00; // imm2 = '00'
2288 let Inst{5-4} = 0b00;
2291 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2292 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2294 //===----------------------------------------------------------------------===//
2295 // Shift and rotate Instructions.
2298 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2299 BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2300 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2301 BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2302 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2303 BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2304 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2305 BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2307 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2308 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2309 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2311 let Uses = [CPSR] in {
2312 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2313 "rrx", "\t$Rd, $Rm",
2314 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2315 let Inst{31-27} = 0b11101;
2316 let Inst{26-25} = 0b01;
2317 let Inst{24-21} = 0b0010;
2318 let Inst{19-16} = 0b1111; // Rn
2319 let Inst{14-12} = 0b000;
2320 let Inst{7-4} = 0b0011;
2324 let isCodeGenOnly = 1, Defs = [CPSR] in {
2325 def t2MOVsrl_flag : T2TwoRegShiftImm<
2326 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2327 "lsrs", ".w\t$Rd, $Rm, #1",
2328 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2330 let Inst{31-27} = 0b11101;
2331 let Inst{26-25} = 0b01;
2332 let Inst{24-21} = 0b0010;
2333 let Inst{20} = 1; // The S bit.
2334 let Inst{19-16} = 0b1111; // Rn
2335 let Inst{5-4} = 0b01; // Shift type.
2336 // Shift amount = Inst{14-12:7-6} = 1.
2337 let Inst{14-12} = 0b000;
2338 let Inst{7-6} = 0b01;
2340 def t2MOVsra_flag : T2TwoRegShiftImm<
2341 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2342 "asrs", ".w\t$Rd, $Rm, #1",
2343 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2345 let Inst{31-27} = 0b11101;
2346 let Inst{26-25} = 0b01;
2347 let Inst{24-21} = 0b0010;
2348 let Inst{20} = 1; // The S bit.
2349 let Inst{19-16} = 0b1111; // Rn
2350 let Inst{5-4} = 0b10; // Shift type.
2351 // Shift amount = Inst{14-12:7-6} = 1.
2352 let Inst{14-12} = 0b000;
2353 let Inst{7-6} = 0b01;
2357 //===----------------------------------------------------------------------===//
2358 // Bitwise Instructions.
2361 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2362 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2363 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2364 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2365 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2366 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2367 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2368 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2369 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2371 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2372 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2373 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2375 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2376 string opc, string asm, list<dag> pattern>
2377 : T2I<oops, iops, itin, opc, asm, pattern> {
2382 let Inst{11-8} = Rd;
2383 let Inst{4-0} = msb{4-0};
2384 let Inst{14-12} = lsb{4-2};
2385 let Inst{7-6} = lsb{1-0};
2388 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2389 string opc, string asm, list<dag> pattern>
2390 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2393 let Inst{19-16} = Rn;
2396 let Constraints = "$src = $Rd" in
2397 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2398 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2399 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2400 let Inst{31-27} = 0b11110;
2401 let Inst{26} = 0; // should be 0.
2403 let Inst{24-20} = 0b10110;
2404 let Inst{19-16} = 0b1111; // Rn
2406 let Inst{5} = 0; // should be 0.
2409 let msb{4-0} = imm{9-5};
2410 let lsb{4-0} = imm{4-0};
2413 def t2SBFX: T2TwoRegBitFI<
2414 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2415 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2416 let Inst{31-27} = 0b11110;
2418 let Inst{24-20} = 0b10100;
2422 def t2UBFX: T2TwoRegBitFI<
2423 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2424 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2425 let Inst{31-27} = 0b11110;
2427 let Inst{24-20} = 0b11100;
2431 // A8.8.247 UDF - Undefined (Encoding T2)
2432 def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
2433 [(int_arm_undefined imm0_65535:$imm16)]> {
2435 let Inst{31-29} = 0b111;
2436 let Inst{28-27} = 0b10;
2437 let Inst{26-20} = 0b1111111;
2438 let Inst{19-16} = imm16{15-12};
2440 let Inst{14-12} = 0b010;
2441 let Inst{11-0} = imm16{11-0};
2444 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2445 let Constraints = "$src = $Rd" in {
2446 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2447 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2448 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2449 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2450 bf_inv_mask_imm:$imm))]> {
2451 let Inst{31-27} = 0b11110;
2452 let Inst{26} = 0; // should be 0.
2454 let Inst{24-20} = 0b10110;
2456 let Inst{5} = 0; // should be 0.
2459 let msb{4-0} = imm{9-5};
2460 let lsb{4-0} = imm{4-0};
2464 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2465 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2466 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2468 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2469 /// unary operation that produces a value. These are predicable and can be
2470 /// changed to modify CPSR.
2471 multiclass T2I_un_irs<bits<4> opcod, string opc,
2472 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2474 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2476 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2478 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2479 let isAsCheapAsAMove = Cheap;
2480 let isReMaterializable = ReMat;
2481 let isMoveImm = MoveImm;
2482 let Inst{31-27} = 0b11110;
2484 let Inst{24-21} = opcod;
2485 let Inst{19-16} = 0b1111; // Rn
2489 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2490 opc, ".w\t$Rd, $Rm",
2491 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2492 let Inst{31-27} = 0b11101;
2493 let Inst{26-25} = 0b01;
2494 let Inst{24-21} = opcod;
2495 let Inst{19-16} = 0b1111; // Rn
2496 let Inst{14-12} = 0b000; // imm3
2497 let Inst{7-6} = 0b00; // imm2
2498 let Inst{5-4} = 0b00; // type
2501 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2502 opc, ".w\t$Rd, $ShiftedRm",
2503 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2505 let Inst{31-27} = 0b11101;
2506 let Inst{26-25} = 0b01;
2507 let Inst{24-21} = opcod;
2508 let Inst{19-16} = 0b1111; // Rn
2512 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2513 let AddedComplexity = 1 in
2514 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2515 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2516 UnOpFrag<(not node:$Src)>, 1, 1, 1>;
2518 let AddedComplexity = 1 in
2519 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2520 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2522 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2523 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2524 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2527 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2528 // will match the extended, not the original bitWidth for $src.
2529 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2530 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2533 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2534 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2535 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2536 Requires<[IsThumb2]>;
2538 def : T2Pat<(t2_so_imm_not:$src),
2539 (t2MVNi t2_so_imm_not:$src)>;
2541 //===----------------------------------------------------------------------===//
2542 // Multiply Instructions.
2544 let isCommutable = 1 in
2545 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2546 "mul", "\t$Rd, $Rn, $Rm",
2547 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2548 let Inst{31-27} = 0b11111;
2549 let Inst{26-23} = 0b0110;
2550 let Inst{22-20} = 0b000;
2551 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2552 let Inst{7-4} = 0b0000; // Multiply
2555 def t2MLA: T2FourReg<
2556 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2557 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2558 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
2559 Requires<[IsThumb2, UseMulOps]> {
2560 let Inst{31-27} = 0b11111;
2561 let Inst{26-23} = 0b0110;
2562 let Inst{22-20} = 0b000;
2563 let Inst{7-4} = 0b0000; // Multiply
2566 def t2MLS: T2FourReg<
2567 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2568 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2569 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
2570 Requires<[IsThumb2, UseMulOps]> {
2571 let Inst{31-27} = 0b11111;
2572 let Inst{26-23} = 0b0110;
2573 let Inst{22-20} = 0b000;
2574 let Inst{7-4} = 0b0001; // Multiply and Subtract
2577 // Extra precision multiplies with low / high results
2578 let hasSideEffects = 0 in {
2579 let isCommutable = 1 in {
2580 def t2SMULL : T2MulLong<0b000, 0b0000,
2581 (outs rGPR:$RdLo, rGPR:$RdHi),
2582 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2583 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2585 def t2UMULL : T2MulLong<0b010, 0b0000,
2586 (outs rGPR:$RdLo, rGPR:$RdHi),
2587 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2588 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2591 // Multiply + accumulate
2592 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2593 (outs rGPR:$RdLo, rGPR:$RdHi),
2594 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2595 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2596 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2598 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2599 (outs rGPR:$RdLo, rGPR:$RdHi),
2600 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2601 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2602 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2604 def t2UMAAL : T2MulLong<0b110, 0b0110,
2605 (outs rGPR:$RdLo, rGPR:$RdHi),
2606 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2607 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2608 Requires<[IsThumb2, HasThumb2DSP]>;
2611 // Rounding variants of the below included for disassembly only
2613 // Most significant word multiply
2614 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2615 "smmul", "\t$Rd, $Rn, $Rm",
2616 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2617 Requires<[IsThumb2, HasThumb2DSP]> {
2618 let Inst{31-27} = 0b11111;
2619 let Inst{26-23} = 0b0110;
2620 let Inst{22-20} = 0b101;
2621 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2622 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2625 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2626 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2627 Requires<[IsThumb2, HasThumb2DSP]> {
2628 let Inst{31-27} = 0b11111;
2629 let Inst{26-23} = 0b0110;
2630 let Inst{22-20} = 0b101;
2631 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2632 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2635 def t2SMMLA : T2FourReg<
2636 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2637 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2638 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2639 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2640 let Inst{31-27} = 0b11111;
2641 let Inst{26-23} = 0b0110;
2642 let Inst{22-20} = 0b101;
2643 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2646 def t2SMMLAR: T2FourReg<
2647 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2648 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2649 Requires<[IsThumb2, HasThumb2DSP]> {
2650 let Inst{31-27} = 0b11111;
2651 let Inst{26-23} = 0b0110;
2652 let Inst{22-20} = 0b101;
2653 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2656 def t2SMMLS: T2FourReg<
2657 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2658 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2659 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2660 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2661 let Inst{31-27} = 0b11111;
2662 let Inst{26-23} = 0b0110;
2663 let Inst{22-20} = 0b110;
2664 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2667 def t2SMMLSR:T2FourReg<
2668 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2669 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2670 Requires<[IsThumb2, HasThumb2DSP]> {
2671 let Inst{31-27} = 0b11111;
2672 let Inst{26-23} = 0b0110;
2673 let Inst{22-20} = 0b110;
2674 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2677 multiclass T2I_smul<string opc, PatFrag opnode> {
2678 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2679 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2680 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2681 (sext_inreg rGPR:$Rm, i16)))]>,
2682 Requires<[IsThumb2, HasThumb2DSP]> {
2683 let Inst{31-27} = 0b11111;
2684 let Inst{26-23} = 0b0110;
2685 let Inst{22-20} = 0b001;
2686 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2687 let Inst{7-6} = 0b00;
2688 let Inst{5-4} = 0b00;
2691 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2692 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2693 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2694 (sra rGPR:$Rm, (i32 16))))]>,
2695 Requires<[IsThumb2, HasThumb2DSP]> {
2696 let Inst{31-27} = 0b11111;
2697 let Inst{26-23} = 0b0110;
2698 let Inst{22-20} = 0b001;
2699 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2700 let Inst{7-6} = 0b00;
2701 let Inst{5-4} = 0b01;
2704 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2705 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2706 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2707 (sext_inreg rGPR:$Rm, i16)))]>,
2708 Requires<[IsThumb2, HasThumb2DSP]> {
2709 let Inst{31-27} = 0b11111;
2710 let Inst{26-23} = 0b0110;
2711 let Inst{22-20} = 0b001;
2712 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2713 let Inst{7-6} = 0b00;
2714 let Inst{5-4} = 0b10;
2717 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2718 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2719 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2720 (sra rGPR:$Rm, (i32 16))))]>,
2721 Requires<[IsThumb2, HasThumb2DSP]> {
2722 let Inst{31-27} = 0b11111;
2723 let Inst{26-23} = 0b0110;
2724 let Inst{22-20} = 0b001;
2725 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2726 let Inst{7-6} = 0b00;
2727 let Inst{5-4} = 0b11;
2730 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2731 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2733 Requires<[IsThumb2, HasThumb2DSP]> {
2734 let Inst{31-27} = 0b11111;
2735 let Inst{26-23} = 0b0110;
2736 let Inst{22-20} = 0b011;
2737 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2738 let Inst{7-6} = 0b00;
2739 let Inst{5-4} = 0b00;
2742 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2743 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2745 Requires<[IsThumb2, HasThumb2DSP]> {
2746 let Inst{31-27} = 0b11111;
2747 let Inst{26-23} = 0b0110;
2748 let Inst{22-20} = 0b011;
2749 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2750 let Inst{7-6} = 0b00;
2751 let Inst{5-4} = 0b01;
2756 multiclass T2I_smla<string opc, PatFrag opnode> {
2758 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2759 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2760 [(set rGPR:$Rd, (add rGPR:$Ra,
2761 (opnode (sext_inreg rGPR:$Rn, i16),
2762 (sext_inreg rGPR:$Rm, i16))))]>,
2763 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2764 let Inst{31-27} = 0b11111;
2765 let Inst{26-23} = 0b0110;
2766 let Inst{22-20} = 0b001;
2767 let Inst{7-6} = 0b00;
2768 let Inst{5-4} = 0b00;
2772 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2773 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2774 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2775 (sra rGPR:$Rm, (i32 16)))))]>,
2776 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2777 let Inst{31-27} = 0b11111;
2778 let Inst{26-23} = 0b0110;
2779 let Inst{22-20} = 0b001;
2780 let Inst{7-6} = 0b00;
2781 let Inst{5-4} = 0b01;
2785 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2786 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2787 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2788 (sext_inreg rGPR:$Rm, i16))))]>,
2789 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2790 let Inst{31-27} = 0b11111;
2791 let Inst{26-23} = 0b0110;
2792 let Inst{22-20} = 0b001;
2793 let Inst{7-6} = 0b00;
2794 let Inst{5-4} = 0b10;
2798 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2799 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2800 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2801 (sra rGPR:$Rm, (i32 16)))))]>,
2802 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2803 let Inst{31-27} = 0b11111;
2804 let Inst{26-23} = 0b0110;
2805 let Inst{22-20} = 0b001;
2806 let Inst{7-6} = 0b00;
2807 let Inst{5-4} = 0b11;
2811 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2812 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2814 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2815 let Inst{31-27} = 0b11111;
2816 let Inst{26-23} = 0b0110;
2817 let Inst{22-20} = 0b011;
2818 let Inst{7-6} = 0b00;
2819 let Inst{5-4} = 0b00;
2823 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2824 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2826 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2827 let Inst{31-27} = 0b11111;
2828 let Inst{26-23} = 0b0110;
2829 let Inst{22-20} = 0b011;
2830 let Inst{7-6} = 0b00;
2831 let Inst{5-4} = 0b01;
2835 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2836 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2838 // Halfword multiple accumulate long: SMLAL<x><y>
2839 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2840 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2841 [/* For disassembly only; pattern left blank */]>,
2842 Requires<[IsThumb2, HasThumb2DSP]>;
2843 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2844 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2845 [/* For disassembly only; pattern left blank */]>,
2846 Requires<[IsThumb2, HasThumb2DSP]>;
2847 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2848 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2849 [/* For disassembly only; pattern left blank */]>,
2850 Requires<[IsThumb2, HasThumb2DSP]>;
2851 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2852 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2853 [/* For disassembly only; pattern left blank */]>,
2854 Requires<[IsThumb2, HasThumb2DSP]>;
2856 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2857 def t2SMUAD: T2ThreeReg_mac<
2858 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2859 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2860 Requires<[IsThumb2, HasThumb2DSP]> {
2861 let Inst{15-12} = 0b1111;
2863 def t2SMUADX:T2ThreeReg_mac<
2864 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2865 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2866 Requires<[IsThumb2, HasThumb2DSP]> {
2867 let Inst{15-12} = 0b1111;
2869 def t2SMUSD: T2ThreeReg_mac<
2870 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2871 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2872 Requires<[IsThumb2, HasThumb2DSP]> {
2873 let Inst{15-12} = 0b1111;
2875 def t2SMUSDX:T2ThreeReg_mac<
2876 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2877 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2878 Requires<[IsThumb2, HasThumb2DSP]> {
2879 let Inst{15-12} = 0b1111;
2881 def t2SMLAD : T2FourReg_mac<
2882 0, 0b010, 0b0000, (outs rGPR:$Rd),
2883 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2884 "\t$Rd, $Rn, $Rm, $Ra", []>,
2885 Requires<[IsThumb2, HasThumb2DSP]>;
2886 def t2SMLADX : T2FourReg_mac<
2887 0, 0b010, 0b0001, (outs rGPR:$Rd),
2888 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2889 "\t$Rd, $Rn, $Rm, $Ra", []>,
2890 Requires<[IsThumb2, HasThumb2DSP]>;
2891 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2892 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2893 "\t$Rd, $Rn, $Rm, $Ra", []>,
2894 Requires<[IsThumb2, HasThumb2DSP]>;
2895 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2896 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2897 "\t$Rd, $Rn, $Rm, $Ra", []>,
2898 Requires<[IsThumb2, HasThumb2DSP]>;
2899 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2900 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2901 "\t$Ra, $Rd, $Rn, $Rm", []>,
2902 Requires<[IsThumb2, HasThumb2DSP]>;
2903 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2904 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2905 "\t$Ra, $Rd, $Rn, $Rm", []>,
2906 Requires<[IsThumb2, HasThumb2DSP]>;
2907 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2908 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2909 "\t$Ra, $Rd, $Rn, $Rm", []>,
2910 Requires<[IsThumb2, HasThumb2DSP]>;
2911 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2912 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2913 "\t$Ra, $Rd, $Rn, $Rm", []>,
2914 Requires<[IsThumb2, HasThumb2DSP]>;
2916 //===----------------------------------------------------------------------===//
2917 // Division Instructions.
2918 // Signed and unsigned division on v7-M
2920 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2921 "sdiv", "\t$Rd, $Rn, $Rm",
2922 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2923 Requires<[HasDivide, IsThumb2]> {
2924 let Inst{31-27} = 0b11111;
2925 let Inst{26-21} = 0b011100;
2927 let Inst{15-12} = 0b1111;
2928 let Inst{7-4} = 0b1111;
2931 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2932 "udiv", "\t$Rd, $Rn, $Rm",
2933 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2934 Requires<[HasDivide, IsThumb2]> {
2935 let Inst{31-27} = 0b11111;
2936 let Inst{26-21} = 0b011101;
2938 let Inst{15-12} = 0b1111;
2939 let Inst{7-4} = 0b1111;
2942 //===----------------------------------------------------------------------===//
2943 // Misc. Arithmetic Instructions.
2946 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2947 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2948 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2949 let Inst{31-27} = 0b11111;
2950 let Inst{26-22} = 0b01010;
2951 let Inst{21-20} = op1;
2952 let Inst{15-12} = 0b1111;
2953 let Inst{7-6} = 0b10;
2954 let Inst{5-4} = op2;
2958 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2959 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2962 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2963 "rbit", "\t$Rd, $Rm",
2964 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>,
2967 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2968 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2971 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2972 "rev16", ".w\t$Rd, $Rm",
2973 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2976 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2977 "revsh", ".w\t$Rd, $Rm",
2978 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2981 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2982 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2983 (t2REVSH rGPR:$Rm)>;
2985 def t2PKHBT : T2ThreeReg<
2986 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2987 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2988 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2989 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2991 Requires<[HasT2ExtractPack, IsThumb2]>,
2992 Sched<[WriteALUsi, ReadALU]> {
2993 let Inst{31-27} = 0b11101;
2994 let Inst{26-25} = 0b01;
2995 let Inst{24-20} = 0b01100;
2996 let Inst{5} = 0; // BT form
3000 let Inst{14-12} = sh{4-2};
3001 let Inst{7-6} = sh{1-0};
3004 // Alternate cases for PKHBT where identities eliminate some nodes.
3005 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
3006 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
3007 Requires<[HasT2ExtractPack, IsThumb2]>;
3008 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
3009 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
3010 Requires<[HasT2ExtractPack, IsThumb2]>;
3012 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3013 // will match the pattern below.
3014 def t2PKHTB : T2ThreeReg<
3015 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
3016 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3017 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
3018 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
3020 Requires<[HasT2ExtractPack, IsThumb2]>,
3021 Sched<[WriteALUsi, ReadALU]> {
3022 let Inst{31-27} = 0b11101;
3023 let Inst{26-25} = 0b01;
3024 let Inst{24-20} = 0b01100;
3025 let Inst{5} = 1; // TB form
3029 let Inst{14-12} = sh{4-2};
3030 let Inst{7-6} = sh{1-0};
3033 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3034 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3035 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
3036 // pkhtb src1, src2, asr (17..31).
3037 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
3038 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
3039 Requires<[HasT2ExtractPack, IsThumb2]>;
3040 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
3041 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
3042 Requires<[HasT2ExtractPack, IsThumb2]>;
3043 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
3044 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
3045 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
3046 Requires<[HasT2ExtractPack, IsThumb2]>;
3048 //===----------------------------------------------------------------------===//
3049 // CRC32 Instructions
3052 // + CRC32{B,H,W} 0x04C11DB7
3053 // + CRC32C{B,H,W} 0x1EDC6F41
3056 class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
3057 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
3058 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
3059 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
3060 Requires<[IsThumb2, HasV8, HasCRC]> {
3061 let Inst{31-27} = 0b11111;
3062 let Inst{26-21} = 0b010110;
3064 let Inst{15-12} = 0b1111;
3065 let Inst{7-6} = 0b10;
3069 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3070 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3071 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
3072 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
3073 def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;
3074 def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;
3076 //===----------------------------------------------------------------------===//
3077 // Comparison Instructions...
3079 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
3080 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
3081 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3083 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
3084 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
3085 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
3086 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
3087 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
3088 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
3090 let isCompare = 1, Defs = [CPSR] in {
3092 def t2CMNri : T2OneRegCmpImm<
3093 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
3094 "cmn", ".w\t$Rn, $imm",
3095 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
3096 Sched<[WriteCMP, ReadALU]> {
3097 let Inst{31-27} = 0b11110;
3099 let Inst{24-21} = 0b1000;
3100 let Inst{20} = 1; // The S bit.
3102 let Inst{11-8} = 0b1111; // Rd
3105 def t2CMNzrr : T2TwoRegCmp<
3106 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
3107 "cmn", ".w\t$Rn, $Rm",
3108 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3109 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
3110 let Inst{31-27} = 0b11101;
3111 let Inst{26-25} = 0b01;
3112 let Inst{24-21} = 0b1000;
3113 let Inst{20} = 1; // The S bit.
3114 let Inst{14-12} = 0b000; // imm3
3115 let Inst{11-8} = 0b1111; // Rd
3116 let Inst{7-6} = 0b00; // imm2
3117 let Inst{5-4} = 0b00; // type
3120 def t2CMNzrs : T2OneRegCmpShiftedReg<
3121 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
3122 "cmn", ".w\t$Rn, $ShiftedRm",
3123 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3124 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
3125 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3126 let Inst{31-27} = 0b11101;
3127 let Inst{26-25} = 0b01;
3128 let Inst{24-21} = 0b1000;
3129 let Inst{20} = 1; // The S bit.
3130 let Inst{11-8} = 0b1111; // Rd
3134 // Assembler aliases w/o the ".w" suffix.
3135 // No alias here for 'rr' version as not all instantiations of this multiclass
3136 // want one (CMP in particular, does not).
3137 def : t2InstAlias<"cmn${p} $Rn, $imm",
3138 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
3139 def : t2InstAlias<"cmn${p} $Rn, $shift",
3140 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
3142 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
3143 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
3145 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
3146 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
3148 defm t2TST : T2I_cmp_irs<0b0000, "tst",
3149 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3150 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3151 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
3152 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3153 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3155 // Conditional moves
3156 let hasSideEffects = 0 in {
3158 let isCommutable = 1, isSelect = 1 in
3159 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3160 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p),
3162 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
3164 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3166 let isMoveImm = 1 in
3168 : t2PseudoInst<(outs rGPR:$Rd),
3169 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3171 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3173 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3175 let isCodeGenOnly = 1 in {
3176 let isMoveImm = 1 in
3178 : t2PseudoInst<(outs rGPR:$Rd),
3179 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
3181 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3183 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3185 let isMoveImm = 1 in
3187 : t2PseudoInst<(outs rGPR:$Rd),
3188 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3191 (ARMcmov rGPR:$false, t2_so_imm_not:$imm,
3193 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3195 class MOVCCShPseudo<SDPatternOperator opnode, Operand ty>
3196 : t2PseudoInst<(outs rGPR:$Rd),
3197 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p),
3199 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3200 (opnode rGPR:$Rm, (i32 ty:$imm)),
3202 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3204 def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>;
3205 def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>;
3206 def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>;
3207 def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>;
3209 let isMoveImm = 1 in
3211 : t2PseudoInst<(outs rGPR:$dst),
3212 (ins rGPR:$false, i32imm:$src, cmovpred:$p),
3214 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src,
3216 RegConstraint<"$false = $dst">;
3217 } // isCodeGenOnly = 1
3221 //===----------------------------------------------------------------------===//
3222 // Atomic operations intrinsics
3225 // memory barriers protect the atomic sequences
3226 let hasSideEffects = 1 in {
3227 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3228 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
3229 Requires<[IsThumb, HasDB]> {
3231 let Inst{31-4} = 0xf3bf8f5;
3232 let Inst{3-0} = opt;
3235 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3236 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
3237 Requires<[IsThumb, HasDB]> {
3239 let Inst{31-4} = 0xf3bf8f4;
3240 let Inst{3-0} = opt;
3243 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3244 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
3245 Requires<[IsThumb, HasDB]> {
3247 let Inst{31-4} = 0xf3bf8f6;
3248 let Inst{3-0} = opt;
3252 class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3253 InstrItinClass itin, string opc, string asm, string cstr,
3254 list<dag> pattern, bits<4> rt2 = 0b1111>
3255 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3256 let Inst{31-27} = 0b11101;
3257 let Inst{26-20} = 0b0001101;
3258 let Inst{11-8} = rt2;
3259 let Inst{7-4} = opcod;
3260 let Inst{3-0} = 0b1111;
3264 let Inst{19-16} = addr;
3265 let Inst{15-12} = Rt;
3267 class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3268 InstrItinClass itin, string opc, string asm, string cstr,
3269 list<dag> pattern, bits<4> rt2 = 0b1111>
3270 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3271 let Inst{31-27} = 0b11101;
3272 let Inst{26-20} = 0b0001100;
3273 let Inst{11-8} = rt2;
3274 let Inst{7-4} = opcod;
3280 let Inst{19-16} = addr;
3281 let Inst{15-12} = Rt;
3284 let mayLoad = 1 in {
3285 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3286 AddrModeNone, 4, NoItinerary,
3287 "ldrexb", "\t$Rt, $addr", "",
3288 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
3289 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3290 AddrModeNone, 4, NoItinerary,
3291 "ldrexh", "\t$Rt, $addr", "",
3292 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
3293 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3294 AddrModeNone, 4, NoItinerary,
3295 "ldrex", "\t$Rt, $addr", "",
3296 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]> {
3299 let Inst{31-27} = 0b11101;
3300 let Inst{26-20} = 0b0000101;
3301 let Inst{19-16} = addr{11-8};
3302 let Inst{15-12} = Rt;
3303 let Inst{11-8} = 0b1111;
3304 let Inst{7-0} = addr{7-0};
3306 let hasExtraDefRegAllocReq = 1 in
3307 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3308 (ins addr_offset_none:$addr),
3309 AddrModeNone, 4, NoItinerary,
3310 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3312 Requires<[IsThumb2, IsNotMClass]> {
3314 let Inst{11-8} = Rt2;
3316 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3317 AddrModeNone, 4, NoItinerary,
3318 "ldaexb", "\t$Rt, $addr", "",
3319 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
3320 Requires<[IsThumb, HasV8]>;
3321 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3322 AddrModeNone, 4, NoItinerary,
3323 "ldaexh", "\t$Rt, $addr", "",
3324 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,
3325 Requires<[IsThumb, HasV8]>;
3326 def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
3327 AddrModeNone, 4, NoItinerary,
3328 "ldaex", "\t$Rt, $addr", "",
3329 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,
3330 Requires<[IsThumb, HasV8]> {
3333 let Inst{31-27} = 0b11101;
3334 let Inst{26-20} = 0b0001101;
3335 let Inst{19-16} = addr;
3336 let Inst{15-12} = Rt;
3337 let Inst{11-8} = 0b1111;
3338 let Inst{7-0} = 0b11101111;
3340 let hasExtraDefRegAllocReq = 1 in
3341 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3342 (ins addr_offset_none:$addr),
3343 AddrModeNone, 4, NoItinerary,
3344 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3345 [], {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> {
3347 let Inst{11-8} = Rt2;
3353 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3354 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3355 (ins rGPR:$Rt, addr_offset_none:$addr),
3356 AddrModeNone, 4, NoItinerary,
3357 "strexb", "\t$Rd, $Rt, $addr", "",
3359 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>;
3360 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3361 (ins rGPR:$Rt, addr_offset_none:$addr),
3362 AddrModeNone, 4, NoItinerary,
3363 "strexh", "\t$Rd, $Rt, $addr", "",
3365 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>;
3367 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3368 t2addrmode_imm0_1020s4:$addr),
3369 AddrModeNone, 4, NoItinerary,
3370 "strex", "\t$Rd, $Rt, $addr", "",
3372 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]> {
3376 let Inst{31-27} = 0b11101;
3377 let Inst{26-20} = 0b0000100;
3378 let Inst{19-16} = addr{11-8};
3379 let Inst{15-12} = Rt;
3380 let Inst{11-8} = Rd;
3381 let Inst{7-0} = addr{7-0};
3383 let hasExtraSrcRegAllocReq = 1 in
3384 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3385 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3386 AddrModeNone, 4, NoItinerary,
3387 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3389 Requires<[IsThumb2, IsNotMClass]> {
3391 let Inst{11-8} = Rt2;
3393 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3394 (ins rGPR:$Rt, addr_offset_none:$addr),
3395 AddrModeNone, 4, NoItinerary,
3396 "stlexb", "\t$Rd, $Rt, $addr", "",
3398 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3399 Requires<[IsThumb, HasV8]>;
3401 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3402 (ins rGPR:$Rt, addr_offset_none:$addr),
3403 AddrModeNone, 4, NoItinerary,
3404 "stlexh", "\t$Rd, $Rt, $addr", "",
3406 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3407 Requires<[IsThumb, HasV8]>;
3409 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3410 addr_offset_none:$addr),
3411 AddrModeNone, 4, NoItinerary,
3412 "stlex", "\t$Rd, $Rt, $addr", "",
3414 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,
3415 Requires<[IsThumb, HasV8]> {
3419 let Inst{31-27} = 0b11101;
3420 let Inst{26-20} = 0b0001100;
3421 let Inst{19-16} = addr;
3422 let Inst{15-12} = Rt;
3423 let Inst{11-4} = 0b11111110;
3426 let hasExtraSrcRegAllocReq = 1 in
3427 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3428 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3429 AddrModeNone, 4, NoItinerary,
3430 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3431 {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> {
3433 let Inst{11-8} = Rt2;
3437 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
3438 Requires<[IsThumb2, HasV7]> {
3439 let Inst{31-16} = 0xf3bf;
3440 let Inst{15-14} = 0b10;
3443 let Inst{11-8} = 0b1111;
3444 let Inst{7-4} = 0b0010;
3445 let Inst{3-0} = 0b1111;
3448 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3449 (t2LDREXB addr_offset_none:$addr)>;
3450 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3451 (t2LDREXH addr_offset_none:$addr)>;
3452 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3453 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>;
3454 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3455 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>;
3457 def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),
3458 (t2LDAEXB addr_offset_none:$addr)>;
3459 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
3460 (t2LDAEXH addr_offset_none:$addr)>;
3461 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3462 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>;
3463 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3464 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>;
3466 //===----------------------------------------------------------------------===//
3467 // SJLJ Exception handling intrinsics
3468 // eh_sjlj_setjmp() is an instruction sequence to store the return
3469 // address and save #0 in R0 for the non-longjmp case.
3470 // Since by its nature we may be coming from some other function to get
3471 // here, and we're using the stack frame for the containing function to
3472 // save/restore registers, we can't keep anything live in regs across
3473 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3474 // when we get here from a longjmp(). We force everything out of registers
3475 // except for our own input by listing the relevant registers in Defs. By
3476 // doing so, we also cause the prologue/epilogue code to actively preserve
3477 // all of the callee-saved resgisters, which is exactly what we want.
3478 // $val is a scratch register for our use.
3480 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3481 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3482 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3483 usesCustomInserter = 1 in {
3484 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3485 AddrModeNone, 0, NoItinerary, "", "",
3486 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3487 Requires<[IsThumb2, HasVFP2]>;
3491 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3492 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3493 usesCustomInserter = 1 in {
3494 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3495 AddrModeNone, 0, NoItinerary, "", "",
3496 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3497 Requires<[IsThumb2, NoVFP]>;
3501 //===----------------------------------------------------------------------===//
3502 // Control-Flow Instructions
3505 // FIXME: remove when we have a way to marking a MI with these properties.
3506 // FIXME: Should pc be an implicit operand like PICADD, etc?
3507 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3508 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3509 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3510 reglist:$regs, variable_ops),
3511 4, IIC_iLoad_mBr, [],
3512 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3513 RegConstraint<"$Rn = $wb">;
3515 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3516 let isPredicable = 1 in
3517 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3519 [(br bb:$target)]>, Sched<[WriteBr]> {
3520 let Inst{31-27} = 0b11110;
3521 let Inst{15-14} = 0b10;
3525 let Inst{26} = target{23};
3526 let Inst{13} = target{22};
3527 let Inst{11} = target{21};
3528 let Inst{25-16} = target{20-11};
3529 let Inst{10-0} = target{10-0};
3530 let DecoderMethod = "DecodeT2BInstruction";
3531 let AsmMatchConverter = "cvtThumbBranches";
3534 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
3535 def t2BR_JT : t2PseudoInst<(outs),
3536 (ins GPR:$target, GPR:$index, i32imm:$jt),
3538 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>,
3541 // FIXME: Add a case that can be predicated.
3542 def t2TBB_JT : t2PseudoInst<(outs),
3543 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3546 def t2TBH_JT : t2PseudoInst<(outs),
3547 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3550 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3551 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3554 let Inst{31-20} = 0b111010001101;
3555 let Inst{19-16} = Rn;
3556 let Inst{15-5} = 0b11110000000;
3557 let Inst{4} = 0; // B form
3560 let DecoderMethod = "DecodeThumbTableBranch";
3563 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3564 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3567 let Inst{31-20} = 0b111010001101;
3568 let Inst{19-16} = Rn;
3569 let Inst{15-5} = 0b11110000000;
3570 let Inst{4} = 1; // H form
3573 let DecoderMethod = "DecodeThumbTableBranch";
3575 } // isNotDuplicable, isIndirectBranch
3577 } // isBranch, isTerminator, isBarrier
3579 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3580 // a two-value operand where a dag node expects ", "two operands. :(
3581 let isBranch = 1, isTerminator = 1 in
3582 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3584 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3585 let Inst{31-27} = 0b11110;
3586 let Inst{15-14} = 0b10;
3590 let Inst{25-22} = p;
3593 let Inst{26} = target{20};
3594 let Inst{11} = target{19};
3595 let Inst{13} = target{18};
3596 let Inst{21-16} = target{17-12};
3597 let Inst{10-0} = target{11-1};
3599 let DecoderMethod = "DecodeThumb2BCCInstruction";
3600 let AsmMatchConverter = "cvtThumbBranches";
3603 // Tail calls. The MachO version of thumb tail calls uses a t2 branch, so
3605 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3608 def tTAILJMPd: tPseudoExpand<(outs),
3609 (ins uncondbrtarget:$dst, pred:$p),
3611 (t2B uncondbrtarget:$dst, pred:$p)>,
3612 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>;
3616 let Defs = [ITSTATE] in
3617 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3618 AddrModeNone, 2, IIC_iALUx,
3619 "it$mask\t$cc", "", []>,
3620 ComplexDeprecationPredicate<"IT"> {
3621 // 16-bit instruction.
3622 let Inst{31-16} = 0x0000;
3623 let Inst{15-8} = 0b10111111;
3628 let Inst{3-0} = mask;
3630 let DecoderMethod = "DecodeIT";
3633 // Branch and Exchange Jazelle -- for disassembly only
3635 def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,
3636 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
3638 let Inst{31-27} = 0b11110;
3640 let Inst{25-20} = 0b111100;
3641 let Inst{19-16} = func;
3642 let Inst{15-0} = 0b1000111100000000;
3645 // Compare and branch on zero / non-zero
3646 let isBranch = 1, isTerminator = 1 in {
3647 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3648 "cbz\t$Rn, $target", []>,
3649 T1Misc<{0,0,?,1,?,?,?}>,
3650 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3654 let Inst{9} = target{5};
3655 let Inst{7-3} = target{4-0};
3659 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3660 "cbnz\t$Rn, $target", []>,
3661 T1Misc<{1,0,?,1,?,?,?}>,
3662 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3666 let Inst{9} = target{5};
3667 let Inst{7-3} = target{4-0};
3673 // Change Processor State is a system instruction.
3674 // FIXME: Since the asm parser has currently no clean way to handle optional
3675 // operands, create 3 versions of the same instruction. Once there's a clean
3676 // framework to represent optional operands, change this behavior.
3677 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3678 !strconcat("cps", asm_op), []>,
3679 Requires<[IsThumb2, IsNotMClass]> {
3685 let Inst{31-11} = 0b111100111010111110000;
3686 let Inst{10-9} = imod;
3688 let Inst{7-5} = iflags;
3689 let Inst{4-0} = mode;
3690 let DecoderMethod = "DecodeT2CPSInstruction";
3694 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3695 "$imod\t$iflags, $mode">;
3696 let mode = 0, M = 0 in
3697 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3698 "$imod.w\t$iflags">;
3699 let imod = 0, iflags = 0, M = 1 in
3700 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3702 def : t2InstAlias<"cps$imod.w $iflags, $mode",
3703 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
3704 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
3706 // A6.3.4 Branches and miscellaneous control
3707 // Table A6-14 Change Processor State, and hint instructions
3708 def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
3709 [(int_arm_hint imm0_239:$imm)]> {
3711 let Inst{31-3} = 0b11110011101011111000000000000;
3712 let Inst{7-0} = imm;
3715 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p)>;
3716 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3717 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3718 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3719 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3720 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3721 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p)> {
3722 let Predicates = [IsThumb2, HasV8];
3725 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
3726 [(int_arm_dbg imm0_15:$opt)]> {
3728 let Inst{31-20} = 0b111100111010;
3729 let Inst{19-16} = 0b1111;
3730 let Inst{15-8} = 0b10000000;
3731 let Inst{7-4} = 0b1111;
3732 let Inst{3-0} = opt;
3735 // Secure Monitor Call is a system instruction.
3736 // Option = Inst{19-16}
3737 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3738 []>, Requires<[IsThumb2, HasTrustZone]> {
3739 let Inst{31-27} = 0b11110;
3740 let Inst{26-20} = 0b1111111;
3741 let Inst{15-12} = 0b1000;
3744 let Inst{19-16} = opt;
3747 class T2DCPS<bits<2> opt, string opc>
3748 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
3749 let Inst{31-27} = 0b11110;
3750 let Inst{26-20} = 0b1111000;
3751 let Inst{19-16} = 0b1111;
3752 let Inst{15-12} = 0b1000;
3753 let Inst{11-2} = 0b0000000000;
3754 let Inst{1-0} = opt;
3757 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
3758 def t2DCPS2 : T2DCPS<0b10, "dcps2">;
3759 def t2DCPS3 : T2DCPS<0b11, "dcps3">;
3761 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3762 string opc, string asm, list<dag> pattern>
3763 : T2I<oops, iops, itin, opc, asm, pattern>,
3764 Requires<[IsThumb2,IsNotMClass]> {
3766 let Inst{31-25} = 0b1110100;
3767 let Inst{24-23} = Op;
3770 let Inst{20-16} = 0b01101;
3771 let Inst{15-5} = 0b11000000000;
3772 let Inst{4-0} = mode{4-0};
3775 // Store Return State is a system instruction.
3776 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3777 "srsdb", "\tsp!, $mode", []>;
3778 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3779 "srsdb","\tsp, $mode", []>;
3780 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3781 "srsia","\tsp!, $mode", []>;
3782 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3783 "srsia","\tsp, $mode", []>;
3786 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3787 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3789 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3790 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3792 // Return From Exception is a system instruction.
3793 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3794 string opc, string asm, list<dag> pattern>
3795 : T2I<oops, iops, itin, opc, asm, pattern>,
3796 Requires<[IsThumb2,IsNotMClass]> {
3797 let Inst{31-20} = op31_20{11-0};
3800 let Inst{19-16} = Rn;
3801 let Inst{15-0} = 0xc000;
3804 def t2RFEDBW : T2RFE<0b111010000011,
3805 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3806 [/* For disassembly only; pattern left blank */]>;
3807 def t2RFEDB : T2RFE<0b111010000001,
3808 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3809 [/* For disassembly only; pattern left blank */]>;
3810 def t2RFEIAW : T2RFE<0b111010011011,
3811 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3812 [/* For disassembly only; pattern left blank */]>;
3813 def t2RFEIA : T2RFE<0b111010011001,
3814 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3815 [/* For disassembly only; pattern left blank */]>;
3817 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
3818 // Exception return instruction is "subs pc, lr, #imm".
3819 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3820 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
3821 "subs", "\tpc, lr, $imm",
3822 [(ARMintretflag imm0_255:$imm)]>,
3823 Requires<[IsThumb2,IsNotMClass]> {
3824 let Inst{31-8} = 0b111100111101111010001111;
3827 let Inst{7-0} = imm;
3830 // Hypervisor Call is a system instruction.
3832 def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>,
3833 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
3835 let Inst{31-20} = 0b111101111110;
3836 let Inst{19-16} = imm16{15-12};
3837 let Inst{15-12} = 0b1000;
3838 let Inst{11-0} = imm16{11-0};
3842 // Alias for HVC without the ".w" optional width specifier
3843 def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;
3845 // ERET - Return from exception in Hypervisor mode.
3846 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
3847 // includes virtualization extensions.
3848 def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p)>,
3849 Requires<[IsThumb2, HasVirtualization]>;
3851 //===----------------------------------------------------------------------===//
3852 // Non-Instruction Patterns
3855 // 32-bit immediate using movw + movt.
3856 // This is a single pseudo instruction to make it re-materializable.
3857 // FIXME: Remove this when we can do generalized remat.
3858 let isReMaterializable = 1, isMoveImm = 1 in
3859 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3860 [(set rGPR:$dst, (i32 imm:$src))]>,
3861 Requires<[IsThumb, UseMovt]>;
3863 // Pseudo instruction that combines movw + movt + add pc (if pic).
3864 // It also makes it possible to rematerialize the instructions.
3865 // FIXME: Remove this when we can do generalized remat and when machine licm
3866 // can properly the instructions.
3867 let isReMaterializable = 1 in {
3868 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3870 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3871 Requires<[IsThumb2, UseMovt]>;
3875 // ConstantPool, GlobalAddress, and JumpTable
3876 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3877 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3878 Requires<[IsThumb2, UseMovt]>;
3880 def : T2Pat<(ARMWrapperJT tjumptable:$dst),
3881 (t2LEApcrelJT tjumptable:$dst)>;
3883 // Pseudo instruction that combines ldr from constpool and add pc. This should
3884 // be expanded into two instructions late to allow if-conversion and
3886 let canFoldAsLoad = 1, isReMaterializable = 1 in
3887 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3889 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3891 Requires<[IsThumb2]>;
3893 // Pseudo isntruction that combines movs + predicated rsbmi
3894 // to implement integer ABS
3895 let usesCustomInserter = 1, Defs = [CPSR] in {
3896 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3897 NoItinerary, []>, Requires<[IsThumb2]>;
3900 //===----------------------------------------------------------------------===//
3901 // Coprocessor load/store -- for disassembly only
3903 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3904 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3905 let Inst{31-28} = op31_28;
3906 let Inst{27-25} = 0b110;
3909 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3910 def _OFFSET : T2CI<op31_28,
3911 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3912 asm, "\t$cop, $CRd, $addr"> {
3916 let Inst{24} = 1; // P = 1
3917 let Inst{23} = addr{8};
3918 let Inst{22} = Dbit;
3919 let Inst{21} = 0; // W = 0
3920 let Inst{20} = load;
3921 let Inst{19-16} = addr{12-9};
3922 let Inst{15-12} = CRd;
3923 let Inst{11-8} = cop;
3924 let Inst{7-0} = addr{7-0};
3925 let DecoderMethod = "DecodeCopMemInstruction";
3927 def _PRE : T2CI<op31_28,
3928 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3929 asm, "\t$cop, $CRd, $addr!"> {
3933 let Inst{24} = 1; // P = 1
3934 let Inst{23} = addr{8};
3935 let Inst{22} = Dbit;
3936 let Inst{21} = 1; // W = 1
3937 let Inst{20} = load;
3938 let Inst{19-16} = addr{12-9};
3939 let Inst{15-12} = CRd;
3940 let Inst{11-8} = cop;
3941 let Inst{7-0} = addr{7-0};
3942 let DecoderMethod = "DecodeCopMemInstruction";
3944 def _POST: T2CI<op31_28,
3945 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3946 postidx_imm8s4:$offset),
3947 asm, "\t$cop, $CRd, $addr, $offset"> {
3952 let Inst{24} = 0; // P = 0
3953 let Inst{23} = offset{8};
3954 let Inst{22} = Dbit;
3955 let Inst{21} = 1; // W = 1
3956 let Inst{20} = load;
3957 let Inst{19-16} = addr;
3958 let Inst{15-12} = CRd;
3959 let Inst{11-8} = cop;
3960 let Inst{7-0} = offset{7-0};
3961 let DecoderMethod = "DecodeCopMemInstruction";
3963 def _OPTION : T2CI<op31_28, (outs),
3964 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3965 coproc_option_imm:$option),
3966 asm, "\t$cop, $CRd, $addr, $option"> {
3971 let Inst{24} = 0; // P = 0
3972 let Inst{23} = 1; // U = 1
3973 let Inst{22} = Dbit;
3974 let Inst{21} = 0; // W = 0
3975 let Inst{20} = load;
3976 let Inst{19-16} = addr;
3977 let Inst{15-12} = CRd;
3978 let Inst{11-8} = cop;
3979 let Inst{7-0} = option;
3980 let DecoderMethod = "DecodeCopMemInstruction";
3984 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3985 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3986 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3987 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3988 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">, Requires<[PreV8,IsThumb2]>;
3989 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">, Requires<[PreV8,IsThumb2]>;
3990 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">, Requires<[PreV8,IsThumb2]>;
3991 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">, Requires<[PreV8,IsThumb2]>;
3994 //===----------------------------------------------------------------------===//
3995 // Move between special register and ARM core register -- for disassembly only
3997 // Move to ARM core register from Special Register
4001 // A/R class can only move from CPSR or SPSR.
4002 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
4003 []>, Requires<[IsThumb2,IsNotMClass]> {
4005 let Inst{31-12} = 0b11110011111011111000;
4006 let Inst{11-8} = Rd;
4007 let Inst{7-0} = 0b00000000;
4010 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
4012 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
4013 []>, Requires<[IsThumb2,IsNotMClass]> {
4015 let Inst{31-12} = 0b11110011111111111000;
4016 let Inst{11-8} = Rd;
4017 let Inst{7-0} = 0b00000000;
4020 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
4021 NoItinerary, "mrs", "\t$Rd, $banked", []>,
4022 Requires<[IsThumb, HasVirtualization]> {
4026 let Inst{31-21} = 0b11110011111;
4027 let Inst{20} = banked{5}; // R bit
4028 let Inst{19-16} = banked{3-0};
4029 let Inst{15-12} = 0b1000;
4030 let Inst{11-8} = Rd;
4031 let Inst{7-5} = 0b001;
4032 let Inst{4} = banked{4};
4033 let Inst{3-0} = 0b0000;
4039 // This MRS has a mask field in bits 7-0 and can take more values than
4040 // the A/R class (a full msr_mask).
4041 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
4042 "mrs", "\t$Rd, $SYSm", []>,
4043 Requires<[IsThumb,IsMClass]> {
4046 let Inst{31-12} = 0b11110011111011111000;
4047 let Inst{11-8} = Rd;
4048 let Inst{7-0} = SYSm;
4050 let Unpredictable{20-16} = 0b11111;
4051 let Unpredictable{13} = 0b1;
4055 // Move from ARM core register to Special Register
4059 // No need to have both system and application versions, the encodings are the
4060 // same and the assembly parser has no way to distinguish between them. The mask
4061 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4062 // the mask with the fields to be accessed in the special register.
4063 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
4064 NoItinerary, "msr", "\t$mask, $Rn", []>,
4065 Requires<[IsThumb2,IsNotMClass]> {
4068 let Inst{31-21} = 0b11110011100;
4069 let Inst{20} = mask{4}; // R Bit
4070 let Inst{19-16} = Rn;
4071 let Inst{15-12} = 0b1000;
4072 let Inst{11-8} = mask{3-0};
4076 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
4077 // separate encoding (distinguished by bit 5.
4078 def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn),
4079 NoItinerary, "msr", "\t$banked, $Rn", []>,
4080 Requires<[IsThumb, HasVirtualization]> {
4084 let Inst{31-21} = 0b11110011100;
4085 let Inst{20} = banked{5}; // R bit
4086 let Inst{19-16} = Rn;
4087 let Inst{15-12} = 0b1000;
4088 let Inst{11-8} = banked{3-0};
4089 let Inst{7-5} = 0b001;
4090 let Inst{4} = banked{4};
4091 let Inst{3-0} = 0b0000;
4097 // Move from ARM core register to Special Register
4098 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
4099 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
4100 Requires<[IsThumb,IsMClass]> {
4103 let Inst{31-21} = 0b11110011100;
4105 let Inst{19-16} = Rn;
4106 let Inst{15-12} = 0b1000;
4107 let Inst{11-10} = SYSm{11-10};
4108 let Inst{9-8} = 0b00;
4109 let Inst{7-0} = SYSm{7-0};
4111 let Unpredictable{20} = 0b1;
4112 let Unpredictable{13} = 0b1;
4113 let Unpredictable{9-8} = 0b11;
4117 //===----------------------------------------------------------------------===//
4118 // Move between coprocessor and ARM core register
4121 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4123 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4125 let Inst{27-24} = 0b1110;
4126 let Inst{20} = direction;
4136 let Inst{15-12} = Rt;
4137 let Inst{11-8} = cop;
4138 let Inst{23-21} = opc1;
4139 let Inst{7-5} = opc2;
4140 let Inst{3-0} = CRm;
4141 let Inst{19-16} = CRn;
4144 class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4145 list<dag> pattern = []>
4146 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4147 let Inst{27-24} = 0b1100;
4148 let Inst{23-21} = 0b010;
4149 let Inst{20} = direction;
4157 let Inst{15-12} = Rt;
4158 let Inst{19-16} = Rt2;
4159 let Inst{11-8} = cop;
4160 let Inst{7-4} = opc1;
4161 let Inst{3-0} = CRm;
4164 /* from ARM core register to coprocessor */
4165 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
4167 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4168 c_imm:$CRm, imm0_7:$opc2),
4169 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4170 imm:$CRm, imm:$opc2)]>,
4171 ComplexDeprecationPredicate<"MCR">;
4172 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4173 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4174 c_imm:$CRm, 0, pred:$p)>;
4175 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
4176 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4177 c_imm:$CRm, imm0_7:$opc2),
4178 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4179 imm:$CRm, imm:$opc2)]> {
4180 let Predicates = [IsThumb2, PreV8];
4182 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4183 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4184 c_imm:$CRm, 0, pred:$p)>;
4186 /* from coprocessor to ARM core register */
4187 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
4188 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4189 c_imm:$CRm, imm0_7:$opc2), []>;
4190 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4191 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4192 c_imm:$CRm, 0, pred:$p)>;
4194 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4195 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4196 c_imm:$CRm, imm0_7:$opc2), []> {
4197 let Predicates = [IsThumb2, PreV8];
4199 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4200 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4201 c_imm:$CRm, 0, pred:$p)>;
4203 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4204 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4206 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4207 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4210 /* from ARM core register to coprocessor */
4211 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs),
4212 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4214 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4216 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs),
4217 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4219 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
4220 GPR:$Rt2, imm:$CRm)]> {
4221 let Predicates = [IsThumb2, PreV8];
4224 /* from coprocessor to ARM core register */
4225 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4226 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)>;
4228 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),
4229 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)> {
4230 let Predicates = [IsThumb2, PreV8];
4233 //===----------------------------------------------------------------------===//
4234 // Other Coprocessor Instructions.
4237 def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4238 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4239 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4240 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4241 imm:$CRm, imm:$opc2)]> {
4242 let Inst{27-24} = 0b1110;
4251 let Inst{3-0} = CRm;
4253 let Inst{7-5} = opc2;
4254 let Inst{11-8} = cop;
4255 let Inst{15-12} = CRd;
4256 let Inst{19-16} = CRn;
4257 let Inst{23-20} = opc1;
4259 let Predicates = [IsThumb2, PreV8];
4262 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4263 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4264 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4265 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4266 imm:$CRm, imm:$opc2)]> {
4267 let Inst{27-24} = 0b1110;
4276 let Inst{3-0} = CRm;
4278 let Inst{7-5} = opc2;
4279 let Inst{11-8} = cop;
4280 let Inst{15-12} = CRd;
4281 let Inst{19-16} = CRn;
4282 let Inst{23-20} = opc1;
4284 let Predicates = [IsThumb2, PreV8];
4289 //===----------------------------------------------------------------------===//
4290 // ARMv8.1 Privilege Access Never extension
4294 def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
4295 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4300 let Inst{2-0} = 0b000;
4302 let Unpredictable{4} = 0b1;
4303 let Unpredictable{2-0} = 0b111;
4306 //===----------------------------------------------------------------------===//
4307 // Non-Instruction Patterns
4310 // SXT/UXT with no rotate
4311 let AddedComplexity = 16 in {
4312 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4313 Requires<[IsThumb2]>;
4314 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4315 Requires<[IsThumb2]>;
4316 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4317 Requires<[HasT2ExtractPack, IsThumb2]>;
4318 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4319 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4320 Requires<[HasT2ExtractPack, IsThumb2]>;
4321 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4322 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4323 Requires<[HasT2ExtractPack, IsThumb2]>;
4326 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4327 Requires<[IsThumb2]>;
4328 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4329 Requires<[IsThumb2]>;
4330 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4331 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4332 Requires<[HasT2ExtractPack, IsThumb2]>;
4333 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4334 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4335 Requires<[HasT2ExtractPack, IsThumb2]>;
4337 // Atomic load/store patterns
4338 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4339 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4340 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4341 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4342 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4343 (t2LDRBs t2addrmode_so_reg:$addr)>;
4344 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4345 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4346 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4347 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4348 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4349 (t2LDRHs t2addrmode_so_reg:$addr)>;
4350 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4351 (t2LDRi12 t2addrmode_imm12:$addr)>;
4352 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4353 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4354 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4355 (t2LDRs t2addrmode_so_reg:$addr)>;
4356 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4357 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4358 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4359 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4360 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4361 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4362 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4363 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4364 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4365 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4366 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4367 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4368 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4369 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4370 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4371 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4372 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4373 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4375 let AddedComplexity = 8 in {
4376 def : T2Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
4377 def : T2Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
4378 def : T2Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;
4379 def : T2Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;
4380 def : T2Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;
4381 def : T2Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>;
4385 //===----------------------------------------------------------------------===//
4386 // Assembler aliases
4389 // Aliases for ADC without the ".w" optional width specifier.
4390 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4391 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4392 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4393 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4394 pred:$p, cc_out:$s)>;
4396 // Aliases for SBC without the ".w" optional width specifier.
4397 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4398 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4399 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4400 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4401 pred:$p, cc_out:$s)>;
4403 // Aliases for ADD without the ".w" optional width specifier.
4404 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4405 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4407 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4408 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4409 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4410 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4411 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4412 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4413 pred:$p, cc_out:$s)>;
4414 // ... and with the destination and source register combined.
4415 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4416 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4417 def : t2InstAlias<"add${p} $Rdn, $imm",
4418 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4419 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4420 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4421 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4422 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4423 pred:$p, cc_out:$s)>;
4425 // add w/ negative immediates is just a sub.
4426 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4427 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4429 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4430 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4431 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4432 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4434 def : t2InstAlias<"add${p} $Rdn, $imm",
4435 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4437 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4438 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4440 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4441 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4442 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4443 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4445 def : t2InstAlias<"addw${p} $Rdn, $imm",
4446 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4449 // Aliases for SUB without the ".w" optional width specifier.
4450 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4451 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4452 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4453 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4454 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4455 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4456 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4457 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4458 pred:$p, cc_out:$s)>;
4459 // ... and with the destination and source register combined.
4460 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4461 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4462 def : t2InstAlias<"sub${p} $Rdn, $imm",
4463 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4464 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4465 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4466 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4467 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4468 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4469 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4470 pred:$p, cc_out:$s)>;
4472 // Alias for compares without the ".w" optional width specifier.
4473 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4474 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4475 def : t2InstAlias<"teq${p} $Rn, $Rm",
4476 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4477 def : t2InstAlias<"tst${p} $Rn, $Rm",
4478 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4481 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p)>, Requires<[HasDB]>;
4482 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p)>, Requires<[HasDB]>;
4483 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p)>, Requires<[HasDB]>;
4485 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4487 def : t2InstAlias<"ldr${p} $Rt, $addr",
4488 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4489 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4490 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4491 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4492 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4493 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4494 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4495 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4496 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4498 def : t2InstAlias<"ldr${p} $Rt, $addr",
4499 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4500 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4501 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4502 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4503 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4504 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4505 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4506 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4507 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4509 def : t2InstAlias<"ldr${p} $Rt, $addr",
4510 (t2LDRpci GPRnopc:$Rt, t2ldrlabel:$addr, pred:$p)>;
4511 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4512 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4513 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4514 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4515 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4516 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4517 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4518 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4520 // Alias for MVN with(out) the ".w" optional width specifier.
4521 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4522 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4523 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4524 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4525 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4526 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4528 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4529 // shift amount is zero (i.e., unspecified).
4530 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4531 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4532 Requires<[HasT2ExtractPack, IsThumb2]>;
4533 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4534 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4535 Requires<[HasT2ExtractPack, IsThumb2]>;
4537 // PUSH/POP aliases for STM/LDM
4538 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4539 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4540 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4541 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4543 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4544 def : t2InstAlias<"stm${p} $Rn, $regs",
4545 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4546 def : t2InstAlias<"stm${p} $Rn!, $regs",
4547 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4549 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4550 def : t2InstAlias<"ldm${p} $Rn, $regs",
4551 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4552 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4553 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4555 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4556 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4557 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4558 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4559 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4561 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4562 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4563 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4564 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4565 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4567 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4568 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4569 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4570 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4573 // Alias for RSB without the ".w" optional width specifier, and with optional
4574 // implied destination register.
4575 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4576 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4577 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4578 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4579 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4580 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4581 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4582 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4585 // SSAT/USAT optional shift operand.
4586 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4587 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4588 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4589 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4591 // STM w/o the .w suffix.
4592 def : t2InstAlias<"stm${p} $Rn, $regs",
4593 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4595 // Alias for STR, STRB, and STRH without the ".w" optional
4597 def : t2InstAlias<"str${p} $Rt, $addr",
4598 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4599 def : t2InstAlias<"strb${p} $Rt, $addr",
4600 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4601 def : t2InstAlias<"strh${p} $Rt, $addr",
4602 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4604 def : t2InstAlias<"str${p} $Rt, $addr",
4605 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4606 def : t2InstAlias<"strb${p} $Rt, $addr",
4607 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4608 def : t2InstAlias<"strh${p} $Rt, $addr",
4609 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4611 // Extend instruction optional rotate operand.
4612 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4613 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4614 Requires<[HasT2ExtractPack, IsThumb2]>;
4615 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4616 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4617 Requires<[HasT2ExtractPack, IsThumb2]>;
4618 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4619 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4620 Requires<[HasT2ExtractPack, IsThumb2]>;
4621 def : InstAlias<"sxtb16${p} $Rd, $Rm",
4622 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>,
4623 Requires<[HasT2ExtractPack, IsThumb2]>;
4625 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4626 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4627 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4628 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4629 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4630 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4631 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4632 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4634 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4635 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4636 Requires<[HasT2ExtractPack, IsThumb2]>;
4637 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4638 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4639 Requires<[HasT2ExtractPack, IsThumb2]>;
4640 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4641 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4642 Requires<[HasT2ExtractPack, IsThumb2]>;
4643 def : InstAlias<"uxtb16${p} $Rd, $Rm",
4644 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>,
4645 Requires<[HasT2ExtractPack, IsThumb2]>;
4647 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4648 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4649 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4650 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4651 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4652 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4653 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4654 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4656 // Extend instruction w/o the ".w" optional width specifier.
4657 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4658 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4659 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4660 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>,
4661 Requires<[HasT2ExtractPack, IsThumb2]>;
4662 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4663 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4665 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4666 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4667 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4668 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>,
4669 Requires<[HasT2ExtractPack, IsThumb2]>;
4670 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4671 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4674 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4676 def : t2InstAlias<"mov${p} $Rd, $imm",
4677 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4678 def : t2InstAlias<"mvn${p} $Rd, $imm",
4679 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4680 // Same for AND <--> BIC
4681 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4682 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4683 pred:$p, cc_out:$s)>;
4684 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4685 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4686 pred:$p, cc_out:$s)>;
4687 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4688 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4689 pred:$p, cc_out:$s)>;
4690 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4691 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4692 pred:$p, cc_out:$s)>;
4693 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4694 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4695 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4696 pred:$p, cc_out:$s)>;
4697 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4698 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4699 pred:$p, cc_out:$s)>;
4700 // Same for CMP <--> CMN via t2_so_imm_neg
4701 def : t2InstAlias<"cmp${p} $Rd, $imm",
4702 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4703 def : t2InstAlias<"cmn${p} $Rd, $imm",
4704 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4707 // Wide 'mul' encoding can be specified with only two operands.
4708 def : t2InstAlias<"mul${p} $Rn, $Rm",
4709 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4711 // "neg" is and alias for "rsb rd, rn, #0"
4712 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4713 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4715 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4716 // these, unfortunately.
4717 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4718 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4719 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4720 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4722 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4723 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4724 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4725 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4727 // ADR w/o the .w suffix
4728 def : t2InstAlias<"adr${p} $Rd, $addr",
4729 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4731 // LDR(literal) w/ alternate [pc, #imm] syntax.
4732 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4733 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4734 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4735 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4736 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4737 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4738 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4739 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4740 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4741 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4742 // Version w/ the .w suffix.
4743 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4744 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;
4745 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4746 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4747 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4748 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4749 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4750 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4751 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4752 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4754 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4755 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
4757 // PLD/PLDW/PLI with alternate literal form.
4758 def : t2InstAlias<"pld${p} $addr",
4759 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
4760 def : InstAlias<"pli${p} $addr",
4761 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p)>,
4762 Requires<[IsThumb2,HasV7]>;