1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
66 // described for so_imm_notSext def below, with sign extension from 16
68 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
69 APInt apIntN = N->getAPIntValue();
70 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
71 return CurDAG->getTargetConstant(~N16bitSignExt, MVT::i32);
74 // t2_so_imm - Match a 32-bit immediate operand, which is an
75 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
76 // immediate splatted into multiple bytes of the word.
77 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
78 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
79 return ARM_AM::getT2SOImmVal(Imm) != -1;
81 let ParserMatchClass = t2_so_imm_asmoperand;
82 let EncoderMethod = "getT2SOImmOpValue";
83 let DecoderMethod = "DecodeT2SOImm";
86 // t2_so_imm_not - Match an immediate that is a complement
88 // Note: this pattern doesn't require an encoder method and such, as it's
89 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
90 // is handled by the destination instructions, which use t2_so_imm.
91 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
92 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
93 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
94 }], t2_so_imm_not_XFORM> {
95 let ParserMatchClass = t2_so_imm_not_asmoperand;
98 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
99 // if the upper 16 bits are zero.
100 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
101 APInt apIntN = N->getAPIntValue();
102 if (!apIntN.isIntN(16)) return false;
103 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
104 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
105 }], t2_so_imm_notSext16_XFORM> {
106 let ParserMatchClass = t2_so_imm_not_asmoperand;
109 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
110 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
111 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
112 int64_t Value = -(int)N->getZExtValue();
113 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
114 }], t2_so_imm_neg_XFORM> {
115 let ParserMatchClass = t2_so_imm_neg_asmoperand;
118 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
119 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
120 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
121 return Imm >= 0 && Imm < 4096;
123 let ParserMatchClass = imm0_4095_asmoperand;
126 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
127 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
128 return (uint32_t)(-N->getZExtValue()) < 4096;
130 let ParserMatchClass = imm0_4095_neg_asmoperand;
133 def imm0_255_neg : PatLeaf<(i32 imm), [{
134 return (uint32_t)(-N->getZExtValue()) < 255;
137 def imm0_255_not : PatLeaf<(i32 imm), [{
138 return (uint32_t)(~N->getZExtValue()) < 255;
141 def lo5AllOne : PatLeaf<(i32 imm), [{
142 // Returns true if all low 5-bits are 1.
143 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
146 // Define Thumb2 specific addressing modes.
148 // t2addrmode_imm12 := reg + imm12
149 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
150 def t2addrmode_imm12 : Operand<i32>,
151 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
152 let PrintMethod = "printAddrModeImm12Operand";
153 let EncoderMethod = "getAddrModeImm12OpValue";
154 let DecoderMethod = "DecodeT2AddrModeImm12";
155 let ParserMatchClass = t2addrmode_imm12_asmoperand;
156 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
159 // t2ldrlabel := imm12
160 def t2ldrlabel : Operand<i32> {
161 let EncoderMethod = "getAddrModeImm12OpValue";
162 let PrintMethod = "printT2LdrLabelOperand";
165 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
166 def t2ldr_pcrel_imm12 : Operand<i32> {
167 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
168 // used for assembler pseudo instruction and maps to t2ldrlabel, so
169 // doesn't need encoder or print methods of its own.
172 // ADR instruction labels.
173 def t2adrlabel : Operand<i32> {
174 let EncoderMethod = "getT2AdrLabelOpValue";
178 // t2addrmode_posimm8 := reg + imm8
179 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
180 def t2addrmode_posimm8 : Operand<i32> {
181 let PrintMethod = "printT2AddrModeImm8Operand";
182 let EncoderMethod = "getT2AddrModeImm8OpValue";
183 let DecoderMethod = "DecodeT2AddrModeImm8";
184 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
185 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
188 // t2addrmode_negimm8 := reg - imm8
189 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
190 def t2addrmode_negimm8 : Operand<i32>,
191 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
192 let PrintMethod = "printT2AddrModeImm8Operand";
193 let EncoderMethod = "getT2AddrModeImm8OpValue";
194 let DecoderMethod = "DecodeT2AddrModeImm8";
195 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
196 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
199 // t2addrmode_imm8 := reg +/- imm8
200 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
201 def t2addrmode_imm8 : Operand<i32>,
202 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
203 let PrintMethod = "printT2AddrModeImm8Operand";
204 let EncoderMethod = "getT2AddrModeImm8OpValue";
205 let DecoderMethod = "DecodeT2AddrModeImm8";
206 let ParserMatchClass = MemImm8OffsetAsmOperand;
207 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
210 def t2am_imm8_offset : Operand<i32>,
211 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
212 [], [SDNPWantRoot]> {
213 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
214 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
215 let DecoderMethod = "DecodeT2Imm8";
218 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
219 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
220 def t2addrmode_imm8s4 : Operand<i32> {
221 let PrintMethod = "printT2AddrModeImm8s4Operand";
222 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
223 let DecoderMethod = "DecodeT2AddrModeImm8s4";
224 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
225 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
228 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
229 def t2am_imm8s4_offset : Operand<i32> {
230 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
231 let EncoderMethod = "getT2Imm8s4OpValue";
232 let DecoderMethod = "DecodeT2Imm8S4";
235 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
236 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
237 let Name = "MemImm0_1020s4Offset";
239 def t2addrmode_imm0_1020s4 : Operand<i32> {
240 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
241 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
242 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
243 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
244 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
247 // t2addrmode_so_reg := reg + (reg << imm2)
248 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
249 def t2addrmode_so_reg : Operand<i32>,
250 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
251 let PrintMethod = "printT2AddrModeSoRegOperand";
252 let EncoderMethod = "getT2AddrModeSORegOpValue";
253 let DecoderMethod = "DecodeT2AddrModeSOReg";
254 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
255 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
258 // Addresses for the TBB/TBH instructions.
259 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
260 def addrmode_tbb : Operand<i32> {
261 let PrintMethod = "printAddrModeTBB";
262 let ParserMatchClass = addrmode_tbb_asmoperand;
263 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
265 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
266 def addrmode_tbh : Operand<i32> {
267 let PrintMethod = "printAddrModeTBH";
268 let ParserMatchClass = addrmode_tbh_asmoperand;
269 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
272 //===----------------------------------------------------------------------===//
273 // Multiclass helpers...
277 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
278 string opc, string asm, list<dag> pattern>
279 : T2I<oops, iops, itin, opc, asm, pattern> {
284 let Inst{26} = imm{11};
285 let Inst{14-12} = imm{10-8};
286 let Inst{7-0} = imm{7-0};
290 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
291 string opc, string asm, list<dag> pattern>
292 : T2sI<oops, iops, itin, opc, asm, pattern> {
298 let Inst{26} = imm{11};
299 let Inst{14-12} = imm{10-8};
300 let Inst{7-0} = imm{7-0};
303 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
304 string opc, string asm, list<dag> pattern>
305 : T2I<oops, iops, itin, opc, asm, pattern> {
309 let Inst{19-16} = Rn;
310 let Inst{26} = imm{11};
311 let Inst{14-12} = imm{10-8};
312 let Inst{7-0} = imm{7-0};
316 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
317 string opc, string asm, list<dag> pattern>
318 : T2I<oops, iops, itin, opc, asm, pattern> {
323 let Inst{3-0} = ShiftedRm{3-0};
324 let Inst{5-4} = ShiftedRm{6-5};
325 let Inst{14-12} = ShiftedRm{11-9};
326 let Inst{7-6} = ShiftedRm{8-7};
329 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
330 string opc, string asm, list<dag> pattern>
331 : T2sI<oops, iops, itin, opc, asm, pattern> {
336 let Inst{3-0} = ShiftedRm{3-0};
337 let Inst{5-4} = ShiftedRm{6-5};
338 let Inst{14-12} = ShiftedRm{11-9};
339 let Inst{7-6} = ShiftedRm{8-7};
342 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
343 string opc, string asm, list<dag> pattern>
344 : T2I<oops, iops, itin, opc, asm, pattern> {
348 let Inst{19-16} = Rn;
349 let Inst{3-0} = ShiftedRm{3-0};
350 let Inst{5-4} = ShiftedRm{6-5};
351 let Inst{14-12} = ShiftedRm{11-9};
352 let Inst{7-6} = ShiftedRm{8-7};
355 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
356 string opc, string asm, list<dag> pattern>
357 : T2I<oops, iops, itin, opc, asm, pattern> {
365 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
366 string opc, string asm, list<dag> pattern>
367 : T2sI<oops, iops, itin, opc, asm, pattern> {
375 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
376 string opc, string asm, list<dag> pattern>
377 : T2I<oops, iops, itin, opc, asm, pattern> {
381 let Inst{19-16} = Rn;
386 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
387 string opc, string asm, list<dag> pattern>
388 : T2I<oops, iops, itin, opc, asm, pattern> {
394 let Inst{19-16} = Rn;
395 let Inst{26} = imm{11};
396 let Inst{14-12} = imm{10-8};
397 let Inst{7-0} = imm{7-0};
400 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
401 string opc, string asm, list<dag> pattern>
402 : T2sI<oops, iops, itin, opc, asm, pattern> {
408 let Inst{19-16} = Rn;
409 let Inst{26} = imm{11};
410 let Inst{14-12} = imm{10-8};
411 let Inst{7-0} = imm{7-0};
414 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
415 string opc, string asm, list<dag> pattern>
416 : T2I<oops, iops, itin, opc, asm, pattern> {
423 let Inst{14-12} = imm{4-2};
424 let Inst{7-6} = imm{1-0};
427 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
428 string opc, string asm, list<dag> pattern>
429 : T2sI<oops, iops, itin, opc, asm, pattern> {
436 let Inst{14-12} = imm{4-2};
437 let Inst{7-6} = imm{1-0};
440 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
441 string opc, string asm, list<dag> pattern>
442 : T2I<oops, iops, itin, opc, asm, pattern> {
448 let Inst{19-16} = Rn;
452 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
453 string opc, string asm, list<dag> pattern>
454 : T2sI<oops, iops, itin, opc, asm, pattern> {
460 let Inst{19-16} = Rn;
464 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
465 string opc, string asm, list<dag> pattern>
466 : T2I<oops, iops, itin, opc, asm, pattern> {
472 let Inst{19-16} = Rn;
473 let Inst{3-0} = ShiftedRm{3-0};
474 let Inst{5-4} = ShiftedRm{6-5};
475 let Inst{14-12} = ShiftedRm{11-9};
476 let Inst{7-6} = ShiftedRm{8-7};
479 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
480 string opc, string asm, list<dag> pattern>
481 : T2sI<oops, iops, itin, opc, asm, pattern> {
487 let Inst{19-16} = Rn;
488 let Inst{3-0} = ShiftedRm{3-0};
489 let Inst{5-4} = ShiftedRm{6-5};
490 let Inst{14-12} = ShiftedRm{11-9};
491 let Inst{7-6} = ShiftedRm{8-7};
494 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : T2I<oops, iops, itin, opc, asm, pattern> {
502 let Inst{19-16} = Rn;
503 let Inst{15-12} = Ra;
508 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
509 dag oops, dag iops, InstrItinClass itin,
510 string opc, string asm, list<dag> pattern>
511 : T2I<oops, iops, itin, opc, asm, pattern> {
517 let Inst{31-23} = 0b111110111;
518 let Inst{22-20} = opc22_20;
519 let Inst{19-16} = Rn;
520 let Inst{15-12} = RdLo;
521 let Inst{11-8} = RdHi;
522 let Inst{7-4} = opc7_4;
527 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
528 /// binary operation that produces a value. These are predicable and can be
529 /// changed to modify CPSR.
530 multiclass T2I_bin_irs<bits<4> opcod, string opc,
531 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
532 PatFrag opnode, string baseOpc, bit Commutable = 0,
535 def ri : T2sTwoRegImm<
536 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
537 opc, "\t$Rd, $Rn, $imm",
538 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
539 let Inst{31-27} = 0b11110;
541 let Inst{24-21} = opcod;
545 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
546 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
547 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
548 let isCommutable = Commutable;
549 let Inst{31-27} = 0b11101;
550 let Inst{26-25} = 0b01;
551 let Inst{24-21} = opcod;
552 let Inst{14-12} = 0b000; // imm3
553 let Inst{7-6} = 0b00; // imm2
554 let Inst{5-4} = 0b00; // type
557 def rs : T2sTwoRegShiftedReg<
558 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
559 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
560 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
561 let Inst{31-27} = 0b11101;
562 let Inst{26-25} = 0b01;
563 let Inst{24-21} = opcod;
565 // Assembly aliases for optional destination operand when it's the same
566 // as the source operand.
567 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
568 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
569 t2_so_imm:$imm, pred:$p,
571 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
572 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
575 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
576 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
577 t2_so_reg:$shift, pred:$p,
581 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
582 // the ".w" suffix to indicate that they are wide.
583 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
584 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
585 PatFrag opnode, string baseOpc, bit Commutable = 0> :
586 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
587 // Assembler aliases w/ the ".w" suffix.
588 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
589 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
590 t2_so_imm:$imm, pred:$p,
592 // Assembler aliases w/o the ".w" suffix.
593 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
594 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
597 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
598 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
599 t2_so_reg:$shift, pred:$p,
602 // and with the optional destination operand, too.
603 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
604 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
605 t2_so_imm:$imm, pred:$p,
607 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
608 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
611 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
612 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
613 t2_so_reg:$shift, pred:$p,
617 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
618 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
619 /// it is equivalent to the T2I_bin_irs counterpart.
620 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
622 def ri : T2sTwoRegImm<
623 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
624 opc, ".w\t$Rd, $Rn, $imm",
625 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
626 let Inst{31-27} = 0b11110;
628 let Inst{24-21} = opcod;
632 def rr : T2sThreeReg<
633 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
634 opc, "\t$Rd, $Rn, $Rm",
635 [/* For disassembly only; pattern left blank */]> {
636 let Inst{31-27} = 0b11101;
637 let Inst{26-25} = 0b01;
638 let Inst{24-21} = opcod;
639 let Inst{14-12} = 0b000; // imm3
640 let Inst{7-6} = 0b00; // imm2
641 let Inst{5-4} = 0b00; // type
644 def rs : T2sTwoRegShiftedReg<
645 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
646 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
647 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
648 let Inst{31-27} = 0b11101;
649 let Inst{26-25} = 0b01;
650 let Inst{24-21} = opcod;
654 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
655 /// instruction modifies the CPSR register.
657 /// These opcodes will be converted to the real non-S opcodes by
658 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
659 let hasPostISelHook = 1, Defs = [CPSR] in {
660 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
661 InstrItinClass iis, PatFrag opnode,
662 bit Commutable = 0> {
664 def ri : t2PseudoInst<(outs rGPR:$Rd),
665 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
667 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
670 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
672 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
674 let isCommutable = Commutable;
677 def rs : t2PseudoInst<(outs rGPR:$Rd),
678 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
680 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
681 t2_so_reg:$ShiftedRm))]>;
685 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
686 /// operands are reversed.
687 let hasPostISelHook = 1, Defs = [CPSR] in {
688 multiclass T2I_rbin_s_is<PatFrag opnode> {
690 def ri : t2PseudoInst<(outs rGPR:$Rd),
691 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
693 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
696 def rs : t2PseudoInst<(outs rGPR:$Rd),
697 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
699 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
704 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
705 /// patterns for a binary operation that produces a value.
706 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
707 bit Commutable = 0> {
709 // The register-immediate version is re-materializable. This is useful
710 // in particular for taking the address of a local.
711 let isReMaterializable = 1 in {
712 def ri : T2sTwoRegImm<
713 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
714 opc, ".w\t$Rd, $Rn, $imm",
715 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
716 let Inst{31-27} = 0b11110;
719 let Inst{23-21} = op23_21;
725 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
726 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
727 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
731 let Inst{31-27} = 0b11110;
732 let Inst{26} = imm{11};
733 let Inst{25-24} = 0b10;
734 let Inst{23-21} = op23_21;
735 let Inst{20} = 0; // The S bit.
736 let Inst{19-16} = Rn;
738 let Inst{14-12} = imm{10-8};
740 let Inst{7-0} = imm{7-0};
743 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
744 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
745 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
746 let isCommutable = Commutable;
747 let Inst{31-27} = 0b11101;
748 let Inst{26-25} = 0b01;
750 let Inst{23-21} = op23_21;
751 let Inst{14-12} = 0b000; // imm3
752 let Inst{7-6} = 0b00; // imm2
753 let Inst{5-4} = 0b00; // type
756 def rs : T2sTwoRegShiftedReg<
757 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
758 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
759 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
760 let Inst{31-27} = 0b11101;
761 let Inst{26-25} = 0b01;
763 let Inst{23-21} = op23_21;
767 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
768 /// for a binary operation that produces a value and use the carry
769 /// bit. It's not predicable.
770 let Defs = [CPSR], Uses = [CPSR] in {
771 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
772 bit Commutable = 0> {
774 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
775 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
776 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
777 Requires<[IsThumb2]> {
778 let Inst{31-27} = 0b11110;
780 let Inst{24-21} = opcod;
784 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
785 opc, ".w\t$Rd, $Rn, $Rm",
786 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
787 Requires<[IsThumb2]> {
788 let isCommutable = Commutable;
789 let Inst{31-27} = 0b11101;
790 let Inst{26-25} = 0b01;
791 let Inst{24-21} = opcod;
792 let Inst{14-12} = 0b000; // imm3
793 let Inst{7-6} = 0b00; // imm2
794 let Inst{5-4} = 0b00; // type
797 def rs : T2sTwoRegShiftedReg<
798 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
799 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
800 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
801 Requires<[IsThumb2]> {
802 let Inst{31-27} = 0b11101;
803 let Inst{26-25} = 0b01;
804 let Inst{24-21} = opcod;
809 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
810 // rotate operation that produces a value.
811 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
814 def ri : T2sTwoRegShiftImm<
815 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
816 opc, ".w\t$Rd, $Rm, $imm",
817 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
818 let Inst{31-27} = 0b11101;
819 let Inst{26-21} = 0b010010;
820 let Inst{19-16} = 0b1111; // Rn
821 let Inst{5-4} = opcod;
824 def rr : T2sThreeReg<
825 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
826 opc, ".w\t$Rd, $Rn, $Rm",
827 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
828 let Inst{31-27} = 0b11111;
829 let Inst{26-23} = 0b0100;
830 let Inst{22-21} = opcod;
831 let Inst{15-12} = 0b1111;
832 let Inst{7-4} = 0b0000;
835 // Optional destination register
836 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
837 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
840 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
841 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
845 // Assembler aliases w/o the ".w" suffix.
846 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
847 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
850 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
851 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
855 // and with the optional destination operand, too.
856 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
857 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
860 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
861 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
866 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
867 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
868 /// a explicit result, only implicitly set CPSR.
869 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
870 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
871 PatFrag opnode, string baseOpc> {
872 let isCompare = 1, Defs = [CPSR] in {
874 def ri : T2OneRegCmpImm<
875 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
876 opc, ".w\t$Rn, $imm",
877 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
878 let Inst{31-27} = 0b11110;
880 let Inst{24-21} = opcod;
881 let Inst{20} = 1; // The S bit.
883 let Inst{11-8} = 0b1111; // Rd
886 def rr : T2TwoRegCmp<
887 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
889 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
890 let Inst{31-27} = 0b11101;
891 let Inst{26-25} = 0b01;
892 let Inst{24-21} = opcod;
893 let Inst{20} = 1; // The S bit.
894 let Inst{14-12} = 0b000; // imm3
895 let Inst{11-8} = 0b1111; // Rd
896 let Inst{7-6} = 0b00; // imm2
897 let Inst{5-4} = 0b00; // type
900 def rs : T2OneRegCmpShiftedReg<
901 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
902 opc, ".w\t$Rn, $ShiftedRm",
903 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
904 let Inst{31-27} = 0b11101;
905 let Inst{26-25} = 0b01;
906 let Inst{24-21} = opcod;
907 let Inst{20} = 1; // The S bit.
908 let Inst{11-8} = 0b1111; // Rd
912 // Assembler aliases w/o the ".w" suffix.
913 // No alias here for 'rr' version as not all instantiations of this
914 // multiclass want one (CMP in particular, does not).
915 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
916 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
917 t2_so_imm:$imm, pred:$p)>;
918 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
919 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
924 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
925 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
926 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
928 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
929 opc, ".w\t$Rt, $addr",
930 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
933 let Inst{31-25} = 0b1111100;
934 let Inst{24} = signed;
936 let Inst{22-21} = opcod;
937 let Inst{20} = 1; // load
938 let Inst{19-16} = addr{16-13}; // Rn
939 let Inst{15-12} = Rt;
940 let Inst{11-0} = addr{11-0}; // imm
942 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
944 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
947 let Inst{31-27} = 0b11111;
948 let Inst{26-25} = 0b00;
949 let Inst{24} = signed;
951 let Inst{22-21} = opcod;
952 let Inst{20} = 1; // load
953 let Inst{19-16} = addr{12-9}; // Rn
954 let Inst{15-12} = Rt;
956 // Offset: index==TRUE, wback==FALSE
957 let Inst{10} = 1; // The P bit.
958 let Inst{9} = addr{8}; // U
959 let Inst{8} = 0; // The W bit.
960 let Inst{7-0} = addr{7-0}; // imm
962 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
963 opc, ".w\t$Rt, $addr",
964 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
965 let Inst{31-27} = 0b11111;
966 let Inst{26-25} = 0b00;
967 let Inst{24} = signed;
969 let Inst{22-21} = opcod;
970 let Inst{20} = 1; // load
971 let Inst{11-6} = 0b000000;
974 let Inst{15-12} = Rt;
977 let Inst{19-16} = addr{9-6}; // Rn
978 let Inst{3-0} = addr{5-2}; // Rm
979 let Inst{5-4} = addr{1-0}; // imm
981 let DecoderMethod = "DecodeT2LoadShift";
984 // pci variant is very similar to i12, but supports negative offsets
986 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
987 opc, ".w\t$Rt, $addr",
988 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
989 let isReMaterializable = 1;
990 let Inst{31-27} = 0b11111;
991 let Inst{26-25} = 0b00;
992 let Inst{24} = signed;
993 let Inst{23} = ?; // add = (U == '1')
994 let Inst{22-21} = opcod;
995 let Inst{20} = 1; // load
996 let Inst{19-16} = 0b1111; // Rn
999 let Inst{15-12} = Rt{3-0};
1000 let Inst{11-0} = addr{11-0};
1004 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1005 multiclass T2I_st<bits<2> opcod, string opc,
1006 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1008 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1009 opc, ".w\t$Rt, $addr",
1010 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1011 let Inst{31-27} = 0b11111;
1012 let Inst{26-23} = 0b0001;
1013 let Inst{22-21} = opcod;
1014 let Inst{20} = 0; // !load
1017 let Inst{15-12} = Rt;
1020 let addr{12} = 1; // add = TRUE
1021 let Inst{19-16} = addr{16-13}; // Rn
1022 let Inst{23} = addr{12}; // U
1023 let Inst{11-0} = addr{11-0}; // imm
1025 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1026 opc, "\t$Rt, $addr",
1027 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1028 let Inst{31-27} = 0b11111;
1029 let Inst{26-23} = 0b0000;
1030 let Inst{22-21} = opcod;
1031 let Inst{20} = 0; // !load
1033 // Offset: index==TRUE, wback==FALSE
1034 let Inst{10} = 1; // The P bit.
1035 let Inst{8} = 0; // The W bit.
1038 let Inst{15-12} = Rt;
1041 let Inst{19-16} = addr{12-9}; // Rn
1042 let Inst{9} = addr{8}; // U
1043 let Inst{7-0} = addr{7-0}; // imm
1045 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1046 opc, ".w\t$Rt, $addr",
1047 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1048 let Inst{31-27} = 0b11111;
1049 let Inst{26-23} = 0b0000;
1050 let Inst{22-21} = opcod;
1051 let Inst{20} = 0; // !load
1052 let Inst{11-6} = 0b000000;
1055 let Inst{15-12} = Rt;
1058 let Inst{19-16} = addr{9-6}; // Rn
1059 let Inst{3-0} = addr{5-2}; // Rm
1060 let Inst{5-4} = addr{1-0}; // imm
1064 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1065 /// register and one whose operand is a register rotated by 8/16/24.
1066 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1067 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1068 opc, ".w\t$Rd, $Rm$rot",
1069 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1070 Requires<[IsThumb2]> {
1071 let Inst{31-27} = 0b11111;
1072 let Inst{26-23} = 0b0100;
1073 let Inst{22-20} = opcod;
1074 let Inst{19-16} = 0b1111; // Rn
1075 let Inst{15-12} = 0b1111;
1079 let Inst{5-4} = rot{1-0}; // rotate
1082 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1083 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1084 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1085 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1086 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1087 Requires<[HasT2ExtractPack, IsThumb2]> {
1089 let Inst{31-27} = 0b11111;
1090 let Inst{26-23} = 0b0100;
1091 let Inst{22-20} = opcod;
1092 let Inst{19-16} = 0b1111; // Rn
1093 let Inst{15-12} = 0b1111;
1095 let Inst{5-4} = rot;
1098 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1100 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1101 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1102 opc, "\t$Rd, $Rm$rot", []>,
1103 Requires<[IsThumb2, HasT2ExtractPack]> {
1105 let Inst{31-27} = 0b11111;
1106 let Inst{26-23} = 0b0100;
1107 let Inst{22-20} = opcod;
1108 let Inst{19-16} = 0b1111; // Rn
1109 let Inst{15-12} = 0b1111;
1111 let Inst{5-4} = rot;
1114 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1115 /// register and one whose operand is a register rotated by 8/16/24.
1116 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1117 : T2ThreeReg<(outs rGPR:$Rd),
1118 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1119 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1120 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1121 Requires<[HasT2ExtractPack, IsThumb2]> {
1123 let Inst{31-27} = 0b11111;
1124 let Inst{26-23} = 0b0100;
1125 let Inst{22-20} = opcod;
1126 let Inst{15-12} = 0b1111;
1128 let Inst{5-4} = rot;
1131 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1132 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1133 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1135 let Inst{31-27} = 0b11111;
1136 let Inst{26-23} = 0b0100;
1137 let Inst{22-20} = opcod;
1138 let Inst{15-12} = 0b1111;
1140 let Inst{5-4} = rot;
1143 //===----------------------------------------------------------------------===//
1145 //===----------------------------------------------------------------------===//
1147 //===----------------------------------------------------------------------===//
1148 // Miscellaneous Instructions.
1151 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1152 string asm, list<dag> pattern>
1153 : T2XI<oops, iops, itin, asm, pattern> {
1157 let Inst{11-8} = Rd;
1158 let Inst{26} = label{11};
1159 let Inst{14-12} = label{10-8};
1160 let Inst{7-0} = label{7-0};
1163 // LEApcrel - Load a pc-relative address into a register without offending the
1165 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1166 (ins t2adrlabel:$addr, pred:$p),
1167 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1168 let Inst{31-27} = 0b11110;
1169 let Inst{25-24} = 0b10;
1170 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1173 let Inst{19-16} = 0b1111; // Rn
1178 let Inst{11-8} = Rd;
1179 let Inst{23} = addr{12};
1180 let Inst{21} = addr{12};
1181 let Inst{26} = addr{11};
1182 let Inst{14-12} = addr{10-8};
1183 let Inst{7-0} = addr{7-0};
1185 let DecoderMethod = "DecodeT2Adr";
1188 let neverHasSideEffects = 1, isReMaterializable = 1 in
1189 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1191 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1192 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1197 //===----------------------------------------------------------------------===//
1198 // Load / store Instructions.
1202 let canFoldAsLoad = 1, isReMaterializable = 1 in
1203 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1204 UnOpFrag<(load node:$Src)>>;
1206 // Loads with zero extension
1207 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1208 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1209 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1210 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1212 // Loads with sign extension
1213 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1214 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1215 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1216 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1218 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1220 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1221 (ins t2addrmode_imm8s4:$addr),
1222 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1223 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1225 // zextload i1 -> zextload i8
1226 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1227 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1228 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1229 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1230 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1231 (t2LDRBs t2addrmode_so_reg:$addr)>;
1232 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1233 (t2LDRBpci tconstpool:$addr)>;
1235 // extload -> zextload
1236 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1238 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1239 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1240 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1241 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1242 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1243 (t2LDRBs t2addrmode_so_reg:$addr)>;
1244 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1245 (t2LDRBpci tconstpool:$addr)>;
1247 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1248 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1249 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1250 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1251 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1252 (t2LDRBs t2addrmode_so_reg:$addr)>;
1253 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1254 (t2LDRBpci tconstpool:$addr)>;
1256 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1257 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1258 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1259 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1260 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1261 (t2LDRHs t2addrmode_so_reg:$addr)>;
1262 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1263 (t2LDRHpci tconstpool:$addr)>;
1265 // FIXME: The destination register of the loads and stores can't be PC, but
1266 // can be SP. We need another regclass (similar to rGPR) to represent
1267 // that. Not a pressing issue since these are selected manually,
1272 let mayLoad = 1, neverHasSideEffects = 1 in {
1273 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1274 (ins t2addrmode_imm8:$addr),
1275 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1276 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1278 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1281 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1282 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1283 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1284 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1286 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1287 (ins t2addrmode_imm8:$addr),
1288 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1289 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1291 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1293 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1294 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1295 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1296 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1298 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1299 (ins t2addrmode_imm8:$addr),
1300 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1301 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1303 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1305 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1306 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1307 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1308 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1310 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1311 (ins t2addrmode_imm8:$addr),
1312 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1313 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1315 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1317 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1318 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1319 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1320 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1322 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1323 (ins t2addrmode_imm8:$addr),
1324 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1325 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1327 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1329 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1330 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1331 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1332 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1333 } // mayLoad = 1, neverHasSideEffects = 1
1335 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1336 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1337 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1338 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1339 "\t$Rt, $addr", []> {
1342 let Inst{31-27} = 0b11111;
1343 let Inst{26-25} = 0b00;
1344 let Inst{24} = signed;
1346 let Inst{22-21} = type;
1347 let Inst{20} = 1; // load
1348 let Inst{19-16} = addr{12-9};
1349 let Inst{15-12} = Rt;
1351 let Inst{10-8} = 0b110; // PUW.
1352 let Inst{7-0} = addr{7-0};
1355 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1356 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1357 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1358 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1359 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1362 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1363 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1364 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1365 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1366 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1367 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1370 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1371 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1372 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1373 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1377 let mayStore = 1, neverHasSideEffects = 1 in {
1378 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1379 (ins GPRnopc:$Rt, t2addrmode_imm8:$addr),
1380 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1381 "str", "\t$Rt, $addr!",
1382 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1383 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1385 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1386 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1387 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1388 "strh", "\t$Rt, $addr!",
1389 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1390 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1393 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1394 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1395 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1396 "strb", "\t$Rt, $addr!",
1397 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1398 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1400 } // mayStore = 1, neverHasSideEffects = 1
1402 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1403 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1404 t2am_imm8_offset:$offset),
1405 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1406 "str", "\t$Rt, $Rn$offset",
1407 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1408 [(set GPRnopc:$Rn_wb,
1409 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1410 t2am_imm8_offset:$offset))]>;
1412 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1413 (ins rGPR:$Rt, addr_offset_none:$Rn,
1414 t2am_imm8_offset:$offset),
1415 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1416 "strh", "\t$Rt, $Rn$offset",
1417 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1418 [(set GPRnopc:$Rn_wb,
1419 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1420 t2am_imm8_offset:$offset))]>;
1422 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1423 (ins rGPR:$Rt, addr_offset_none:$Rn,
1424 t2am_imm8_offset:$offset),
1425 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1426 "strb", "\t$Rt, $Rn$offset",
1427 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1428 [(set GPRnopc:$Rn_wb,
1429 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1430 t2am_imm8_offset:$offset))]>;
1432 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1433 // put the patterns on the instruction definitions directly as ISel wants
1434 // the address base and offset to be separate operands, not a single
1435 // complex operand like we represent the instructions themselves. The
1436 // pseudos map between the two.
1437 let usesCustomInserter = 1,
1438 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1439 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1440 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1442 [(set GPRnopc:$Rn_wb,
1443 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1444 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1445 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1447 [(set GPRnopc:$Rn_wb,
1448 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1449 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1450 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1452 [(set GPRnopc:$Rn_wb,
1453 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1456 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1458 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1459 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1460 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1461 "\t$Rt, $addr", []> {
1462 let Inst{31-27} = 0b11111;
1463 let Inst{26-25} = 0b00;
1464 let Inst{24} = 0; // not signed
1466 let Inst{22-21} = type;
1467 let Inst{20} = 0; // store
1469 let Inst{10-8} = 0b110; // PUW
1473 let Inst{15-12} = Rt;
1474 let Inst{19-16} = addr{12-9};
1475 let Inst{7-0} = addr{7-0};
1478 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1479 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1480 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1482 // ldrd / strd pre / post variants
1483 // For disassembly only.
1485 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1486 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1487 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1488 let AsmMatchConverter = "cvtT2LdrdPre";
1489 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1492 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1493 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1494 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1495 "$addr.base = $wb", []>;
1497 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1498 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1499 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1500 "$addr.base = $wb", []> {
1501 let AsmMatchConverter = "cvtT2StrdPre";
1502 let DecoderMethod = "DecodeT2STRDPreInstruction";
1505 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1506 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1507 t2am_imm8s4_offset:$imm),
1508 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1509 "$addr.base = $wb", []>;
1511 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1512 // data/instruction access.
1513 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1514 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1515 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1517 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1519 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1520 let Inst{31-25} = 0b1111100;
1521 let Inst{24} = instr;
1523 let Inst{21} = write;
1525 let Inst{15-12} = 0b1111;
1528 let addr{12} = 1; // add = TRUE
1529 let Inst{19-16} = addr{16-13}; // Rn
1530 let Inst{23} = addr{12}; // U
1531 let Inst{11-0} = addr{11-0}; // imm12
1534 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1536 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1537 let Inst{31-25} = 0b1111100;
1538 let Inst{24} = instr;
1539 let Inst{23} = 0; // U = 0
1541 let Inst{21} = write;
1543 let Inst{15-12} = 0b1111;
1544 let Inst{11-8} = 0b1100;
1547 let Inst{19-16} = addr{12-9}; // Rn
1548 let Inst{7-0} = addr{7-0}; // imm8
1551 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1553 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1554 let Inst{31-25} = 0b1111100;
1555 let Inst{24} = instr;
1556 let Inst{23} = 0; // add = TRUE for T1
1558 let Inst{21} = write;
1560 let Inst{15-12} = 0b1111;
1561 let Inst{11-6} = 0000000;
1564 let Inst{19-16} = addr{9-6}; // Rn
1565 let Inst{3-0} = addr{5-2}; // Rm
1566 let Inst{5-4} = addr{1-0}; // imm2
1568 let DecoderMethod = "DecodeT2LoadShift";
1570 // FIXME: We should have a separate 'pci' variant here. As-is we represent
1571 // it via the i12 variant, which it's related to, but that means we can
1572 // represent negative immediates, which aren't legal for anything except
1573 // the 'pci' case (Rn == 15).
1576 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1577 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1578 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1580 //===----------------------------------------------------------------------===//
1581 // Load / store multiple Instructions.
1584 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1585 InstrItinClass itin_upd, bit L_bit> {
1587 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1588 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1592 let Inst{31-27} = 0b11101;
1593 let Inst{26-25} = 0b00;
1594 let Inst{24-23} = 0b01; // Increment After
1596 let Inst{21} = 0; // No writeback
1597 let Inst{20} = L_bit;
1598 let Inst{19-16} = Rn;
1599 let Inst{15-0} = regs;
1602 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1603 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1607 let Inst{31-27} = 0b11101;
1608 let Inst{26-25} = 0b00;
1609 let Inst{24-23} = 0b01; // Increment After
1611 let Inst{21} = 1; // Writeback
1612 let Inst{20} = L_bit;
1613 let Inst{19-16} = Rn;
1614 let Inst{15-0} = regs;
1617 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1618 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1622 let Inst{31-27} = 0b11101;
1623 let Inst{26-25} = 0b00;
1624 let Inst{24-23} = 0b10; // Decrement Before
1626 let Inst{21} = 0; // No writeback
1627 let Inst{20} = L_bit;
1628 let Inst{19-16} = Rn;
1629 let Inst{15-0} = regs;
1632 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1633 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1637 let Inst{31-27} = 0b11101;
1638 let Inst{26-25} = 0b00;
1639 let Inst{24-23} = 0b10; // Decrement Before
1641 let Inst{21} = 1; // Writeback
1642 let Inst{20} = L_bit;
1643 let Inst{19-16} = Rn;
1644 let Inst{15-0} = regs;
1648 let neverHasSideEffects = 1 in {
1650 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1651 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1653 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1654 InstrItinClass itin_upd, bit L_bit> {
1656 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1657 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1661 let Inst{31-27} = 0b11101;
1662 let Inst{26-25} = 0b00;
1663 let Inst{24-23} = 0b01; // Increment After
1665 let Inst{21} = 0; // No writeback
1666 let Inst{20} = L_bit;
1667 let Inst{19-16} = Rn;
1669 let Inst{14} = regs{14};
1671 let Inst{12-0} = regs{12-0};
1674 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1675 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1679 let Inst{31-27} = 0b11101;
1680 let Inst{26-25} = 0b00;
1681 let Inst{24-23} = 0b01; // Increment After
1683 let Inst{21} = 1; // Writeback
1684 let Inst{20} = L_bit;
1685 let Inst{19-16} = Rn;
1687 let Inst{14} = regs{14};
1689 let Inst{12-0} = regs{12-0};
1692 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1693 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1697 let Inst{31-27} = 0b11101;
1698 let Inst{26-25} = 0b00;
1699 let Inst{24-23} = 0b10; // Decrement Before
1701 let Inst{21} = 0; // No writeback
1702 let Inst{20} = L_bit;
1703 let Inst{19-16} = Rn;
1705 let Inst{14} = regs{14};
1707 let Inst{12-0} = regs{12-0};
1710 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1711 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1715 let Inst{31-27} = 0b11101;
1716 let Inst{26-25} = 0b00;
1717 let Inst{24-23} = 0b10; // Decrement Before
1719 let Inst{21} = 1; // Writeback
1720 let Inst{20} = L_bit;
1721 let Inst{19-16} = Rn;
1723 let Inst{14} = regs{14};
1725 let Inst{12-0} = regs{12-0};
1730 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1731 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1733 } // neverHasSideEffects
1736 //===----------------------------------------------------------------------===//
1737 // Move Instructions.
1740 let neverHasSideEffects = 1 in
1741 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1742 "mov", ".w\t$Rd, $Rm", []> {
1743 let Inst{31-27} = 0b11101;
1744 let Inst{26-25} = 0b01;
1745 let Inst{24-21} = 0b0010;
1746 let Inst{19-16} = 0b1111; // Rn
1747 let Inst{14-12} = 0b000;
1748 let Inst{7-4} = 0b0000;
1750 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1751 pred:$p, zero_reg)>;
1752 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1754 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1757 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1758 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1759 AddedComplexity = 1 in
1760 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1761 "mov", ".w\t$Rd, $imm",
1762 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1763 let Inst{31-27} = 0b11110;
1765 let Inst{24-21} = 0b0010;
1766 let Inst{19-16} = 0b1111; // Rn
1770 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1771 // Use aliases to get that to play nice here.
1772 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1774 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1777 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1778 pred:$p, zero_reg)>;
1779 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1780 pred:$p, zero_reg)>;
1782 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1783 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1784 "movw", "\t$Rd, $imm",
1785 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1786 let Inst{31-27} = 0b11110;
1788 let Inst{24-21} = 0b0010;
1789 let Inst{20} = 0; // The S bit.
1795 let Inst{11-8} = Rd;
1796 let Inst{19-16} = imm{15-12};
1797 let Inst{26} = imm{11};
1798 let Inst{14-12} = imm{10-8};
1799 let Inst{7-0} = imm{7-0};
1800 let DecoderMethod = "DecodeT2MOVTWInstruction";
1803 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1804 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1806 let Constraints = "$src = $Rd" in {
1807 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1808 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1809 "movt", "\t$Rd, $imm",
1811 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1812 let Inst{31-27} = 0b11110;
1814 let Inst{24-21} = 0b0110;
1815 let Inst{20} = 0; // The S bit.
1821 let Inst{11-8} = Rd;
1822 let Inst{19-16} = imm{15-12};
1823 let Inst{26} = imm{11};
1824 let Inst{14-12} = imm{10-8};
1825 let Inst{7-0} = imm{7-0};
1826 let DecoderMethod = "DecodeT2MOVTWInstruction";
1829 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1830 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1833 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1835 //===----------------------------------------------------------------------===//
1836 // Extend Instructions.
1841 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1842 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1843 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1844 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1845 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1847 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1848 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1849 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1850 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1851 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1855 let AddedComplexity = 16 in {
1856 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1857 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1858 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1859 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1860 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1861 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1863 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1864 // The transformation should probably be done as a combiner action
1865 // instead so we can include a check for masking back in the upper
1866 // eight bits of the source into the lower eight bits of the result.
1867 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1868 // (t2UXTB16 rGPR:$Src, 3)>,
1869 // Requires<[HasT2ExtractPack, IsThumb2]>;
1870 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1871 (t2UXTB16 rGPR:$Src, 1)>,
1872 Requires<[HasT2ExtractPack, IsThumb2]>;
1874 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1875 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1876 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1877 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1878 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1881 //===----------------------------------------------------------------------===//
1882 // Arithmetic Instructions.
1885 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1886 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1887 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1888 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1890 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1892 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1893 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1894 // AdjustInstrPostInstrSelection where we determine whether or not to
1895 // set the "s" bit based on CPSR liveness.
1897 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1898 // support for an optional CPSR definition that corresponds to the DAG
1899 // node's second value. We can then eliminate the implicit def of CPSR.
1900 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1901 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1902 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1903 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1905 let hasPostISelHook = 1 in {
1906 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1907 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1908 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1909 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1913 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1914 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1916 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1917 // CPSR and the implicit def of CPSR is not needed.
1918 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1920 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1921 // The assume-no-carry-in form uses the negation of the input since add/sub
1922 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1923 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1925 // The AddedComplexity preferences the first variant over the others since
1926 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1927 let AddedComplexity = 1 in
1928 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1929 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1930 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1931 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1932 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1933 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1934 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
1935 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
1937 let AddedComplexity = 1 in
1938 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1939 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1940 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1941 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1942 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
1943 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
1944 // The with-carry-in form matches bitwise not instead of the negation.
1945 // Effectively, the inverse interpretation of the carry flag already accounts
1946 // for part of the negation.
1947 let AddedComplexity = 1 in
1948 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1949 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1950 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1951 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1952 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
1953 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
1955 // Select Bytes -- for disassembly only
1957 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1958 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1959 Requires<[IsThumb2, HasThumb2DSP]> {
1960 let Inst{31-27} = 0b11111;
1961 let Inst{26-24} = 0b010;
1963 let Inst{22-20} = 0b010;
1964 let Inst{15-12} = 0b1111;
1966 let Inst{6-4} = 0b000;
1969 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1970 // And Miscellaneous operations -- for disassembly only
1971 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1972 list<dag> pat = [/* For disassembly only; pattern left blank */],
1973 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1974 string asm = "\t$Rd, $Rn, $Rm">
1975 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1976 Requires<[IsThumb2, HasThumb2DSP]> {
1977 let Inst{31-27} = 0b11111;
1978 let Inst{26-23} = 0b0101;
1979 let Inst{22-20} = op22_20;
1980 let Inst{15-12} = 0b1111;
1981 let Inst{7-4} = op7_4;
1987 let Inst{11-8} = Rd;
1988 let Inst{19-16} = Rn;
1992 // Saturating add/subtract -- for disassembly only
1994 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1995 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1996 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1997 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1998 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1999 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2000 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2001 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2002 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2003 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2004 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2005 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2006 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2007 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2008 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2009 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2010 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2011 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2012 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2013 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2014 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2015 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2017 // Signed/Unsigned add/subtract -- for disassembly only
2019 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2020 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2021 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2022 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2023 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2024 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2025 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2026 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2027 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2028 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2029 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2030 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2032 // Signed/Unsigned halving add/subtract -- for disassembly only
2034 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2035 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2036 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2037 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2038 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2039 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2040 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2041 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2042 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2043 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2044 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2045 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2047 // Helper class for disassembly only
2048 // A6.3.16 & A6.3.17
2049 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2050 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2051 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2052 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2053 let Inst{31-27} = 0b11111;
2054 let Inst{26-24} = 0b011;
2055 let Inst{23} = long;
2056 let Inst{22-20} = op22_20;
2057 let Inst{7-4} = op7_4;
2060 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2061 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2062 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2063 let Inst{31-27} = 0b11111;
2064 let Inst{26-24} = 0b011;
2065 let Inst{23} = long;
2066 let Inst{22-20} = op22_20;
2067 let Inst{7-4} = op7_4;
2070 // Unsigned Sum of Absolute Differences [and Accumulate].
2071 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2072 (ins rGPR:$Rn, rGPR:$Rm),
2073 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2074 Requires<[IsThumb2, HasThumb2DSP]> {
2075 let Inst{15-12} = 0b1111;
2077 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2078 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2079 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2080 Requires<[IsThumb2, HasThumb2DSP]>;
2082 // Signed/Unsigned saturate.
2083 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2084 string opc, string asm, list<dag> pattern>
2085 : T2I<oops, iops, itin, opc, asm, pattern> {
2091 let Inst{11-8} = Rd;
2092 let Inst{19-16} = Rn;
2093 let Inst{4-0} = sat_imm;
2094 let Inst{21} = sh{5};
2095 let Inst{14-12} = sh{4-2};
2096 let Inst{7-6} = sh{1-0};
2101 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2102 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2103 let Inst{31-27} = 0b11110;
2104 let Inst{25-22} = 0b1100;
2110 def t2SSAT16: T2SatI<
2111 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2112 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2113 Requires<[IsThumb2, HasThumb2DSP]> {
2114 let Inst{31-27} = 0b11110;
2115 let Inst{25-22} = 0b1100;
2118 let Inst{21} = 1; // sh = '1'
2119 let Inst{14-12} = 0b000; // imm3 = '000'
2120 let Inst{7-6} = 0b00; // imm2 = '00'
2121 let Inst{5-4} = 0b00;
2126 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2127 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2128 let Inst{31-27} = 0b11110;
2129 let Inst{25-22} = 0b1110;
2134 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2136 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2137 Requires<[IsThumb2, HasThumb2DSP]> {
2138 let Inst{31-22} = 0b1111001110;
2141 let Inst{21} = 1; // sh = '1'
2142 let Inst{14-12} = 0b000; // imm3 = '000'
2143 let Inst{7-6} = 0b00; // imm2 = '00'
2144 let Inst{5-4} = 0b00;
2147 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2148 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2150 //===----------------------------------------------------------------------===//
2151 // Shift and rotate Instructions.
2154 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2155 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2156 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2157 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2158 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2159 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2160 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2161 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2163 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2164 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2165 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2167 let Uses = [CPSR] in {
2168 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2169 "rrx", "\t$Rd, $Rm",
2170 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2171 let Inst{31-27} = 0b11101;
2172 let Inst{26-25} = 0b01;
2173 let Inst{24-21} = 0b0010;
2174 let Inst{19-16} = 0b1111; // Rn
2175 let Inst{14-12} = 0b000;
2176 let Inst{7-4} = 0b0011;
2180 let isCodeGenOnly = 1, Defs = [CPSR] in {
2181 def t2MOVsrl_flag : T2TwoRegShiftImm<
2182 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2183 "lsrs", ".w\t$Rd, $Rm, #1",
2184 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2185 let Inst{31-27} = 0b11101;
2186 let Inst{26-25} = 0b01;
2187 let Inst{24-21} = 0b0010;
2188 let Inst{20} = 1; // The S bit.
2189 let Inst{19-16} = 0b1111; // Rn
2190 let Inst{5-4} = 0b01; // Shift type.
2191 // Shift amount = Inst{14-12:7-6} = 1.
2192 let Inst{14-12} = 0b000;
2193 let Inst{7-6} = 0b01;
2195 def t2MOVsra_flag : T2TwoRegShiftImm<
2196 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2197 "asrs", ".w\t$Rd, $Rm, #1",
2198 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2199 let Inst{31-27} = 0b11101;
2200 let Inst{26-25} = 0b01;
2201 let Inst{24-21} = 0b0010;
2202 let Inst{20} = 1; // The S bit.
2203 let Inst{19-16} = 0b1111; // Rn
2204 let Inst{5-4} = 0b10; // Shift type.
2205 // Shift amount = Inst{14-12:7-6} = 1.
2206 let Inst{14-12} = 0b000;
2207 let Inst{7-6} = 0b01;
2211 //===----------------------------------------------------------------------===//
2212 // Bitwise Instructions.
2215 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2216 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2217 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2218 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2219 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2220 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2221 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2222 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2223 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2225 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2226 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2227 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2230 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2231 string opc, string asm, list<dag> pattern>
2232 : T2I<oops, iops, itin, opc, asm, pattern> {
2237 let Inst{11-8} = Rd;
2238 let Inst{4-0} = msb{4-0};
2239 let Inst{14-12} = lsb{4-2};
2240 let Inst{7-6} = lsb{1-0};
2243 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2244 string opc, string asm, list<dag> pattern>
2245 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2248 let Inst{19-16} = Rn;
2251 let Constraints = "$src = $Rd" in
2252 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2253 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2254 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2255 let Inst{31-27} = 0b11110;
2256 let Inst{26} = 0; // should be 0.
2258 let Inst{24-20} = 0b10110;
2259 let Inst{19-16} = 0b1111; // Rn
2261 let Inst{5} = 0; // should be 0.
2264 let msb{4-0} = imm{9-5};
2265 let lsb{4-0} = imm{4-0};
2268 def t2SBFX: T2TwoRegBitFI<
2269 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2270 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2271 let Inst{31-27} = 0b11110;
2273 let Inst{24-20} = 0b10100;
2277 def t2UBFX: T2TwoRegBitFI<
2278 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2279 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2280 let Inst{31-27} = 0b11110;
2282 let Inst{24-20} = 0b11100;
2286 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2287 let Constraints = "$src = $Rd" in {
2288 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2289 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2290 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2291 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2292 bf_inv_mask_imm:$imm))]> {
2293 let Inst{31-27} = 0b11110;
2294 let Inst{26} = 0; // should be 0.
2296 let Inst{24-20} = 0b10110;
2298 let Inst{5} = 0; // should be 0.
2301 let msb{4-0} = imm{9-5};
2302 let lsb{4-0} = imm{4-0};
2306 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2307 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2308 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2311 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2312 /// unary operation that produces a value. These are predicable and can be
2313 /// changed to modify CPSR.
2314 multiclass T2I_un_irs<bits<4> opcod, string opc,
2315 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2316 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2318 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2320 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2321 let isAsCheapAsAMove = Cheap;
2322 let isReMaterializable = ReMat;
2323 let Inst{31-27} = 0b11110;
2325 let Inst{24-21} = opcod;
2326 let Inst{19-16} = 0b1111; // Rn
2330 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2331 opc, ".w\t$Rd, $Rm",
2332 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2333 let Inst{31-27} = 0b11101;
2334 let Inst{26-25} = 0b01;
2335 let Inst{24-21} = opcod;
2336 let Inst{19-16} = 0b1111; // Rn
2337 let Inst{14-12} = 0b000; // imm3
2338 let Inst{7-6} = 0b00; // imm2
2339 let Inst{5-4} = 0b00; // type
2342 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2343 opc, ".w\t$Rd, $ShiftedRm",
2344 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2345 let Inst{31-27} = 0b11101;
2346 let Inst{26-25} = 0b01;
2347 let Inst{24-21} = opcod;
2348 let Inst{19-16} = 0b1111; // Rn
2352 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2353 let AddedComplexity = 1 in
2354 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2355 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2356 UnOpFrag<(not node:$Src)>, 1, 1>;
2358 let AddedComplexity = 1 in
2359 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2360 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2362 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2363 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2364 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2367 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2368 // will match the extended, not the original bitWidth for $src.
2369 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2370 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2373 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2374 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2375 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2376 Requires<[IsThumb2]>;
2378 def : T2Pat<(t2_so_imm_not:$src),
2379 (t2MVNi t2_so_imm_not:$src)>;
2381 //===----------------------------------------------------------------------===//
2382 // Multiply Instructions.
2384 let isCommutable = 1 in
2385 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2386 "mul", "\t$Rd, $Rn, $Rm",
2387 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2388 let Inst{31-27} = 0b11111;
2389 let Inst{26-23} = 0b0110;
2390 let Inst{22-20} = 0b000;
2391 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2392 let Inst{7-4} = 0b0000; // Multiply
2395 def t2MLA: T2FourReg<
2396 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2397 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2398 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2399 let Inst{31-27} = 0b11111;
2400 let Inst{26-23} = 0b0110;
2401 let Inst{22-20} = 0b000;
2402 let Inst{7-4} = 0b0000; // Multiply
2405 def t2MLS: T2FourReg<
2406 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2407 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2408 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2409 let Inst{31-27} = 0b11111;
2410 let Inst{26-23} = 0b0110;
2411 let Inst{22-20} = 0b000;
2412 let Inst{7-4} = 0b0001; // Multiply and Subtract
2415 // Extra precision multiplies with low / high results
2416 let neverHasSideEffects = 1 in {
2417 let isCommutable = 1 in {
2418 def t2SMULL : T2MulLong<0b000, 0b0000,
2419 (outs rGPR:$RdLo, rGPR:$RdHi),
2420 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2421 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2423 def t2UMULL : T2MulLong<0b010, 0b0000,
2424 (outs rGPR:$RdLo, rGPR:$RdHi),
2425 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2426 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2429 // Multiply + accumulate
2430 def t2SMLAL : T2MulLong<0b100, 0b0000,
2431 (outs rGPR:$RdLo, rGPR:$RdHi),
2432 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2433 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2435 def t2UMLAL : T2MulLong<0b110, 0b0000,
2436 (outs rGPR:$RdLo, rGPR:$RdHi),
2437 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2438 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2440 def t2UMAAL : T2MulLong<0b110, 0b0110,
2441 (outs rGPR:$RdLo, rGPR:$RdHi),
2442 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2443 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2444 Requires<[IsThumb2, HasThumb2DSP]>;
2445 } // neverHasSideEffects
2447 // Rounding variants of the below included for disassembly only
2449 // Most significant word multiply
2450 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2451 "smmul", "\t$Rd, $Rn, $Rm",
2452 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2453 Requires<[IsThumb2, HasThumb2DSP]> {
2454 let Inst{31-27} = 0b11111;
2455 let Inst{26-23} = 0b0110;
2456 let Inst{22-20} = 0b101;
2457 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2458 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2461 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2462 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2463 Requires<[IsThumb2, HasThumb2DSP]> {
2464 let Inst{31-27} = 0b11111;
2465 let Inst{26-23} = 0b0110;
2466 let Inst{22-20} = 0b101;
2467 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2468 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2471 def t2SMMLA : T2FourReg<
2472 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2473 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2474 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2475 Requires<[IsThumb2, HasThumb2DSP]> {
2476 let Inst{31-27} = 0b11111;
2477 let Inst{26-23} = 0b0110;
2478 let Inst{22-20} = 0b101;
2479 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2482 def t2SMMLAR: T2FourReg<
2483 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2484 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2485 Requires<[IsThumb2, HasThumb2DSP]> {
2486 let Inst{31-27} = 0b11111;
2487 let Inst{26-23} = 0b0110;
2488 let Inst{22-20} = 0b101;
2489 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2492 def t2SMMLS: T2FourReg<
2493 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2494 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2495 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2496 Requires<[IsThumb2, HasThumb2DSP]> {
2497 let Inst{31-27} = 0b11111;
2498 let Inst{26-23} = 0b0110;
2499 let Inst{22-20} = 0b110;
2500 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2503 def t2SMMLSR:T2FourReg<
2504 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2505 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2506 Requires<[IsThumb2, HasThumb2DSP]> {
2507 let Inst{31-27} = 0b11111;
2508 let Inst{26-23} = 0b0110;
2509 let Inst{22-20} = 0b110;
2510 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2513 multiclass T2I_smul<string opc, PatFrag opnode> {
2514 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2515 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2516 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2517 (sext_inreg rGPR:$Rm, i16)))]>,
2518 Requires<[IsThumb2, HasThumb2DSP]> {
2519 let Inst{31-27} = 0b11111;
2520 let Inst{26-23} = 0b0110;
2521 let Inst{22-20} = 0b001;
2522 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2523 let Inst{7-6} = 0b00;
2524 let Inst{5-4} = 0b00;
2527 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2528 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2529 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2530 (sra rGPR:$Rm, (i32 16))))]>,
2531 Requires<[IsThumb2, HasThumb2DSP]> {
2532 let Inst{31-27} = 0b11111;
2533 let Inst{26-23} = 0b0110;
2534 let Inst{22-20} = 0b001;
2535 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2536 let Inst{7-6} = 0b00;
2537 let Inst{5-4} = 0b01;
2540 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2541 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2542 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2543 (sext_inreg rGPR:$Rm, i16)))]>,
2544 Requires<[IsThumb2, HasThumb2DSP]> {
2545 let Inst{31-27} = 0b11111;
2546 let Inst{26-23} = 0b0110;
2547 let Inst{22-20} = 0b001;
2548 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2549 let Inst{7-6} = 0b00;
2550 let Inst{5-4} = 0b10;
2553 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2554 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2555 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2556 (sra rGPR:$Rm, (i32 16))))]>,
2557 Requires<[IsThumb2, HasThumb2DSP]> {
2558 let Inst{31-27} = 0b11111;
2559 let Inst{26-23} = 0b0110;
2560 let Inst{22-20} = 0b001;
2561 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2562 let Inst{7-6} = 0b00;
2563 let Inst{5-4} = 0b11;
2566 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2567 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2568 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2569 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2570 Requires<[IsThumb2, HasThumb2DSP]> {
2571 let Inst{31-27} = 0b11111;
2572 let Inst{26-23} = 0b0110;
2573 let Inst{22-20} = 0b011;
2574 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2575 let Inst{7-6} = 0b00;
2576 let Inst{5-4} = 0b00;
2579 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2580 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2581 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2582 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2583 Requires<[IsThumb2, HasThumb2DSP]> {
2584 let Inst{31-27} = 0b11111;
2585 let Inst{26-23} = 0b0110;
2586 let Inst{22-20} = 0b011;
2587 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2588 let Inst{7-6} = 0b00;
2589 let Inst{5-4} = 0b01;
2594 multiclass T2I_smla<string opc, PatFrag opnode> {
2596 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2597 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2598 [(set rGPR:$Rd, (add rGPR:$Ra,
2599 (opnode (sext_inreg rGPR:$Rn, i16),
2600 (sext_inreg rGPR:$Rm, i16))))]>,
2601 Requires<[IsThumb2, HasThumb2DSP]> {
2602 let Inst{31-27} = 0b11111;
2603 let Inst{26-23} = 0b0110;
2604 let Inst{22-20} = 0b001;
2605 let Inst{7-6} = 0b00;
2606 let Inst{5-4} = 0b00;
2610 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2611 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2612 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2613 (sra rGPR:$Rm, (i32 16)))))]>,
2614 Requires<[IsThumb2, HasThumb2DSP]> {
2615 let Inst{31-27} = 0b11111;
2616 let Inst{26-23} = 0b0110;
2617 let Inst{22-20} = 0b001;
2618 let Inst{7-6} = 0b00;
2619 let Inst{5-4} = 0b01;
2623 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2624 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2625 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2626 (sext_inreg rGPR:$Rm, i16))))]>,
2627 Requires<[IsThumb2, HasThumb2DSP]> {
2628 let Inst{31-27} = 0b11111;
2629 let Inst{26-23} = 0b0110;
2630 let Inst{22-20} = 0b001;
2631 let Inst{7-6} = 0b00;
2632 let Inst{5-4} = 0b10;
2636 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2637 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2638 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2639 (sra rGPR:$Rm, (i32 16)))))]>,
2640 Requires<[IsThumb2, HasThumb2DSP]> {
2641 let Inst{31-27} = 0b11111;
2642 let Inst{26-23} = 0b0110;
2643 let Inst{22-20} = 0b001;
2644 let Inst{7-6} = 0b00;
2645 let Inst{5-4} = 0b11;
2649 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2650 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2651 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2652 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2653 Requires<[IsThumb2, HasThumb2DSP]> {
2654 let Inst{31-27} = 0b11111;
2655 let Inst{26-23} = 0b0110;
2656 let Inst{22-20} = 0b011;
2657 let Inst{7-6} = 0b00;
2658 let Inst{5-4} = 0b00;
2662 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2663 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2664 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2665 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2666 Requires<[IsThumb2, HasThumb2DSP]> {
2667 let Inst{31-27} = 0b11111;
2668 let Inst{26-23} = 0b0110;
2669 let Inst{22-20} = 0b011;
2670 let Inst{7-6} = 0b00;
2671 let Inst{5-4} = 0b01;
2675 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2676 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2678 // Halfword multiple accumulate long: SMLAL<x><y>
2679 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2680 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2681 [/* For disassembly only; pattern left blank */]>,
2682 Requires<[IsThumb2, HasThumb2DSP]>;
2683 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2684 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2685 [/* For disassembly only; pattern left blank */]>,
2686 Requires<[IsThumb2, HasThumb2DSP]>;
2687 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2688 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2689 [/* For disassembly only; pattern left blank */]>,
2690 Requires<[IsThumb2, HasThumb2DSP]>;
2691 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2692 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2693 [/* For disassembly only; pattern left blank */]>,
2694 Requires<[IsThumb2, HasThumb2DSP]>;
2696 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2697 def t2SMUAD: T2ThreeReg_mac<
2698 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2699 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2700 Requires<[IsThumb2, HasThumb2DSP]> {
2701 let Inst{15-12} = 0b1111;
2703 def t2SMUADX:T2ThreeReg_mac<
2704 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2705 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2706 Requires<[IsThumb2, HasThumb2DSP]> {
2707 let Inst{15-12} = 0b1111;
2709 def t2SMUSD: T2ThreeReg_mac<
2710 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2711 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2712 Requires<[IsThumb2, HasThumb2DSP]> {
2713 let Inst{15-12} = 0b1111;
2715 def t2SMUSDX:T2ThreeReg_mac<
2716 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2717 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2718 Requires<[IsThumb2, HasThumb2DSP]> {
2719 let Inst{15-12} = 0b1111;
2721 def t2SMLAD : T2FourReg_mac<
2722 0, 0b010, 0b0000, (outs rGPR:$Rd),
2723 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2724 "\t$Rd, $Rn, $Rm, $Ra", []>,
2725 Requires<[IsThumb2, HasThumb2DSP]>;
2726 def t2SMLADX : T2FourReg_mac<
2727 0, 0b010, 0b0001, (outs rGPR:$Rd),
2728 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2729 "\t$Rd, $Rn, $Rm, $Ra", []>,
2730 Requires<[IsThumb2, HasThumb2DSP]>;
2731 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2732 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2733 "\t$Rd, $Rn, $Rm, $Ra", []>,
2734 Requires<[IsThumb2, HasThumb2DSP]>;
2735 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2736 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2737 "\t$Rd, $Rn, $Rm, $Ra", []>,
2738 Requires<[IsThumb2, HasThumb2DSP]>;
2739 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2740 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2741 "\t$Ra, $Rd, $Rn, $Rm", []>,
2742 Requires<[IsThumb2, HasThumb2DSP]>;
2743 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2744 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2745 "\t$Ra, $Rd, $Rn, $Rm", []>,
2746 Requires<[IsThumb2, HasThumb2DSP]>;
2747 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2748 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2749 "\t$Ra, $Rd, $Rn, $Rm", []>,
2750 Requires<[IsThumb2, HasThumb2DSP]>;
2751 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2752 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2753 "\t$Ra, $Rd, $Rn, $Rm", []>,
2754 Requires<[IsThumb2, HasThumb2DSP]>;
2756 //===----------------------------------------------------------------------===//
2757 // Division Instructions.
2758 // Signed and unsigned division on v7-M
2760 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2761 "sdiv", "\t$Rd, $Rn, $Rm",
2762 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2763 Requires<[HasDivide, IsThumb2]> {
2764 let Inst{31-27} = 0b11111;
2765 let Inst{26-21} = 0b011100;
2767 let Inst{15-12} = 0b1111;
2768 let Inst{7-4} = 0b1111;
2771 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2772 "udiv", "\t$Rd, $Rn, $Rm",
2773 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2774 Requires<[HasDivide, IsThumb2]> {
2775 let Inst{31-27} = 0b11111;
2776 let Inst{26-21} = 0b011101;
2778 let Inst{15-12} = 0b1111;
2779 let Inst{7-4} = 0b1111;
2782 //===----------------------------------------------------------------------===//
2783 // Misc. Arithmetic Instructions.
2786 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2787 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2788 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2789 let Inst{31-27} = 0b11111;
2790 let Inst{26-22} = 0b01010;
2791 let Inst{21-20} = op1;
2792 let Inst{15-12} = 0b1111;
2793 let Inst{7-6} = 0b10;
2794 let Inst{5-4} = op2;
2798 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2799 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2801 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2802 "rbit", "\t$Rd, $Rm",
2803 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2805 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2806 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2808 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2809 "rev16", ".w\t$Rd, $Rm",
2810 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2812 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2813 "revsh", ".w\t$Rd, $Rm",
2814 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2816 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2817 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2818 (t2REVSH rGPR:$Rm)>;
2820 def t2PKHBT : T2ThreeReg<
2821 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2822 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2823 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2824 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2826 Requires<[HasT2ExtractPack, IsThumb2]> {
2827 let Inst{31-27} = 0b11101;
2828 let Inst{26-25} = 0b01;
2829 let Inst{24-20} = 0b01100;
2830 let Inst{5} = 0; // BT form
2834 let Inst{14-12} = sh{4-2};
2835 let Inst{7-6} = sh{1-0};
2838 // Alternate cases for PKHBT where identities eliminate some nodes.
2839 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2840 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2841 Requires<[HasT2ExtractPack, IsThumb2]>;
2842 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2843 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2844 Requires<[HasT2ExtractPack, IsThumb2]>;
2846 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2847 // will match the pattern below.
2848 def t2PKHTB : T2ThreeReg<
2849 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2850 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2851 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2852 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2854 Requires<[HasT2ExtractPack, IsThumb2]> {
2855 let Inst{31-27} = 0b11101;
2856 let Inst{26-25} = 0b01;
2857 let Inst{24-20} = 0b01100;
2858 let Inst{5} = 1; // TB form
2862 let Inst{14-12} = sh{4-2};
2863 let Inst{7-6} = sh{1-0};
2866 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2867 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2868 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2869 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2870 Requires<[HasT2ExtractPack, IsThumb2]>;
2871 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2872 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2873 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2874 Requires<[HasT2ExtractPack, IsThumb2]>;
2876 //===----------------------------------------------------------------------===//
2877 // Comparison Instructions...
2879 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2880 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2881 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2883 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2884 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2885 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2886 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2887 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2888 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2890 let isCompare = 1, Defs = [CPSR] in {
2892 def t2CMNri : T2OneRegCmpImm<
2893 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
2894 "cmn", ".w\t$Rn, $imm",
2895 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]> {
2896 let Inst{31-27} = 0b11110;
2898 let Inst{24-21} = 0b1000;
2899 let Inst{20} = 1; // The S bit.
2901 let Inst{11-8} = 0b1111; // Rd
2904 def t2CMNzrr : T2TwoRegCmp<
2905 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
2906 "cmn", ".w\t$Rn, $Rm",
2907 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2908 GPRnopc:$Rn, rGPR:$Rm)]> {
2909 let Inst{31-27} = 0b11101;
2910 let Inst{26-25} = 0b01;
2911 let Inst{24-21} = 0b1000;
2912 let Inst{20} = 1; // The S bit.
2913 let Inst{14-12} = 0b000; // imm3
2914 let Inst{11-8} = 0b1111; // Rd
2915 let Inst{7-6} = 0b00; // imm2
2916 let Inst{5-4} = 0b00; // type
2919 def t2CMNzrs : T2OneRegCmpShiftedReg<
2920 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
2921 "cmn", ".w\t$Rn, $ShiftedRm",
2922 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2923 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
2924 let Inst{31-27} = 0b11101;
2925 let Inst{26-25} = 0b01;
2926 let Inst{24-21} = 0b1000;
2927 let Inst{20} = 1; // The S bit.
2928 let Inst{11-8} = 0b1111; // Rd
2932 // Assembler aliases w/o the ".w" suffix.
2933 // No alias here for 'rr' version as not all instantiations of this multiclass
2934 // want one (CMP in particular, does not).
2935 def : t2InstAlias<!strconcat("cmn", "${p}", " $Rn, $imm"),
2936 (!cast<Instruction>(!strconcat("t2CMN", "ri")) GPRnopc:$Rn,
2937 t2_so_imm:$imm, pred:$p)>;
2938 def : t2InstAlias<!strconcat("cmn", "${p}", " $Rn, $shift"),
2939 (!cast<Instruction>(!strconcat("t2CMNz", "rs")) GPRnopc:$Rn,
2943 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2944 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2946 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2947 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2949 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2950 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2951 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2953 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2954 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2955 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2958 // Conditional moves
2959 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2960 // a two-value operand where a dag node expects two operands. :(
2961 let neverHasSideEffects = 1 in {
2963 let isCommutable = 1 in
2964 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2965 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2967 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2968 RegConstraint<"$false = $Rd">;
2970 let isMoveImm = 1 in
2971 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2972 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2974 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2975 RegConstraint<"$false = $Rd">;
2977 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2978 let isCodeGenOnly = 1 in {
2979 let isMoveImm = 1 in
2980 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2982 "movw", "\t$Rd, $imm", []>,
2983 RegConstraint<"$false = $Rd"> {
2984 let Inst{31-27} = 0b11110;
2986 let Inst{24-21} = 0b0010;
2987 let Inst{20} = 0; // The S bit.
2993 let Inst{11-8} = Rd;
2994 let Inst{19-16} = imm{15-12};
2995 let Inst{26} = imm{11};
2996 let Inst{14-12} = imm{10-8};
2997 let Inst{7-0} = imm{7-0};
3000 let isMoveImm = 1 in
3001 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
3002 (ins rGPR:$false, i32imm:$src, pred:$p),
3003 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
3005 let isMoveImm = 1 in
3006 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
3007 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
3008 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
3009 imm:$cc, CCR:$ccr))*/]>,
3010 RegConstraint<"$false = $Rd"> {
3011 let Inst{31-27} = 0b11110;
3013 let Inst{24-21} = 0b0011;
3014 let Inst{20} = 0; // The S bit.
3015 let Inst{19-16} = 0b1111; // Rn
3019 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
3020 string opc, string asm, list<dag> pattern>
3021 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
3022 let Inst{31-27} = 0b11101;
3023 let Inst{26-25} = 0b01;
3024 let Inst{24-21} = 0b0010;
3025 let Inst{20} = 0; // The S bit.
3026 let Inst{19-16} = 0b1111; // Rn
3027 let Inst{5-4} = opcod; // Shift type.
3029 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
3030 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3031 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
3032 RegConstraint<"$false = $Rd">;
3033 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
3034 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3035 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
3036 RegConstraint<"$false = $Rd">;
3037 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
3038 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3039 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
3040 RegConstraint<"$false = $Rd">;
3041 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
3042 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3043 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
3044 RegConstraint<"$false = $Rd">;
3045 } // isCodeGenOnly = 1
3047 multiclass T2I_bincc_irs<Instruction iri, Instruction irr, Instruction irs,
3048 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
3050 def ri : t2PseudoExpand<(outs rGPR:$Rd),
3051 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s),
3053 (iri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
3054 RegConstraint<"$Rn = $Rd">;
3056 def rr : t2PseudoExpand<(outs rGPR:$Rd),
3057 (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s),
3059 (irr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
3060 RegConstraint<"$Rn = $Rd">;
3062 def rs : t2PseudoExpand<(outs rGPR:$Rd),
3063 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s),
3065 (irs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>,
3066 RegConstraint<"$Rn = $Rd">;
3069 defm t2ANDCC : T2I_bincc_irs<t2ANDri, t2ANDrr, t2ANDrs,
3070 IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
3071 defm t2ORRCC : T2I_bincc_irs<t2ORRri, t2ORRrr, t2ORRrs,
3072 IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
3073 defm t2EORCC : T2I_bincc_irs<t2EORri, t2EORrr, t2EORrs,
3074 IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
3075 } // neverHasSideEffects
3077 //===----------------------------------------------------------------------===//
3078 // Atomic operations intrinsics
3081 // memory barriers protect the atomic sequences
3082 let hasSideEffects = 1 in {
3083 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3084 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3085 Requires<[IsThumb, HasDB]> {
3087 let Inst{31-4} = 0xf3bf8f5;
3088 let Inst{3-0} = opt;
3092 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3093 "dsb", "\t$opt", []>,
3094 Requires<[IsThumb, HasDB]> {
3096 let Inst{31-4} = 0xf3bf8f4;
3097 let Inst{3-0} = opt;
3100 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3102 []>, Requires<[IsThumb, HasDB]> {
3104 let Inst{31-4} = 0xf3bf8f6;
3105 let Inst{3-0} = opt;
3108 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3109 InstrItinClass itin, string opc, string asm, string cstr,
3110 list<dag> pattern, bits<4> rt2 = 0b1111>
3111 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3112 let Inst{31-27} = 0b11101;
3113 let Inst{26-20} = 0b0001101;
3114 let Inst{11-8} = rt2;
3115 let Inst{7-6} = 0b01;
3116 let Inst{5-4} = opcod;
3117 let Inst{3-0} = 0b1111;
3121 let Inst{19-16} = addr;
3122 let Inst{15-12} = Rt;
3124 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3125 InstrItinClass itin, string opc, string asm, string cstr,
3126 list<dag> pattern, bits<4> rt2 = 0b1111>
3127 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3128 let Inst{31-27} = 0b11101;
3129 let Inst{26-20} = 0b0001100;
3130 let Inst{11-8} = rt2;
3131 let Inst{7-6} = 0b01;
3132 let Inst{5-4} = opcod;
3138 let Inst{19-16} = addr;
3139 let Inst{15-12} = Rt;
3142 let mayLoad = 1 in {
3143 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3144 AddrModeNone, 4, NoItinerary,
3145 "ldrexb", "\t$Rt, $addr", "", []>;
3146 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3147 AddrModeNone, 4, NoItinerary,
3148 "ldrexh", "\t$Rt, $addr", "", []>;
3149 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3150 AddrModeNone, 4, NoItinerary,
3151 "ldrex", "\t$Rt, $addr", "", []> {
3154 let Inst{31-27} = 0b11101;
3155 let Inst{26-20} = 0b0000101;
3156 let Inst{19-16} = addr{11-8};
3157 let Inst{15-12} = Rt;
3158 let Inst{11-8} = 0b1111;
3159 let Inst{7-0} = addr{7-0};
3161 let hasExtraDefRegAllocReq = 1 in
3162 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3163 (ins addr_offset_none:$addr),
3164 AddrModeNone, 4, NoItinerary,
3165 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3168 let Inst{11-8} = Rt2;
3172 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3173 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3174 (ins rGPR:$Rt, addr_offset_none:$addr),
3175 AddrModeNone, 4, NoItinerary,
3176 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3177 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3178 (ins rGPR:$Rt, addr_offset_none:$addr),
3179 AddrModeNone, 4, NoItinerary,
3180 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3181 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3182 t2addrmode_imm0_1020s4:$addr),
3183 AddrModeNone, 4, NoItinerary,
3184 "strex", "\t$Rd, $Rt, $addr", "",
3189 let Inst{31-27} = 0b11101;
3190 let Inst{26-20} = 0b0000100;
3191 let Inst{19-16} = addr{11-8};
3192 let Inst{15-12} = Rt;
3193 let Inst{11-8} = Rd;
3194 let Inst{7-0} = addr{7-0};
3196 let hasExtraSrcRegAllocReq = 1 in
3197 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3198 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3199 AddrModeNone, 4, NoItinerary,
3200 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3203 let Inst{11-8} = Rt2;
3207 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3208 Requires<[IsThumb2, HasV7]> {
3209 let Inst{31-16} = 0xf3bf;
3210 let Inst{15-14} = 0b10;
3213 let Inst{11-8} = 0b1111;
3214 let Inst{7-4} = 0b0010;
3215 let Inst{3-0} = 0b1111;
3218 //===----------------------------------------------------------------------===//
3219 // SJLJ Exception handling intrinsics
3220 // eh_sjlj_setjmp() is an instruction sequence to store the return
3221 // address and save #0 in R0 for the non-longjmp case.
3222 // Since by its nature we may be coming from some other function to get
3223 // here, and we're using the stack frame for the containing function to
3224 // save/restore registers, we can't keep anything live in regs across
3225 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3226 // when we get here from a longjmp(). We force everything out of registers
3227 // except for our own input by listing the relevant registers in Defs. By
3228 // doing so, we also cause the prologue/epilogue code to actively preserve
3229 // all of the callee-saved resgisters, which is exactly what we want.
3230 // $val is a scratch register for our use.
3232 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3233 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3234 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3235 usesCustomInserter = 1 in {
3236 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3237 AddrModeNone, 0, NoItinerary, "", "",
3238 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3239 Requires<[IsThumb2, HasVFP2]>;
3243 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3244 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3245 usesCustomInserter = 1 in {
3246 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3247 AddrModeNone, 0, NoItinerary, "", "",
3248 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3249 Requires<[IsThumb2, NoVFP]>;
3253 //===----------------------------------------------------------------------===//
3254 // Control-Flow Instructions
3257 // FIXME: remove when we have a way to marking a MI with these properties.
3258 // FIXME: Should pc be an implicit operand like PICADD, etc?
3259 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3260 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3261 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3262 reglist:$regs, variable_ops),
3263 4, IIC_iLoad_mBr, [],
3264 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3265 RegConstraint<"$Rn = $wb">;
3267 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3268 let isPredicable = 1 in
3269 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3271 [(br bb:$target)]> {
3272 let Inst{31-27} = 0b11110;
3273 let Inst{15-14} = 0b10;
3277 let Inst{26} = target{19};
3278 let Inst{11} = target{18};
3279 let Inst{13} = target{17};
3280 let Inst{21-16} = target{16-11};
3281 let Inst{10-0} = target{10-0};
3282 let DecoderMethod = "DecodeT2BInstruction";
3285 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3286 def t2BR_JT : t2PseudoInst<(outs),
3287 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3289 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3291 // FIXME: Add a non-pc based case that can be predicated.
3292 def t2TBB_JT : t2PseudoInst<(outs),
3293 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3295 def t2TBH_JT : t2PseudoInst<(outs),
3296 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3298 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3299 "tbb", "\t$addr", []> {
3302 let Inst{31-20} = 0b111010001101;
3303 let Inst{19-16} = Rn;
3304 let Inst{15-5} = 0b11110000000;
3305 let Inst{4} = 0; // B form
3308 let DecoderMethod = "DecodeThumbTableBranch";
3311 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3312 "tbh", "\t$addr", []> {
3315 let Inst{31-20} = 0b111010001101;
3316 let Inst{19-16} = Rn;
3317 let Inst{15-5} = 0b11110000000;
3318 let Inst{4} = 1; // H form
3321 let DecoderMethod = "DecodeThumbTableBranch";
3323 } // isNotDuplicable, isIndirectBranch
3325 } // isBranch, isTerminator, isBarrier
3327 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3328 // a two-value operand where a dag node expects ", "two operands. :(
3329 let isBranch = 1, isTerminator = 1 in
3330 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3332 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3333 let Inst{31-27} = 0b11110;
3334 let Inst{15-14} = 0b10;
3338 let Inst{25-22} = p;
3341 let Inst{26} = target{20};
3342 let Inst{11} = target{19};
3343 let Inst{13} = target{18};
3344 let Inst{21-16} = target{17-12};
3345 let Inst{10-0} = target{11-1};
3347 let DecoderMethod = "DecodeThumb2BCCInstruction";
3350 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3352 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3355 def tTAILJMPd: tPseudoExpand<(outs),
3356 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3358 (t2B uncondbrtarget:$dst, pred:$p)>,
3359 Requires<[IsThumb2, IsIOS]>;
3362 let isCall = 1, Defs = [LR], Uses = [SP] in {
3363 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
3364 // return stack predictor.
3365 def t2BMOVPCB_CALL : tPseudoInst<(outs),
3366 (ins t_bltarget:$func, variable_ops),
3367 6, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
3368 Requires<[IsThumb]>;
3372 def : T2Pat<(ARMcall_nolink texternalsym:$func),
3373 (t2BMOVPCB_CALL texternalsym:$func)>,
3374 Requires<[IsThumb]>;
3377 let Defs = [ITSTATE] in
3378 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3379 AddrModeNone, 2, IIC_iALUx,
3380 "it$mask\t$cc", "", []> {
3381 // 16-bit instruction.
3382 let Inst{31-16} = 0x0000;
3383 let Inst{15-8} = 0b10111111;
3388 let Inst{3-0} = mask;
3390 let DecoderMethod = "DecodeIT";
3393 // Branch and Exchange Jazelle -- for disassembly only
3395 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3397 let Inst{31-27} = 0b11110;
3399 let Inst{25-20} = 0b111100;
3400 let Inst{19-16} = func;
3401 let Inst{15-0} = 0b1000111100000000;
3404 // Compare and branch on zero / non-zero
3405 let isBranch = 1, isTerminator = 1 in {
3406 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3407 "cbz\t$Rn, $target", []>,
3408 T1Misc<{0,0,?,1,?,?,?}>,
3409 Requires<[IsThumb2]> {
3413 let Inst{9} = target{5};
3414 let Inst{7-3} = target{4-0};
3418 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3419 "cbnz\t$Rn, $target", []>,
3420 T1Misc<{1,0,?,1,?,?,?}>,
3421 Requires<[IsThumb2]> {
3425 let Inst{9} = target{5};
3426 let Inst{7-3} = target{4-0};
3432 // Change Processor State is a system instruction.
3433 // FIXME: Since the asm parser has currently no clean way to handle optional
3434 // operands, create 3 versions of the same instruction. Once there's a clean
3435 // framework to represent optional operands, change this behavior.
3436 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3437 !strconcat("cps", asm_op), []> {
3443 let Inst{31-27} = 0b11110;
3445 let Inst{25-20} = 0b111010;
3446 let Inst{19-16} = 0b1111;
3447 let Inst{15-14} = 0b10;
3449 let Inst{10-9} = imod;
3451 let Inst{7-5} = iflags;
3452 let Inst{4-0} = mode;
3453 let DecoderMethod = "DecodeT2CPSInstruction";
3457 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3458 "$imod.w\t$iflags, $mode">;
3459 let mode = 0, M = 0 in
3460 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3461 "$imod.w\t$iflags">;
3462 let imod = 0, iflags = 0, M = 1 in
3463 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3465 // A6.3.4 Branches and miscellaneous control
3466 // Table A6-14 Change Processor State, and hint instructions
3467 def t2HINT : T2I<(outs), (ins imm0_255:$imm), NoItinerary, "hint", "\t$imm",[]>{
3469 let Inst{31-8} = 0b111100111010111110000000;
3470 let Inst{7-0} = imm;
3473 def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_255:$imm, pred:$p)>;
3474 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3475 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3476 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3477 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3478 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3480 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3482 let Inst{31-20} = 0b111100111010;
3483 let Inst{19-16} = 0b1111;
3484 let Inst{15-8} = 0b10000000;
3485 let Inst{7-4} = 0b1111;
3486 let Inst{3-0} = opt;
3489 // Secure Monitor Call is a system instruction.
3490 // Option = Inst{19-16}
3491 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3492 let Inst{31-27} = 0b11110;
3493 let Inst{26-20} = 0b1111111;
3494 let Inst{15-12} = 0b1000;
3497 let Inst{19-16} = opt;
3500 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3501 string opc, string asm, list<dag> pattern>
3502 : T2I<oops, iops, itin, opc, asm, pattern> {
3504 let Inst{31-25} = 0b1110100;
3505 let Inst{24-23} = Op;
3508 let Inst{20-16} = 0b01101;
3509 let Inst{15-5} = 0b11000000000;
3510 let Inst{4-0} = mode{4-0};
3513 // Store Return State is a system instruction.
3514 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3515 "srsdb", "\tsp!, $mode", []>;
3516 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3517 "srsdb","\tsp, $mode", []>;
3518 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3519 "srsia","\tsp!, $mode", []>;
3520 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3521 "srsia","\tsp, $mode", []>;
3523 // Return From Exception is a system instruction.
3524 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3525 string opc, string asm, list<dag> pattern>
3526 : T2I<oops, iops, itin, opc, asm, pattern> {
3527 let Inst{31-20} = op31_20{11-0};
3530 let Inst{19-16} = Rn;
3531 let Inst{15-0} = 0xc000;
3534 def t2RFEDBW : T2RFE<0b111010000011,
3535 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3536 [/* For disassembly only; pattern left blank */]>;
3537 def t2RFEDB : T2RFE<0b111010000001,
3538 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3539 [/* For disassembly only; pattern left blank */]>;
3540 def t2RFEIAW : T2RFE<0b111010011011,
3541 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3542 [/* For disassembly only; pattern left blank */]>;
3543 def t2RFEIA : T2RFE<0b111010011001,
3544 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3545 [/* For disassembly only; pattern left blank */]>;
3547 //===----------------------------------------------------------------------===//
3548 // Non-Instruction Patterns
3551 // 32-bit immediate using movw + movt.
3552 // This is a single pseudo instruction to make it re-materializable.
3553 // FIXME: Remove this when we can do generalized remat.
3554 let isReMaterializable = 1, isMoveImm = 1 in
3555 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3556 [(set rGPR:$dst, (i32 imm:$src))]>,
3557 Requires<[IsThumb, HasV6T2]>;
3559 // Pseudo instruction that combines movw + movt + add pc (if pic).
3560 // It also makes it possible to rematerialize the instructions.
3561 // FIXME: Remove this when we can do generalized remat and when machine licm
3562 // can properly the instructions.
3563 let isReMaterializable = 1 in {
3564 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3566 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3567 Requires<[IsThumb2, UseMovt]>;
3569 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3571 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3572 Requires<[IsThumb2, UseMovt]>;
3575 // ConstantPool, GlobalAddress, and JumpTable
3576 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3577 Requires<[IsThumb2, DontUseMovt]>;
3578 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3579 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3580 Requires<[IsThumb2, UseMovt]>;
3582 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3583 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3585 // Pseudo instruction that combines ldr from constpool and add pc. This should
3586 // be expanded into two instructions late to allow if-conversion and
3588 let canFoldAsLoad = 1, isReMaterializable = 1 in
3589 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3591 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3593 Requires<[IsThumb2]>;
3595 // Pseudo isntruction that combines movs + predicated rsbmi
3596 // to implement integer ABS
3597 let usesCustomInserter = 1, Defs = [CPSR] in {
3598 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3599 NoItinerary, []>, Requires<[IsThumb2]>;
3602 //===----------------------------------------------------------------------===//
3603 // Coprocessor load/store -- for disassembly only
3605 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3606 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3607 let Inst{31-28} = op31_28;
3608 let Inst{27-25} = 0b110;
3611 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3612 def _OFFSET : T2CI<op31_28,
3613 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3614 asm, "\t$cop, $CRd, $addr"> {
3618 let Inst{24} = 1; // P = 1
3619 let Inst{23} = addr{8};
3620 let Inst{22} = Dbit;
3621 let Inst{21} = 0; // W = 0
3622 let Inst{20} = load;
3623 let Inst{19-16} = addr{12-9};
3624 let Inst{15-12} = CRd;
3625 let Inst{11-8} = cop;
3626 let Inst{7-0} = addr{7-0};
3627 let DecoderMethod = "DecodeCopMemInstruction";
3629 def _PRE : T2CI<op31_28,
3630 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3631 asm, "\t$cop, $CRd, $addr!"> {
3635 let Inst{24} = 1; // P = 1
3636 let Inst{23} = addr{8};
3637 let Inst{22} = Dbit;
3638 let Inst{21} = 1; // W = 1
3639 let Inst{20} = load;
3640 let Inst{19-16} = addr{12-9};
3641 let Inst{15-12} = CRd;
3642 let Inst{11-8} = cop;
3643 let Inst{7-0} = addr{7-0};
3644 let DecoderMethod = "DecodeCopMemInstruction";
3646 def _POST: T2CI<op31_28,
3647 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3648 postidx_imm8s4:$offset),
3649 asm, "\t$cop, $CRd, $addr, $offset"> {
3654 let Inst{24} = 0; // P = 0
3655 let Inst{23} = offset{8};
3656 let Inst{22} = Dbit;
3657 let Inst{21} = 1; // W = 1
3658 let Inst{20} = load;
3659 let Inst{19-16} = addr;
3660 let Inst{15-12} = CRd;
3661 let Inst{11-8} = cop;
3662 let Inst{7-0} = offset{7-0};
3663 let DecoderMethod = "DecodeCopMemInstruction";
3665 def _OPTION : T2CI<op31_28, (outs),
3666 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3667 coproc_option_imm:$option),
3668 asm, "\t$cop, $CRd, $addr, $option"> {
3673 let Inst{24} = 0; // P = 0
3674 let Inst{23} = 1; // U = 1
3675 let Inst{22} = Dbit;
3676 let Inst{21} = 0; // W = 0
3677 let Inst{20} = load;
3678 let Inst{19-16} = addr;
3679 let Inst{15-12} = CRd;
3680 let Inst{11-8} = cop;
3681 let Inst{7-0} = option;
3682 let DecoderMethod = "DecodeCopMemInstruction";
3686 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3687 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3688 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3689 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3690 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3691 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3692 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3693 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3696 //===----------------------------------------------------------------------===//
3697 // Move between special register and ARM core register -- for disassembly only
3699 // Move to ARM core register from Special Register
3703 // A/R class can only move from CPSR or SPSR.
3704 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3705 []>, Requires<[IsThumb2,IsARClass]> {
3707 let Inst{31-12} = 0b11110011111011111000;
3708 let Inst{11-8} = Rd;
3709 let Inst{7-0} = 0b0000;
3712 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3714 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3715 []>, Requires<[IsThumb2,IsARClass]> {
3717 let Inst{31-12} = 0b11110011111111111000;
3718 let Inst{11-8} = Rd;
3719 let Inst{7-0} = 0b0000;
3724 // This MRS has a mask field in bits 7-0 and can take more values than
3725 // the A/R class (a full msr_mask).
3726 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3727 "mrs", "\t$Rd, $mask", []>,
3728 Requires<[IsThumb,IsMClass]> {
3731 let Inst{31-12} = 0b11110011111011111000;
3732 let Inst{11-8} = Rd;
3733 let Inst{19-16} = 0b1111;
3734 let Inst{7-0} = mask;
3738 // Move from ARM core register to Special Register
3742 // No need to have both system and application versions, the encodings are the
3743 // same and the assembly parser has no way to distinguish between them. The mask
3744 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3745 // the mask with the fields to be accessed in the special register.
3746 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3747 NoItinerary, "msr", "\t$mask, $Rn", []>,
3748 Requires<[IsThumb2,IsARClass]> {
3751 let Inst{31-21} = 0b11110011100;
3752 let Inst{20} = mask{4}; // R Bit
3753 let Inst{19-16} = Rn;
3754 let Inst{15-12} = 0b1000;
3755 let Inst{11-8} = mask{3-0};
3761 // Move from ARM core register to Special Register
3762 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3763 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3764 Requires<[IsThumb,IsMClass]> {
3767 let Inst{31-21} = 0b11110011100;
3769 let Inst{19-16} = Rn;
3770 let Inst{15-12} = 0b1000;
3771 let Inst{11-0} = SYSm;
3775 //===----------------------------------------------------------------------===//
3776 // Move between coprocessor and ARM core register
3779 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3781 : T2Cop<Op, oops, iops,
3782 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3784 let Inst{27-24} = 0b1110;
3785 let Inst{20} = direction;
3795 let Inst{15-12} = Rt;
3796 let Inst{11-8} = cop;
3797 let Inst{23-21} = opc1;
3798 let Inst{7-5} = opc2;
3799 let Inst{3-0} = CRm;
3800 let Inst{19-16} = CRn;
3803 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3804 list<dag> pattern = []>
3806 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3807 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3808 let Inst{27-24} = 0b1100;
3809 let Inst{23-21} = 0b010;
3810 let Inst{20} = direction;
3818 let Inst{15-12} = Rt;
3819 let Inst{19-16} = Rt2;
3820 let Inst{11-8} = cop;
3821 let Inst{7-4} = opc1;
3822 let Inst{3-0} = CRm;
3825 /* from ARM core register to coprocessor */
3826 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3828 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3829 c_imm:$CRm, imm0_7:$opc2),
3830 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3831 imm:$CRm, imm:$opc2)]>;
3832 def : t2InstAlias<"mcr $cop, $opc1, $Rt, $CRn, $CRm",
3833 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3835 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3836 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3837 c_imm:$CRm, imm0_7:$opc2),
3838 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3839 imm:$CRm, imm:$opc2)]>;
3840 def : t2InstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
3841 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3844 /* from coprocessor to ARM core register */
3845 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3846 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3847 c_imm:$CRm, imm0_7:$opc2), []>;
3848 def : t2InstAlias<"mrc $cop, $opc1, $Rt, $CRn, $CRm",
3849 (t2MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3852 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3853 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3854 c_imm:$CRm, imm0_7:$opc2), []>;
3855 def : t2InstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
3856 (t2MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3859 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3860 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3862 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3863 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3866 /* from ARM core register to coprocessor */
3867 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3868 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3870 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3871 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3872 GPR:$Rt2, imm:$CRm)]>;
3873 /* from coprocessor to ARM core register */
3874 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3876 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3878 //===----------------------------------------------------------------------===//
3879 // Other Coprocessor Instructions.
3882 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3883 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3884 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3885 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3886 imm:$CRm, imm:$opc2)]> {
3887 let Inst{27-24} = 0b1110;
3896 let Inst{3-0} = CRm;
3898 let Inst{7-5} = opc2;
3899 let Inst{11-8} = cop;
3900 let Inst{15-12} = CRd;
3901 let Inst{19-16} = CRn;
3902 let Inst{23-20} = opc1;
3905 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3906 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3907 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3908 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3909 imm:$CRm, imm:$opc2)]> {
3910 let Inst{27-24} = 0b1110;
3919 let Inst{3-0} = CRm;
3921 let Inst{7-5} = opc2;
3922 let Inst{11-8} = cop;
3923 let Inst{15-12} = CRd;
3924 let Inst{19-16} = CRn;
3925 let Inst{23-20} = opc1;
3930 //===----------------------------------------------------------------------===//
3931 // Non-Instruction Patterns
3934 // SXT/UXT with no rotate
3935 let AddedComplexity = 16 in {
3936 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3937 Requires<[IsThumb2]>;
3938 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3939 Requires<[IsThumb2]>;
3940 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3941 Requires<[HasT2ExtractPack, IsThumb2]>;
3942 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3943 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3944 Requires<[HasT2ExtractPack, IsThumb2]>;
3945 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3946 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3947 Requires<[HasT2ExtractPack, IsThumb2]>;
3950 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3951 Requires<[IsThumb2]>;
3952 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3953 Requires<[IsThumb2]>;
3954 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3955 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3956 Requires<[HasT2ExtractPack, IsThumb2]>;
3957 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3958 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3959 Requires<[HasT2ExtractPack, IsThumb2]>;
3961 // Atomic load/store patterns
3962 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3963 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3964 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3965 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3966 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3967 (t2LDRBs t2addrmode_so_reg:$addr)>;
3968 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3969 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3970 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3971 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3972 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3973 (t2LDRHs t2addrmode_so_reg:$addr)>;
3974 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3975 (t2LDRi12 t2addrmode_imm12:$addr)>;
3976 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3977 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3978 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3979 (t2LDRs t2addrmode_so_reg:$addr)>;
3980 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3981 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3982 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3983 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3984 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3985 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3986 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3987 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3988 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3989 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3990 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3991 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3992 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3993 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3994 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3995 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3996 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3997 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4000 //===----------------------------------------------------------------------===//
4001 // Assembler aliases
4004 // Aliases for ADC without the ".w" optional width specifier.
4005 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4006 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4007 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4008 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4009 pred:$p, cc_out:$s)>;
4011 // Aliases for SBC without the ".w" optional width specifier.
4012 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4013 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4014 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4015 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4016 pred:$p, cc_out:$s)>;
4018 // Aliases for ADD without the ".w" optional width specifier.
4019 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4020 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4021 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4022 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4023 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4024 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4025 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4026 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4027 pred:$p, cc_out:$s)>;
4028 // ... and with the destination and source register combined.
4029 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4030 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4031 def : t2InstAlias<"add${p} $Rdn, $imm",
4032 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4033 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4034 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4035 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4036 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4037 pred:$p, cc_out:$s)>;
4039 // add w/ negative immediates is just a sub.
4040 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4041 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4043 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4044 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4045 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4046 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4048 def : t2InstAlias<"add${p} $Rdn, $imm",
4049 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4051 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4052 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4054 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4055 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4056 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4057 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4059 def : t2InstAlias<"addw${p} $Rdn, $imm",
4060 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4063 // Aliases for SUB without the ".w" optional width specifier.
4064 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4065 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4066 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4067 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4068 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4069 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4070 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4071 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4072 pred:$p, cc_out:$s)>;
4073 // ... and with the destination and source register combined.
4074 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4075 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4076 def : t2InstAlias<"sub${p} $Rdn, $imm",
4077 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4078 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4079 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4080 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4081 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4082 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4083 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4084 pred:$p, cc_out:$s)>;
4086 // Alias for compares without the ".w" optional width specifier.
4087 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4088 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4089 def : t2InstAlias<"teq${p} $Rn, $Rm",
4090 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4091 def : t2InstAlias<"tst${p} $Rn, $Rm",
4092 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4095 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>;
4096 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>;
4097 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>;
4099 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4101 def : t2InstAlias<"ldr${p} $Rt, $addr",
4102 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4103 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4104 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4105 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4106 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4107 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4108 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4109 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4110 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4112 def : t2InstAlias<"ldr${p} $Rt, $addr",
4113 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4114 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4115 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4116 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4117 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4118 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4119 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4120 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4121 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4123 def : t2InstAlias<"ldr${p} $Rt, $addr",
4124 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4125 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4126 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4127 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4128 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4129 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4130 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4131 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4132 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4134 // Alias for MVN with(out) the ".w" optional width specifier.
4135 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4136 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4137 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4138 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4139 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4140 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4142 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4143 // shift amount is zero (i.e., unspecified).
4144 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4145 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4146 Requires<[HasT2ExtractPack, IsThumb2]>;
4147 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4148 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4149 Requires<[HasT2ExtractPack, IsThumb2]>;
4151 // PUSH/POP aliases for STM/LDM
4152 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4153 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4154 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4155 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4157 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4158 def : t2InstAlias<"stm${p} $Rn, $regs",
4159 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4160 def : t2InstAlias<"stm${p} $Rn!, $regs",
4161 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4163 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4164 def : t2InstAlias<"ldm${p} $Rn, $regs",
4165 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4166 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4167 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4169 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4170 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4171 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4172 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4173 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4175 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4176 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4177 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4178 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4179 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4181 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4182 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4183 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4184 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4187 // Alias for RSB without the ".w" optional width specifier, and with optional
4188 // implied destination register.
4189 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4190 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4191 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4192 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4193 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4194 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4195 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4196 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4199 // SSAT/USAT optional shift operand.
4200 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4201 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4202 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4203 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4205 // STM w/o the .w suffix.
4206 def : t2InstAlias<"stm${p} $Rn, $regs",
4207 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4209 // Alias for STR, STRB, and STRH without the ".w" optional
4211 def : t2InstAlias<"str${p} $Rt, $addr",
4212 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4213 def : t2InstAlias<"strb${p} $Rt, $addr",
4214 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4215 def : t2InstAlias<"strh${p} $Rt, $addr",
4216 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4218 def : t2InstAlias<"str${p} $Rt, $addr",
4219 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4220 def : t2InstAlias<"strb${p} $Rt, $addr",
4221 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4222 def : t2InstAlias<"strh${p} $Rt, $addr",
4223 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4225 // Extend instruction optional rotate operand.
4226 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4227 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4228 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4229 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4230 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4231 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4233 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4234 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4235 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4236 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4237 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4238 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4239 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4240 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4241 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4242 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4244 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4245 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4246 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4247 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4248 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4249 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4250 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4251 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4252 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4253 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4254 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4255 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4257 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4258 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4259 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4260 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4262 // Extend instruction w/o the ".w" optional width specifier.
4263 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4264 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4265 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4266 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4267 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4268 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4270 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4271 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4272 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4273 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4274 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4275 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4278 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4280 def : t2InstAlias<"mov${p} $Rd, $imm",
4281 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4282 def : t2InstAlias<"mvn${p} $Rd, $imm",
4283 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4284 // Same for AND <--> BIC
4285 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4286 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4287 pred:$p, cc_out:$s)>;
4288 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4289 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4290 pred:$p, cc_out:$s)>;
4291 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4292 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4293 pred:$p, cc_out:$s)>;
4294 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4295 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4296 pred:$p, cc_out:$s)>;
4297 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4298 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4299 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4300 pred:$p, cc_out:$s)>;
4301 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4302 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4303 pred:$p, cc_out:$s)>;
4304 // Same for CMP <--> CMN via t2_so_imm_neg
4305 def : t2InstAlias<"cmp${p} $Rd, $imm",
4306 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4307 def : t2InstAlias<"cmn${p} $Rd, $imm",
4308 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4311 // Wide 'mul' encoding can be specified with only two operands.
4312 def : t2InstAlias<"mul${p} $Rn, $Rm",
4313 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4315 // "neg" is and alias for "rsb rd, rn, #0"
4316 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4317 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4319 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4320 // these, unfortunately.
4321 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4322 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4323 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4324 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4326 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4327 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4328 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4329 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4331 // ADR w/o the .w suffix
4332 def : t2InstAlias<"adr${p} $Rd, $addr",
4333 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4335 // LDR(literal) w/ alternate [pc, #imm] syntax.
4336 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4337 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4338 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4339 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4340 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4341 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4342 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4343 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4344 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4345 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4346 // Version w/ the .w suffix.
4347 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4348 (t2LDRpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4349 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4350 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4351 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4352 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4353 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4354 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4355 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4356 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4358 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4359 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;