1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // t2_so_imm - Match a 32-bit immediate operand, which is an
66 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
67 // immediate splatted into multiple bytes of the word.
68 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
69 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
70 return ARM_AM::getT2SOImmVal(Imm) != -1;
72 let ParserMatchClass = t2_so_imm_asmoperand;
73 let EncoderMethod = "getT2SOImmOpValue";
74 let DecoderMethod = "DecodeT2SOImm";
77 // t2_so_imm_not - Match an immediate that is a complement
79 // Note: this pattern doesn't require an encoder method and such, as it's
80 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
81 // is handled by the destination instructions, which use t2_so_imm.
82 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
83 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
84 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
85 }], t2_so_imm_not_XFORM> {
86 let ParserMatchClass = t2_so_imm_not_asmoperand;
89 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
90 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
91 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
92 int64_t Value = -(int)N->getZExtValue();
93 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
94 }], t2_so_imm_neg_XFORM> {
95 let ParserMatchClass = t2_so_imm_neg_asmoperand;
98 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
99 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
100 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
101 return Imm >= 0 && Imm < 4096;
103 let ParserMatchClass = imm0_4095_asmoperand;
106 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
107 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
108 return (uint32_t)(-N->getZExtValue()) < 4096;
110 let ParserMatchClass = imm0_4095_neg_asmoperand;
113 def imm0_255_neg : PatLeaf<(i32 imm), [{
114 return (uint32_t)(-N->getZExtValue()) < 255;
117 def imm0_255_not : PatLeaf<(i32 imm), [{
118 return (uint32_t)(~N->getZExtValue()) < 255;
121 def lo5AllOne : PatLeaf<(i32 imm), [{
122 // Returns true if all low 5-bits are 1.
123 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
126 // Define Thumb2 specific addressing modes.
128 // t2addrmode_imm12 := reg + imm12
129 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
130 def t2addrmode_imm12 : Operand<i32>,
131 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
132 let PrintMethod = "printAddrModeImm12Operand";
133 let EncoderMethod = "getAddrModeImm12OpValue";
134 let DecoderMethod = "DecodeT2AddrModeImm12";
135 let ParserMatchClass = t2addrmode_imm12_asmoperand;
136 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
139 // t2ldrlabel := imm12
140 def t2ldrlabel : Operand<i32> {
141 let EncoderMethod = "getAddrModeImm12OpValue";
142 let PrintMethod = "printT2LdrLabelOperand";
145 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
146 def t2ldr_pcrel_imm12 : Operand<i32> {
147 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
148 // used for assembler pseudo instruction and maps to t2ldrlabel, so
149 // doesn't need encoder or print methods of its own.
152 // ADR instruction labels.
153 def t2adrlabel : Operand<i32> {
154 let EncoderMethod = "getT2AdrLabelOpValue";
158 // t2addrmode_posimm8 := reg + imm8
159 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
160 def t2addrmode_posimm8 : Operand<i32> {
161 let PrintMethod = "printT2AddrModeImm8Operand";
162 let EncoderMethod = "getT2AddrModeImm8OpValue";
163 let DecoderMethod = "DecodeT2AddrModeImm8";
164 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
165 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
168 // t2addrmode_negimm8 := reg - imm8
169 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
170 def t2addrmode_negimm8 : Operand<i32>,
171 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
172 let PrintMethod = "printT2AddrModeImm8Operand";
173 let EncoderMethod = "getT2AddrModeImm8OpValue";
174 let DecoderMethod = "DecodeT2AddrModeImm8";
175 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
176 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
179 // t2addrmode_imm8 := reg +/- imm8
180 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
181 def t2addrmode_imm8 : Operand<i32>,
182 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
183 let PrintMethod = "printT2AddrModeImm8Operand";
184 let EncoderMethod = "getT2AddrModeImm8OpValue";
185 let DecoderMethod = "DecodeT2AddrModeImm8";
186 let ParserMatchClass = MemImm8OffsetAsmOperand;
187 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
190 def t2am_imm8_offset : Operand<i32>,
191 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
192 [], [SDNPWantRoot]> {
193 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
194 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
195 let DecoderMethod = "DecodeT2Imm8";
198 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
199 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
200 def t2addrmode_imm8s4 : Operand<i32> {
201 let PrintMethod = "printT2AddrModeImm8s4Operand";
202 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
203 let DecoderMethod = "DecodeT2AddrModeImm8s4";
204 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
205 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
208 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
209 def t2am_imm8s4_offset : Operand<i32> {
210 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
211 let EncoderMethod = "getT2Imm8s4OpValue";
212 let DecoderMethod = "DecodeT2Imm8S4";
215 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
216 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
217 let Name = "MemImm0_1020s4Offset";
219 def t2addrmode_imm0_1020s4 : Operand<i32> {
220 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
221 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
222 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
223 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
224 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
227 // t2addrmode_so_reg := reg + (reg << imm2)
228 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
229 def t2addrmode_so_reg : Operand<i32>,
230 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
231 let PrintMethod = "printT2AddrModeSoRegOperand";
232 let EncoderMethod = "getT2AddrModeSORegOpValue";
233 let DecoderMethod = "DecodeT2AddrModeSOReg";
234 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
235 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
238 // Addresses for the TBB/TBH instructions.
239 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
240 def addrmode_tbb : Operand<i32> {
241 let PrintMethod = "printAddrModeTBB";
242 let ParserMatchClass = addrmode_tbb_asmoperand;
243 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
245 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
246 def addrmode_tbh : Operand<i32> {
247 let PrintMethod = "printAddrModeTBH";
248 let ParserMatchClass = addrmode_tbh_asmoperand;
249 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
252 //===----------------------------------------------------------------------===//
253 // Multiclass helpers...
257 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
258 string opc, string asm, list<dag> pattern>
259 : T2I<oops, iops, itin, opc, asm, pattern> {
264 let Inst{26} = imm{11};
265 let Inst{14-12} = imm{10-8};
266 let Inst{7-0} = imm{7-0};
270 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
271 string opc, string asm, list<dag> pattern>
272 : T2sI<oops, iops, itin, opc, asm, pattern> {
278 let Inst{26} = imm{11};
279 let Inst{14-12} = imm{10-8};
280 let Inst{7-0} = imm{7-0};
283 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
284 string opc, string asm, list<dag> pattern>
285 : T2I<oops, iops, itin, opc, asm, pattern> {
289 let Inst{19-16} = Rn;
290 let Inst{26} = imm{11};
291 let Inst{14-12} = imm{10-8};
292 let Inst{7-0} = imm{7-0};
296 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
297 string opc, string asm, list<dag> pattern>
298 : T2I<oops, iops, itin, opc, asm, pattern> {
303 let Inst{3-0} = ShiftedRm{3-0};
304 let Inst{5-4} = ShiftedRm{6-5};
305 let Inst{14-12} = ShiftedRm{11-9};
306 let Inst{7-6} = ShiftedRm{8-7};
309 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
310 string opc, string asm, list<dag> pattern>
311 : T2sI<oops, iops, itin, opc, asm, pattern> {
316 let Inst{3-0} = ShiftedRm{3-0};
317 let Inst{5-4} = ShiftedRm{6-5};
318 let Inst{14-12} = ShiftedRm{11-9};
319 let Inst{7-6} = ShiftedRm{8-7};
322 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
323 string opc, string asm, list<dag> pattern>
324 : T2I<oops, iops, itin, opc, asm, pattern> {
328 let Inst{19-16} = Rn;
329 let Inst{3-0} = ShiftedRm{3-0};
330 let Inst{5-4} = ShiftedRm{6-5};
331 let Inst{14-12} = ShiftedRm{11-9};
332 let Inst{7-6} = ShiftedRm{8-7};
335 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
336 string opc, string asm, list<dag> pattern>
337 : T2I<oops, iops, itin, opc, asm, pattern> {
345 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
346 string opc, string asm, list<dag> pattern>
347 : T2sI<oops, iops, itin, opc, asm, pattern> {
355 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
356 string opc, string asm, list<dag> pattern>
357 : T2I<oops, iops, itin, opc, asm, pattern> {
361 let Inst{19-16} = Rn;
366 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
367 string opc, string asm, list<dag> pattern>
368 : T2I<oops, iops, itin, opc, asm, pattern> {
374 let Inst{19-16} = Rn;
375 let Inst{26} = imm{11};
376 let Inst{14-12} = imm{10-8};
377 let Inst{7-0} = imm{7-0};
380 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
381 string opc, string asm, list<dag> pattern>
382 : T2sI<oops, iops, itin, opc, asm, pattern> {
388 let Inst{19-16} = Rn;
389 let Inst{26} = imm{11};
390 let Inst{14-12} = imm{10-8};
391 let Inst{7-0} = imm{7-0};
394 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
395 string opc, string asm, list<dag> pattern>
396 : T2I<oops, iops, itin, opc, asm, pattern> {
403 let Inst{14-12} = imm{4-2};
404 let Inst{7-6} = imm{1-0};
407 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
408 string opc, string asm, list<dag> pattern>
409 : T2sI<oops, iops, itin, opc, asm, pattern> {
416 let Inst{14-12} = imm{4-2};
417 let Inst{7-6} = imm{1-0};
420 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
421 string opc, string asm, list<dag> pattern>
422 : T2I<oops, iops, itin, opc, asm, pattern> {
428 let Inst{19-16} = Rn;
432 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
433 string opc, string asm, list<dag> pattern>
434 : T2sI<oops, iops, itin, opc, asm, pattern> {
440 let Inst{19-16} = Rn;
444 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
445 string opc, string asm, list<dag> pattern>
446 : T2I<oops, iops, itin, opc, asm, pattern> {
452 let Inst{19-16} = Rn;
453 let Inst{3-0} = ShiftedRm{3-0};
454 let Inst{5-4} = ShiftedRm{6-5};
455 let Inst{14-12} = ShiftedRm{11-9};
456 let Inst{7-6} = ShiftedRm{8-7};
459 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
460 string opc, string asm, list<dag> pattern>
461 : T2sI<oops, iops, itin, opc, asm, pattern> {
467 let Inst{19-16} = Rn;
468 let Inst{3-0} = ShiftedRm{3-0};
469 let Inst{5-4} = ShiftedRm{6-5};
470 let Inst{14-12} = ShiftedRm{11-9};
471 let Inst{7-6} = ShiftedRm{8-7};
474 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
475 string opc, string asm, list<dag> pattern>
476 : T2I<oops, iops, itin, opc, asm, pattern> {
482 let Inst{19-16} = Rn;
483 let Inst{15-12} = Ra;
488 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
489 dag oops, dag iops, InstrItinClass itin,
490 string opc, string asm, list<dag> pattern>
491 : T2I<oops, iops, itin, opc, asm, pattern> {
497 let Inst{31-23} = 0b111110111;
498 let Inst{22-20} = opc22_20;
499 let Inst{19-16} = Rn;
500 let Inst{15-12} = RdLo;
501 let Inst{11-8} = RdHi;
502 let Inst{7-4} = opc7_4;
507 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
508 /// binary operation that produces a value. These are predicable and can be
509 /// changed to modify CPSR.
510 multiclass T2I_bin_irs<bits<4> opcod, string opc,
511 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
512 PatFrag opnode, string baseOpc, bit Commutable = 0,
515 def ri : T2sTwoRegImm<
516 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
517 opc, "\t$Rd, $Rn, $imm",
518 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
519 let Inst{31-27} = 0b11110;
521 let Inst{24-21} = opcod;
525 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
526 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
527 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
528 let isCommutable = Commutable;
529 let Inst{31-27} = 0b11101;
530 let Inst{26-25} = 0b01;
531 let Inst{24-21} = opcod;
532 let Inst{14-12} = 0b000; // imm3
533 let Inst{7-6} = 0b00; // imm2
534 let Inst{5-4} = 0b00; // type
537 def rs : T2sTwoRegShiftedReg<
538 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
539 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
540 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
541 let Inst{31-27} = 0b11101;
542 let Inst{26-25} = 0b01;
543 let Inst{24-21} = opcod;
545 // Assembly aliases for optional destination operand when it's the same
546 // as the source operand.
547 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
548 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
549 t2_so_imm:$imm, pred:$p,
551 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
552 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
555 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
556 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
557 t2_so_reg:$shift, pred:$p,
561 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
562 // the ".w" suffix to indicate that they are wide.
563 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
564 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
565 PatFrag opnode, string baseOpc, bit Commutable = 0> :
566 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
567 // Assembler aliases w/ the ".w" suffix.
568 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
569 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
570 t2_so_imm:$imm, pred:$p,
572 // Assembler aliases w/o the ".w" suffix.
573 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
574 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
577 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
578 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
579 t2_so_reg:$shift, pred:$p,
582 // and with the optional destination operand, too.
583 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
584 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
585 t2_so_imm:$imm, pred:$p,
587 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
588 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
591 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
592 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
593 t2_so_reg:$shift, pred:$p,
597 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
598 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
599 /// it is equivalent to the T2I_bin_irs counterpart.
600 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
602 def ri : T2sTwoRegImm<
603 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
604 opc, ".w\t$Rd, $Rn, $imm",
605 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
606 let Inst{31-27} = 0b11110;
608 let Inst{24-21} = opcod;
612 def rr : T2sThreeReg<
613 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
614 opc, "\t$Rd, $Rn, $Rm",
615 [/* For disassembly only; pattern left blank */]> {
616 let Inst{31-27} = 0b11101;
617 let Inst{26-25} = 0b01;
618 let Inst{24-21} = opcod;
619 let Inst{14-12} = 0b000; // imm3
620 let Inst{7-6} = 0b00; // imm2
621 let Inst{5-4} = 0b00; // type
624 def rs : T2sTwoRegShiftedReg<
625 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
626 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
627 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
628 let Inst{31-27} = 0b11101;
629 let Inst{26-25} = 0b01;
630 let Inst{24-21} = opcod;
634 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
635 /// instruction modifies the CPSR register.
637 /// These opcodes will be converted to the real non-S opcodes by
638 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
639 let hasPostISelHook = 1, Defs = [CPSR] in {
640 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
641 InstrItinClass iis, PatFrag opnode,
642 bit Commutable = 0> {
644 def ri : t2PseudoInst<(outs rGPR:$Rd),
645 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
647 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
650 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
652 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
654 let isCommutable = Commutable;
657 def rs : t2PseudoInst<(outs rGPR:$Rd),
658 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
660 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
661 t2_so_reg:$ShiftedRm))]>;
665 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
666 /// operands are reversed.
667 let hasPostISelHook = 1, Defs = [CPSR] in {
668 multiclass T2I_rbin_s_is<PatFrag opnode> {
670 def ri : t2PseudoInst<(outs rGPR:$Rd),
671 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
673 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
676 def rs : t2PseudoInst<(outs rGPR:$Rd),
677 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
679 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
684 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
685 /// patterns for a binary operation that produces a value.
686 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
687 bit Commutable = 0> {
689 // The register-immediate version is re-materializable. This is useful
690 // in particular for taking the address of a local.
691 let isReMaterializable = 1 in {
692 def ri : T2sTwoRegImm<
693 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
694 opc, ".w\t$Rd, $Rn, $imm",
695 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
696 let Inst{31-27} = 0b11110;
699 let Inst{23-21} = op23_21;
705 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
706 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
707 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
711 let Inst{31-27} = 0b11110;
712 let Inst{26} = imm{11};
713 let Inst{25-24} = 0b10;
714 let Inst{23-21} = op23_21;
715 let Inst{20} = 0; // The S bit.
716 let Inst{19-16} = Rn;
718 let Inst{14-12} = imm{10-8};
720 let Inst{7-0} = imm{7-0};
723 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
724 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
725 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
726 let isCommutable = Commutable;
727 let Inst{31-27} = 0b11101;
728 let Inst{26-25} = 0b01;
730 let Inst{23-21} = op23_21;
731 let Inst{14-12} = 0b000; // imm3
732 let Inst{7-6} = 0b00; // imm2
733 let Inst{5-4} = 0b00; // type
736 def rs : T2sTwoRegShiftedReg<
737 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
738 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
739 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
740 let Inst{31-27} = 0b11101;
741 let Inst{26-25} = 0b01;
743 let Inst{23-21} = op23_21;
747 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
748 /// for a binary operation that produces a value and use the carry
749 /// bit. It's not predicable.
750 let Defs = [CPSR], Uses = [CPSR] in {
751 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
752 bit Commutable = 0> {
754 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
755 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
756 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
757 Requires<[IsThumb2]> {
758 let Inst{31-27} = 0b11110;
760 let Inst{24-21} = opcod;
764 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
765 opc, ".w\t$Rd, $Rn, $Rm",
766 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
767 Requires<[IsThumb2]> {
768 let isCommutable = Commutable;
769 let Inst{31-27} = 0b11101;
770 let Inst{26-25} = 0b01;
771 let Inst{24-21} = opcod;
772 let Inst{14-12} = 0b000; // imm3
773 let Inst{7-6} = 0b00; // imm2
774 let Inst{5-4} = 0b00; // type
777 def rs : T2sTwoRegShiftedReg<
778 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
779 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
780 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
781 Requires<[IsThumb2]> {
782 let Inst{31-27} = 0b11101;
783 let Inst{26-25} = 0b01;
784 let Inst{24-21} = opcod;
789 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
790 // rotate operation that produces a value.
791 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
794 def ri : T2sTwoRegShiftImm<
795 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
796 opc, ".w\t$Rd, $Rm, $imm",
797 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
798 let Inst{31-27} = 0b11101;
799 let Inst{26-21} = 0b010010;
800 let Inst{19-16} = 0b1111; // Rn
801 let Inst{5-4} = opcod;
804 def rr : T2sThreeReg<
805 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
806 opc, ".w\t$Rd, $Rn, $Rm",
807 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
808 let Inst{31-27} = 0b11111;
809 let Inst{26-23} = 0b0100;
810 let Inst{22-21} = opcod;
811 let Inst{15-12} = 0b1111;
812 let Inst{7-4} = 0b0000;
815 // Optional destination register
816 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
817 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
820 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
821 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
825 // Assembler aliases w/o the ".w" suffix.
826 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
827 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
830 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
831 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
835 // and with the optional destination operand, too.
836 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
837 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
840 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
841 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
846 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
847 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
848 /// a explicit result, only implicitly set CPSR.
849 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
850 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
851 PatFrag opnode, string baseOpc> {
852 let isCompare = 1, Defs = [CPSR] in {
854 def ri : T2OneRegCmpImm<
855 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
856 opc, ".w\t$Rn, $imm",
857 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
858 let Inst{31-27} = 0b11110;
860 let Inst{24-21} = opcod;
861 let Inst{20} = 1; // The S bit.
863 let Inst{11-8} = 0b1111; // Rd
866 def rr : T2TwoRegCmp<
867 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
869 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
870 let Inst{31-27} = 0b11101;
871 let Inst{26-25} = 0b01;
872 let Inst{24-21} = opcod;
873 let Inst{20} = 1; // The S bit.
874 let Inst{14-12} = 0b000; // imm3
875 let Inst{11-8} = 0b1111; // Rd
876 let Inst{7-6} = 0b00; // imm2
877 let Inst{5-4} = 0b00; // type
880 def rs : T2OneRegCmpShiftedReg<
881 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
882 opc, ".w\t$Rn, $ShiftedRm",
883 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
884 let Inst{31-27} = 0b11101;
885 let Inst{26-25} = 0b01;
886 let Inst{24-21} = opcod;
887 let Inst{20} = 1; // The S bit.
888 let Inst{11-8} = 0b1111; // Rd
892 // Assembler aliases w/o the ".w" suffix.
893 // No alias here for 'rr' version as not all instantiations of this
894 // multiclass want one (CMP in particular, does not).
895 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
896 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
897 t2_so_imm:$imm, pred:$p)>;
898 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
899 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
904 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
905 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
906 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
908 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
909 opc, ".w\t$Rt, $addr",
910 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
913 let Inst{31-25} = 0b1111100;
914 let Inst{24} = signed;
916 let Inst{22-21} = opcod;
917 let Inst{20} = 1; // load
918 let Inst{19-16} = addr{16-13}; // Rn
919 let Inst{15-12} = Rt;
920 let Inst{11-0} = addr{11-0}; // imm
922 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
924 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
927 let Inst{31-27} = 0b11111;
928 let Inst{26-25} = 0b00;
929 let Inst{24} = signed;
931 let Inst{22-21} = opcod;
932 let Inst{20} = 1; // load
933 let Inst{19-16} = addr{12-9}; // Rn
934 let Inst{15-12} = Rt;
936 // Offset: index==TRUE, wback==FALSE
937 let Inst{10} = 1; // The P bit.
938 let Inst{9} = addr{8}; // U
939 let Inst{8} = 0; // The W bit.
940 let Inst{7-0} = addr{7-0}; // imm
942 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
943 opc, ".w\t$Rt, $addr",
944 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
945 let Inst{31-27} = 0b11111;
946 let Inst{26-25} = 0b00;
947 let Inst{24} = signed;
949 let Inst{22-21} = opcod;
950 let Inst{20} = 1; // load
951 let Inst{11-6} = 0b000000;
954 let Inst{15-12} = Rt;
957 let Inst{19-16} = addr{9-6}; // Rn
958 let Inst{3-0} = addr{5-2}; // Rm
959 let Inst{5-4} = addr{1-0}; // imm
961 let DecoderMethod = "DecodeT2LoadShift";
964 // pci variant is very similar to i12, but supports negative offsets
966 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
967 opc, ".w\t$Rt, $addr",
968 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
969 let isReMaterializable = 1;
970 let Inst{31-27} = 0b11111;
971 let Inst{26-25} = 0b00;
972 let Inst{24} = signed;
973 let Inst{23} = ?; // add = (U == '1')
974 let Inst{22-21} = opcod;
975 let Inst{20} = 1; // load
976 let Inst{19-16} = 0b1111; // Rn
979 let Inst{15-12} = Rt{3-0};
980 let Inst{11-0} = addr{11-0};
984 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
985 multiclass T2I_st<bits<2> opcod, string opc,
986 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
988 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
989 opc, ".w\t$Rt, $addr",
990 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
991 let Inst{31-27} = 0b11111;
992 let Inst{26-23} = 0b0001;
993 let Inst{22-21} = opcod;
994 let Inst{20} = 0; // !load
997 let Inst{15-12} = Rt;
1000 let addr{12} = 1; // add = TRUE
1001 let Inst{19-16} = addr{16-13}; // Rn
1002 let Inst{23} = addr{12}; // U
1003 let Inst{11-0} = addr{11-0}; // imm
1005 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1006 opc, "\t$Rt, $addr",
1007 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1008 let Inst{31-27} = 0b11111;
1009 let Inst{26-23} = 0b0000;
1010 let Inst{22-21} = opcod;
1011 let Inst{20} = 0; // !load
1013 // Offset: index==TRUE, wback==FALSE
1014 let Inst{10} = 1; // The P bit.
1015 let Inst{8} = 0; // The W bit.
1018 let Inst{15-12} = Rt;
1021 let Inst{19-16} = addr{12-9}; // Rn
1022 let Inst{9} = addr{8}; // U
1023 let Inst{7-0} = addr{7-0}; // imm
1025 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1026 opc, ".w\t$Rt, $addr",
1027 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1028 let Inst{31-27} = 0b11111;
1029 let Inst{26-23} = 0b0000;
1030 let Inst{22-21} = opcod;
1031 let Inst{20} = 0; // !load
1032 let Inst{11-6} = 0b000000;
1035 let Inst{15-12} = Rt;
1038 let Inst{19-16} = addr{9-6}; // Rn
1039 let Inst{3-0} = addr{5-2}; // Rm
1040 let Inst{5-4} = addr{1-0}; // imm
1044 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1045 /// register and one whose operand is a register rotated by 8/16/24.
1046 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1047 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1048 opc, ".w\t$Rd, $Rm$rot",
1049 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1050 Requires<[IsThumb2]> {
1051 let Inst{31-27} = 0b11111;
1052 let Inst{26-23} = 0b0100;
1053 let Inst{22-20} = opcod;
1054 let Inst{19-16} = 0b1111; // Rn
1055 let Inst{15-12} = 0b1111;
1059 let Inst{5-4} = rot{1-0}; // rotate
1062 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1063 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1064 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1065 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1066 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1067 Requires<[HasT2ExtractPack, IsThumb2]> {
1069 let Inst{31-27} = 0b11111;
1070 let Inst{26-23} = 0b0100;
1071 let Inst{22-20} = opcod;
1072 let Inst{19-16} = 0b1111; // Rn
1073 let Inst{15-12} = 0b1111;
1075 let Inst{5-4} = rot;
1078 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1080 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1081 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1082 opc, "\t$Rd, $Rm$rot", []>,
1083 Requires<[IsThumb2, HasT2ExtractPack]> {
1085 let Inst{31-27} = 0b11111;
1086 let Inst{26-23} = 0b0100;
1087 let Inst{22-20} = opcod;
1088 let Inst{19-16} = 0b1111; // Rn
1089 let Inst{15-12} = 0b1111;
1091 let Inst{5-4} = rot;
1094 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1095 /// register and one whose operand is a register rotated by 8/16/24.
1096 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1097 : T2ThreeReg<(outs rGPR:$Rd),
1098 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1099 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1100 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1101 Requires<[HasT2ExtractPack, IsThumb2]> {
1103 let Inst{31-27} = 0b11111;
1104 let Inst{26-23} = 0b0100;
1105 let Inst{22-20} = opcod;
1106 let Inst{15-12} = 0b1111;
1108 let Inst{5-4} = rot;
1111 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1112 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1113 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1115 let Inst{31-27} = 0b11111;
1116 let Inst{26-23} = 0b0100;
1117 let Inst{22-20} = opcod;
1118 let Inst{15-12} = 0b1111;
1120 let Inst{5-4} = rot;
1123 //===----------------------------------------------------------------------===//
1125 //===----------------------------------------------------------------------===//
1127 //===----------------------------------------------------------------------===//
1128 // Miscellaneous Instructions.
1131 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1132 string asm, list<dag> pattern>
1133 : T2XI<oops, iops, itin, asm, pattern> {
1137 let Inst{11-8} = Rd;
1138 let Inst{26} = label{11};
1139 let Inst{14-12} = label{10-8};
1140 let Inst{7-0} = label{7-0};
1143 // LEApcrel - Load a pc-relative address into a register without offending the
1145 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1146 (ins t2adrlabel:$addr, pred:$p),
1147 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1148 let Inst{31-27} = 0b11110;
1149 let Inst{25-24} = 0b10;
1150 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1153 let Inst{19-16} = 0b1111; // Rn
1158 let Inst{11-8} = Rd;
1159 let Inst{23} = addr{12};
1160 let Inst{21} = addr{12};
1161 let Inst{26} = addr{11};
1162 let Inst{14-12} = addr{10-8};
1163 let Inst{7-0} = addr{7-0};
1165 let DecoderMethod = "DecodeT2Adr";
1168 let neverHasSideEffects = 1, isReMaterializable = 1 in
1169 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1171 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1172 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1177 //===----------------------------------------------------------------------===//
1178 // Load / store Instructions.
1182 let canFoldAsLoad = 1, isReMaterializable = 1 in
1183 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1184 UnOpFrag<(load node:$Src)>>;
1186 // Loads with zero extension
1187 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1188 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1189 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1190 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1192 // Loads with sign extension
1193 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1194 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1195 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1196 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1198 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1200 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1201 (ins t2addrmode_imm8s4:$addr),
1202 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1203 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1205 // zextload i1 -> zextload i8
1206 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1207 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1208 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1209 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1210 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1211 (t2LDRBs t2addrmode_so_reg:$addr)>;
1212 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1213 (t2LDRBpci tconstpool:$addr)>;
1215 // extload -> zextload
1216 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1218 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1219 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1220 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1221 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1222 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1223 (t2LDRBs t2addrmode_so_reg:$addr)>;
1224 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1225 (t2LDRBpci tconstpool:$addr)>;
1227 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1228 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1229 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1230 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1231 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1232 (t2LDRBs t2addrmode_so_reg:$addr)>;
1233 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1234 (t2LDRBpci tconstpool:$addr)>;
1236 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1237 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1238 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1239 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1240 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1241 (t2LDRHs t2addrmode_so_reg:$addr)>;
1242 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1243 (t2LDRHpci tconstpool:$addr)>;
1245 // FIXME: The destination register of the loads and stores can't be PC, but
1246 // can be SP. We need another regclass (similar to rGPR) to represent
1247 // that. Not a pressing issue since these are selected manually,
1252 let mayLoad = 1, neverHasSideEffects = 1 in {
1253 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1254 (ins t2addrmode_imm8:$addr),
1255 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1256 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1258 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1261 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1262 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1263 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1264 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1266 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1267 (ins t2addrmode_imm8:$addr),
1268 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1269 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1271 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1273 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1274 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1275 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1276 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1278 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1279 (ins t2addrmode_imm8:$addr),
1280 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1281 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1283 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1285 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1286 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1287 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1288 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1290 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1291 (ins t2addrmode_imm8:$addr),
1292 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1293 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1295 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1297 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1298 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1299 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1300 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1302 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1303 (ins t2addrmode_imm8:$addr),
1304 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1305 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1307 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1309 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1310 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1311 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1312 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1313 } // mayLoad = 1, neverHasSideEffects = 1
1315 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1316 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1317 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1318 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1319 "\t$Rt, $addr", []> {
1322 let Inst{31-27} = 0b11111;
1323 let Inst{26-25} = 0b00;
1324 let Inst{24} = signed;
1326 let Inst{22-21} = type;
1327 let Inst{20} = 1; // load
1328 let Inst{19-16} = addr{12-9};
1329 let Inst{15-12} = Rt;
1331 let Inst{10-8} = 0b110; // PUW.
1332 let Inst{7-0} = addr{7-0};
1335 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1336 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1337 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1338 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1339 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1342 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1343 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1344 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1345 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1346 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1347 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1350 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1351 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1352 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1353 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1357 let mayStore = 1, neverHasSideEffects = 1 in {
1358 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1359 (ins GPRnopc:$Rt, t2addrmode_imm8:$addr),
1360 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1361 "str", "\t$Rt, $addr!",
1362 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1363 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1365 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1366 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1367 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1368 "strh", "\t$Rt, $addr!",
1369 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1370 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1373 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1374 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1375 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1376 "strb", "\t$Rt, $addr!",
1377 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1378 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1380 } // mayStore = 1, neverHasSideEffects = 1
1382 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1383 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1384 t2am_imm8_offset:$offset),
1385 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1386 "str", "\t$Rt, $Rn$offset",
1387 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1388 [(set GPRnopc:$Rn_wb,
1389 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1390 t2am_imm8_offset:$offset))]>;
1392 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1393 (ins rGPR:$Rt, addr_offset_none:$Rn,
1394 t2am_imm8_offset:$offset),
1395 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1396 "strh", "\t$Rt, $Rn$offset",
1397 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1398 [(set GPRnopc:$Rn_wb,
1399 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1400 t2am_imm8_offset:$offset))]>;
1402 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1403 (ins rGPR:$Rt, addr_offset_none:$Rn,
1404 t2am_imm8_offset:$offset),
1405 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1406 "strb", "\t$Rt, $Rn$offset",
1407 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1408 [(set GPRnopc:$Rn_wb,
1409 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1410 t2am_imm8_offset:$offset))]>;
1412 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1413 // put the patterns on the instruction definitions directly as ISel wants
1414 // the address base and offset to be separate operands, not a single
1415 // complex operand like we represent the instructions themselves. The
1416 // pseudos map between the two.
1417 let usesCustomInserter = 1,
1418 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1419 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1420 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1422 [(set GPRnopc:$Rn_wb,
1423 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1424 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1425 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1427 [(set GPRnopc:$Rn_wb,
1428 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1429 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1430 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1432 [(set GPRnopc:$Rn_wb,
1433 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1436 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1438 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1439 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1440 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1441 "\t$Rt, $addr", []> {
1442 let Inst{31-27} = 0b11111;
1443 let Inst{26-25} = 0b00;
1444 let Inst{24} = 0; // not signed
1446 let Inst{22-21} = type;
1447 let Inst{20} = 0; // store
1449 let Inst{10-8} = 0b110; // PUW
1453 let Inst{15-12} = Rt;
1454 let Inst{19-16} = addr{12-9};
1455 let Inst{7-0} = addr{7-0};
1458 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1459 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1460 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1462 // ldrd / strd pre / post variants
1463 // For disassembly only.
1465 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1466 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1467 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1468 let AsmMatchConverter = "cvtT2LdrdPre";
1469 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1472 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1473 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1474 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1475 "$addr.base = $wb", []>;
1477 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1478 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1479 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1480 "$addr.base = $wb", []> {
1481 let AsmMatchConverter = "cvtT2StrdPre";
1482 let DecoderMethod = "DecodeT2STRDPreInstruction";
1485 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1486 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1487 t2am_imm8s4_offset:$imm),
1488 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1489 "$addr.base = $wb", []>;
1491 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1492 // data/instruction access.
1493 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1494 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1495 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1497 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1499 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1500 let Inst{31-25} = 0b1111100;
1501 let Inst{24} = instr;
1503 let Inst{21} = write;
1505 let Inst{15-12} = 0b1111;
1508 let addr{12} = 1; // add = TRUE
1509 let Inst{19-16} = addr{16-13}; // Rn
1510 let Inst{23} = addr{12}; // U
1511 let Inst{11-0} = addr{11-0}; // imm12
1514 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1516 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1517 let Inst{31-25} = 0b1111100;
1518 let Inst{24} = instr;
1519 let Inst{23} = 0; // U = 0
1521 let Inst{21} = write;
1523 let Inst{15-12} = 0b1111;
1524 let Inst{11-8} = 0b1100;
1527 let Inst{19-16} = addr{12-9}; // Rn
1528 let Inst{7-0} = addr{7-0}; // imm8
1531 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1533 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1534 let Inst{31-25} = 0b1111100;
1535 let Inst{24} = instr;
1536 let Inst{23} = 0; // add = TRUE for T1
1538 let Inst{21} = write;
1540 let Inst{15-12} = 0b1111;
1541 let Inst{11-6} = 0000000;
1544 let Inst{19-16} = addr{9-6}; // Rn
1545 let Inst{3-0} = addr{5-2}; // Rm
1546 let Inst{5-4} = addr{1-0}; // imm2
1548 let DecoderMethod = "DecodeT2LoadShift";
1550 // FIXME: We should have a separate 'pci' variant here. As-is we represent
1551 // it via the i12 variant, which it's related to, but that means we can
1552 // represent negative immediates, which aren't legal for anything except
1553 // the 'pci' case (Rn == 15).
1556 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1557 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1558 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1560 //===----------------------------------------------------------------------===//
1561 // Load / store multiple Instructions.
1564 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1565 InstrItinClass itin_upd, bit L_bit> {
1567 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1568 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1572 let Inst{31-27} = 0b11101;
1573 let Inst{26-25} = 0b00;
1574 let Inst{24-23} = 0b01; // Increment After
1576 let Inst{21} = 0; // No writeback
1577 let Inst{20} = L_bit;
1578 let Inst{19-16} = Rn;
1579 let Inst{15-0} = regs;
1582 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1583 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1587 let Inst{31-27} = 0b11101;
1588 let Inst{26-25} = 0b00;
1589 let Inst{24-23} = 0b01; // Increment After
1591 let Inst{21} = 1; // Writeback
1592 let Inst{20} = L_bit;
1593 let Inst{19-16} = Rn;
1594 let Inst{15-0} = regs;
1597 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1598 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1602 let Inst{31-27} = 0b11101;
1603 let Inst{26-25} = 0b00;
1604 let Inst{24-23} = 0b10; // Decrement Before
1606 let Inst{21} = 0; // No writeback
1607 let Inst{20} = L_bit;
1608 let Inst{19-16} = Rn;
1609 let Inst{15-0} = regs;
1612 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1613 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1617 let Inst{31-27} = 0b11101;
1618 let Inst{26-25} = 0b00;
1619 let Inst{24-23} = 0b10; // Decrement Before
1621 let Inst{21} = 1; // Writeback
1622 let Inst{20} = L_bit;
1623 let Inst{19-16} = Rn;
1624 let Inst{15-0} = regs;
1628 let neverHasSideEffects = 1 in {
1630 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1631 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1633 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1634 InstrItinClass itin_upd, bit L_bit> {
1636 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1637 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1641 let Inst{31-27} = 0b11101;
1642 let Inst{26-25} = 0b00;
1643 let Inst{24-23} = 0b01; // Increment After
1645 let Inst{21} = 0; // No writeback
1646 let Inst{20} = L_bit;
1647 let Inst{19-16} = Rn;
1649 let Inst{14} = regs{14};
1651 let Inst{12-0} = regs{12-0};
1654 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1655 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1659 let Inst{31-27} = 0b11101;
1660 let Inst{26-25} = 0b00;
1661 let Inst{24-23} = 0b01; // Increment After
1663 let Inst{21} = 1; // Writeback
1664 let Inst{20} = L_bit;
1665 let Inst{19-16} = Rn;
1667 let Inst{14} = regs{14};
1669 let Inst{12-0} = regs{12-0};
1672 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1673 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1677 let Inst{31-27} = 0b11101;
1678 let Inst{26-25} = 0b00;
1679 let Inst{24-23} = 0b10; // Decrement Before
1681 let Inst{21} = 0; // No writeback
1682 let Inst{20} = L_bit;
1683 let Inst{19-16} = Rn;
1685 let Inst{14} = regs{14};
1687 let Inst{12-0} = regs{12-0};
1690 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1691 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1695 let Inst{31-27} = 0b11101;
1696 let Inst{26-25} = 0b00;
1697 let Inst{24-23} = 0b10; // Decrement Before
1699 let Inst{21} = 1; // Writeback
1700 let Inst{20} = L_bit;
1701 let Inst{19-16} = Rn;
1703 let Inst{14} = regs{14};
1705 let Inst{12-0} = regs{12-0};
1710 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1711 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1713 } // neverHasSideEffects
1716 //===----------------------------------------------------------------------===//
1717 // Move Instructions.
1720 let neverHasSideEffects = 1 in
1721 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1722 "mov", ".w\t$Rd, $Rm", []> {
1723 let Inst{31-27} = 0b11101;
1724 let Inst{26-25} = 0b01;
1725 let Inst{24-21} = 0b0010;
1726 let Inst{19-16} = 0b1111; // Rn
1727 let Inst{14-12} = 0b000;
1728 let Inst{7-4} = 0b0000;
1730 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1731 pred:$p, zero_reg)>;
1732 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1734 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1737 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1738 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1739 AddedComplexity = 1 in
1740 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1741 "mov", ".w\t$Rd, $imm",
1742 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1743 let Inst{31-27} = 0b11110;
1745 let Inst{24-21} = 0b0010;
1746 let Inst{19-16} = 0b1111; // Rn
1750 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1751 // Use aliases to get that to play nice here.
1752 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1754 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1757 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1758 pred:$p, zero_reg)>;
1759 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1760 pred:$p, zero_reg)>;
1762 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1763 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1764 "movw", "\t$Rd, $imm",
1765 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1766 let Inst{31-27} = 0b11110;
1768 let Inst{24-21} = 0b0010;
1769 let Inst{20} = 0; // The S bit.
1775 let Inst{11-8} = Rd;
1776 let Inst{19-16} = imm{15-12};
1777 let Inst{26} = imm{11};
1778 let Inst{14-12} = imm{10-8};
1779 let Inst{7-0} = imm{7-0};
1780 let DecoderMethod = "DecodeT2MOVTWInstruction";
1783 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1784 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1786 let Constraints = "$src = $Rd" in {
1787 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1788 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1789 "movt", "\t$Rd, $imm",
1791 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1792 let Inst{31-27} = 0b11110;
1794 let Inst{24-21} = 0b0110;
1795 let Inst{20} = 0; // The S bit.
1801 let Inst{11-8} = Rd;
1802 let Inst{19-16} = imm{15-12};
1803 let Inst{26} = imm{11};
1804 let Inst{14-12} = imm{10-8};
1805 let Inst{7-0} = imm{7-0};
1806 let DecoderMethod = "DecodeT2MOVTWInstruction";
1809 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1810 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1813 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1815 //===----------------------------------------------------------------------===//
1816 // Extend Instructions.
1821 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1822 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1823 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1824 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1825 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1827 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1828 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1829 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1830 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1831 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1835 let AddedComplexity = 16 in {
1836 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1837 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1838 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1839 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1840 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1841 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1843 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1844 // The transformation should probably be done as a combiner action
1845 // instead so we can include a check for masking back in the upper
1846 // eight bits of the source into the lower eight bits of the result.
1847 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1848 // (t2UXTB16 rGPR:$Src, 3)>,
1849 // Requires<[HasT2ExtractPack, IsThumb2]>;
1850 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1851 (t2UXTB16 rGPR:$Src, 1)>,
1852 Requires<[HasT2ExtractPack, IsThumb2]>;
1854 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1855 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1856 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1857 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1858 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1861 //===----------------------------------------------------------------------===//
1862 // Arithmetic Instructions.
1865 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1866 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1867 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1868 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1870 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1872 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1873 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1874 // AdjustInstrPostInstrSelection where we determine whether or not to
1875 // set the "s" bit based on CPSR liveness.
1877 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1878 // support for an optional CPSR definition that corresponds to the DAG
1879 // node's second value. We can then eliminate the implicit def of CPSR.
1880 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1881 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1882 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1883 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1885 let hasPostISelHook = 1 in {
1886 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1887 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1888 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1889 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1893 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1894 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1896 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1897 // CPSR and the implicit def of CPSR is not needed.
1898 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1900 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1901 // The assume-no-carry-in form uses the negation of the input since add/sub
1902 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1903 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1905 // The AddedComplexity preferences the first variant over the others since
1906 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1907 let AddedComplexity = 1 in
1908 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1909 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1910 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1911 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1912 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1913 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1914 let AddedComplexity = 1 in
1915 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1916 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1917 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1918 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1919 // The with-carry-in form matches bitwise not instead of the negation.
1920 // Effectively, the inverse interpretation of the carry flag already accounts
1921 // for part of the negation.
1922 let AddedComplexity = 1 in
1923 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1924 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1925 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1926 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1928 // Select Bytes -- for disassembly only
1930 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1931 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1932 Requires<[IsThumb2, HasThumb2DSP]> {
1933 let Inst{31-27} = 0b11111;
1934 let Inst{26-24} = 0b010;
1936 let Inst{22-20} = 0b010;
1937 let Inst{15-12} = 0b1111;
1939 let Inst{6-4} = 0b000;
1942 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1943 // And Miscellaneous operations -- for disassembly only
1944 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1945 list<dag> pat = [/* For disassembly only; pattern left blank */],
1946 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1947 string asm = "\t$Rd, $Rn, $Rm">
1948 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1949 Requires<[IsThumb2, HasThumb2DSP]> {
1950 let Inst{31-27} = 0b11111;
1951 let Inst{26-23} = 0b0101;
1952 let Inst{22-20} = op22_20;
1953 let Inst{15-12} = 0b1111;
1954 let Inst{7-4} = op7_4;
1960 let Inst{11-8} = Rd;
1961 let Inst{19-16} = Rn;
1965 // Saturating add/subtract -- for disassembly only
1967 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1968 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1969 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1970 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1971 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1972 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1973 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1974 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1975 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1976 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1977 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1978 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1979 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1980 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1981 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1982 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1983 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1984 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1985 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1986 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1987 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1988 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1990 // Signed/Unsigned add/subtract -- for disassembly only
1992 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1993 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1994 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1995 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1996 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1997 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1998 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1999 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2000 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2001 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2002 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2003 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2005 // Signed/Unsigned halving add/subtract -- for disassembly only
2007 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2008 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2009 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2010 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2011 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2012 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2013 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2014 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2015 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2016 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2017 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2018 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2020 // Helper class for disassembly only
2021 // A6.3.16 & A6.3.17
2022 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2023 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2024 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2025 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2026 let Inst{31-27} = 0b11111;
2027 let Inst{26-24} = 0b011;
2028 let Inst{23} = long;
2029 let Inst{22-20} = op22_20;
2030 let Inst{7-4} = op7_4;
2033 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2034 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2035 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2036 let Inst{31-27} = 0b11111;
2037 let Inst{26-24} = 0b011;
2038 let Inst{23} = long;
2039 let Inst{22-20} = op22_20;
2040 let Inst{7-4} = op7_4;
2043 // Unsigned Sum of Absolute Differences [and Accumulate].
2044 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2045 (ins rGPR:$Rn, rGPR:$Rm),
2046 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2047 Requires<[IsThumb2, HasThumb2DSP]> {
2048 let Inst{15-12} = 0b1111;
2050 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2051 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2052 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2053 Requires<[IsThumb2, HasThumb2DSP]>;
2055 // Signed/Unsigned saturate.
2056 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2057 string opc, string asm, list<dag> pattern>
2058 : T2I<oops, iops, itin, opc, asm, pattern> {
2064 let Inst{11-8} = Rd;
2065 let Inst{19-16} = Rn;
2066 let Inst{4-0} = sat_imm;
2067 let Inst{21} = sh{5};
2068 let Inst{14-12} = sh{4-2};
2069 let Inst{7-6} = sh{1-0};
2074 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2075 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2076 let Inst{31-27} = 0b11110;
2077 let Inst{25-22} = 0b1100;
2083 def t2SSAT16: T2SatI<
2084 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2085 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2086 Requires<[IsThumb2, HasThumb2DSP]> {
2087 let Inst{31-27} = 0b11110;
2088 let Inst{25-22} = 0b1100;
2091 let Inst{21} = 1; // sh = '1'
2092 let Inst{14-12} = 0b000; // imm3 = '000'
2093 let Inst{7-6} = 0b00; // imm2 = '00'
2094 let Inst{5-4} = 0b00;
2099 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2100 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2101 let Inst{31-27} = 0b11110;
2102 let Inst{25-22} = 0b1110;
2107 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2109 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2110 Requires<[IsThumb2, HasThumb2DSP]> {
2111 let Inst{31-22} = 0b1111001110;
2114 let Inst{21} = 1; // sh = '1'
2115 let Inst{14-12} = 0b000; // imm3 = '000'
2116 let Inst{7-6} = 0b00; // imm2 = '00'
2117 let Inst{5-4} = 0b00;
2120 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2121 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2123 //===----------------------------------------------------------------------===//
2124 // Shift and rotate Instructions.
2127 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2128 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2129 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2130 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2131 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2132 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2133 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2134 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2136 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2137 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2138 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2140 let Uses = [CPSR] in {
2141 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2142 "rrx", "\t$Rd, $Rm",
2143 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2144 let Inst{31-27} = 0b11101;
2145 let Inst{26-25} = 0b01;
2146 let Inst{24-21} = 0b0010;
2147 let Inst{19-16} = 0b1111; // Rn
2148 let Inst{14-12} = 0b000;
2149 let Inst{7-4} = 0b0011;
2153 let isCodeGenOnly = 1, Defs = [CPSR] in {
2154 def t2MOVsrl_flag : T2TwoRegShiftImm<
2155 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2156 "lsrs", ".w\t$Rd, $Rm, #1",
2157 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2158 let Inst{31-27} = 0b11101;
2159 let Inst{26-25} = 0b01;
2160 let Inst{24-21} = 0b0010;
2161 let Inst{20} = 1; // The S bit.
2162 let Inst{19-16} = 0b1111; // Rn
2163 let Inst{5-4} = 0b01; // Shift type.
2164 // Shift amount = Inst{14-12:7-6} = 1.
2165 let Inst{14-12} = 0b000;
2166 let Inst{7-6} = 0b01;
2168 def t2MOVsra_flag : T2TwoRegShiftImm<
2169 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2170 "asrs", ".w\t$Rd, $Rm, #1",
2171 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2172 let Inst{31-27} = 0b11101;
2173 let Inst{26-25} = 0b01;
2174 let Inst{24-21} = 0b0010;
2175 let Inst{20} = 1; // The S bit.
2176 let Inst{19-16} = 0b1111; // Rn
2177 let Inst{5-4} = 0b10; // Shift type.
2178 // Shift amount = Inst{14-12:7-6} = 1.
2179 let Inst{14-12} = 0b000;
2180 let Inst{7-6} = 0b01;
2184 //===----------------------------------------------------------------------===//
2185 // Bitwise Instructions.
2188 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2189 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2190 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2191 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2192 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2193 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2194 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2195 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2196 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2198 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2199 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2200 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2203 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2204 string opc, string asm, list<dag> pattern>
2205 : T2I<oops, iops, itin, opc, asm, pattern> {
2210 let Inst{11-8} = Rd;
2211 let Inst{4-0} = msb{4-0};
2212 let Inst{14-12} = lsb{4-2};
2213 let Inst{7-6} = lsb{1-0};
2216 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2217 string opc, string asm, list<dag> pattern>
2218 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2221 let Inst{19-16} = Rn;
2224 let Constraints = "$src = $Rd" in
2225 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2226 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2227 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2228 let Inst{31-27} = 0b11110;
2229 let Inst{26} = 0; // should be 0.
2231 let Inst{24-20} = 0b10110;
2232 let Inst{19-16} = 0b1111; // Rn
2234 let Inst{5} = 0; // should be 0.
2237 let msb{4-0} = imm{9-5};
2238 let lsb{4-0} = imm{4-0};
2241 def t2SBFX: T2TwoRegBitFI<
2242 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2243 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2244 let Inst{31-27} = 0b11110;
2246 let Inst{24-20} = 0b10100;
2250 def t2UBFX: T2TwoRegBitFI<
2251 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2252 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2253 let Inst{31-27} = 0b11110;
2255 let Inst{24-20} = 0b11100;
2259 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2260 let Constraints = "$src = $Rd" in {
2261 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2262 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2263 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2264 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2265 bf_inv_mask_imm:$imm))]> {
2266 let Inst{31-27} = 0b11110;
2267 let Inst{26} = 0; // should be 0.
2269 let Inst{24-20} = 0b10110;
2271 let Inst{5} = 0; // should be 0.
2274 let msb{4-0} = imm{9-5};
2275 let lsb{4-0} = imm{4-0};
2279 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2280 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2281 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2284 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2285 /// unary operation that produces a value. These are predicable and can be
2286 /// changed to modify CPSR.
2287 multiclass T2I_un_irs<bits<4> opcod, string opc,
2288 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2289 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2291 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2293 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2294 let isAsCheapAsAMove = Cheap;
2295 let isReMaterializable = ReMat;
2296 let Inst{31-27} = 0b11110;
2298 let Inst{24-21} = opcod;
2299 let Inst{19-16} = 0b1111; // Rn
2303 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2304 opc, ".w\t$Rd, $Rm",
2305 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2306 let Inst{31-27} = 0b11101;
2307 let Inst{26-25} = 0b01;
2308 let Inst{24-21} = opcod;
2309 let Inst{19-16} = 0b1111; // Rn
2310 let Inst{14-12} = 0b000; // imm3
2311 let Inst{7-6} = 0b00; // imm2
2312 let Inst{5-4} = 0b00; // type
2315 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2316 opc, ".w\t$Rd, $ShiftedRm",
2317 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2318 let Inst{31-27} = 0b11101;
2319 let Inst{26-25} = 0b01;
2320 let Inst{24-21} = opcod;
2321 let Inst{19-16} = 0b1111; // Rn
2325 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2326 let AddedComplexity = 1 in
2327 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2328 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2329 UnOpFrag<(not node:$Src)>, 1, 1>;
2331 let AddedComplexity = 1 in
2332 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2333 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2335 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2336 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2337 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2338 Requires<[IsThumb2]>;
2340 def : T2Pat<(t2_so_imm_not:$src),
2341 (t2MVNi t2_so_imm_not:$src)>;
2343 //===----------------------------------------------------------------------===//
2344 // Multiply Instructions.
2346 let isCommutable = 1 in
2347 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2348 "mul", "\t$Rd, $Rn, $Rm",
2349 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2350 let Inst{31-27} = 0b11111;
2351 let Inst{26-23} = 0b0110;
2352 let Inst{22-20} = 0b000;
2353 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2354 let Inst{7-4} = 0b0000; // Multiply
2357 def t2MLA: T2FourReg<
2358 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2359 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2360 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2361 let Inst{31-27} = 0b11111;
2362 let Inst{26-23} = 0b0110;
2363 let Inst{22-20} = 0b000;
2364 let Inst{7-4} = 0b0000; // Multiply
2367 def t2MLS: T2FourReg<
2368 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2369 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2370 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2371 let Inst{31-27} = 0b11111;
2372 let Inst{26-23} = 0b0110;
2373 let Inst{22-20} = 0b000;
2374 let Inst{7-4} = 0b0001; // Multiply and Subtract
2377 // Extra precision multiplies with low / high results
2378 let neverHasSideEffects = 1 in {
2379 let isCommutable = 1 in {
2380 def t2SMULL : T2MulLong<0b000, 0b0000,
2381 (outs rGPR:$RdLo, rGPR:$RdHi),
2382 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2383 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2385 def t2UMULL : T2MulLong<0b010, 0b0000,
2386 (outs rGPR:$RdLo, rGPR:$RdHi),
2387 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2388 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2391 // Multiply + accumulate
2392 def t2SMLAL : T2MulLong<0b100, 0b0000,
2393 (outs rGPR:$RdLo, rGPR:$RdHi),
2394 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2395 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2397 def t2UMLAL : T2MulLong<0b110, 0b0000,
2398 (outs rGPR:$RdLo, rGPR:$RdHi),
2399 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2400 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2402 def t2UMAAL : T2MulLong<0b110, 0b0110,
2403 (outs rGPR:$RdLo, rGPR:$RdHi),
2404 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2405 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2406 Requires<[IsThumb2, HasThumb2DSP]>;
2407 } // neverHasSideEffects
2409 // Rounding variants of the below included for disassembly only
2411 // Most significant word multiply
2412 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2413 "smmul", "\t$Rd, $Rn, $Rm",
2414 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2415 Requires<[IsThumb2, HasThumb2DSP]> {
2416 let Inst{31-27} = 0b11111;
2417 let Inst{26-23} = 0b0110;
2418 let Inst{22-20} = 0b101;
2419 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2420 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2423 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2424 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2425 Requires<[IsThumb2, HasThumb2DSP]> {
2426 let Inst{31-27} = 0b11111;
2427 let Inst{26-23} = 0b0110;
2428 let Inst{22-20} = 0b101;
2429 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2430 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2433 def t2SMMLA : T2FourReg<
2434 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2435 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2436 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2437 Requires<[IsThumb2, HasThumb2DSP]> {
2438 let Inst{31-27} = 0b11111;
2439 let Inst{26-23} = 0b0110;
2440 let Inst{22-20} = 0b101;
2441 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2444 def t2SMMLAR: T2FourReg<
2445 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2446 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2447 Requires<[IsThumb2, HasThumb2DSP]> {
2448 let Inst{31-27} = 0b11111;
2449 let Inst{26-23} = 0b0110;
2450 let Inst{22-20} = 0b101;
2451 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2454 def t2SMMLS: T2FourReg<
2455 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2456 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2457 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2458 Requires<[IsThumb2, HasThumb2DSP]> {
2459 let Inst{31-27} = 0b11111;
2460 let Inst{26-23} = 0b0110;
2461 let Inst{22-20} = 0b110;
2462 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2465 def t2SMMLSR:T2FourReg<
2466 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2467 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2468 Requires<[IsThumb2, HasThumb2DSP]> {
2469 let Inst{31-27} = 0b11111;
2470 let Inst{26-23} = 0b0110;
2471 let Inst{22-20} = 0b110;
2472 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2475 multiclass T2I_smul<string opc, PatFrag opnode> {
2476 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2477 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2478 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2479 (sext_inreg rGPR:$Rm, i16)))]>,
2480 Requires<[IsThumb2, HasThumb2DSP]> {
2481 let Inst{31-27} = 0b11111;
2482 let Inst{26-23} = 0b0110;
2483 let Inst{22-20} = 0b001;
2484 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2485 let Inst{7-6} = 0b00;
2486 let Inst{5-4} = 0b00;
2489 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2490 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2491 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2492 (sra rGPR:$Rm, (i32 16))))]>,
2493 Requires<[IsThumb2, HasThumb2DSP]> {
2494 let Inst{31-27} = 0b11111;
2495 let Inst{26-23} = 0b0110;
2496 let Inst{22-20} = 0b001;
2497 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2498 let Inst{7-6} = 0b00;
2499 let Inst{5-4} = 0b01;
2502 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2503 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2504 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2505 (sext_inreg rGPR:$Rm, i16)))]>,
2506 Requires<[IsThumb2, HasThumb2DSP]> {
2507 let Inst{31-27} = 0b11111;
2508 let Inst{26-23} = 0b0110;
2509 let Inst{22-20} = 0b001;
2510 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2511 let Inst{7-6} = 0b00;
2512 let Inst{5-4} = 0b10;
2515 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2516 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2517 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2518 (sra rGPR:$Rm, (i32 16))))]>,
2519 Requires<[IsThumb2, HasThumb2DSP]> {
2520 let Inst{31-27} = 0b11111;
2521 let Inst{26-23} = 0b0110;
2522 let Inst{22-20} = 0b001;
2523 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2524 let Inst{7-6} = 0b00;
2525 let Inst{5-4} = 0b11;
2528 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2529 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2530 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2531 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2532 Requires<[IsThumb2, HasThumb2DSP]> {
2533 let Inst{31-27} = 0b11111;
2534 let Inst{26-23} = 0b0110;
2535 let Inst{22-20} = 0b011;
2536 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2537 let Inst{7-6} = 0b00;
2538 let Inst{5-4} = 0b00;
2541 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2542 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2543 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2544 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2545 Requires<[IsThumb2, HasThumb2DSP]> {
2546 let Inst{31-27} = 0b11111;
2547 let Inst{26-23} = 0b0110;
2548 let Inst{22-20} = 0b011;
2549 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2550 let Inst{7-6} = 0b00;
2551 let Inst{5-4} = 0b01;
2556 multiclass T2I_smla<string opc, PatFrag opnode> {
2558 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2559 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2560 [(set rGPR:$Rd, (add rGPR:$Ra,
2561 (opnode (sext_inreg rGPR:$Rn, i16),
2562 (sext_inreg rGPR:$Rm, i16))))]>,
2563 Requires<[IsThumb2, HasThumb2DSP]> {
2564 let Inst{31-27} = 0b11111;
2565 let Inst{26-23} = 0b0110;
2566 let Inst{22-20} = 0b001;
2567 let Inst{7-6} = 0b00;
2568 let Inst{5-4} = 0b00;
2572 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2573 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2574 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2575 (sra rGPR:$Rm, (i32 16)))))]>,
2576 Requires<[IsThumb2, HasThumb2DSP]> {
2577 let Inst{31-27} = 0b11111;
2578 let Inst{26-23} = 0b0110;
2579 let Inst{22-20} = 0b001;
2580 let Inst{7-6} = 0b00;
2581 let Inst{5-4} = 0b01;
2585 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2586 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2587 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2588 (sext_inreg rGPR:$Rm, i16))))]>,
2589 Requires<[IsThumb2, HasThumb2DSP]> {
2590 let Inst{31-27} = 0b11111;
2591 let Inst{26-23} = 0b0110;
2592 let Inst{22-20} = 0b001;
2593 let Inst{7-6} = 0b00;
2594 let Inst{5-4} = 0b10;
2598 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2599 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2600 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2601 (sra rGPR:$Rm, (i32 16)))))]>,
2602 Requires<[IsThumb2, HasThumb2DSP]> {
2603 let Inst{31-27} = 0b11111;
2604 let Inst{26-23} = 0b0110;
2605 let Inst{22-20} = 0b001;
2606 let Inst{7-6} = 0b00;
2607 let Inst{5-4} = 0b11;
2611 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2612 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2613 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2614 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2615 Requires<[IsThumb2, HasThumb2DSP]> {
2616 let Inst{31-27} = 0b11111;
2617 let Inst{26-23} = 0b0110;
2618 let Inst{22-20} = 0b011;
2619 let Inst{7-6} = 0b00;
2620 let Inst{5-4} = 0b00;
2624 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2625 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2626 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2627 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2628 Requires<[IsThumb2, HasThumb2DSP]> {
2629 let Inst{31-27} = 0b11111;
2630 let Inst{26-23} = 0b0110;
2631 let Inst{22-20} = 0b011;
2632 let Inst{7-6} = 0b00;
2633 let Inst{5-4} = 0b01;
2637 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2638 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2640 // Halfword multiple accumulate long: SMLAL<x><y>
2641 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2642 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2643 [/* For disassembly only; pattern left blank */]>,
2644 Requires<[IsThumb2, HasThumb2DSP]>;
2645 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2646 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2647 [/* For disassembly only; pattern left blank */]>,
2648 Requires<[IsThumb2, HasThumb2DSP]>;
2649 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2650 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2651 [/* For disassembly only; pattern left blank */]>,
2652 Requires<[IsThumb2, HasThumb2DSP]>;
2653 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2654 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2655 [/* For disassembly only; pattern left blank */]>,
2656 Requires<[IsThumb2, HasThumb2DSP]>;
2658 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2659 def t2SMUAD: T2ThreeReg_mac<
2660 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2661 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2662 Requires<[IsThumb2, HasThumb2DSP]> {
2663 let Inst{15-12} = 0b1111;
2665 def t2SMUADX:T2ThreeReg_mac<
2666 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2667 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2668 Requires<[IsThumb2, HasThumb2DSP]> {
2669 let Inst{15-12} = 0b1111;
2671 def t2SMUSD: T2ThreeReg_mac<
2672 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2673 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2674 Requires<[IsThumb2, HasThumb2DSP]> {
2675 let Inst{15-12} = 0b1111;
2677 def t2SMUSDX:T2ThreeReg_mac<
2678 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2679 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2680 Requires<[IsThumb2, HasThumb2DSP]> {
2681 let Inst{15-12} = 0b1111;
2683 def t2SMLAD : T2FourReg_mac<
2684 0, 0b010, 0b0000, (outs rGPR:$Rd),
2685 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2686 "\t$Rd, $Rn, $Rm, $Ra", []>,
2687 Requires<[IsThumb2, HasThumb2DSP]>;
2688 def t2SMLADX : T2FourReg_mac<
2689 0, 0b010, 0b0001, (outs rGPR:$Rd),
2690 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2691 "\t$Rd, $Rn, $Rm, $Ra", []>,
2692 Requires<[IsThumb2, HasThumb2DSP]>;
2693 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2694 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2695 "\t$Rd, $Rn, $Rm, $Ra", []>,
2696 Requires<[IsThumb2, HasThumb2DSP]>;
2697 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2698 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2699 "\t$Rd, $Rn, $Rm, $Ra", []>,
2700 Requires<[IsThumb2, HasThumb2DSP]>;
2701 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2702 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2703 "\t$Ra, $Rd, $Rn, $Rm", []>,
2704 Requires<[IsThumb2, HasThumb2DSP]>;
2705 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2706 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2707 "\t$Ra, $Rd, $Rn, $Rm", []>,
2708 Requires<[IsThumb2, HasThumb2DSP]>;
2709 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2710 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2711 "\t$Ra, $Rd, $Rn, $Rm", []>,
2712 Requires<[IsThumb2, HasThumb2DSP]>;
2713 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2714 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2715 "\t$Ra, $Rd, $Rn, $Rm", []>,
2716 Requires<[IsThumb2, HasThumb2DSP]>;
2718 //===----------------------------------------------------------------------===//
2719 // Division Instructions.
2720 // Signed and unsigned division on v7-M
2722 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2723 "sdiv", "\t$Rd, $Rn, $Rm",
2724 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2725 Requires<[HasDivide, IsThumb2]> {
2726 let Inst{31-27} = 0b11111;
2727 let Inst{26-21} = 0b011100;
2729 let Inst{15-12} = 0b1111;
2730 let Inst{7-4} = 0b1111;
2733 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2734 "udiv", "\t$Rd, $Rn, $Rm",
2735 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2736 Requires<[HasDivide, IsThumb2]> {
2737 let Inst{31-27} = 0b11111;
2738 let Inst{26-21} = 0b011101;
2740 let Inst{15-12} = 0b1111;
2741 let Inst{7-4} = 0b1111;
2744 //===----------------------------------------------------------------------===//
2745 // Misc. Arithmetic Instructions.
2748 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2749 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2750 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2751 let Inst{31-27} = 0b11111;
2752 let Inst{26-22} = 0b01010;
2753 let Inst{21-20} = op1;
2754 let Inst{15-12} = 0b1111;
2755 let Inst{7-6} = 0b10;
2756 let Inst{5-4} = op2;
2760 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2761 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2763 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2764 "rbit", "\t$Rd, $Rm",
2765 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2767 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2768 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2770 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2771 "rev16", ".w\t$Rd, $Rm",
2772 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2774 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2775 "revsh", ".w\t$Rd, $Rm",
2776 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2778 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2779 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2780 (t2REVSH rGPR:$Rm)>;
2782 def t2PKHBT : T2ThreeReg<
2783 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2784 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2785 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2786 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2788 Requires<[HasT2ExtractPack, IsThumb2]> {
2789 let Inst{31-27} = 0b11101;
2790 let Inst{26-25} = 0b01;
2791 let Inst{24-20} = 0b01100;
2792 let Inst{5} = 0; // BT form
2796 let Inst{14-12} = sh{4-2};
2797 let Inst{7-6} = sh{1-0};
2800 // Alternate cases for PKHBT where identities eliminate some nodes.
2801 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2802 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2803 Requires<[HasT2ExtractPack, IsThumb2]>;
2804 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2805 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2806 Requires<[HasT2ExtractPack, IsThumb2]>;
2808 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2809 // will match the pattern below.
2810 def t2PKHTB : T2ThreeReg<
2811 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2812 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2813 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2814 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2816 Requires<[HasT2ExtractPack, IsThumb2]> {
2817 let Inst{31-27} = 0b11101;
2818 let Inst{26-25} = 0b01;
2819 let Inst{24-20} = 0b01100;
2820 let Inst{5} = 1; // TB form
2824 let Inst{14-12} = sh{4-2};
2825 let Inst{7-6} = sh{1-0};
2828 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2829 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2830 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2831 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2832 Requires<[HasT2ExtractPack, IsThumb2]>;
2833 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2834 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2835 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2836 Requires<[HasT2ExtractPack, IsThumb2]>;
2838 //===----------------------------------------------------------------------===//
2839 // Comparison Instructions...
2841 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2842 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2843 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2845 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2846 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2847 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2848 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2849 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2850 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2852 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2853 // Compare-to-zero still works out, just not the relationals
2854 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2855 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2856 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2857 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2858 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2861 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2862 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2864 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2865 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2867 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2868 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2869 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2871 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2872 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2873 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2876 // Conditional moves
2877 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2878 // a two-value operand where a dag node expects two operands. :(
2879 let neverHasSideEffects = 1 in {
2881 let isCommutable = 1 in
2882 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2883 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2885 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2886 RegConstraint<"$false = $Rd">;
2888 let isMoveImm = 1 in
2889 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2890 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2892 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2893 RegConstraint<"$false = $Rd">;
2895 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2896 let isCodeGenOnly = 1 in {
2897 let isMoveImm = 1 in
2898 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2900 "movw", "\t$Rd, $imm", []>,
2901 RegConstraint<"$false = $Rd"> {
2902 let Inst{31-27} = 0b11110;
2904 let Inst{24-21} = 0b0010;
2905 let Inst{20} = 0; // The S bit.
2911 let Inst{11-8} = Rd;
2912 let Inst{19-16} = imm{15-12};
2913 let Inst{26} = imm{11};
2914 let Inst{14-12} = imm{10-8};
2915 let Inst{7-0} = imm{7-0};
2918 let isMoveImm = 1 in
2919 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2920 (ins rGPR:$false, i32imm:$src, pred:$p),
2921 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2923 let isMoveImm = 1 in
2924 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2925 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
2926 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2927 imm:$cc, CCR:$ccr))*/]>,
2928 RegConstraint<"$false = $Rd"> {
2929 let Inst{31-27} = 0b11110;
2931 let Inst{24-21} = 0b0011;
2932 let Inst{20} = 0; // The S bit.
2933 let Inst{19-16} = 0b1111; // Rn
2937 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2938 string opc, string asm, list<dag> pattern>
2939 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2940 let Inst{31-27} = 0b11101;
2941 let Inst{26-25} = 0b01;
2942 let Inst{24-21} = 0b0010;
2943 let Inst{20} = 0; // The S bit.
2944 let Inst{19-16} = 0b1111; // Rn
2945 let Inst{5-4} = opcod; // Shift type.
2947 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2948 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2949 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2950 RegConstraint<"$false = $Rd">;
2951 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2952 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2953 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2954 RegConstraint<"$false = $Rd">;
2955 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2956 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2957 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2958 RegConstraint<"$false = $Rd">;
2959 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2960 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2961 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2962 RegConstraint<"$false = $Rd">;
2963 } // isCodeGenOnly = 1
2965 multiclass T2I_bincc_irs<Instruction iri, Instruction irr, Instruction irs,
2966 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
2968 def ri : t2PseudoExpand<(outs rGPR:$Rd),
2969 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s),
2971 (iri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
2972 RegConstraint<"$Rn = $Rd">;
2974 def rr : t2PseudoExpand<(outs rGPR:$Rd),
2975 (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s),
2977 (irr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
2978 RegConstraint<"$Rn = $Rd">;
2980 def rs : t2PseudoExpand<(outs rGPR:$Rd),
2981 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s),
2983 (irs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>,
2984 RegConstraint<"$Rn = $Rd">;
2987 defm t2ANDCC : T2I_bincc_irs<t2ANDri, t2ANDrr, t2ANDrs,
2988 IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
2989 defm t2ORRCC : T2I_bincc_irs<t2ORRri, t2ORRrr, t2ORRrs,
2990 IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
2991 defm t2EORCC : T2I_bincc_irs<t2EORri, t2EORrr, t2EORrs,
2992 IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
2993 } // neverHasSideEffects
2995 //===----------------------------------------------------------------------===//
2996 // Atomic operations intrinsics
2999 // memory barriers protect the atomic sequences
3000 let hasSideEffects = 1 in {
3001 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3002 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3003 Requires<[IsThumb, HasDB]> {
3005 let Inst{31-4} = 0xf3bf8f5;
3006 let Inst{3-0} = opt;
3010 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3011 "dsb", "\t$opt", []>,
3012 Requires<[IsThumb, HasDB]> {
3014 let Inst{31-4} = 0xf3bf8f4;
3015 let Inst{3-0} = opt;
3018 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3020 []>, Requires<[IsThumb, HasDB]> {
3022 let Inst{31-4} = 0xf3bf8f6;
3023 let Inst{3-0} = opt;
3026 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3027 InstrItinClass itin, string opc, string asm, string cstr,
3028 list<dag> pattern, bits<4> rt2 = 0b1111>
3029 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3030 let Inst{31-27} = 0b11101;
3031 let Inst{26-20} = 0b0001101;
3032 let Inst{11-8} = rt2;
3033 let Inst{7-6} = 0b01;
3034 let Inst{5-4} = opcod;
3035 let Inst{3-0} = 0b1111;
3039 let Inst{19-16} = addr;
3040 let Inst{15-12} = Rt;
3042 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3043 InstrItinClass itin, string opc, string asm, string cstr,
3044 list<dag> pattern, bits<4> rt2 = 0b1111>
3045 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3046 let Inst{31-27} = 0b11101;
3047 let Inst{26-20} = 0b0001100;
3048 let Inst{11-8} = rt2;
3049 let Inst{7-6} = 0b01;
3050 let Inst{5-4} = opcod;
3056 let Inst{19-16} = addr;
3057 let Inst{15-12} = Rt;
3060 let mayLoad = 1 in {
3061 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3062 AddrModeNone, 4, NoItinerary,
3063 "ldrexb", "\t$Rt, $addr", "", []>;
3064 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3065 AddrModeNone, 4, NoItinerary,
3066 "ldrexh", "\t$Rt, $addr", "", []>;
3067 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3068 AddrModeNone, 4, NoItinerary,
3069 "ldrex", "\t$Rt, $addr", "", []> {
3072 let Inst{31-27} = 0b11101;
3073 let Inst{26-20} = 0b0000101;
3074 let Inst{19-16} = addr{11-8};
3075 let Inst{15-12} = Rt;
3076 let Inst{11-8} = 0b1111;
3077 let Inst{7-0} = addr{7-0};
3079 let hasExtraDefRegAllocReq = 1 in
3080 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3081 (ins addr_offset_none:$addr),
3082 AddrModeNone, 4, NoItinerary,
3083 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3086 let Inst{11-8} = Rt2;
3090 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3091 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3092 (ins rGPR:$Rt, addr_offset_none:$addr),
3093 AddrModeNone, 4, NoItinerary,
3094 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3095 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3096 (ins rGPR:$Rt, addr_offset_none:$addr),
3097 AddrModeNone, 4, NoItinerary,
3098 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3099 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3100 t2addrmode_imm0_1020s4:$addr),
3101 AddrModeNone, 4, NoItinerary,
3102 "strex", "\t$Rd, $Rt, $addr", "",
3107 let Inst{31-27} = 0b11101;
3108 let Inst{26-20} = 0b0000100;
3109 let Inst{19-16} = addr{11-8};
3110 let Inst{15-12} = Rt;
3111 let Inst{11-8} = Rd;
3112 let Inst{7-0} = addr{7-0};
3114 let hasExtraSrcRegAllocReq = 1 in
3115 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3116 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3117 AddrModeNone, 4, NoItinerary,
3118 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3121 let Inst{11-8} = Rt2;
3125 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3126 Requires<[IsThumb2, HasV7]> {
3127 let Inst{31-16} = 0xf3bf;
3128 let Inst{15-14} = 0b10;
3131 let Inst{11-8} = 0b1111;
3132 let Inst{7-4} = 0b0010;
3133 let Inst{3-0} = 0b1111;
3136 //===----------------------------------------------------------------------===//
3137 // SJLJ Exception handling intrinsics
3138 // eh_sjlj_setjmp() is an instruction sequence to store the return
3139 // address and save #0 in R0 for the non-longjmp case.
3140 // Since by its nature we may be coming from some other function to get
3141 // here, and we're using the stack frame for the containing function to
3142 // save/restore registers, we can't keep anything live in regs across
3143 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3144 // when we get here from a longjmp(). We force everything out of registers
3145 // except for our own input by listing the relevant registers in Defs. By
3146 // doing so, we also cause the prologue/epilogue code to actively preserve
3147 // all of the callee-saved resgisters, which is exactly what we want.
3148 // $val is a scratch register for our use.
3150 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3151 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3152 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3153 usesCustomInserter = 1 in {
3154 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3155 AddrModeNone, 0, NoItinerary, "", "",
3156 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3157 Requires<[IsThumb2, HasVFP2]>;
3161 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3162 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3163 usesCustomInserter = 1 in {
3164 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3165 AddrModeNone, 0, NoItinerary, "", "",
3166 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3167 Requires<[IsThumb2, NoVFP]>;
3171 //===----------------------------------------------------------------------===//
3172 // Control-Flow Instructions
3175 // FIXME: remove when we have a way to marking a MI with these properties.
3176 // FIXME: Should pc be an implicit operand like PICADD, etc?
3177 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3178 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3179 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3180 reglist:$regs, variable_ops),
3181 4, IIC_iLoad_mBr, [],
3182 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3183 RegConstraint<"$Rn = $wb">;
3185 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3186 let isPredicable = 1 in
3187 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3189 [(br bb:$target)]> {
3190 let Inst{31-27} = 0b11110;
3191 let Inst{15-14} = 0b10;
3195 let Inst{26} = target{19};
3196 let Inst{11} = target{18};
3197 let Inst{13} = target{17};
3198 let Inst{21-16} = target{16-11};
3199 let Inst{10-0} = target{10-0};
3200 let DecoderMethod = "DecodeT2BInstruction";
3203 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3204 def t2BR_JT : t2PseudoInst<(outs),
3205 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3207 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3209 // FIXME: Add a non-pc based case that can be predicated.
3210 def t2TBB_JT : t2PseudoInst<(outs),
3211 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3213 def t2TBH_JT : t2PseudoInst<(outs),
3214 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3216 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3217 "tbb", "\t$addr", []> {
3220 let Inst{31-20} = 0b111010001101;
3221 let Inst{19-16} = Rn;
3222 let Inst{15-5} = 0b11110000000;
3223 let Inst{4} = 0; // B form
3226 let DecoderMethod = "DecodeThumbTableBranch";
3229 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3230 "tbh", "\t$addr", []> {
3233 let Inst{31-20} = 0b111010001101;
3234 let Inst{19-16} = Rn;
3235 let Inst{15-5} = 0b11110000000;
3236 let Inst{4} = 1; // H form
3239 let DecoderMethod = "DecodeThumbTableBranch";
3241 } // isNotDuplicable, isIndirectBranch
3243 } // isBranch, isTerminator, isBarrier
3245 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3246 // a two-value operand where a dag node expects ", "two operands. :(
3247 let isBranch = 1, isTerminator = 1 in
3248 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3250 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3251 let Inst{31-27} = 0b11110;
3252 let Inst{15-14} = 0b10;
3256 let Inst{25-22} = p;
3259 let Inst{26} = target{20};
3260 let Inst{11} = target{19};
3261 let Inst{13} = target{18};
3262 let Inst{21-16} = target{17-12};
3263 let Inst{10-0} = target{11-1};
3265 let DecoderMethod = "DecodeThumb2BCCInstruction";
3268 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3270 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3273 def tTAILJMPd: tPseudoExpand<(outs),
3274 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3276 (t2B uncondbrtarget:$dst, pred:$p)>,
3277 Requires<[IsThumb2, IsIOS]>;
3280 let isCall = 1, Defs = [LR], Uses = [SP] in {
3281 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
3282 // return stack predictor.
3283 def t2BMOVPCB_CALL : tPseudoInst<(outs),
3284 (ins t_bltarget:$func, variable_ops),
3285 6, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
3286 Requires<[IsThumb]>;
3290 def : T2Pat<(ARMcall_nolink texternalsym:$func),
3291 (t2BMOVPCB_CALL texternalsym:$func)>,
3292 Requires<[IsThumb]>;
3295 let Defs = [ITSTATE] in
3296 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3297 AddrModeNone, 2, IIC_iALUx,
3298 "it$mask\t$cc", "", []> {
3299 // 16-bit instruction.
3300 let Inst{31-16} = 0x0000;
3301 let Inst{15-8} = 0b10111111;
3306 let Inst{3-0} = mask;
3308 let DecoderMethod = "DecodeIT";
3311 // Branch and Exchange Jazelle -- for disassembly only
3313 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3315 let Inst{31-27} = 0b11110;
3317 let Inst{25-20} = 0b111100;
3318 let Inst{19-16} = func;
3319 let Inst{15-0} = 0b1000111100000000;
3322 // Compare and branch on zero / non-zero
3323 let isBranch = 1, isTerminator = 1 in {
3324 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3325 "cbz\t$Rn, $target", []>,
3326 T1Misc<{0,0,?,1,?,?,?}>,
3327 Requires<[IsThumb2]> {
3331 let Inst{9} = target{5};
3332 let Inst{7-3} = target{4-0};
3336 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3337 "cbnz\t$Rn, $target", []>,
3338 T1Misc<{1,0,?,1,?,?,?}>,
3339 Requires<[IsThumb2]> {
3343 let Inst{9} = target{5};
3344 let Inst{7-3} = target{4-0};
3350 // Change Processor State is a system instruction.
3351 // FIXME: Since the asm parser has currently no clean way to handle optional
3352 // operands, create 3 versions of the same instruction. Once there's a clean
3353 // framework to represent optional operands, change this behavior.
3354 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3355 !strconcat("cps", asm_op), []> {
3361 let Inst{31-27} = 0b11110;
3363 let Inst{25-20} = 0b111010;
3364 let Inst{19-16} = 0b1111;
3365 let Inst{15-14} = 0b10;
3367 let Inst{10-9} = imod;
3369 let Inst{7-5} = iflags;
3370 let Inst{4-0} = mode;
3371 let DecoderMethod = "DecodeT2CPSInstruction";
3375 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3376 "$imod.w\t$iflags, $mode">;
3377 let mode = 0, M = 0 in
3378 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3379 "$imod.w\t$iflags">;
3380 let imod = 0, iflags = 0, M = 1 in
3381 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3383 // A6.3.4 Branches and miscellaneous control
3384 // Table A6-14 Change Processor State, and hint instructions
3385 class T2I_hint<bits<8> op7_0, string opc, string asm>
3386 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3387 let Inst{31-20} = 0xf3a;
3388 let Inst{19-16} = 0b1111;
3389 let Inst{15-14} = 0b10;
3391 let Inst{10-8} = 0b000;
3392 let Inst{7-0} = op7_0;
3395 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3396 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3397 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3398 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3399 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3401 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3403 let Inst{31-20} = 0b111100111010;
3404 let Inst{19-16} = 0b1111;
3405 let Inst{15-8} = 0b10000000;
3406 let Inst{7-4} = 0b1111;
3407 let Inst{3-0} = opt;
3410 // Secure Monitor Call is a system instruction.
3411 // Option = Inst{19-16}
3412 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3413 let Inst{31-27} = 0b11110;
3414 let Inst{26-20} = 0b1111111;
3415 let Inst{15-12} = 0b1000;
3418 let Inst{19-16} = opt;
3421 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3422 string opc, string asm, list<dag> pattern>
3423 : T2I<oops, iops, itin, opc, asm, pattern> {
3425 let Inst{31-25} = 0b1110100;
3426 let Inst{24-23} = Op;
3429 let Inst{20-16} = 0b01101;
3430 let Inst{15-5} = 0b11000000000;
3431 let Inst{4-0} = mode{4-0};
3434 // Store Return State is a system instruction.
3435 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3436 "srsdb", "\tsp!, $mode", []>;
3437 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3438 "srsdb","\tsp, $mode", []>;
3439 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3440 "srsia","\tsp!, $mode", []>;
3441 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3442 "srsia","\tsp, $mode", []>;
3444 // Return From Exception is a system instruction.
3445 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3446 string opc, string asm, list<dag> pattern>
3447 : T2I<oops, iops, itin, opc, asm, pattern> {
3448 let Inst{31-20} = op31_20{11-0};
3451 let Inst{19-16} = Rn;
3452 let Inst{15-0} = 0xc000;
3455 def t2RFEDBW : T2RFE<0b111010000011,
3456 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3457 [/* For disassembly only; pattern left blank */]>;
3458 def t2RFEDB : T2RFE<0b111010000001,
3459 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3460 [/* For disassembly only; pattern left blank */]>;
3461 def t2RFEIAW : T2RFE<0b111010011011,
3462 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3463 [/* For disassembly only; pattern left blank */]>;
3464 def t2RFEIA : T2RFE<0b111010011001,
3465 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3466 [/* For disassembly only; pattern left blank */]>;
3468 //===----------------------------------------------------------------------===//
3469 // Non-Instruction Patterns
3472 // 32-bit immediate using movw + movt.
3473 // This is a single pseudo instruction to make it re-materializable.
3474 // FIXME: Remove this when we can do generalized remat.
3475 let isReMaterializable = 1, isMoveImm = 1 in
3476 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3477 [(set rGPR:$dst, (i32 imm:$src))]>,
3478 Requires<[IsThumb, HasV6T2]>;
3480 // Pseudo instruction that combines movw + movt + add pc (if pic).
3481 // It also makes it possible to rematerialize the instructions.
3482 // FIXME: Remove this when we can do generalized remat and when machine licm
3483 // can properly the instructions.
3484 let isReMaterializable = 1 in {
3485 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3487 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3488 Requires<[IsThumb2, UseMovt]>;
3490 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3492 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3493 Requires<[IsThumb2, UseMovt]>;
3496 // ConstantPool, GlobalAddress, and JumpTable
3497 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3498 Requires<[IsThumb2, DontUseMovt]>;
3499 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3500 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3501 Requires<[IsThumb2, UseMovt]>;
3503 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3504 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3506 // Pseudo instruction that combines ldr from constpool and add pc. This should
3507 // be expanded into two instructions late to allow if-conversion and
3509 let canFoldAsLoad = 1, isReMaterializable = 1 in
3510 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3512 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3514 Requires<[IsThumb2]>;
3516 // Pseudo isntruction that combines movs + predicated rsbmi
3517 // to implement integer ABS
3518 let usesCustomInserter = 1, Defs = [CPSR] in {
3519 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3520 NoItinerary, []>, Requires<[IsThumb2]>;
3523 //===----------------------------------------------------------------------===//
3524 // Coprocessor load/store -- for disassembly only
3526 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3527 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3528 let Inst{31-28} = op31_28;
3529 let Inst{27-25} = 0b110;
3532 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3533 def _OFFSET : T2CI<op31_28,
3534 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3535 asm, "\t$cop, $CRd, $addr"> {
3539 let Inst{24} = 1; // P = 1
3540 let Inst{23} = addr{8};
3541 let Inst{22} = Dbit;
3542 let Inst{21} = 0; // W = 0
3543 let Inst{20} = load;
3544 let Inst{19-16} = addr{12-9};
3545 let Inst{15-12} = CRd;
3546 let Inst{11-8} = cop;
3547 let Inst{7-0} = addr{7-0};
3548 let DecoderMethod = "DecodeCopMemInstruction";
3550 def _PRE : T2CI<op31_28,
3551 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3552 asm, "\t$cop, $CRd, $addr!"> {
3556 let Inst{24} = 1; // P = 1
3557 let Inst{23} = addr{8};
3558 let Inst{22} = Dbit;
3559 let Inst{21} = 1; // W = 1
3560 let Inst{20} = load;
3561 let Inst{19-16} = addr{12-9};
3562 let Inst{15-12} = CRd;
3563 let Inst{11-8} = cop;
3564 let Inst{7-0} = addr{7-0};
3565 let DecoderMethod = "DecodeCopMemInstruction";
3567 def _POST: T2CI<op31_28,
3568 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3569 postidx_imm8s4:$offset),
3570 asm, "\t$cop, $CRd, $addr, $offset"> {
3575 let Inst{24} = 0; // P = 0
3576 let Inst{23} = offset{8};
3577 let Inst{22} = Dbit;
3578 let Inst{21} = 1; // W = 1
3579 let Inst{20} = load;
3580 let Inst{19-16} = addr;
3581 let Inst{15-12} = CRd;
3582 let Inst{11-8} = cop;
3583 let Inst{7-0} = offset{7-0};
3584 let DecoderMethod = "DecodeCopMemInstruction";
3586 def _OPTION : T2CI<op31_28, (outs),
3587 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3588 coproc_option_imm:$option),
3589 asm, "\t$cop, $CRd, $addr, $option"> {
3594 let Inst{24} = 0; // P = 0
3595 let Inst{23} = 1; // U = 1
3596 let Inst{22} = Dbit;
3597 let Inst{21} = 0; // W = 0
3598 let Inst{20} = load;
3599 let Inst{19-16} = addr;
3600 let Inst{15-12} = CRd;
3601 let Inst{11-8} = cop;
3602 let Inst{7-0} = option;
3603 let DecoderMethod = "DecodeCopMemInstruction";
3607 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3608 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3609 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3610 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3611 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3612 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3613 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3614 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3617 //===----------------------------------------------------------------------===//
3618 // Move between special register and ARM core register -- for disassembly only
3620 // Move to ARM core register from Special Register
3624 // A/R class can only move from CPSR or SPSR.
3625 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3626 []>, Requires<[IsThumb2,IsARClass]> {
3628 let Inst{31-12} = 0b11110011111011111000;
3629 let Inst{11-8} = Rd;
3630 let Inst{7-0} = 0b0000;
3633 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3635 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3636 []>, Requires<[IsThumb2,IsARClass]> {
3638 let Inst{31-12} = 0b11110011111111111000;
3639 let Inst{11-8} = Rd;
3640 let Inst{7-0} = 0b0000;
3645 // This MRS has a mask field in bits 7-0 and can take more values than
3646 // the A/R class (a full msr_mask).
3647 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3648 "mrs", "\t$Rd, $mask", []>,
3649 Requires<[IsThumb,IsMClass]> {
3652 let Inst{31-12} = 0b11110011111011111000;
3653 let Inst{11-8} = Rd;
3654 let Inst{19-16} = 0b1111;
3655 let Inst{7-0} = mask;
3659 // Move from ARM core register to Special Register
3663 // No need to have both system and application versions, the encodings are the
3664 // same and the assembly parser has no way to distinguish between them. The mask
3665 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3666 // the mask with the fields to be accessed in the special register.
3667 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3668 NoItinerary, "msr", "\t$mask, $Rn", []>,
3669 Requires<[IsThumb2,IsARClass]> {
3672 let Inst{31-21} = 0b11110011100;
3673 let Inst{20} = mask{4}; // R Bit
3674 let Inst{19-16} = Rn;
3675 let Inst{15-12} = 0b1000;
3676 let Inst{11-8} = mask{3-0};
3682 // Move from ARM core register to Special Register
3683 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3684 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3685 Requires<[IsThumb,IsMClass]> {
3688 let Inst{31-21} = 0b11110011100;
3690 let Inst{19-16} = Rn;
3691 let Inst{15-12} = 0b1000;
3692 let Inst{11-0} = SYSm;
3696 //===----------------------------------------------------------------------===//
3697 // Move between coprocessor and ARM core register
3700 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3702 : T2Cop<Op, oops, iops,
3703 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3705 let Inst{27-24} = 0b1110;
3706 let Inst{20} = direction;
3716 let Inst{15-12} = Rt;
3717 let Inst{11-8} = cop;
3718 let Inst{23-21} = opc1;
3719 let Inst{7-5} = opc2;
3720 let Inst{3-0} = CRm;
3721 let Inst{19-16} = CRn;
3724 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3725 list<dag> pattern = []>
3727 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3728 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3729 let Inst{27-24} = 0b1100;
3730 let Inst{23-21} = 0b010;
3731 let Inst{20} = direction;
3739 let Inst{15-12} = Rt;
3740 let Inst{19-16} = Rt2;
3741 let Inst{11-8} = cop;
3742 let Inst{7-4} = opc1;
3743 let Inst{3-0} = CRm;
3746 /* from ARM core register to coprocessor */
3747 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3749 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3750 c_imm:$CRm, imm0_7:$opc2),
3751 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3752 imm:$CRm, imm:$opc2)]>;
3753 def : t2InstAlias<"mcr $cop, $opc1, $Rt, $CRn, $CRm",
3754 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3756 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3757 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3758 c_imm:$CRm, imm0_7:$opc2),
3759 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3760 imm:$CRm, imm:$opc2)]>;
3761 def : t2InstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
3762 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3765 /* from coprocessor to ARM core register */
3766 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3767 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3768 c_imm:$CRm, imm0_7:$opc2), []>;
3769 def : t2InstAlias<"mrc $cop, $opc1, $Rt, $CRn, $CRm",
3770 (t2MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3773 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3774 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3775 c_imm:$CRm, imm0_7:$opc2), []>;
3776 def : t2InstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
3777 (t2MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3780 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3781 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3783 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3784 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3787 /* from ARM core register to coprocessor */
3788 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3789 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3791 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3792 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3793 GPR:$Rt2, imm:$CRm)]>;
3794 /* from coprocessor to ARM core register */
3795 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3797 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3799 //===----------------------------------------------------------------------===//
3800 // Other Coprocessor Instructions.
3803 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3804 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3805 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3806 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3807 imm:$CRm, imm:$opc2)]> {
3808 let Inst{27-24} = 0b1110;
3817 let Inst{3-0} = CRm;
3819 let Inst{7-5} = opc2;
3820 let Inst{11-8} = cop;
3821 let Inst{15-12} = CRd;
3822 let Inst{19-16} = CRn;
3823 let Inst{23-20} = opc1;
3826 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3827 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3828 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3829 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3830 imm:$CRm, imm:$opc2)]> {
3831 let Inst{27-24} = 0b1110;
3840 let Inst{3-0} = CRm;
3842 let Inst{7-5} = opc2;
3843 let Inst{11-8} = cop;
3844 let Inst{15-12} = CRd;
3845 let Inst{19-16} = CRn;
3846 let Inst{23-20} = opc1;
3851 //===----------------------------------------------------------------------===//
3852 // Non-Instruction Patterns
3855 // SXT/UXT with no rotate
3856 let AddedComplexity = 16 in {
3857 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3858 Requires<[IsThumb2]>;
3859 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3860 Requires<[IsThumb2]>;
3861 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3862 Requires<[HasT2ExtractPack, IsThumb2]>;
3863 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3864 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3865 Requires<[HasT2ExtractPack, IsThumb2]>;
3866 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3867 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3868 Requires<[HasT2ExtractPack, IsThumb2]>;
3871 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3872 Requires<[IsThumb2]>;
3873 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3874 Requires<[IsThumb2]>;
3875 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3876 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3877 Requires<[HasT2ExtractPack, IsThumb2]>;
3878 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3879 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3880 Requires<[HasT2ExtractPack, IsThumb2]>;
3882 // Atomic load/store patterns
3883 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3884 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3885 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3886 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3887 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3888 (t2LDRBs t2addrmode_so_reg:$addr)>;
3889 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3890 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3891 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3892 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3893 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3894 (t2LDRHs t2addrmode_so_reg:$addr)>;
3895 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3896 (t2LDRi12 t2addrmode_imm12:$addr)>;
3897 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3898 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3899 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3900 (t2LDRs t2addrmode_so_reg:$addr)>;
3901 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3902 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3903 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3904 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3905 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3906 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3907 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3908 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3909 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3910 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3911 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3912 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3913 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3914 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3915 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3916 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3917 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3918 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3921 //===----------------------------------------------------------------------===//
3922 // Assembler aliases
3925 // Aliases for ADC without the ".w" optional width specifier.
3926 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3927 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3928 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3929 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3930 pred:$p, cc_out:$s)>;
3932 // Aliases for SBC without the ".w" optional width specifier.
3933 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3934 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3935 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3936 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3937 pred:$p, cc_out:$s)>;
3939 // Aliases for ADD without the ".w" optional width specifier.
3940 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3941 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3942 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3943 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3944 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3945 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3946 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3947 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3948 pred:$p, cc_out:$s)>;
3949 // ... and with the destination and source register combined.
3950 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
3951 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3952 def : t2InstAlias<"add${p} $Rdn, $imm",
3953 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3954 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
3955 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3956 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
3957 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
3958 pred:$p, cc_out:$s)>;
3960 // add w/ negative immediates is just a sub.
3961 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3962 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
3964 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3965 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
3966 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
3967 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
3969 def : t2InstAlias<"add${p} $Rdn, $imm",
3970 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
3972 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
3973 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
3975 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
3976 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
3977 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
3978 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
3980 def : t2InstAlias<"addw${p} $Rdn, $imm",
3981 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
3984 // Aliases for SUB without the ".w" optional width specifier.
3985 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3986 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3987 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3988 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3989 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3990 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3991 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3992 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3993 pred:$p, cc_out:$s)>;
3994 // ... and with the destination and source register combined.
3995 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
3996 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3997 def : t2InstAlias<"sub${p} $Rdn, $imm",
3998 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3999 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4000 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4001 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4002 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4003 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4004 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4005 pred:$p, cc_out:$s)>;
4007 // Alias for compares without the ".w" optional width specifier.
4008 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4009 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4010 def : t2InstAlias<"teq${p} $Rn, $Rm",
4011 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4012 def : t2InstAlias<"tst${p} $Rn, $Rm",
4013 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4016 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>;
4017 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>;
4018 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>;
4020 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4022 def : t2InstAlias<"ldr${p} $Rt, $addr",
4023 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4024 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4025 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4026 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4027 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4028 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4029 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4030 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4031 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4033 def : t2InstAlias<"ldr${p} $Rt, $addr",
4034 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4035 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4036 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4037 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4038 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4039 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4040 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4041 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4042 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4044 def : t2InstAlias<"ldr${p} $Rt, $addr",
4045 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4046 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4047 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4048 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4049 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4050 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4051 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4052 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4053 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4055 // Alias for MVN with(out) the ".w" optional width specifier.
4056 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4057 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4058 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4059 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4060 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4061 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4063 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4064 // shift amount is zero (i.e., unspecified).
4065 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4066 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4067 Requires<[HasT2ExtractPack, IsThumb2]>;
4068 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4069 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4070 Requires<[HasT2ExtractPack, IsThumb2]>;
4072 // PUSH/POP aliases for STM/LDM
4073 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4074 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4075 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4076 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4078 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4079 def : t2InstAlias<"stm${p} $Rn, $regs",
4080 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4081 def : t2InstAlias<"stm${p} $Rn!, $regs",
4082 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4084 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4085 def : t2InstAlias<"ldm${p} $Rn, $regs",
4086 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4087 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4088 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4090 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4091 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4092 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4093 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4094 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4096 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4097 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4098 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4099 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4100 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4102 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4103 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4104 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4105 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4108 // Alias for RSB without the ".w" optional width specifier, and with optional
4109 // implied destination register.
4110 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4111 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4112 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4113 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4114 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4115 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4116 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4117 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4120 // SSAT/USAT optional shift operand.
4121 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4122 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4123 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4124 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4126 // STM w/o the .w suffix.
4127 def : t2InstAlias<"stm${p} $Rn, $regs",
4128 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4130 // Alias for STR, STRB, and STRH without the ".w" optional
4132 def : t2InstAlias<"str${p} $Rt, $addr",
4133 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4134 def : t2InstAlias<"strb${p} $Rt, $addr",
4135 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4136 def : t2InstAlias<"strh${p} $Rt, $addr",
4137 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4139 def : t2InstAlias<"str${p} $Rt, $addr",
4140 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4141 def : t2InstAlias<"strb${p} $Rt, $addr",
4142 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4143 def : t2InstAlias<"strh${p} $Rt, $addr",
4144 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4146 // Extend instruction optional rotate operand.
4147 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4148 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4149 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4150 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4151 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4152 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4154 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4155 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4156 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4157 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4158 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4159 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4160 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4161 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4162 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4163 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4165 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4166 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4167 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4168 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4169 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4170 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4171 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4172 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4173 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4174 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4175 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4176 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4178 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4179 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4180 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4181 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4183 // Extend instruction w/o the ".w" optional width specifier.
4184 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4185 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4186 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4187 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4188 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4189 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4191 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4192 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4193 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4194 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4195 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4196 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4199 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4201 def : t2InstAlias<"mov${p} $Rd, $imm",
4202 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4203 def : t2InstAlias<"mvn${p} $Rd, $imm",
4204 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4205 // Same for AND <--> BIC
4206 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4207 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4208 pred:$p, cc_out:$s)>;
4209 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4210 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4211 pred:$p, cc_out:$s)>;
4212 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4213 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4214 pred:$p, cc_out:$s)>;
4215 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4216 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4217 pred:$p, cc_out:$s)>;
4218 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4219 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4220 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4221 pred:$p, cc_out:$s)>;
4222 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4223 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4224 pred:$p, cc_out:$s)>;
4225 // Same for CMP <--> CMN via t2_so_imm_neg
4226 def : t2InstAlias<"cmp${p} $Rd, $imm",
4227 (t2CMNzri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4228 def : t2InstAlias<"cmn${p} $Rd, $imm",
4229 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4232 // Wide 'mul' encoding can be specified with only two operands.
4233 def : t2InstAlias<"mul${p} $Rn, $Rm",
4234 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4236 // "neg" is and alias for "rsb rd, rn, #0"
4237 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4238 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4240 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4241 // these, unfortunately.
4242 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4243 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4244 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4245 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4247 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4248 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4249 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4250 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4252 // ADR w/o the .w suffix
4253 def : t2InstAlias<"adr${p} $Rd, $addr",
4254 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4256 // LDR(literal) w/ alternate [pc, #imm] syntax.
4257 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4258 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4259 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4260 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4261 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4262 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4263 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4264 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4265 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4266 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4267 // Version w/ the .w suffix.
4268 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4269 (t2LDRpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4270 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4271 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4272 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4273 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4274 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4275 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4276 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4277 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4279 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4280 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;