1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
19 let PrintMethod = "printT2SOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
24 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
28 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
29 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
30 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
33 // t2_so_imm - Match a 32-bit immediate operand, which is an
34 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
35 // immediate splatted into multiple bytes of the word. t2_so_imm values are
36 // represented in the imm field in the same 12-bit form that they are encoded
37 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
38 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
39 def t2_so_imm : Operand<i32>,
41 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
44 // t2_so_imm_not - Match an immediate that is a complement
46 def t2_so_imm_not : Operand<i32>,
48 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
49 }], t2_so_imm_not_XFORM>;
51 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
52 def t2_so_imm_neg : Operand<i32>,
54 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
55 }], t2_so_imm_neg_XFORM>;
57 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
58 def imm1_31 : PatLeaf<(i32 imm), [{
59 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
62 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
63 def imm0_4095 : PatLeaf<(i32 imm), [{
64 return (uint32_t)N->getZExtValue() < 4096;
67 def imm0_4095_neg : PatLeaf<(i32 imm), [{
68 return (uint32_t)(-N->getZExtValue()) < 4096;
71 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
73 def imm0_65535 : PatLeaf<(i32 imm), [{
74 return (uint32_t)N->getZExtValue() < 65536;
77 /// Split a 32-bit immediate into two 16 bit parts.
78 def t2_lo16 : SDNodeXForm<imm, [{
79 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
83 def t2_hi16 : SDNodeXForm<imm, [{
84 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
87 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
88 // Returns true if all low 16-bits are 0.
89 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
93 // Define Thumb2 specific addressing modes.
95 // t2addrmode_imm12 := reg + imm12
96 def t2addrmode_imm12 : Operand<i32>,
97 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
98 let PrintMethod = "printT2AddrModeImm12Operand";
99 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
102 // t2addrmode_imm8 := reg - imm8
103 def t2addrmode_imm8 : Operand<i32>,
104 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
105 let PrintMethod = "printT2AddrModeImm8Operand";
106 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
109 def t2am_imm8_offset : Operand<i32>,
110 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
111 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
114 // t2addrmode_imm8s4 := reg + (imm8 << 2)
115 def t2addrmode_imm8s4 : Operand<i32>,
116 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
117 let PrintMethod = "printT2AddrModeImm8Operand";
118 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
121 // t2addrmode_so_reg := reg + (reg << imm2)
122 def t2addrmode_so_reg : Operand<i32>,
123 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
124 let PrintMethod = "printT2AddrModeSoRegOperand";
125 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
129 //===----------------------------------------------------------------------===//
130 // Multiclass helpers...
133 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
134 /// unary operation that produces a value. These are predicable and can be
135 /// changed to modify CPSR.
136 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
138 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
140 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
141 let isAsCheapAsAMove = Cheap;
142 let isReMaterializable = ReMat;
145 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
147 [(set GPR:$dst, (opnode GPR:$src))]>;
149 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
151 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
154 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
155 // binary operation that produces a value. These are predicable and can be
156 /// changed to modify CPSR.
157 multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
159 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
160 opc, " $dst, $lhs, $rhs",
161 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
163 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
164 opc, " $dst, $lhs, $rhs",
165 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
166 let isCommutable = Commutable;
169 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
170 opc, " $dst, $lhs, $rhs",
171 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
174 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
175 /// reversed. It doesn't define the 'rr' form since it's handled by its
176 /// T2I_bin_irs counterpart.
177 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
179 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
180 opc, " $dst, $rhs, $lhs",
181 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
183 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
184 opc, " $dst, $rhs, $lhs",
185 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
188 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
189 /// instruction modifies the CPSR register.
190 let Defs = [CPSR] in {
191 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
193 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
194 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
195 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
197 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
198 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
199 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
200 let isCommutable = Commutable;
203 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
204 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
205 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
209 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
210 /// patterns for a binary operation that produces a value.
211 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
213 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
214 opc, " $dst, $lhs, $rhs",
215 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
217 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
218 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
219 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
221 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
222 opc, " $dst, $lhs, $rhs",
223 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
224 let isCommutable = Commutable;
227 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
228 opc, " $dst, $lhs, $rhs",
229 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
232 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
233 /// binary operation that produces a value and use and define the carry bit.
234 /// It's not predicable.
235 let Uses = [CPSR] in {
236 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
238 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
239 opc, " $dst, $lhs, $rhs",
240 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
241 Requires<[IsThumb2, CarryDefIsUnused]>;
243 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
244 opc, " $dst, $lhs, $rhs",
245 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
246 Requires<[IsThumb2, CarryDefIsUnused]> {
247 let isCommutable = Commutable;
250 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
251 opc, " $dst, $lhs, $rhs",
252 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
253 Requires<[IsThumb2, CarryDefIsUnused]>;
254 // Carry setting variants
256 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
257 !strconcat(opc, "s $dst, $lhs, $rhs"),
258 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
259 Requires<[IsThumb2, CarryDefIsUsed]> {
263 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
264 !strconcat(opc, "s $dst, $lhs, $rhs"),
265 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
266 Requires<[IsThumb2, CarryDefIsUsed]> {
268 let isCommutable = Commutable;
271 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
272 !strconcat(opc, "s $dst, $lhs, $rhs"),
273 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
274 Requires<[IsThumb2, CarryDefIsUsed]> {
280 /// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
281 /// reversed. It doesn't define the 'rr' form since it's handled by its
282 /// T2I_adde_sube_irs counterpart.
283 let Defs = [CPSR], Uses = [CPSR] in {
284 multiclass T2I_rsc_is<string opc, PatFrag opnode> {
286 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
287 opc, " $dst, $rhs, $lhs",
288 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
289 Requires<[IsThumb2, CarryDefIsUnused]>;
291 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
292 opc, " $dst, $rhs, $lhs",
293 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
294 Requires<[IsThumb2, CarryDefIsUnused]>;
296 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
297 !strconcat(opc, "s $dst, $rhs, $lhs"),
298 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
299 Requires<[IsThumb2, CarryDefIsUsed]> {
303 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
304 !strconcat(opc, "s $dst, $rhs, $lhs"),
305 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
306 Requires<[IsThumb2, CarryDefIsUsed]> {
312 /// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
313 /// reversed. It doesn't define the 'rr' form since it's handled by its
314 /// T2I_bin_s_irs counterpart.
315 let Defs = [CPSR] in {
316 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
318 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
319 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
320 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
322 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
323 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
324 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
328 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
329 // rotate operation that produces a value.
330 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
332 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
333 opc, " $dst, $lhs, $rhs",
334 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
336 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
337 opc, " $dst, $lhs, $rhs",
338 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
341 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
342 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
343 /// a explicit result, only implicitly set CPSR.
344 let Uses = [CPSR] in {
345 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
347 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
349 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
351 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
353 [(opnode GPR:$lhs, GPR:$rhs)]>;
355 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
357 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
361 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
362 multiclass T2I_ld<string opc, PatFrag opnode> {
363 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
365 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
366 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
368 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
369 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
371 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
372 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
374 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
377 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
378 multiclass T2I_st<string opc, PatFrag opnode> {
379 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
381 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
382 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
384 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
385 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
387 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
390 /// T2I_picld - Defines the PIC load pattern.
391 class T2I_picld<string opc, PatFrag opnode> :
392 T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
393 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
394 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
396 /// T2I_picst - Defines the PIC store pattern.
397 class T2I_picst<string opc, PatFrag opnode> :
398 T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
399 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
400 [(opnode GPR:$src, addrmodepc:$addr)]>;
403 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
404 /// register and one whose operand is a register rotated by 8/16/24.
405 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
406 def r : T2I<(outs GPR:$dst), (ins GPR:$Src),
408 [(set GPR:$dst, (opnode GPR:$Src))]>;
409 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
410 opc, " $dst, $Src, ror $rot",
411 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
414 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
415 /// register and one whose operand is a register rotated by 8/16/24.
416 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
417 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
418 opc, " $dst, $LHS, $RHS",
419 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
420 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
421 opc, " $dst, $LHS, $RHS, ror $rot",
422 [(set GPR:$dst, (opnode GPR:$LHS,
423 (rotr GPR:$RHS, rot_imm:$rot)))]>;
426 //===----------------------------------------------------------------------===//
428 //===----------------------------------------------------------------------===//
430 //===----------------------------------------------------------------------===//
431 // Miscellaneous Instructions.
434 let isNotDuplicable = 1 in
435 def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
436 "$cp:\n\tadd $dst, pc",
437 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
440 // LEApcrel - Load a pc-relative address into a register without offending the
442 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
443 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
444 "${:private}PCRELL${:uid}+8))\n"),
445 !strconcat("${:private}PCRELL${:uid}:\n\t",
446 "add$p $dst, pc, #PCRELV${:uid}")),
449 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
450 (ins i32imm:$label, i32imm:$id, pred:$p),
451 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
452 "${:private}PCRELL${:uid}+8))\n"),
453 !strconcat("${:private}PCRELL${:uid}:\n\t",
454 "add$p $dst, pc, #PCRELV${:uid}")),
457 // ADD rd, sp, #so_imm
458 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
459 "add $dst, $sp, $imm",
462 // ADD rd, sp, #imm12
463 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
464 "addw $dst, $sp, $imm",
467 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
468 "addw $dst, $sp, $rhs",
472 //===----------------------------------------------------------------------===//
473 // Load / store Instructions.
477 let canFoldAsLoad = 1 in
478 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
480 // Loads with zero extension
481 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
482 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
484 // Loads with sign extension
485 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
486 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
490 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
491 "ldrd", " $dst, $addr", []>;
492 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
493 "ldrd", " $dst, $addr", []>;
496 // zextload i1 -> zextload i8
497 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
498 (t2LDRBi12 t2addrmode_imm12:$addr)>;
499 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
500 (t2LDRBi8 t2addrmode_imm8:$addr)>;
501 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
502 (t2LDRBs t2addrmode_so_reg:$addr)>;
503 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
504 (t2LDRBpci tconstpool:$addr)>;
506 // extload -> zextload
507 // FIXME: Reduce the number of patterns by legalizing extload to zextload
509 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
510 (t2LDRBi12 t2addrmode_imm12:$addr)>;
511 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
512 (t2LDRBi8 t2addrmode_imm8:$addr)>;
513 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
514 (t2LDRBs t2addrmode_so_reg:$addr)>;
515 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
516 (t2LDRBpci tconstpool:$addr)>;
518 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
519 (t2LDRBi12 t2addrmode_imm12:$addr)>;
520 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
521 (t2LDRBi8 t2addrmode_imm8:$addr)>;
522 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
523 (t2LDRBs t2addrmode_so_reg:$addr)>;
524 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
525 (t2LDRBpci tconstpool:$addr)>;
527 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
528 (t2LDRHi12 t2addrmode_imm12:$addr)>;
529 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
530 (t2LDRHi8 t2addrmode_imm8:$addr)>;
531 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
532 (t2LDRHs t2addrmode_so_reg:$addr)>;
533 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
534 (t2LDRHpci tconstpool:$addr)>;
538 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
539 (ins t2addrmode_imm8:$addr),
540 AddrModeT2_i8, IndexModePre,
541 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
544 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
545 (ins GPR:$base, t2am_imm8_offset:$offset),
546 AddrModeT2_i8, IndexModePost,
547 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
550 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
551 (ins t2addrmode_imm8:$addr),
552 AddrModeT2_i8, IndexModePre,
553 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
555 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
556 (ins GPR:$base, t2am_imm8_offset:$offset),
557 AddrModeT2_i8, IndexModePost,
558 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
561 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
562 (ins t2addrmode_imm8:$addr),
563 AddrModeT2_i8, IndexModePre,
564 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
566 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
567 (ins GPR:$base, t2am_imm8_offset:$offset),
568 AddrModeT2_i8, IndexModePost,
569 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
572 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
573 (ins t2addrmode_imm8:$addr),
574 AddrModeT2_i8, IndexModePre,
575 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
577 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
578 (ins GPR:$base, t2am_imm8_offset:$offset),
579 AddrModeT2_i8, IndexModePost,
580 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
583 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
584 (ins t2addrmode_imm8:$addr),
585 AddrModeT2_i8, IndexModePre,
586 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
588 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
589 (ins GPR:$base, t2am_imm8_offset:$offset),
590 AddrModeT2_i8, IndexModePost,
591 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
596 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
597 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
598 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
602 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
603 "strd", " $src, $addr", []>;
606 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
607 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
608 AddrModeT2_i8, IndexModePre,
609 "str", " $src, [$base, $offset]!", "$base = $base_wb",
611 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
613 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
614 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
615 AddrModeT2_i8, IndexModePost,
616 "str", " $src, [$base], $offset", "$base = $base_wb",
618 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
620 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
621 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
622 AddrModeT2_i8, IndexModePre,
623 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
625 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
627 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
628 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
629 AddrModeT2_i8, IndexModePost,
630 "strh", " $src, [$base], $offset", "$base = $base_wb",
632 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
634 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
635 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
636 AddrModeT2_i8, IndexModePre,
637 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
639 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
641 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
642 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
643 AddrModeT2_i8, IndexModePost,
644 "strb", " $src, [$base], $offset", "$base = $base_wb",
646 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
649 // Address computation and loads and stores in PIC mode.
650 let isNotDuplicable = 1, AddedComplexity = 10 in {
651 let canFoldAsLoad = 1 in
652 def t2PICLDR : T2I_picld<"ldr", UnOpFrag<(load node:$Src)>>;
654 def t2PICLDRH : T2I_picld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
655 def t2PICLDRB : T2I_picld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
656 def t2PICLDRSH : T2I_picld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
657 def t2PICLDRSB : T2I_picld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
659 def t2PICSTR : T2I_picst<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
660 def t2PICSTRH : T2I_picst<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
661 def t2PICSTRB : T2I_picst<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
662 } // isNotDuplicable = 1, AddedComplexity = 10
665 //===----------------------------------------------------------------------===//
666 // Load / store multiple Instructions.
670 def t2LDM : T2XI<(outs),
671 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
672 "ldm${p}${addr:submode} $addr, $dst1", []>;
675 def t2STM : T2XI<(outs),
676 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
677 "stm${p}${addr:submode} $addr, $src1", []>;
679 //===----------------------------------------------------------------------===//
680 // Move Instructions.
683 let neverHasSideEffects = 1 in
684 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
685 "mov", " $dst, $src", []>;
687 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
688 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
689 "mov", " $dst, $src",
690 [(set GPR:$dst, t2_so_imm:$src)]>;
692 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
693 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
694 "movw", " $dst, $src",
695 [(set GPR:$dst, imm0_65535:$src)]>;
697 // FIXME: Also available in ARM mode.
698 let Constraints = "$src = $dst" in
699 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
700 "movt", " $dst, $imm",
702 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
704 //===----------------------------------------------------------------------===//
705 // Extend Instructions.
710 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
711 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
713 defm t2SXTAB : T2I_bin_rrot<"sxtab",
714 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
715 defm t2SXTAH : T2I_bin_rrot<"sxtah",
716 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
718 // TODO: SXT(A){B|H}16
722 let AddedComplexity = 16 in {
723 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
724 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
725 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
727 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
728 (t2UXTB16r_rot GPR:$Src, 24)>;
729 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
730 (t2UXTB16r_rot GPR:$Src, 8)>;
732 defm t2UXTAB : T2I_bin_rrot<"uxtab",
733 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
734 defm t2UXTAH : T2I_bin_rrot<"uxtah",
735 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
738 //===----------------------------------------------------------------------===//
739 // Arithmetic Instructions.
742 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
743 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
745 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
746 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
747 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
749 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
750 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
753 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
754 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
755 defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
757 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
758 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
759 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
760 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
761 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
764 //===----------------------------------------------------------------------===//
765 // Shift and rotate Instructions.
768 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
769 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
770 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
771 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
773 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
774 "mov", " $dst, $src, rrx",
775 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
777 //===----------------------------------------------------------------------===//
778 // Bitwise Instructions.
781 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
782 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
783 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
785 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
787 let Constraints = "$src = $dst" in
788 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
789 "bfc", " $dst, $imm",
790 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
792 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
794 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
796 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
797 let AddedComplexity = 1 in
798 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
801 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
802 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
804 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
805 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
807 def : T2Pat<(t2_so_imm_not:$src),
808 (t2MVNi t2_so_imm_not:$src)>;
810 //===----------------------------------------------------------------------===//
811 // Multiply Instructions.
813 let isCommutable = 1 in
814 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
815 "mul", " $dst, $a, $b",
816 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
818 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
819 "mla", " $dst, $a, $b, $c",
820 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
822 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
823 "mls", " $dst, $a, $b, $c",
824 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
826 // Extra precision multiplies with low / high results
827 let neverHasSideEffects = 1 in {
828 let isCommutable = 1 in {
829 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
830 "smull", " $ldst, $hdst, $a, $b", []>;
832 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
833 "umull", " $ldst, $hdst, $a, $b", []>;
836 // Multiply + accumulate
837 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
838 "smlal", " $ldst, $hdst, $a, $b", []>;
840 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
841 "umlal", " $ldst, $hdst, $a, $b", []>;
843 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
844 "umaal", " $ldst, $hdst, $a, $b", []>;
845 } // neverHasSideEffects
847 // Most significant word multiply
848 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
849 "smmul", " $dst, $a, $b",
850 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
852 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
853 "smmla", " $dst, $a, $b, $c",
854 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
857 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
858 "smmls", " $dst, $a, $b, $c",
859 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
861 multiclass T2I_smul<string opc, PatFrag opnode> {
862 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
863 !strconcat(opc, "bb"), " $dst, $a, $b",
864 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
865 (sext_inreg GPR:$b, i16)))]>;
867 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
868 !strconcat(opc, "bt"), " $dst, $a, $b",
869 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
870 (sra GPR:$b, (i32 16))))]>;
872 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
873 !strconcat(opc, "tb"), " $dst, $a, $b",
874 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
875 (sext_inreg GPR:$b, i16)))]>;
877 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
878 !strconcat(opc, "tt"), " $dst, $a, $b",
879 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
880 (sra GPR:$b, (i32 16))))]>;
882 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
883 !strconcat(opc, "wb"), " $dst, $a, $b",
884 [(set GPR:$dst, (sra (opnode GPR:$a,
885 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
887 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
888 !strconcat(opc, "wt"), " $dst, $a, $b",
889 [(set GPR:$dst, (sra (opnode GPR:$a,
890 (sra GPR:$b, (i32 16))), (i32 16)))]>;
894 multiclass T2I_smla<string opc, PatFrag opnode> {
895 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
896 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
897 [(set GPR:$dst, (add GPR:$acc,
898 (opnode (sext_inreg GPR:$a, i16),
899 (sext_inreg GPR:$b, i16))))]>;
901 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
902 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
903 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
904 (sra GPR:$b, (i32 16)))))]>;
906 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
907 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
908 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
909 (sext_inreg GPR:$b, i16))))]>;
911 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
912 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
913 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
914 (sra GPR:$b, (i32 16)))))]>;
916 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
917 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
918 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
919 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
921 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
922 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
923 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
924 (sra GPR:$b, (i32 16))), (i32 16))))]>;
927 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
928 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
930 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
931 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
934 //===----------------------------------------------------------------------===//
935 // Misc. Arithmetic Instructions.
938 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
939 "clz", " $dst, $src",
940 [(set GPR:$dst, (ctlz GPR:$src))]>;
942 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
943 "rev", " $dst, $src",
944 [(set GPR:$dst, (bswap GPR:$src))]>;
946 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
947 "rev16", " $dst, $src",
949 (or (and (srl GPR:$src, (i32 8)), 0xFF),
950 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
951 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
952 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
954 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
955 "revsh", " $dst, $src",
958 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
959 (shl GPR:$src, (i32 8))), i16))]>;
961 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
962 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
963 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
964 (and (shl GPR:$src2, (i32 imm:$shamt)),
967 // Alternate cases for PKHBT where identities eliminate some nodes.
968 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
969 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
970 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
971 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
973 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
974 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
975 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
976 (and (sra GPR:$src2, imm16_31:$shamt),
979 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
980 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
981 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
982 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
983 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
984 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
985 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
987 //===----------------------------------------------------------------------===//
988 // Comparison Instructions...
991 defm t2CMP : T2I_cmp_is<"cmp",
992 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
993 defm t2CMPz : T2I_cmp_is<"cmp",
994 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
996 defm t2CMN : T2I_cmp_is<"cmn",
997 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
998 defm t2CMNz : T2I_cmp_is<"cmn",
999 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1001 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1002 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1004 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1005 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1007 defm t2TST : T2I_cmp_is<"tst",
1008 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1009 defm t2TEQ : T2I_cmp_is<"teq",
1010 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1012 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1013 // Short range conditional branch. Looks awesome for loops. Need to figure
1014 // out how to use this one.
1017 // Conditional moves
1018 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1019 // a two-value operand where a dag node expects two operands. :(
1020 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
1021 "mov", " $dst, $true",
1022 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1023 RegConstraint<"$false = $dst">;
1025 def t2MOVCCs : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_reg:$true),
1026 "mov", " $dst, $true",
1027 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1028 RegConstraint<"$false = $dst">;
1030 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1031 "mov", " $dst, $true",
1032 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1033 RegConstraint<"$false = $dst">;
1035 //===----------------------------------------------------------------------===//
1039 // __aeabi_read_tp preserves the registers r1-r3.
1041 Defs = [R0, R12, LR, CPSR] in {
1042 def t2TPsoft : T2XI<(outs), (ins),
1043 "bl __aeabi_read_tp",
1044 [(set R0, ARMthread_pointer)]>;
1047 //===----------------------------------------------------------------------===//
1048 // Control-Flow Instructions
1051 let isReturn = 1, isTerminator = 1 in
1052 def t2BX_RET : T2XI<(outs), (ins), "bx lr", [(ARMretflag)]>;
1054 // On non-Darwin platforms R9 is callee-saved.
1056 Defs = [R0, R1, R2, R3, R12, LR,
1057 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1058 def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
1060 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
1062 def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
1064 [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
1067 // On Darwin R9 is call-clobbered.
1069 Defs = [R0, R1, R2, R3, R9, R12, LR,
1070 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1071 def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
1073 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
1075 def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
1077 [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
1080 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1081 let isPredicable = 1 in
1082 def t2B : T2XI<(outs), (ins brtarget:$target),
1086 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1087 def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1088 "mov pc, $target \n$jt",
1089 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1093 (ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id),
1094 "ldr pc, $target \n$jt",
1095 [(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt,
1100 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1101 "add pc, $target, $idx \n$jt",
1102 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>;
1103 } // isNotDuplicate, isIndirectBranch
1104 } // isBranch, isTerminator, isBarrier
1106 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1107 // a two-value operand where a dag node expects two operands. :(
1108 let isBranch = 1, isTerminator = 1 in
1109 def t2Bcc : T2I<(outs), (ins brtarget:$target),
1111 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1113 //===----------------------------------------------------------------------===//
1114 // Non-Instruction Patterns
1117 // ConstantPool, GlobalAddress, and JumpTable
1118 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1119 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1120 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1121 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1123 // Large immediate handling.
1125 def : T2Pat<(i32 imm:$src),
1126 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;