1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
66 // described for so_imm_notSext def below, with sign extension from 16
68 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
69 APInt apIntN = N->getAPIntValue();
70 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
71 return CurDAG->getTargetConstant(~N16bitSignExt, MVT::i32);
74 // t2_so_imm - Match a 32-bit immediate operand, which is an
75 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
76 // immediate splatted into multiple bytes of the word.
77 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
78 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
79 return ARM_AM::getT2SOImmVal(Imm) != -1;
81 let ParserMatchClass = t2_so_imm_asmoperand;
82 let EncoderMethod = "getT2SOImmOpValue";
83 let DecoderMethod = "DecodeT2SOImm";
86 // t2_so_imm_not - Match an immediate that is a complement
88 // Note: this pattern doesn't require an encoder method and such, as it's
89 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
90 // is handled by the destination instructions, which use t2_so_imm.
91 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
92 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
93 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
94 }], t2_so_imm_not_XFORM> {
95 let ParserMatchClass = t2_so_imm_not_asmoperand;
98 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
99 // if the upper 16 bits are zero.
100 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
101 APInt apIntN = N->getAPIntValue();
102 if (!apIntN.isIntN(16)) return false;
103 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
104 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
105 }], t2_so_imm_notSext16_XFORM> {
106 let ParserMatchClass = t2_so_imm_not_asmoperand;
109 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
110 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
111 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
112 int64_t Value = -(int)N->getZExtValue();
113 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
114 }], t2_so_imm_neg_XFORM> {
115 let ParserMatchClass = t2_so_imm_neg_asmoperand;
118 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
119 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
120 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
121 return Imm >= 0 && Imm < 4096;
123 let ParserMatchClass = imm0_4095_asmoperand;
126 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
127 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
128 return (uint32_t)(-N->getZExtValue()) < 4096;
130 let ParserMatchClass = imm0_4095_neg_asmoperand;
133 def imm1_255_neg : PatLeaf<(i32 imm), [{
134 uint32_t Val = -N->getZExtValue();
135 return (Val > 0 && Val < 255);
138 def imm0_255_not : PatLeaf<(i32 imm), [{
139 return (uint32_t)(~N->getZExtValue()) < 255;
142 def lo5AllOne : PatLeaf<(i32 imm), [{
143 // Returns true if all low 5-bits are 1.
144 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
147 // Define Thumb2 specific addressing modes.
149 // t2addrmode_imm12 := reg + imm12
150 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
151 def t2addrmode_imm12 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
153 let PrintMethod = "printAddrModeImm12Operand<false>";
154 let EncoderMethod = "getAddrModeImm12OpValue";
155 let DecoderMethod = "DecodeT2AddrModeImm12";
156 let ParserMatchClass = t2addrmode_imm12_asmoperand;
157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
160 // t2ldrlabel := imm12
161 def t2ldrlabel : Operand<i32> {
162 let EncoderMethod = "getAddrModeImm12OpValue";
163 let PrintMethod = "printThumbLdrLabelOperand";
166 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
167 def t2ldr_pcrel_imm12 : Operand<i32> {
168 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
169 // used for assembler pseudo instruction and maps to t2ldrlabel, so
170 // doesn't need encoder or print methods of its own.
173 // ADR instruction labels.
174 def t2adrlabel : Operand<i32> {
175 let EncoderMethod = "getT2AdrLabelOpValue";
176 let PrintMethod = "printAdrLabelOperand<0>";
179 // t2addrmode_posimm8 := reg + imm8
180 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
181 def t2addrmode_posimm8 : Operand<i32> {
182 let PrintMethod = "printT2AddrModeImm8Operand<false>";
183 let EncoderMethod = "getT2AddrModeImm8OpValue";
184 let DecoderMethod = "DecodeT2AddrModeImm8";
185 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
189 // t2addrmode_negimm8 := reg - imm8
190 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
191 def t2addrmode_negimm8 : Operand<i32>,
192 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
193 let PrintMethod = "printT2AddrModeImm8Operand<false>";
194 let EncoderMethod = "getT2AddrModeImm8OpValue";
195 let DecoderMethod = "DecodeT2AddrModeImm8";
196 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
197 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
200 // t2addrmode_imm8 := reg +/- imm8
201 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
202 class T2AddrMode_Imm8 : Operand<i32>,
203 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
204 let EncoderMethod = "getT2AddrModeImm8OpValue";
205 let DecoderMethod = "DecodeT2AddrModeImm8";
206 let ParserMatchClass = MemImm8OffsetAsmOperand;
207 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
210 def t2addrmode_imm8 : T2AddrMode_Imm8 {
211 let PrintMethod = "printT2AddrModeImm8Operand<false>";
214 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
215 let PrintMethod = "printT2AddrModeImm8Operand<true>";
218 def t2am_imm8_offset : Operand<i32>,
219 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
220 [], [SDNPWantRoot]> {
221 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
222 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
223 let DecoderMethod = "DecodeT2Imm8";
226 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
227 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
228 class T2AddrMode_Imm8s4 : Operand<i32> {
229 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
230 let DecoderMethod = "DecodeT2AddrModeImm8s4";
231 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
232 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
235 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
236 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
239 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
240 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
243 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
244 def t2am_imm8s4_offset : Operand<i32> {
245 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
246 let EncoderMethod = "getT2Imm8s4OpValue";
247 let DecoderMethod = "DecodeT2Imm8S4";
250 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
251 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
252 let Name = "MemImm0_1020s4Offset";
254 def t2addrmode_imm0_1020s4 : Operand<i32> {
255 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
256 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
257 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
258 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
259 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
262 // t2addrmode_so_reg := reg + (reg << imm2)
263 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
264 def t2addrmode_so_reg : Operand<i32>,
265 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
266 let PrintMethod = "printT2AddrModeSoRegOperand";
267 let EncoderMethod = "getT2AddrModeSORegOpValue";
268 let DecoderMethod = "DecodeT2AddrModeSOReg";
269 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
270 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
273 // Addresses for the TBB/TBH instructions.
274 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
275 def addrmode_tbb : Operand<i32> {
276 let PrintMethod = "printAddrModeTBB";
277 let ParserMatchClass = addrmode_tbb_asmoperand;
278 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
280 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
281 def addrmode_tbh : Operand<i32> {
282 let PrintMethod = "printAddrModeTBH";
283 let ParserMatchClass = addrmode_tbh_asmoperand;
284 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
287 //===----------------------------------------------------------------------===//
288 // Multiclass helpers...
292 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
293 string opc, string asm, list<dag> pattern>
294 : T2I<oops, iops, itin, opc, asm, pattern> {
299 let Inst{26} = imm{11};
300 let Inst{14-12} = imm{10-8};
301 let Inst{7-0} = imm{7-0};
305 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
306 string opc, string asm, list<dag> pattern>
307 : T2sI<oops, iops, itin, opc, asm, pattern> {
313 let Inst{26} = imm{11};
314 let Inst{14-12} = imm{10-8};
315 let Inst{7-0} = imm{7-0};
318 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
319 string opc, string asm, list<dag> pattern>
320 : T2I<oops, iops, itin, opc, asm, pattern> {
324 let Inst{19-16} = Rn;
325 let Inst{26} = imm{11};
326 let Inst{14-12} = imm{10-8};
327 let Inst{7-0} = imm{7-0};
331 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
332 string opc, string asm, list<dag> pattern>
333 : T2I<oops, iops, itin, opc, asm, pattern> {
338 let Inst{3-0} = ShiftedRm{3-0};
339 let Inst{5-4} = ShiftedRm{6-5};
340 let Inst{14-12} = ShiftedRm{11-9};
341 let Inst{7-6} = ShiftedRm{8-7};
344 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
345 string opc, string asm, list<dag> pattern>
346 : T2sI<oops, iops, itin, opc, asm, pattern> {
351 let Inst{3-0} = ShiftedRm{3-0};
352 let Inst{5-4} = ShiftedRm{6-5};
353 let Inst{14-12} = ShiftedRm{11-9};
354 let Inst{7-6} = ShiftedRm{8-7};
357 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
358 string opc, string asm, list<dag> pattern>
359 : T2I<oops, iops, itin, opc, asm, pattern> {
363 let Inst{19-16} = Rn;
364 let Inst{3-0} = ShiftedRm{3-0};
365 let Inst{5-4} = ShiftedRm{6-5};
366 let Inst{14-12} = ShiftedRm{11-9};
367 let Inst{7-6} = ShiftedRm{8-7};
370 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
371 string opc, string asm, list<dag> pattern>
372 : T2I<oops, iops, itin, opc, asm, pattern> {
380 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
381 string opc, string asm, list<dag> pattern>
382 : T2sI<oops, iops, itin, opc, asm, pattern> {
390 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
391 string opc, string asm, list<dag> pattern>
392 : T2I<oops, iops, itin, opc, asm, pattern> {
396 let Inst{19-16} = Rn;
401 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
402 string opc, string asm, list<dag> pattern>
403 : T2I<oops, iops, itin, opc, asm, pattern> {
409 let Inst{19-16} = Rn;
410 let Inst{26} = imm{11};
411 let Inst{14-12} = imm{10-8};
412 let Inst{7-0} = imm{7-0};
415 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
416 string opc, string asm, list<dag> pattern>
417 : T2sI<oops, iops, itin, opc, asm, pattern> {
423 let Inst{19-16} = Rn;
424 let Inst{26} = imm{11};
425 let Inst{14-12} = imm{10-8};
426 let Inst{7-0} = imm{7-0};
429 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
430 string opc, string asm, list<dag> pattern>
431 : T2I<oops, iops, itin, opc, asm, pattern> {
438 let Inst{14-12} = imm{4-2};
439 let Inst{7-6} = imm{1-0};
442 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
443 string opc, string asm, list<dag> pattern>
444 : T2sI<oops, iops, itin, opc, asm, pattern> {
451 let Inst{14-12} = imm{4-2};
452 let Inst{7-6} = imm{1-0};
455 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
456 string opc, string asm, list<dag> pattern>
457 : T2I<oops, iops, itin, opc, asm, pattern> {
463 let Inst{19-16} = Rn;
467 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
468 string opc, string asm, list<dag> pattern>
469 : T2sI<oops, iops, itin, opc, asm, pattern> {
475 let Inst{19-16} = Rn;
479 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
480 string opc, string asm, list<dag> pattern>
481 : T2I<oops, iops, itin, opc, asm, pattern> {
487 let Inst{19-16} = Rn;
488 let Inst{3-0} = ShiftedRm{3-0};
489 let Inst{5-4} = ShiftedRm{6-5};
490 let Inst{14-12} = ShiftedRm{11-9};
491 let Inst{7-6} = ShiftedRm{8-7};
494 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : T2sI<oops, iops, itin, opc, asm, pattern> {
502 let Inst{19-16} = Rn;
503 let Inst{3-0} = ShiftedRm{3-0};
504 let Inst{5-4} = ShiftedRm{6-5};
505 let Inst{14-12} = ShiftedRm{11-9};
506 let Inst{7-6} = ShiftedRm{8-7};
509 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
510 string opc, string asm, list<dag> pattern>
511 : T2I<oops, iops, itin, opc, asm, pattern> {
517 let Inst{19-16} = Rn;
518 let Inst{15-12} = Ra;
523 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
524 dag oops, dag iops, InstrItinClass itin,
525 string opc, string asm, list<dag> pattern>
526 : T2I<oops, iops, itin, opc, asm, pattern> {
532 let Inst{31-23} = 0b111110111;
533 let Inst{22-20} = opc22_20;
534 let Inst{19-16} = Rn;
535 let Inst{15-12} = RdLo;
536 let Inst{11-8} = RdHi;
537 let Inst{7-4} = opc7_4;
540 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
541 dag oops, dag iops, InstrItinClass itin,
542 string opc, string asm, list<dag> pattern>
543 : T2I<oops, iops, itin, opc, asm, pattern> {
549 let Inst{31-23} = 0b111110111;
550 let Inst{22-20} = opc22_20;
551 let Inst{19-16} = Rn;
552 let Inst{15-12} = RdLo;
553 let Inst{11-8} = RdHi;
554 let Inst{7-4} = opc7_4;
559 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
560 /// binary operation that produces a value. These are predicable and can be
561 /// changed to modify CPSR.
562 multiclass T2I_bin_irs<bits<4> opcod, string opc,
563 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
564 PatFrag opnode, bit Commutable = 0,
567 def ri : T2sTwoRegImm<
568 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
569 opc, "\t$Rd, $Rn, $imm",
570 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
571 Sched<[WriteALU, ReadALU]> {
572 let Inst{31-27} = 0b11110;
574 let Inst{24-21} = opcod;
578 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
579 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
580 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
581 Sched<[WriteALU, ReadALU, ReadALU]> {
582 let isCommutable = Commutable;
583 let Inst{31-27} = 0b11101;
584 let Inst{26-25} = 0b01;
585 let Inst{24-21} = opcod;
586 let Inst{14-12} = 0b000; // imm3
587 let Inst{7-6} = 0b00; // imm2
588 let Inst{5-4} = 0b00; // type
591 def rs : T2sTwoRegShiftedReg<
592 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
593 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
594 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
595 Sched<[WriteALUsi, ReadALU]> {
596 let Inst{31-27} = 0b11101;
597 let Inst{26-25} = 0b01;
598 let Inst{24-21} = opcod;
600 // Assembly aliases for optional destination operand when it's the same
601 // as the source operand.
602 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
603 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
604 t2_so_imm:$imm, pred:$p,
606 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
607 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
610 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
611 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
612 t2_so_reg:$shift, pred:$p,
616 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
617 // the ".w" suffix to indicate that they are wide.
618 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
619 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
620 PatFrag opnode, bit Commutable = 0> :
621 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
622 // Assembler aliases w/ the ".w" suffix.
623 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
624 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
626 // Assembler aliases w/o the ".w" suffix.
627 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
628 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
630 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
631 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
632 pred:$p, cc_out:$s)>;
634 // and with the optional destination operand, too.
635 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
636 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
637 pred:$p, cc_out:$s)>;
638 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
639 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
641 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
642 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
643 pred:$p, cc_out:$s)>;
646 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
647 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
648 /// it is equivalent to the T2I_bin_irs counterpart.
649 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
651 def ri : T2sTwoRegImm<
652 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
653 opc, ".w\t$Rd, $Rn, $imm",
654 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
655 Sched<[WriteALU, ReadALU]> {
656 let Inst{31-27} = 0b11110;
658 let Inst{24-21} = opcod;
662 def rr : T2sThreeReg<
663 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
664 opc, "\t$Rd, $Rn, $Rm",
665 [/* For disassembly only; pattern left blank */]>,
666 Sched<[WriteALU, ReadALU, ReadALU]> {
667 let Inst{31-27} = 0b11101;
668 let Inst{26-25} = 0b01;
669 let Inst{24-21} = opcod;
670 let Inst{14-12} = 0b000; // imm3
671 let Inst{7-6} = 0b00; // imm2
672 let Inst{5-4} = 0b00; // type
675 def rs : T2sTwoRegShiftedReg<
676 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
677 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
678 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
679 Sched<[WriteALUsi, ReadALU]> {
680 let Inst{31-27} = 0b11101;
681 let Inst{26-25} = 0b01;
682 let Inst{24-21} = opcod;
686 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
687 /// instruction modifies the CPSR register.
689 /// These opcodes will be converted to the real non-S opcodes by
690 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
691 let hasPostISelHook = 1, Defs = [CPSR] in {
692 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
693 InstrItinClass iis, PatFrag opnode,
694 bit Commutable = 0> {
696 def ri : t2PseudoInst<(outs rGPR:$Rd),
697 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
699 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
701 Sched<[WriteALU, ReadALU]>;
703 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
705 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
707 Sched<[WriteALU, ReadALU, ReadALU]> {
708 let isCommutable = Commutable;
711 def rs : t2PseudoInst<(outs rGPR:$Rd),
712 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
714 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
715 t2_so_reg:$ShiftedRm))]>,
716 Sched<[WriteALUsi, ReadALUsr]>;
720 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
721 /// operands are reversed.
722 let hasPostISelHook = 1, Defs = [CPSR] in {
723 multiclass T2I_rbin_s_is<PatFrag opnode> {
725 def ri : t2PseudoInst<(outs rGPR:$Rd),
726 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
728 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
730 Sched<[WriteALU, ReadALU]>;
732 def rs : t2PseudoInst<(outs rGPR:$Rd),
733 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
735 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
737 Sched<[WriteALUsi, ReadALU]>;
741 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
742 /// patterns for a binary operation that produces a value.
743 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
744 bit Commutable = 0> {
746 // The register-immediate version is re-materializable. This is useful
747 // in particular for taking the address of a local.
748 let isReMaterializable = 1 in {
749 def ri : T2sTwoRegImm<
750 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
751 opc, ".w\t$Rd, $Rn, $imm",
752 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
753 Sched<[WriteALU, ReadALU]> {
754 let Inst{31-27} = 0b11110;
757 let Inst{23-21} = op23_21;
763 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
764 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
765 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
766 Sched<[WriteALU, ReadALU]> {
770 let Inst{31-27} = 0b11110;
771 let Inst{26} = imm{11};
772 let Inst{25-24} = 0b10;
773 let Inst{23-21} = op23_21;
774 let Inst{20} = 0; // The S bit.
775 let Inst{19-16} = Rn;
777 let Inst{14-12} = imm{10-8};
779 let Inst{7-0} = imm{7-0};
782 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
783 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
784 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
785 Sched<[WriteALU, ReadALU, ReadALU]> {
786 let isCommutable = Commutable;
787 let Inst{31-27} = 0b11101;
788 let Inst{26-25} = 0b01;
790 let Inst{23-21} = op23_21;
791 let Inst{14-12} = 0b000; // imm3
792 let Inst{7-6} = 0b00; // imm2
793 let Inst{5-4} = 0b00; // type
796 def rs : T2sTwoRegShiftedReg<
797 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
798 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
799 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
800 Sched<[WriteALUsi, ReadALU]> {
801 let Inst{31-27} = 0b11101;
802 let Inst{26-25} = 0b01;
804 let Inst{23-21} = op23_21;
808 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
809 /// for a binary operation that produces a value and use the carry
810 /// bit. It's not predicable.
811 let Defs = [CPSR], Uses = [CPSR] in {
812 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
813 bit Commutable = 0> {
815 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
816 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
817 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
818 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
819 let Inst{31-27} = 0b11110;
821 let Inst{24-21} = opcod;
825 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
826 opc, ".w\t$Rd, $Rn, $Rm",
827 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
828 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
829 let isCommutable = Commutable;
830 let Inst{31-27} = 0b11101;
831 let Inst{26-25} = 0b01;
832 let Inst{24-21} = opcod;
833 let Inst{14-12} = 0b000; // imm3
834 let Inst{7-6} = 0b00; // imm2
835 let Inst{5-4} = 0b00; // type
838 def rs : T2sTwoRegShiftedReg<
839 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
840 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
841 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
842 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
843 let Inst{31-27} = 0b11101;
844 let Inst{26-25} = 0b01;
845 let Inst{24-21} = opcod;
850 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
851 // rotate operation that produces a value.
852 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
854 def ri : T2sTwoRegShiftImm<
855 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
856 opc, ".w\t$Rd, $Rm, $imm",
857 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
859 let Inst{31-27} = 0b11101;
860 let Inst{26-21} = 0b010010;
861 let Inst{19-16} = 0b1111; // Rn
862 let Inst{5-4} = opcod;
865 def rr : T2sThreeReg<
866 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
867 opc, ".w\t$Rd, $Rn, $Rm",
868 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
870 let Inst{31-27} = 0b11111;
871 let Inst{26-23} = 0b0100;
872 let Inst{22-21} = opcod;
873 let Inst{15-12} = 0b1111;
874 let Inst{7-4} = 0b0000;
877 // Optional destination register
878 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
879 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
881 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
882 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
885 // Assembler aliases w/o the ".w" suffix.
886 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
887 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
889 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
890 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
893 // and with the optional destination operand, too.
894 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
895 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
897 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
898 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
902 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
903 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
904 /// a explicit result, only implicitly set CPSR.
905 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
906 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
908 let isCompare = 1, Defs = [CPSR] in {
910 def ri : T2OneRegCmpImm<
911 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
912 opc, ".w\t$Rn, $imm",
913 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
914 let Inst{31-27} = 0b11110;
916 let Inst{24-21} = opcod;
917 let Inst{20} = 1; // The S bit.
919 let Inst{11-8} = 0b1111; // Rd
922 def rr : T2TwoRegCmp<
923 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
925 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
926 let Inst{31-27} = 0b11101;
927 let Inst{26-25} = 0b01;
928 let Inst{24-21} = opcod;
929 let Inst{20} = 1; // The S bit.
930 let Inst{14-12} = 0b000; // imm3
931 let Inst{11-8} = 0b1111; // Rd
932 let Inst{7-6} = 0b00; // imm2
933 let Inst{5-4} = 0b00; // type
936 def rs : T2OneRegCmpShiftedReg<
937 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
938 opc, ".w\t$Rn, $ShiftedRm",
939 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
940 Sched<[WriteCMPsi]> {
941 let Inst{31-27} = 0b11101;
942 let Inst{26-25} = 0b01;
943 let Inst{24-21} = opcod;
944 let Inst{20} = 1; // The S bit.
945 let Inst{11-8} = 0b1111; // Rd
949 // Assembler aliases w/o the ".w" suffix.
950 // No alias here for 'rr' version as not all instantiations of this
951 // multiclass want one (CMP in particular, does not).
952 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
953 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
954 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
955 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
958 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
959 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
960 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
962 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
963 opc, ".w\t$Rt, $addr",
964 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
967 let Inst{31-25} = 0b1111100;
968 let Inst{24} = signed;
970 let Inst{22-21} = opcod;
971 let Inst{20} = 1; // load
972 let Inst{19-16} = addr{16-13}; // Rn
973 let Inst{15-12} = Rt;
974 let Inst{11-0} = addr{11-0}; // imm
976 let DecoderMethod = "DecodeT2LoadImm12";
978 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
980 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
983 let Inst{31-27} = 0b11111;
984 let Inst{26-25} = 0b00;
985 let Inst{24} = signed;
987 let Inst{22-21} = opcod;
988 let Inst{20} = 1; // load
989 let Inst{19-16} = addr{12-9}; // Rn
990 let Inst{15-12} = Rt;
992 // Offset: index==TRUE, wback==FALSE
993 let Inst{10} = 1; // The P bit.
994 let Inst{9} = addr{8}; // U
995 let Inst{8} = 0; // The W bit.
996 let Inst{7-0} = addr{7-0}; // imm
998 let DecoderMethod = "DecodeT2LoadImm8";
1000 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1001 opc, ".w\t$Rt, $addr",
1002 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
1003 let Inst{31-27} = 0b11111;
1004 let Inst{26-25} = 0b00;
1005 let Inst{24} = signed;
1007 let Inst{22-21} = opcod;
1008 let Inst{20} = 1; // load
1009 let Inst{11-6} = 0b000000;
1012 let Inst{15-12} = Rt;
1015 let Inst{19-16} = addr{9-6}; // Rn
1016 let Inst{3-0} = addr{5-2}; // Rm
1017 let Inst{5-4} = addr{1-0}; // imm
1019 let DecoderMethod = "DecodeT2LoadShift";
1022 // pci variant is very similar to i12, but supports negative offsets
1024 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1025 opc, ".w\t$Rt, $addr",
1026 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
1027 let isReMaterializable = 1;
1028 let Inst{31-27} = 0b11111;
1029 let Inst{26-25} = 0b00;
1030 let Inst{24} = signed;
1031 let Inst{22-21} = opcod;
1032 let Inst{20} = 1; // load
1033 let Inst{19-16} = 0b1111; // Rn
1036 let Inst{15-12} = Rt{3-0};
1039 let Inst{23} = addr{12}; // add = (U == '1')
1040 let Inst{11-0} = addr{11-0};
1042 let DecoderMethod = "DecodeT2LoadLabel";
1046 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1047 multiclass T2I_st<bits<2> opcod, string opc,
1048 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1050 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1051 opc, ".w\t$Rt, $addr",
1052 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1053 let Inst{31-27} = 0b11111;
1054 let Inst{26-23} = 0b0001;
1055 let Inst{22-21} = opcod;
1056 let Inst{20} = 0; // !load
1059 let Inst{15-12} = Rt;
1062 let addr{12} = 1; // add = TRUE
1063 let Inst{19-16} = addr{16-13}; // Rn
1064 let Inst{23} = addr{12}; // U
1065 let Inst{11-0} = addr{11-0}; // imm
1067 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1068 opc, "\t$Rt, $addr",
1069 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1070 let Inst{31-27} = 0b11111;
1071 let Inst{26-23} = 0b0000;
1072 let Inst{22-21} = opcod;
1073 let Inst{20} = 0; // !load
1075 // Offset: index==TRUE, wback==FALSE
1076 let Inst{10} = 1; // The P bit.
1077 let Inst{8} = 0; // The W bit.
1080 let Inst{15-12} = Rt;
1083 let Inst{19-16} = addr{12-9}; // Rn
1084 let Inst{9} = addr{8}; // U
1085 let Inst{7-0} = addr{7-0}; // imm
1087 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1088 opc, ".w\t$Rt, $addr",
1089 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1090 let Inst{31-27} = 0b11111;
1091 let Inst{26-23} = 0b0000;
1092 let Inst{22-21} = opcod;
1093 let Inst{20} = 0; // !load
1094 let Inst{11-6} = 0b000000;
1097 let Inst{15-12} = Rt;
1100 let Inst{19-16} = addr{9-6}; // Rn
1101 let Inst{3-0} = addr{5-2}; // Rm
1102 let Inst{5-4} = addr{1-0}; // imm
1106 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1107 /// register and one whose operand is a register rotated by 8/16/24.
1108 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1109 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1110 opc, ".w\t$Rd, $Rm$rot",
1111 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1112 Requires<[IsThumb2]> {
1113 let Inst{31-27} = 0b11111;
1114 let Inst{26-23} = 0b0100;
1115 let Inst{22-20} = opcod;
1116 let Inst{19-16} = 0b1111; // Rn
1117 let Inst{15-12} = 0b1111;
1121 let Inst{5-4} = rot{1-0}; // rotate
1124 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1125 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1126 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1127 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1128 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1129 Requires<[HasT2ExtractPack, IsThumb2]> {
1131 let Inst{31-27} = 0b11111;
1132 let Inst{26-23} = 0b0100;
1133 let Inst{22-20} = opcod;
1134 let Inst{19-16} = 0b1111; // Rn
1135 let Inst{15-12} = 0b1111;
1137 let Inst{5-4} = rot;
1140 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1142 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1143 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1144 opc, "\t$Rd, $Rm$rot", []>,
1145 Requires<[IsThumb2, HasT2ExtractPack]> {
1147 let Inst{31-27} = 0b11111;
1148 let Inst{26-23} = 0b0100;
1149 let Inst{22-20} = opcod;
1150 let Inst{19-16} = 0b1111; // Rn
1151 let Inst{15-12} = 0b1111;
1153 let Inst{5-4} = rot;
1156 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1157 /// register and one whose operand is a register rotated by 8/16/24.
1158 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1159 : T2ThreeReg<(outs rGPR:$Rd),
1160 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1161 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1162 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1163 Requires<[HasT2ExtractPack, IsThumb2]> {
1165 let Inst{31-27} = 0b11111;
1166 let Inst{26-23} = 0b0100;
1167 let Inst{22-20} = opcod;
1168 let Inst{15-12} = 0b1111;
1170 let Inst{5-4} = rot;
1173 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1174 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1175 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1177 let Inst{31-27} = 0b11111;
1178 let Inst{26-23} = 0b0100;
1179 let Inst{22-20} = opcod;
1180 let Inst{15-12} = 0b1111;
1182 let Inst{5-4} = rot;
1185 //===----------------------------------------------------------------------===//
1187 //===----------------------------------------------------------------------===//
1189 //===----------------------------------------------------------------------===//
1190 // Miscellaneous Instructions.
1193 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1194 string asm, list<dag> pattern>
1195 : T2XI<oops, iops, itin, asm, pattern> {
1199 let Inst{11-8} = Rd;
1200 let Inst{26} = label{11};
1201 let Inst{14-12} = label{10-8};
1202 let Inst{7-0} = label{7-0};
1205 // LEApcrel - Load a pc-relative address into a register without offending the
1207 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1208 (ins t2adrlabel:$addr, pred:$p),
1209 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1210 Sched<[WriteALU, ReadALU]> {
1211 let Inst{31-27} = 0b11110;
1212 let Inst{25-24} = 0b10;
1213 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1216 let Inst{19-16} = 0b1111; // Rn
1221 let Inst{11-8} = Rd;
1222 let Inst{23} = addr{12};
1223 let Inst{21} = addr{12};
1224 let Inst{26} = addr{11};
1225 let Inst{14-12} = addr{10-8};
1226 let Inst{7-0} = addr{7-0};
1228 let DecoderMethod = "DecodeT2Adr";
1231 let neverHasSideEffects = 1, isReMaterializable = 1 in
1232 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1233 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1234 let hasSideEffects = 1 in
1235 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1236 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1238 []>, Sched<[WriteALU, ReadALU]>;
1241 //===----------------------------------------------------------------------===//
1242 // Load / store Instructions.
1246 let canFoldAsLoad = 1, isReMaterializable = 1 in
1247 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1248 UnOpFrag<(load node:$Src)>>;
1250 // Loads with zero extension
1251 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1252 GPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1253 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1254 GPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1256 // Loads with sign extension
1257 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1258 GPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1259 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1260 GPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1262 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1264 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1265 (ins t2addrmode_imm8s4:$addr),
1266 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1267 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1269 // zextload i1 -> zextload i8
1270 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1271 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1272 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1273 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1274 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1275 (t2LDRBs t2addrmode_so_reg:$addr)>;
1276 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1277 (t2LDRBpci tconstpool:$addr)>;
1279 // extload -> zextload
1280 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1282 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1283 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1284 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1285 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1286 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1287 (t2LDRBs t2addrmode_so_reg:$addr)>;
1288 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1289 (t2LDRBpci tconstpool:$addr)>;
1291 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1292 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1293 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1294 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1295 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1296 (t2LDRBs t2addrmode_so_reg:$addr)>;
1297 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1298 (t2LDRBpci tconstpool:$addr)>;
1300 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1301 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1302 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1303 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1304 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1305 (t2LDRHs t2addrmode_so_reg:$addr)>;
1306 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1307 (t2LDRHpci tconstpool:$addr)>;
1309 // FIXME: The destination register of the loads and stores can't be PC, but
1310 // can be SP. We need another regclass (similar to rGPR) to represent
1311 // that. Not a pressing issue since these are selected manually,
1316 let mayLoad = 1, neverHasSideEffects = 1 in {
1317 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1318 (ins t2addrmode_imm8_pre:$addr),
1319 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1320 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1322 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1325 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1326 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1327 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1328 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1330 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1331 (ins t2addrmode_imm8_pre:$addr),
1332 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1333 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1335 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1337 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1338 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1339 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1340 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1342 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1343 (ins t2addrmode_imm8_pre:$addr),
1344 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1345 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1347 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1349 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1350 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1351 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1352 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1354 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1355 (ins t2addrmode_imm8_pre:$addr),
1356 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1357 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1359 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1361 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1362 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1363 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1364 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1366 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1367 (ins t2addrmode_imm8_pre:$addr),
1368 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1369 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1371 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1373 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1374 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1375 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1376 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1377 } // mayLoad = 1, neverHasSideEffects = 1
1379 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1380 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1381 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1382 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1383 "\t$Rt, $addr", []> {
1386 let Inst{31-27} = 0b11111;
1387 let Inst{26-25} = 0b00;
1388 let Inst{24} = signed;
1390 let Inst{22-21} = type;
1391 let Inst{20} = 1; // load
1392 let Inst{19-16} = addr{12-9};
1393 let Inst{15-12} = Rt;
1395 let Inst{10-8} = 0b110; // PUW.
1396 let Inst{7-0} = addr{7-0};
1398 let DecoderMethod = "DecodeT2LoadT";
1401 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1402 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1403 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1404 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1405 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1408 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1409 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1410 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1411 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1412 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1413 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1416 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1417 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1418 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1419 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1423 let mayStore = 1, neverHasSideEffects = 1 in {
1424 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1425 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1426 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1427 "str", "\t$Rt, $addr!",
1428 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1429 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1431 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1432 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1433 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1434 "strh", "\t$Rt, $addr!",
1435 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1436 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1439 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1440 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1441 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1442 "strb", "\t$Rt, $addr!",
1443 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1444 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1446 } // mayStore = 1, neverHasSideEffects = 1
1448 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1449 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1450 t2am_imm8_offset:$offset),
1451 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1452 "str", "\t$Rt, $Rn$offset",
1453 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1454 [(set GPRnopc:$Rn_wb,
1455 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1456 t2am_imm8_offset:$offset))]>;
1458 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1459 (ins rGPR:$Rt, addr_offset_none:$Rn,
1460 t2am_imm8_offset:$offset),
1461 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1462 "strh", "\t$Rt, $Rn$offset",
1463 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1464 [(set GPRnopc:$Rn_wb,
1465 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1466 t2am_imm8_offset:$offset))]>;
1468 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1469 (ins rGPR:$Rt, addr_offset_none:$Rn,
1470 t2am_imm8_offset:$offset),
1471 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1472 "strb", "\t$Rt, $Rn$offset",
1473 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1474 [(set GPRnopc:$Rn_wb,
1475 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1476 t2am_imm8_offset:$offset))]>;
1478 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1479 // put the patterns on the instruction definitions directly as ISel wants
1480 // the address base and offset to be separate operands, not a single
1481 // complex operand like we represent the instructions themselves. The
1482 // pseudos map between the two.
1483 let usesCustomInserter = 1,
1484 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1485 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1486 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1488 [(set GPRnopc:$Rn_wb,
1489 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1490 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1491 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1493 [(set GPRnopc:$Rn_wb,
1494 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1495 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1496 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1498 [(set GPRnopc:$Rn_wb,
1499 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1502 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1504 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1505 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1506 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1507 "\t$Rt, $addr", []> {
1508 let Inst{31-27} = 0b11111;
1509 let Inst{26-25} = 0b00;
1510 let Inst{24} = 0; // not signed
1512 let Inst{22-21} = type;
1513 let Inst{20} = 0; // store
1515 let Inst{10-8} = 0b110; // PUW
1519 let Inst{15-12} = Rt;
1520 let Inst{19-16} = addr{12-9};
1521 let Inst{7-0} = addr{7-0};
1524 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1525 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1526 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1528 // ldrd / strd pre / post variants
1529 // For disassembly only.
1531 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1532 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1533 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1534 let AsmMatchConverter = "cvtT2LdrdPre";
1535 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1538 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1539 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1540 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1541 "$addr.base = $wb", []>;
1543 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1544 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1545 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1546 "$addr.base = $wb", []> {
1547 let AsmMatchConverter = "cvtT2StrdPre";
1548 let DecoderMethod = "DecodeT2STRDPreInstruction";
1551 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1552 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1553 t2am_imm8s4_offset:$imm),
1554 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1555 "$addr.base = $wb", []>;
1557 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1558 // data/instruction access.
1559 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1560 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1561 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1563 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1565 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1566 Sched<[WritePreLd]> {
1567 let Inst{31-25} = 0b1111100;
1568 let Inst{24} = instr;
1571 let Inst{21} = write;
1573 let Inst{15-12} = 0b1111;
1576 let Inst{19-16} = addr{16-13}; // Rn
1577 let Inst{11-0} = addr{11-0}; // imm12
1579 let DecoderMethod = "DecodeT2LoadImm12";
1582 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1584 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1585 Sched<[WritePreLd]> {
1586 let Inst{31-25} = 0b1111100;
1587 let Inst{24} = instr;
1588 let Inst{23} = 0; // U = 0
1590 let Inst{21} = write;
1592 let Inst{15-12} = 0b1111;
1593 let Inst{11-8} = 0b1100;
1596 let Inst{19-16} = addr{12-9}; // Rn
1597 let Inst{7-0} = addr{7-0}; // imm8
1599 let DecoderMethod = "DecodeT2LoadImm8";
1602 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1604 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1605 Sched<[WritePreLd]> {
1606 let Inst{31-25} = 0b1111100;
1607 let Inst{24} = instr;
1608 let Inst{23} = 0; // add = TRUE for T1
1610 let Inst{21} = write;
1612 let Inst{15-12} = 0b1111;
1613 let Inst{11-6} = 0b000000;
1616 let Inst{19-16} = addr{9-6}; // Rn
1617 let Inst{3-0} = addr{5-2}; // Rm
1618 let Inst{5-4} = addr{1-0}; // imm2
1620 let DecoderMethod = "DecodeT2LoadShift";
1623 // pci variant is very similar to i12, but supports negative offsets
1625 def pci : T2Iso<(outs), (ins t2ldrlabel:$addr), IIC_Preload, opc,
1627 [(ARMPreload (ARMWrapper tconstpool:$addr),
1628 (i32 write), (i32 instr))]>,
1629 Sched<[WritePreLd]> {
1630 let Inst{31-25} = 0b1111100;
1631 let Inst{24} = instr;
1633 let Inst{21} = write;
1635 let Inst{19-16} = 0b1111;
1636 let Inst{15-12} = 0b1111;
1639 let Inst{23} = addr{12}; // add = (U == '1')
1640 let Inst{11-0} = addr{11-0}; // imm12
1642 let DecoderMethod = "DecodeT2LoadLabel";
1646 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1647 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1648 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1650 //===----------------------------------------------------------------------===//
1651 // Load / store multiple Instructions.
1654 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1655 InstrItinClass itin_upd, bit L_bit> {
1657 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1658 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1662 let Inst{31-27} = 0b11101;
1663 let Inst{26-25} = 0b00;
1664 let Inst{24-23} = 0b01; // Increment After
1666 let Inst{21} = 0; // No writeback
1667 let Inst{20} = L_bit;
1668 let Inst{19-16} = Rn;
1669 let Inst{15-0} = regs;
1672 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1673 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1677 let Inst{31-27} = 0b11101;
1678 let Inst{26-25} = 0b00;
1679 let Inst{24-23} = 0b01; // Increment After
1681 let Inst{21} = 1; // Writeback
1682 let Inst{20} = L_bit;
1683 let Inst{19-16} = Rn;
1684 let Inst{15-0} = regs;
1687 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1688 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1692 let Inst{31-27} = 0b11101;
1693 let Inst{26-25} = 0b00;
1694 let Inst{24-23} = 0b10; // Decrement Before
1696 let Inst{21} = 0; // No writeback
1697 let Inst{20} = L_bit;
1698 let Inst{19-16} = Rn;
1699 let Inst{15-0} = regs;
1702 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1703 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1707 let Inst{31-27} = 0b11101;
1708 let Inst{26-25} = 0b00;
1709 let Inst{24-23} = 0b10; // Decrement Before
1711 let Inst{21} = 1; // Writeback
1712 let Inst{20} = L_bit;
1713 let Inst{19-16} = Rn;
1714 let Inst{15-0} = regs;
1718 let neverHasSideEffects = 1 in {
1720 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1721 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1723 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1724 InstrItinClass itin_upd, bit L_bit> {
1726 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1727 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1731 let Inst{31-27} = 0b11101;
1732 let Inst{26-25} = 0b00;
1733 let Inst{24-23} = 0b01; // Increment After
1735 let Inst{21} = 0; // No writeback
1736 let Inst{20} = L_bit;
1737 let Inst{19-16} = Rn;
1739 let Inst{14} = regs{14};
1741 let Inst{12-0} = regs{12-0};
1744 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1745 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1749 let Inst{31-27} = 0b11101;
1750 let Inst{26-25} = 0b00;
1751 let Inst{24-23} = 0b01; // Increment After
1753 let Inst{21} = 1; // Writeback
1754 let Inst{20} = L_bit;
1755 let Inst{19-16} = Rn;
1757 let Inst{14} = regs{14};
1759 let Inst{12-0} = regs{12-0};
1762 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1763 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1767 let Inst{31-27} = 0b11101;
1768 let Inst{26-25} = 0b00;
1769 let Inst{24-23} = 0b10; // Decrement Before
1771 let Inst{21} = 0; // No writeback
1772 let Inst{20} = L_bit;
1773 let Inst{19-16} = Rn;
1775 let Inst{14} = regs{14};
1777 let Inst{12-0} = regs{12-0};
1780 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1781 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1785 let Inst{31-27} = 0b11101;
1786 let Inst{26-25} = 0b00;
1787 let Inst{24-23} = 0b10; // Decrement Before
1789 let Inst{21} = 1; // Writeback
1790 let Inst{20} = L_bit;
1791 let Inst{19-16} = Rn;
1793 let Inst{14} = regs{14};
1795 let Inst{12-0} = regs{12-0};
1800 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1801 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1803 } // neverHasSideEffects
1806 //===----------------------------------------------------------------------===//
1807 // Move Instructions.
1810 let neverHasSideEffects = 1 in
1811 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1812 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1813 let Inst{31-27} = 0b11101;
1814 let Inst{26-25} = 0b01;
1815 let Inst{24-21} = 0b0010;
1816 let Inst{19-16} = 0b1111; // Rn
1817 let Inst{14-12} = 0b000;
1818 let Inst{7-4} = 0b0000;
1820 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1821 pred:$p, zero_reg)>;
1822 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1824 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1827 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1828 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1829 AddedComplexity = 1 in
1830 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1831 "mov", ".w\t$Rd, $imm",
1832 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1833 let Inst{31-27} = 0b11110;
1835 let Inst{24-21} = 0b0010;
1836 let Inst{19-16} = 0b1111; // Rn
1840 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1841 // Use aliases to get that to play nice here.
1842 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1844 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1847 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1848 pred:$p, zero_reg)>;
1849 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1850 pred:$p, zero_reg)>;
1852 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1853 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1854 "movw", "\t$Rd, $imm",
1855 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> {
1856 let Inst{31-27} = 0b11110;
1858 let Inst{24-21} = 0b0010;
1859 let Inst{20} = 0; // The S bit.
1865 let Inst{11-8} = Rd;
1866 let Inst{19-16} = imm{15-12};
1867 let Inst{26} = imm{11};
1868 let Inst{14-12} = imm{10-8};
1869 let Inst{7-0} = imm{7-0};
1870 let DecoderMethod = "DecodeT2MOVTWInstruction";
1873 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1874 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1876 let Constraints = "$src = $Rd" in {
1877 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1878 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1879 "movt", "\t$Rd, $imm",
1881 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1883 let Inst{31-27} = 0b11110;
1885 let Inst{24-21} = 0b0110;
1886 let Inst{20} = 0; // The S bit.
1892 let Inst{11-8} = Rd;
1893 let Inst{19-16} = imm{15-12};
1894 let Inst{26} = imm{11};
1895 let Inst{14-12} = imm{10-8};
1896 let Inst{7-0} = imm{7-0};
1897 let DecoderMethod = "DecodeT2MOVTWInstruction";
1900 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1901 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1905 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1907 //===----------------------------------------------------------------------===//
1908 // Extend Instructions.
1913 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1914 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1915 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1916 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1917 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1919 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1920 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1921 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1922 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1923 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1927 let AddedComplexity = 16 in {
1928 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1929 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1930 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1931 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1932 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1933 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1935 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1936 // The transformation should probably be done as a combiner action
1937 // instead so we can include a check for masking back in the upper
1938 // eight bits of the source into the lower eight bits of the result.
1939 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1940 // (t2UXTB16 rGPR:$Src, 3)>,
1941 // Requires<[HasT2ExtractPack, IsThumb2]>;
1942 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1943 (t2UXTB16 rGPR:$Src, 1)>,
1944 Requires<[HasT2ExtractPack, IsThumb2]>;
1946 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1947 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1948 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1949 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1950 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1953 //===----------------------------------------------------------------------===//
1954 // Arithmetic Instructions.
1957 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1958 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1959 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1960 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1962 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1964 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1965 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1966 // AdjustInstrPostInstrSelection where we determine whether or not to
1967 // set the "s" bit based on CPSR liveness.
1969 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1970 // support for an optional CPSR definition that corresponds to the DAG
1971 // node's second value. We can then eliminate the implicit def of CPSR.
1972 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1973 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1974 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1975 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1977 let hasPostISelHook = 1 in {
1978 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1979 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1980 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1981 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1985 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1986 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1988 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1989 // CPSR and the implicit def of CPSR is not needed.
1990 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1992 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1993 // The assume-no-carry-in form uses the negation of the input since add/sub
1994 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1995 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1997 // The AddedComplexity preferences the first variant over the others since
1998 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1999 let AddedComplexity = 1 in
2000 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2001 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2002 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2003 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2004 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2005 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2006 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2007 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2009 let AddedComplexity = 1 in
2010 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2011 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2012 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2013 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2014 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2015 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2016 // The with-carry-in form matches bitwise not instead of the negation.
2017 // Effectively, the inverse interpretation of the carry flag already accounts
2018 // for part of the negation.
2019 let AddedComplexity = 1 in
2020 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2021 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2022 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2023 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2024 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2025 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2027 // Select Bytes -- for disassembly only
2029 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2030 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
2031 Requires<[IsThumb2, HasThumb2DSP]> {
2032 let Inst{31-27} = 0b11111;
2033 let Inst{26-24} = 0b010;
2035 let Inst{22-20} = 0b010;
2036 let Inst{15-12} = 0b1111;
2038 let Inst{6-4} = 0b000;
2041 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2042 // And Miscellaneous operations -- for disassembly only
2043 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2044 list<dag> pat = [/* For disassembly only; pattern left blank */],
2045 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
2046 string asm = "\t$Rd, $Rn, $Rm">
2047 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2048 Requires<[IsThumb2, HasThumb2DSP]> {
2049 let Inst{31-27} = 0b11111;
2050 let Inst{26-23} = 0b0101;
2051 let Inst{22-20} = op22_20;
2052 let Inst{15-12} = 0b1111;
2053 let Inst{7-4} = op7_4;
2059 let Inst{11-8} = Rd;
2060 let Inst{19-16} = Rn;
2064 // Saturating add/subtract -- for disassembly only
2066 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2067 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
2068 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2069 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2070 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2071 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2072 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2073 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2074 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2075 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2076 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2077 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2078 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2079 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2080 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2081 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2082 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2083 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2084 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2085 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2086 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2087 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2089 // Signed/Unsigned add/subtract -- for disassembly only
2091 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2092 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2093 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2094 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2095 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2096 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2097 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2098 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2099 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2100 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2101 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2102 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2104 // Signed/Unsigned halving add/subtract -- for disassembly only
2106 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2107 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2108 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2109 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2110 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2111 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2112 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2113 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2114 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2115 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2116 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2117 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2119 // Helper class for disassembly only
2120 // A6.3.16 & A6.3.17
2121 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2122 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2123 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2124 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2125 let Inst{31-27} = 0b11111;
2126 let Inst{26-24} = 0b011;
2127 let Inst{23} = long;
2128 let Inst{22-20} = op22_20;
2129 let Inst{7-4} = op7_4;
2132 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2133 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2134 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2135 let Inst{31-27} = 0b11111;
2136 let Inst{26-24} = 0b011;
2137 let Inst{23} = long;
2138 let Inst{22-20} = op22_20;
2139 let Inst{7-4} = op7_4;
2142 // Unsigned Sum of Absolute Differences [and Accumulate].
2143 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2144 (ins rGPR:$Rn, rGPR:$Rm),
2145 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2146 Requires<[IsThumb2, HasThumb2DSP]> {
2147 let Inst{15-12} = 0b1111;
2149 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2150 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2151 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2152 Requires<[IsThumb2, HasThumb2DSP]>;
2154 // Signed/Unsigned saturate.
2155 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2156 string opc, string asm, list<dag> pattern>
2157 : T2I<oops, iops, itin, opc, asm, pattern> {
2163 let Inst{11-8} = Rd;
2164 let Inst{19-16} = Rn;
2165 let Inst{4-0} = sat_imm;
2166 let Inst{21} = sh{5};
2167 let Inst{14-12} = sh{4-2};
2168 let Inst{7-6} = sh{1-0};
2173 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2174 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2175 let Inst{31-27} = 0b11110;
2176 let Inst{25-22} = 0b1100;
2182 def t2SSAT16: T2SatI<
2183 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2184 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2185 Requires<[IsThumb2, HasThumb2DSP]> {
2186 let Inst{31-27} = 0b11110;
2187 let Inst{25-22} = 0b1100;
2190 let Inst{21} = 1; // sh = '1'
2191 let Inst{14-12} = 0b000; // imm3 = '000'
2192 let Inst{7-6} = 0b00; // imm2 = '00'
2193 let Inst{5-4} = 0b00;
2198 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2199 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2200 let Inst{31-27} = 0b11110;
2201 let Inst{25-22} = 0b1110;
2206 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2208 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2209 Requires<[IsThumb2, HasThumb2DSP]> {
2210 let Inst{31-22} = 0b1111001110;
2213 let Inst{21} = 1; // sh = '1'
2214 let Inst{14-12} = 0b000; // imm3 = '000'
2215 let Inst{7-6} = 0b00; // imm2 = '00'
2216 let Inst{5-4} = 0b00;
2219 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2220 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2222 //===----------------------------------------------------------------------===//
2223 // Shift and rotate Instructions.
2226 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2227 BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2228 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2229 BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2230 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2231 BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2232 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2233 BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2235 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2236 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2237 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2239 let Uses = [CPSR] in {
2240 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2241 "rrx", "\t$Rd, $Rm",
2242 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2243 let Inst{31-27} = 0b11101;
2244 let Inst{26-25} = 0b01;
2245 let Inst{24-21} = 0b0010;
2246 let Inst{19-16} = 0b1111; // Rn
2247 let Inst{14-12} = 0b000;
2248 let Inst{7-4} = 0b0011;
2252 let isCodeGenOnly = 1, Defs = [CPSR] in {
2253 def t2MOVsrl_flag : T2TwoRegShiftImm<
2254 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2255 "lsrs", ".w\t$Rd, $Rm, #1",
2256 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2258 let Inst{31-27} = 0b11101;
2259 let Inst{26-25} = 0b01;
2260 let Inst{24-21} = 0b0010;
2261 let Inst{20} = 1; // The S bit.
2262 let Inst{19-16} = 0b1111; // Rn
2263 let Inst{5-4} = 0b01; // Shift type.
2264 // Shift amount = Inst{14-12:7-6} = 1.
2265 let Inst{14-12} = 0b000;
2266 let Inst{7-6} = 0b01;
2268 def t2MOVsra_flag : T2TwoRegShiftImm<
2269 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2270 "asrs", ".w\t$Rd, $Rm, #1",
2271 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2273 let Inst{31-27} = 0b11101;
2274 let Inst{26-25} = 0b01;
2275 let Inst{24-21} = 0b0010;
2276 let Inst{20} = 1; // The S bit.
2277 let Inst{19-16} = 0b1111; // Rn
2278 let Inst{5-4} = 0b10; // Shift type.
2279 // Shift amount = Inst{14-12:7-6} = 1.
2280 let Inst{14-12} = 0b000;
2281 let Inst{7-6} = 0b01;
2285 //===----------------------------------------------------------------------===//
2286 // Bitwise Instructions.
2289 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2290 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2291 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2292 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2293 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2294 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2295 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2296 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2297 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2299 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2300 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2301 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2303 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2304 string opc, string asm, list<dag> pattern>
2305 : T2I<oops, iops, itin, opc, asm, pattern> {
2310 let Inst{11-8} = Rd;
2311 let Inst{4-0} = msb{4-0};
2312 let Inst{14-12} = lsb{4-2};
2313 let Inst{7-6} = lsb{1-0};
2316 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2317 string opc, string asm, list<dag> pattern>
2318 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2321 let Inst{19-16} = Rn;
2324 let Constraints = "$src = $Rd" in
2325 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2326 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2327 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2328 let Inst{31-27} = 0b11110;
2329 let Inst{26} = 0; // should be 0.
2331 let Inst{24-20} = 0b10110;
2332 let Inst{19-16} = 0b1111; // Rn
2334 let Inst{5} = 0; // should be 0.
2337 let msb{4-0} = imm{9-5};
2338 let lsb{4-0} = imm{4-0};
2341 def t2SBFX: T2TwoRegBitFI<
2342 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2343 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2344 let Inst{31-27} = 0b11110;
2346 let Inst{24-20} = 0b10100;
2350 def t2UBFX: T2TwoRegBitFI<
2351 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2352 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2353 let Inst{31-27} = 0b11110;
2355 let Inst{24-20} = 0b11100;
2359 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2360 let Constraints = "$src = $Rd" in {
2361 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2362 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2363 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2364 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2365 bf_inv_mask_imm:$imm))]> {
2366 let Inst{31-27} = 0b11110;
2367 let Inst{26} = 0; // should be 0.
2369 let Inst{24-20} = 0b10110;
2371 let Inst{5} = 0; // should be 0.
2374 let msb{4-0} = imm{9-5};
2375 let lsb{4-0} = imm{4-0};
2379 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2380 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2381 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2383 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2384 /// unary operation that produces a value. These are predicable and can be
2385 /// changed to modify CPSR.
2386 multiclass T2I_un_irs<bits<4> opcod, string opc,
2387 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2389 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2391 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2393 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2394 let isAsCheapAsAMove = Cheap;
2395 let isReMaterializable = ReMat;
2396 let isMoveImm = MoveImm;
2397 let Inst{31-27} = 0b11110;
2399 let Inst{24-21} = opcod;
2400 let Inst{19-16} = 0b1111; // Rn
2404 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2405 opc, ".w\t$Rd, $Rm",
2406 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2407 let Inst{31-27} = 0b11101;
2408 let Inst{26-25} = 0b01;
2409 let Inst{24-21} = opcod;
2410 let Inst{19-16} = 0b1111; // Rn
2411 let Inst{14-12} = 0b000; // imm3
2412 let Inst{7-6} = 0b00; // imm2
2413 let Inst{5-4} = 0b00; // type
2416 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2417 opc, ".w\t$Rd, $ShiftedRm",
2418 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2420 let Inst{31-27} = 0b11101;
2421 let Inst{26-25} = 0b01;
2422 let Inst{24-21} = opcod;
2423 let Inst{19-16} = 0b1111; // Rn
2427 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2428 let AddedComplexity = 1 in
2429 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2430 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2431 UnOpFrag<(not node:$Src)>, 1, 1, 1>;
2433 let AddedComplexity = 1 in
2434 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2435 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2437 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2438 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2439 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2442 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2443 // will match the extended, not the original bitWidth for $src.
2444 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2445 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2448 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2449 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2450 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2451 Requires<[IsThumb2]>;
2453 def : T2Pat<(t2_so_imm_not:$src),
2454 (t2MVNi t2_so_imm_not:$src)>;
2456 //===----------------------------------------------------------------------===//
2457 // Multiply Instructions.
2459 let isCommutable = 1 in
2460 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2461 "mul", "\t$Rd, $Rn, $Rm",
2462 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2463 let Inst{31-27} = 0b11111;
2464 let Inst{26-23} = 0b0110;
2465 let Inst{22-20} = 0b000;
2466 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2467 let Inst{7-4} = 0b0000; // Multiply
2470 def t2MLA: T2FourReg<
2471 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2472 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2473 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
2474 Requires<[IsThumb2, UseMulOps]> {
2475 let Inst{31-27} = 0b11111;
2476 let Inst{26-23} = 0b0110;
2477 let Inst{22-20} = 0b000;
2478 let Inst{7-4} = 0b0000; // Multiply
2481 def t2MLS: T2FourReg<
2482 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2483 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2484 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
2485 Requires<[IsThumb2, UseMulOps]> {
2486 let Inst{31-27} = 0b11111;
2487 let Inst{26-23} = 0b0110;
2488 let Inst{22-20} = 0b000;
2489 let Inst{7-4} = 0b0001; // Multiply and Subtract
2492 // Extra precision multiplies with low / high results
2493 let neverHasSideEffects = 1 in {
2494 let isCommutable = 1 in {
2495 def t2SMULL : T2MulLong<0b000, 0b0000,
2496 (outs rGPR:$RdLo, rGPR:$RdHi),
2497 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2498 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2500 def t2UMULL : T2MulLong<0b010, 0b0000,
2501 (outs rGPR:$RdLo, rGPR:$RdHi),
2502 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2503 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2506 // Multiply + accumulate
2507 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2508 (outs rGPR:$RdLo, rGPR:$RdHi),
2509 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2510 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2511 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2513 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2514 (outs rGPR:$RdLo, rGPR:$RdHi),
2515 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2516 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2517 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2519 def t2UMAAL : T2MulLong<0b110, 0b0110,
2520 (outs rGPR:$RdLo, rGPR:$RdHi),
2521 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2522 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2523 Requires<[IsThumb2, HasThumb2DSP]>;
2524 } // neverHasSideEffects
2526 // Rounding variants of the below included for disassembly only
2528 // Most significant word multiply
2529 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2530 "smmul", "\t$Rd, $Rn, $Rm",
2531 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2532 Requires<[IsThumb2, HasThumb2DSP]> {
2533 let Inst{31-27} = 0b11111;
2534 let Inst{26-23} = 0b0110;
2535 let Inst{22-20} = 0b101;
2536 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2537 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2540 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2541 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2542 Requires<[IsThumb2, HasThumb2DSP]> {
2543 let Inst{31-27} = 0b11111;
2544 let Inst{26-23} = 0b0110;
2545 let Inst{22-20} = 0b101;
2546 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2547 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2550 def t2SMMLA : T2FourReg<
2551 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2552 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2553 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2554 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2555 let Inst{31-27} = 0b11111;
2556 let Inst{26-23} = 0b0110;
2557 let Inst{22-20} = 0b101;
2558 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2561 def t2SMMLAR: T2FourReg<
2562 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2563 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2564 Requires<[IsThumb2, HasThumb2DSP]> {
2565 let Inst{31-27} = 0b11111;
2566 let Inst{26-23} = 0b0110;
2567 let Inst{22-20} = 0b101;
2568 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2571 def t2SMMLS: T2FourReg<
2572 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2573 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2574 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2575 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2576 let Inst{31-27} = 0b11111;
2577 let Inst{26-23} = 0b0110;
2578 let Inst{22-20} = 0b110;
2579 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2582 def t2SMMLSR:T2FourReg<
2583 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2584 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2585 Requires<[IsThumb2, HasThumb2DSP]> {
2586 let Inst{31-27} = 0b11111;
2587 let Inst{26-23} = 0b0110;
2588 let Inst{22-20} = 0b110;
2589 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2592 multiclass T2I_smul<string opc, PatFrag opnode> {
2593 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2594 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2595 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2596 (sext_inreg rGPR:$Rm, i16)))]>,
2597 Requires<[IsThumb2, HasThumb2DSP]> {
2598 let Inst{31-27} = 0b11111;
2599 let Inst{26-23} = 0b0110;
2600 let Inst{22-20} = 0b001;
2601 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2602 let Inst{7-6} = 0b00;
2603 let Inst{5-4} = 0b00;
2606 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2607 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2608 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2609 (sra rGPR:$Rm, (i32 16))))]>,
2610 Requires<[IsThumb2, HasThumb2DSP]> {
2611 let Inst{31-27} = 0b11111;
2612 let Inst{26-23} = 0b0110;
2613 let Inst{22-20} = 0b001;
2614 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2615 let Inst{7-6} = 0b00;
2616 let Inst{5-4} = 0b01;
2619 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2620 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2621 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2622 (sext_inreg rGPR:$Rm, i16)))]>,
2623 Requires<[IsThumb2, HasThumb2DSP]> {
2624 let Inst{31-27} = 0b11111;
2625 let Inst{26-23} = 0b0110;
2626 let Inst{22-20} = 0b001;
2627 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2628 let Inst{7-6} = 0b00;
2629 let Inst{5-4} = 0b10;
2632 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2633 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2634 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2635 (sra rGPR:$Rm, (i32 16))))]>,
2636 Requires<[IsThumb2, HasThumb2DSP]> {
2637 let Inst{31-27} = 0b11111;
2638 let Inst{26-23} = 0b0110;
2639 let Inst{22-20} = 0b001;
2640 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2641 let Inst{7-6} = 0b00;
2642 let Inst{5-4} = 0b11;
2645 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2646 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2647 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2648 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2649 Requires<[IsThumb2, HasThumb2DSP]> {
2650 let Inst{31-27} = 0b11111;
2651 let Inst{26-23} = 0b0110;
2652 let Inst{22-20} = 0b011;
2653 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2654 let Inst{7-6} = 0b00;
2655 let Inst{5-4} = 0b00;
2658 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2659 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2660 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2661 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2662 Requires<[IsThumb2, HasThumb2DSP]> {
2663 let Inst{31-27} = 0b11111;
2664 let Inst{26-23} = 0b0110;
2665 let Inst{22-20} = 0b011;
2666 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2667 let Inst{7-6} = 0b00;
2668 let Inst{5-4} = 0b01;
2673 multiclass T2I_smla<string opc, PatFrag opnode> {
2675 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2676 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2677 [(set rGPR:$Rd, (add rGPR:$Ra,
2678 (opnode (sext_inreg rGPR:$Rn, i16),
2679 (sext_inreg rGPR:$Rm, i16))))]>,
2680 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2681 let Inst{31-27} = 0b11111;
2682 let Inst{26-23} = 0b0110;
2683 let Inst{22-20} = 0b001;
2684 let Inst{7-6} = 0b00;
2685 let Inst{5-4} = 0b00;
2689 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2690 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2691 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2692 (sra rGPR:$Rm, (i32 16)))))]>,
2693 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2694 let Inst{31-27} = 0b11111;
2695 let Inst{26-23} = 0b0110;
2696 let Inst{22-20} = 0b001;
2697 let Inst{7-6} = 0b00;
2698 let Inst{5-4} = 0b01;
2702 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2703 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2704 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2705 (sext_inreg rGPR:$Rm, i16))))]>,
2706 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2707 let Inst{31-27} = 0b11111;
2708 let Inst{26-23} = 0b0110;
2709 let Inst{22-20} = 0b001;
2710 let Inst{7-6} = 0b00;
2711 let Inst{5-4} = 0b10;
2715 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2716 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2717 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2718 (sra rGPR:$Rm, (i32 16)))))]>,
2719 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2720 let Inst{31-27} = 0b11111;
2721 let Inst{26-23} = 0b0110;
2722 let Inst{22-20} = 0b001;
2723 let Inst{7-6} = 0b00;
2724 let Inst{5-4} = 0b11;
2728 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2729 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2730 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2731 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2732 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2733 let Inst{31-27} = 0b11111;
2734 let Inst{26-23} = 0b0110;
2735 let Inst{22-20} = 0b011;
2736 let Inst{7-6} = 0b00;
2737 let Inst{5-4} = 0b00;
2741 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2742 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2743 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2744 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2745 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2746 let Inst{31-27} = 0b11111;
2747 let Inst{26-23} = 0b0110;
2748 let Inst{22-20} = 0b011;
2749 let Inst{7-6} = 0b00;
2750 let Inst{5-4} = 0b01;
2754 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2755 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2757 // Halfword multiple accumulate long: SMLAL<x><y>
2758 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2759 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2760 [/* For disassembly only; pattern left blank */]>,
2761 Requires<[IsThumb2, HasThumb2DSP]>;
2762 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2763 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2764 [/* For disassembly only; pattern left blank */]>,
2765 Requires<[IsThumb2, HasThumb2DSP]>;
2766 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2767 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2768 [/* For disassembly only; pattern left blank */]>,
2769 Requires<[IsThumb2, HasThumb2DSP]>;
2770 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2771 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2772 [/* For disassembly only; pattern left blank */]>,
2773 Requires<[IsThumb2, HasThumb2DSP]>;
2775 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2776 def t2SMUAD: T2ThreeReg_mac<
2777 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2778 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2779 Requires<[IsThumb2, HasThumb2DSP]> {
2780 let Inst{15-12} = 0b1111;
2782 def t2SMUADX:T2ThreeReg_mac<
2783 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2784 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2785 Requires<[IsThumb2, HasThumb2DSP]> {
2786 let Inst{15-12} = 0b1111;
2788 def t2SMUSD: T2ThreeReg_mac<
2789 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2790 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2791 Requires<[IsThumb2, HasThumb2DSP]> {
2792 let Inst{15-12} = 0b1111;
2794 def t2SMUSDX:T2ThreeReg_mac<
2795 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2796 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2797 Requires<[IsThumb2, HasThumb2DSP]> {
2798 let Inst{15-12} = 0b1111;
2800 def t2SMLAD : T2FourReg_mac<
2801 0, 0b010, 0b0000, (outs rGPR:$Rd),
2802 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2803 "\t$Rd, $Rn, $Rm, $Ra", []>,
2804 Requires<[IsThumb2, HasThumb2DSP]>;
2805 def t2SMLADX : T2FourReg_mac<
2806 0, 0b010, 0b0001, (outs rGPR:$Rd),
2807 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2808 "\t$Rd, $Rn, $Rm, $Ra", []>,
2809 Requires<[IsThumb2, HasThumb2DSP]>;
2810 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2811 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2812 "\t$Rd, $Rn, $Rm, $Ra", []>,
2813 Requires<[IsThumb2, HasThumb2DSP]>;
2814 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2815 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2816 "\t$Rd, $Rn, $Rm, $Ra", []>,
2817 Requires<[IsThumb2, HasThumb2DSP]>;
2818 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2819 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2820 "\t$Ra, $Rd, $Rn, $Rm", []>,
2821 Requires<[IsThumb2, HasThumb2DSP]>;
2822 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2823 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2824 "\t$Ra, $Rd, $Rn, $Rm", []>,
2825 Requires<[IsThumb2, HasThumb2DSP]>;
2826 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2827 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2828 "\t$Ra, $Rd, $Rn, $Rm", []>,
2829 Requires<[IsThumb2, HasThumb2DSP]>;
2830 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2831 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2832 "\t$Ra, $Rd, $Rn, $Rm", []>,
2833 Requires<[IsThumb2, HasThumb2DSP]>;
2835 //===----------------------------------------------------------------------===//
2836 // Division Instructions.
2837 // Signed and unsigned division on v7-M
2839 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2840 "sdiv", "\t$Rd, $Rn, $Rm",
2841 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2842 Requires<[HasDivide, IsThumb2]> {
2843 let Inst{31-27} = 0b11111;
2844 let Inst{26-21} = 0b011100;
2846 let Inst{15-12} = 0b1111;
2847 let Inst{7-4} = 0b1111;
2850 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2851 "udiv", "\t$Rd, $Rn, $Rm",
2852 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2853 Requires<[HasDivide, IsThumb2]> {
2854 let Inst{31-27} = 0b11111;
2855 let Inst{26-21} = 0b011101;
2857 let Inst{15-12} = 0b1111;
2858 let Inst{7-4} = 0b1111;
2861 //===----------------------------------------------------------------------===//
2862 // Misc. Arithmetic Instructions.
2865 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2866 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2867 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2868 let Inst{31-27} = 0b11111;
2869 let Inst{26-22} = 0b01010;
2870 let Inst{21-20} = op1;
2871 let Inst{15-12} = 0b1111;
2872 let Inst{7-6} = 0b10;
2873 let Inst{5-4} = op2;
2877 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2878 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2881 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2882 "rbit", "\t$Rd, $Rm",
2883 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>,
2886 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2887 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2890 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2891 "rev16", ".w\t$Rd, $Rm",
2892 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2895 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2896 "revsh", ".w\t$Rd, $Rm",
2897 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2900 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2901 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2902 (t2REVSH rGPR:$Rm)>;
2904 def t2PKHBT : T2ThreeReg<
2905 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2906 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2907 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2908 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2910 Requires<[HasT2ExtractPack, IsThumb2]>,
2911 Sched<[WriteALUsi, ReadALU]> {
2912 let Inst{31-27} = 0b11101;
2913 let Inst{26-25} = 0b01;
2914 let Inst{24-20} = 0b01100;
2915 let Inst{5} = 0; // BT form
2919 let Inst{14-12} = sh{4-2};
2920 let Inst{7-6} = sh{1-0};
2923 // Alternate cases for PKHBT where identities eliminate some nodes.
2924 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2925 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2926 Requires<[HasT2ExtractPack, IsThumb2]>;
2927 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2928 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2929 Requires<[HasT2ExtractPack, IsThumb2]>;
2931 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2932 // will match the pattern below.
2933 def t2PKHTB : T2ThreeReg<
2934 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2935 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2936 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2937 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2939 Requires<[HasT2ExtractPack, IsThumb2]>,
2940 Sched<[WriteALUsi, ReadALU]> {
2941 let Inst{31-27} = 0b11101;
2942 let Inst{26-25} = 0b01;
2943 let Inst{24-20} = 0b01100;
2944 let Inst{5} = 1; // TB form
2948 let Inst{14-12} = sh{4-2};
2949 let Inst{7-6} = sh{1-0};
2952 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2953 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2954 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2955 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2956 Requires<[HasT2ExtractPack, IsThumb2]>;
2957 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2958 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2959 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2960 Requires<[HasT2ExtractPack, IsThumb2]>;
2962 //===----------------------------------------------------------------------===//
2963 // Comparison Instructions...
2965 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2966 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2967 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2969 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2970 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2971 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2972 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2973 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2974 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2976 let isCompare = 1, Defs = [CPSR] in {
2978 def t2CMNri : T2OneRegCmpImm<
2979 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
2980 "cmn", ".w\t$Rn, $imm",
2981 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
2982 Sched<[WriteCMP, ReadALU]> {
2983 let Inst{31-27} = 0b11110;
2985 let Inst{24-21} = 0b1000;
2986 let Inst{20} = 1; // The S bit.
2988 let Inst{11-8} = 0b1111; // Rd
2991 def t2CMNzrr : T2TwoRegCmp<
2992 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
2993 "cmn", ".w\t$Rn, $Rm",
2994 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2995 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
2996 let Inst{31-27} = 0b11101;
2997 let Inst{26-25} = 0b01;
2998 let Inst{24-21} = 0b1000;
2999 let Inst{20} = 1; // The S bit.
3000 let Inst{14-12} = 0b000; // imm3
3001 let Inst{11-8} = 0b1111; // Rd
3002 let Inst{7-6} = 0b00; // imm2
3003 let Inst{5-4} = 0b00; // type
3006 def t2CMNzrs : T2OneRegCmpShiftedReg<
3007 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
3008 "cmn", ".w\t$Rn, $ShiftedRm",
3009 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3010 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
3011 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3012 let Inst{31-27} = 0b11101;
3013 let Inst{26-25} = 0b01;
3014 let Inst{24-21} = 0b1000;
3015 let Inst{20} = 1; // The S bit.
3016 let Inst{11-8} = 0b1111; // Rd
3020 // Assembler aliases w/o the ".w" suffix.
3021 // No alias here for 'rr' version as not all instantiations of this multiclass
3022 // want one (CMP in particular, does not).
3023 def : t2InstAlias<"cmn${p} $Rn, $imm",
3024 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
3025 def : t2InstAlias<"cmn${p} $Rn, $shift",
3026 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
3028 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
3029 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
3031 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
3032 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
3034 defm t2TST : T2I_cmp_irs<0b0000, "tst",
3035 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3036 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3037 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
3038 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3039 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3041 // Conditional moves
3042 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3043 // a two-value operand where a dag node expects two operands. :(
3044 let neverHasSideEffects = 1 in {
3046 let isCommutable = 1, isSelect = 1 in
3047 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3048 (ins rGPR:$false, rGPR:$Rm, pred:$p),
3050 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3051 RegConstraint<"$false = $Rd">,
3054 let isMoveImm = 1 in
3055 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
3056 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
3058 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3059 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3061 // FIXME: Pseudo-ize these. For now, just mark codegen only.
3062 let isCodeGenOnly = 1 in {
3063 let isMoveImm = 1 in
3064 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
3066 "movw", "\t$Rd, $imm", []>,
3067 RegConstraint<"$false = $Rd">, Sched<[WriteALU]> {
3068 let Inst{31-27} = 0b11110;
3070 let Inst{24-21} = 0b0010;
3071 let Inst{20} = 0; // The S bit.
3077 let Inst{11-8} = Rd;
3078 let Inst{19-16} = imm{15-12};
3079 let Inst{26} = imm{11};
3080 let Inst{14-12} = imm{10-8};
3081 let Inst{7-0} = imm{7-0};
3084 let isMoveImm = 1 in
3085 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
3086 (ins rGPR:$false, i32imm:$src, pred:$p),
3087 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
3089 let isMoveImm = 1 in
3090 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
3091 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
3092 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
3093 imm:$cc, CCR:$ccr))*/]>,
3094 RegConstraint<"$false = $Rd">, Sched<[WriteALU]> {
3095 let Inst{31-27} = 0b11110;
3097 let Inst{24-21} = 0b0011;
3098 let Inst{20} = 0; // The S bit.
3099 let Inst{19-16} = 0b1111; // Rn
3103 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
3104 string opc, string asm, list<dag> pattern>
3105 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern>, Sched<[WriteALU]> {
3106 let Inst{31-27} = 0b11101;
3107 let Inst{26-25} = 0b01;
3108 let Inst{24-21} = 0b0010;
3109 let Inst{20} = 0; // The S bit.
3110 let Inst{19-16} = 0b1111; // Rn
3111 let Inst{5-4} = opcod; // Shift type.
3113 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
3114 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3115 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
3116 RegConstraint<"$false = $Rd">;
3117 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
3118 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3119 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
3120 RegConstraint<"$false = $Rd">;
3121 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
3122 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3123 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
3124 RegConstraint<"$false = $Rd">;
3125 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
3126 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3127 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
3128 RegConstraint<"$false = $Rd">;
3129 } // isCodeGenOnly = 1
3131 } // neverHasSideEffects
3133 //===----------------------------------------------------------------------===//
3134 // Atomic operations intrinsics
3137 // memory barriers protect the atomic sequences
3138 let hasSideEffects = 1 in {
3139 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3140 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3143 let Inst{31-4} = 0xf3bf8f5;
3144 let Inst{3-0} = opt;
3148 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3149 "dsb", "\t$opt", []>, Requires<[HasDB]> {
3151 let Inst{31-4} = 0xf3bf8f4;
3152 let Inst{3-0} = opt;
3155 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3156 "isb", "\t$opt", []>, Requires<[HasDB]> {
3158 let Inst{31-4} = 0xf3bf8f6;
3159 let Inst{3-0} = opt;
3162 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3163 InstrItinClass itin, string opc, string asm, string cstr,
3164 list<dag> pattern, bits<4> rt2 = 0b1111>
3165 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3166 let Inst{31-27} = 0b11101;
3167 let Inst{26-20} = 0b0001101;
3168 let Inst{11-8} = rt2;
3169 let Inst{7-6} = 0b01;
3170 let Inst{5-4} = opcod;
3171 let Inst{3-0} = 0b1111;
3175 let Inst{19-16} = addr;
3176 let Inst{15-12} = Rt;
3178 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3179 InstrItinClass itin, string opc, string asm, string cstr,
3180 list<dag> pattern, bits<4> rt2 = 0b1111>
3181 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3182 let Inst{31-27} = 0b11101;
3183 let Inst{26-20} = 0b0001100;
3184 let Inst{11-8} = rt2;
3185 let Inst{7-6} = 0b01;
3186 let Inst{5-4} = opcod;
3192 let Inst{19-16} = addr;
3193 let Inst{15-12} = Rt;
3196 let mayLoad = 1 in {
3197 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3198 AddrModeNone, 4, NoItinerary,
3199 "ldrexb", "\t$Rt, $addr", "", []>;
3200 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3201 AddrModeNone, 4, NoItinerary,
3202 "ldrexh", "\t$Rt, $addr", "", []>;
3203 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3204 AddrModeNone, 4, NoItinerary,
3205 "ldrex", "\t$Rt, $addr", "", []> {
3208 let Inst{31-27} = 0b11101;
3209 let Inst{26-20} = 0b0000101;
3210 let Inst{19-16} = addr{11-8};
3211 let Inst{15-12} = Rt;
3212 let Inst{11-8} = 0b1111;
3213 let Inst{7-0} = addr{7-0};
3215 let hasExtraDefRegAllocReq = 1 in
3216 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3217 (ins addr_offset_none:$addr),
3218 AddrModeNone, 4, NoItinerary,
3219 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3222 let Inst{11-8} = Rt2;
3226 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3227 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3228 (ins rGPR:$Rt, addr_offset_none:$addr),
3229 AddrModeNone, 4, NoItinerary,
3230 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3231 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3232 (ins rGPR:$Rt, addr_offset_none:$addr),
3233 AddrModeNone, 4, NoItinerary,
3234 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3235 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3236 t2addrmode_imm0_1020s4:$addr),
3237 AddrModeNone, 4, NoItinerary,
3238 "strex", "\t$Rd, $Rt, $addr", "",
3243 let Inst{31-27} = 0b11101;
3244 let Inst{26-20} = 0b0000100;
3245 let Inst{19-16} = addr{11-8};
3246 let Inst{15-12} = Rt;
3247 let Inst{11-8} = Rd;
3248 let Inst{7-0} = addr{7-0};
3250 let hasExtraSrcRegAllocReq = 1 in
3251 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3252 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3253 AddrModeNone, 4, NoItinerary,
3254 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3257 let Inst{11-8} = Rt2;
3261 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3262 Requires<[IsThumb2, HasV7]> {
3263 let Inst{31-16} = 0xf3bf;
3264 let Inst{15-14} = 0b10;
3267 let Inst{11-8} = 0b1111;
3268 let Inst{7-4} = 0b0010;
3269 let Inst{3-0} = 0b1111;
3272 //===----------------------------------------------------------------------===//
3273 // SJLJ Exception handling intrinsics
3274 // eh_sjlj_setjmp() is an instruction sequence to store the return
3275 // address and save #0 in R0 for the non-longjmp case.
3276 // Since by its nature we may be coming from some other function to get
3277 // here, and we're using the stack frame for the containing function to
3278 // save/restore registers, we can't keep anything live in regs across
3279 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3280 // when we get here from a longjmp(). We force everything out of registers
3281 // except for our own input by listing the relevant registers in Defs. By
3282 // doing so, we also cause the prologue/epilogue code to actively preserve
3283 // all of the callee-saved resgisters, which is exactly what we want.
3284 // $val is a scratch register for our use.
3286 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3287 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3288 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3289 usesCustomInserter = 1 in {
3290 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3291 AddrModeNone, 0, NoItinerary, "", "",
3292 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3293 Requires<[IsThumb2, HasVFP2]>;
3297 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3298 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3299 usesCustomInserter = 1 in {
3300 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3301 AddrModeNone, 0, NoItinerary, "", "",
3302 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3303 Requires<[IsThumb2, NoVFP]>;
3307 //===----------------------------------------------------------------------===//
3308 // Control-Flow Instructions
3311 // FIXME: remove when we have a way to marking a MI with these properties.
3312 // FIXME: Should pc be an implicit operand like PICADD, etc?
3313 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3314 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3315 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3316 reglist:$regs, variable_ops),
3317 4, IIC_iLoad_mBr, [],
3318 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3319 RegConstraint<"$Rn = $wb">;
3321 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3322 let isPredicable = 1 in
3323 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3325 [(br bb:$target)]>, Sched<[WriteBr]> {
3326 let Inst{31-27} = 0b11110;
3327 let Inst{15-14} = 0b10;
3331 let Inst{26} = target{19};
3332 let Inst{11} = target{18};
3333 let Inst{13} = target{17};
3334 let Inst{25-16} = target{20-11};
3335 let Inst{10-0} = target{10-0};
3336 let DecoderMethod = "DecodeT2BInstruction";
3339 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3340 def t2BR_JT : t2PseudoInst<(outs),
3341 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3343 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>,
3346 // FIXME: Add a non-pc based case that can be predicated.
3347 def t2TBB_JT : t2PseudoInst<(outs),
3348 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3351 def t2TBH_JT : t2PseudoInst<(outs),
3352 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3355 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3356 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3359 let Inst{31-20} = 0b111010001101;
3360 let Inst{19-16} = Rn;
3361 let Inst{15-5} = 0b11110000000;
3362 let Inst{4} = 0; // B form
3365 let DecoderMethod = "DecodeThumbTableBranch";
3368 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3369 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3372 let Inst{31-20} = 0b111010001101;
3373 let Inst{19-16} = Rn;
3374 let Inst{15-5} = 0b11110000000;
3375 let Inst{4} = 1; // H form
3378 let DecoderMethod = "DecodeThumbTableBranch";
3380 } // isNotDuplicable, isIndirectBranch
3382 } // isBranch, isTerminator, isBarrier
3384 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3385 // a two-value operand where a dag node expects ", "two operands. :(
3386 let isBranch = 1, isTerminator = 1 in
3387 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3389 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3390 let Inst{31-27} = 0b11110;
3391 let Inst{15-14} = 0b10;
3395 let Inst{25-22} = p;
3398 let Inst{26} = target{20};
3399 let Inst{11} = target{19};
3400 let Inst{13} = target{18};
3401 let Inst{21-16} = target{17-12};
3402 let Inst{10-0} = target{11-1};
3404 let DecoderMethod = "DecodeThumb2BCCInstruction";
3407 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3409 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3412 def tTAILJMPd: tPseudoExpand<(outs),
3413 (ins uncondbrtarget:$dst, pred:$p),
3415 (t2B uncondbrtarget:$dst, pred:$p)>,
3416 Requires<[IsThumb2, IsIOS]>, Sched<[WriteBr]>;
3420 let Defs = [ITSTATE] in
3421 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3422 AddrModeNone, 2, IIC_iALUx,
3423 "it$mask\t$cc", "", []> {
3424 // 16-bit instruction.
3425 let Inst{31-16} = 0x0000;
3426 let Inst{15-8} = 0b10111111;
3431 let Inst{3-0} = mask;
3433 let DecoderMethod = "DecodeIT";
3436 // Branch and Exchange Jazelle -- for disassembly only
3438 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []>,
3441 let Inst{31-27} = 0b11110;
3443 let Inst{25-20} = 0b111100;
3444 let Inst{19-16} = func;
3445 let Inst{15-0} = 0b1000111100000000;
3448 // Compare and branch on zero / non-zero
3449 let isBranch = 1, isTerminator = 1 in {
3450 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3451 "cbz\t$Rn, $target", []>,
3452 T1Misc<{0,0,?,1,?,?,?}>,
3453 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3457 let Inst{9} = target{5};
3458 let Inst{7-3} = target{4-0};
3462 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3463 "cbnz\t$Rn, $target", []>,
3464 T1Misc<{1,0,?,1,?,?,?}>,
3465 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3469 let Inst{9} = target{5};
3470 let Inst{7-3} = target{4-0};
3476 // Change Processor State is a system instruction.
3477 // FIXME: Since the asm parser has currently no clean way to handle optional
3478 // operands, create 3 versions of the same instruction. Once there's a clean
3479 // framework to represent optional operands, change this behavior.
3480 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3481 !strconcat("cps", asm_op), []> {
3487 let Inst{31-11} = 0b111100111010111110000;
3488 let Inst{10-9} = imod;
3490 let Inst{7-5} = iflags;
3491 let Inst{4-0} = mode;
3492 let DecoderMethod = "DecodeT2CPSInstruction";
3496 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3497 "$imod.w\t$iflags, $mode">;
3498 let mode = 0, M = 0 in
3499 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3500 "$imod.w\t$iflags">;
3501 let imod = 0, iflags = 0, M = 1 in
3502 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3504 // A6.3.4 Branches and miscellaneous control
3505 // Table A6-14 Change Processor State, and hint instructions
3506 def t2HINT : T2I<(outs), (ins imm0_4:$imm), NoItinerary, "hint", "\t$imm",[]> {
3508 let Inst{31-3} = 0b11110011101011111000000000000;
3509 let Inst{2-0} = imm;
3512 def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_4:$imm, pred:$p)>;
3513 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3514 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3515 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3516 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3517 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3519 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3521 let Inst{31-20} = 0b111100111010;
3522 let Inst{19-16} = 0b1111;
3523 let Inst{15-8} = 0b10000000;
3524 let Inst{7-4} = 0b1111;
3525 let Inst{3-0} = opt;
3528 // Secure Monitor Call is a system instruction.
3529 // Option = Inst{19-16}
3530 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3531 []>, Requires<[IsThumb2, HasTrustZone]> {
3532 let Inst{31-27} = 0b11110;
3533 let Inst{26-20} = 0b1111111;
3534 let Inst{15-12} = 0b1000;
3537 let Inst{19-16} = opt;
3540 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3541 string opc, string asm, list<dag> pattern>
3542 : T2I<oops, iops, itin, opc, asm, pattern> {
3544 let Inst{31-25} = 0b1110100;
3545 let Inst{24-23} = Op;
3548 let Inst{20-16} = 0b01101;
3549 let Inst{15-5} = 0b11000000000;
3550 let Inst{4-0} = mode{4-0};
3553 // Store Return State is a system instruction.
3554 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3555 "srsdb", "\tsp!, $mode", []>;
3556 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3557 "srsdb","\tsp, $mode", []>;
3558 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3559 "srsia","\tsp!, $mode", []>;
3560 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3561 "srsia","\tsp, $mode", []>;
3564 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3565 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3567 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3568 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3570 // Return From Exception is a system instruction.
3571 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3572 string opc, string asm, list<dag> pattern>
3573 : T2I<oops, iops, itin, opc, asm, pattern> {
3574 let Inst{31-20} = op31_20{11-0};
3577 let Inst{19-16} = Rn;
3578 let Inst{15-0} = 0xc000;
3581 def t2RFEDBW : T2RFE<0b111010000011,
3582 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3583 [/* For disassembly only; pattern left blank */]>;
3584 def t2RFEDB : T2RFE<0b111010000001,
3585 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3586 [/* For disassembly only; pattern left blank */]>;
3587 def t2RFEIAW : T2RFE<0b111010011011,
3588 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3589 [/* For disassembly only; pattern left blank */]>;
3590 def t2RFEIA : T2RFE<0b111010011001,
3591 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3592 [/* For disassembly only; pattern left blank */]>;
3594 //===----------------------------------------------------------------------===//
3595 // Non-Instruction Patterns
3598 // 32-bit immediate using movw + movt.
3599 // This is a single pseudo instruction to make it re-materializable.
3600 // FIXME: Remove this when we can do generalized remat.
3601 let isReMaterializable = 1, isMoveImm = 1 in
3602 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3603 [(set rGPR:$dst, (i32 imm:$src))]>,
3604 Requires<[IsThumb, HasV6T2]>;
3606 // Pseudo instruction that combines movw + movt + add pc (if pic).
3607 // It also makes it possible to rematerialize the instructions.
3608 // FIXME: Remove this when we can do generalized remat and when machine licm
3609 // can properly the instructions.
3610 let isReMaterializable = 1 in {
3611 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3613 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3614 Requires<[IsThumb2, UseMovt]>;
3616 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3618 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3619 Requires<[IsThumb2, UseMovt]>;
3622 // ConstantPool, GlobalAddress, and JumpTable
3623 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3624 Requires<[IsThumb2, DontUseMovt]>;
3625 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3626 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3627 Requires<[IsThumb2, UseMovt]>;
3629 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3630 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3632 // Pseudo instruction that combines ldr from constpool and add pc. This should
3633 // be expanded into two instructions late to allow if-conversion and
3635 let canFoldAsLoad = 1, isReMaterializable = 1 in
3636 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3638 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3640 Requires<[IsThumb2]>;
3642 // Pseudo isntruction that combines movs + predicated rsbmi
3643 // to implement integer ABS
3644 let usesCustomInserter = 1, Defs = [CPSR] in {
3645 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3646 NoItinerary, []>, Requires<[IsThumb2]>;
3649 //===----------------------------------------------------------------------===//
3650 // Coprocessor load/store -- for disassembly only
3652 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3653 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3654 let Inst{31-28} = op31_28;
3655 let Inst{27-25} = 0b110;
3658 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3659 def _OFFSET : T2CI<op31_28,
3660 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3661 asm, "\t$cop, $CRd, $addr"> {
3665 let Inst{24} = 1; // P = 1
3666 let Inst{23} = addr{8};
3667 let Inst{22} = Dbit;
3668 let Inst{21} = 0; // W = 0
3669 let Inst{20} = load;
3670 let Inst{19-16} = addr{12-9};
3671 let Inst{15-12} = CRd;
3672 let Inst{11-8} = cop;
3673 let Inst{7-0} = addr{7-0};
3674 let DecoderMethod = "DecodeCopMemInstruction";
3676 def _PRE : T2CI<op31_28,
3677 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3678 asm, "\t$cop, $CRd, $addr!"> {
3682 let Inst{24} = 1; // P = 1
3683 let Inst{23} = addr{8};
3684 let Inst{22} = Dbit;
3685 let Inst{21} = 1; // W = 1
3686 let Inst{20} = load;
3687 let Inst{19-16} = addr{12-9};
3688 let Inst{15-12} = CRd;
3689 let Inst{11-8} = cop;
3690 let Inst{7-0} = addr{7-0};
3691 let DecoderMethod = "DecodeCopMemInstruction";
3693 def _POST: T2CI<op31_28,
3694 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3695 postidx_imm8s4:$offset),
3696 asm, "\t$cop, $CRd, $addr, $offset"> {
3701 let Inst{24} = 0; // P = 0
3702 let Inst{23} = offset{8};
3703 let Inst{22} = Dbit;
3704 let Inst{21} = 1; // W = 1
3705 let Inst{20} = load;
3706 let Inst{19-16} = addr;
3707 let Inst{15-12} = CRd;
3708 let Inst{11-8} = cop;
3709 let Inst{7-0} = offset{7-0};
3710 let DecoderMethod = "DecodeCopMemInstruction";
3712 def _OPTION : T2CI<op31_28, (outs),
3713 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3714 coproc_option_imm:$option),
3715 asm, "\t$cop, $CRd, $addr, $option"> {
3720 let Inst{24} = 0; // P = 0
3721 let Inst{23} = 1; // U = 1
3722 let Inst{22} = Dbit;
3723 let Inst{21} = 0; // W = 0
3724 let Inst{20} = load;
3725 let Inst{19-16} = addr;
3726 let Inst{15-12} = CRd;
3727 let Inst{11-8} = cop;
3728 let Inst{7-0} = option;
3729 let DecoderMethod = "DecodeCopMemInstruction";
3733 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3734 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3735 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3736 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3737 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3738 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3739 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3740 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3743 //===----------------------------------------------------------------------===//
3744 // Move between special register and ARM core register -- for disassembly only
3746 // Move to ARM core register from Special Register
3750 // A/R class can only move from CPSR or SPSR.
3751 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3752 []>, Requires<[IsThumb2,IsARClass]> {
3754 let Inst{31-12} = 0b11110011111011111000;
3755 let Inst{11-8} = Rd;
3756 let Inst{7-0} = 0b0000;
3759 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3761 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3762 []>, Requires<[IsThumb2,IsARClass]> {
3764 let Inst{31-12} = 0b11110011111111111000;
3765 let Inst{11-8} = Rd;
3766 let Inst{7-0} = 0b0000;
3771 // This MRS has a mask field in bits 7-0 and can take more values than
3772 // the A/R class (a full msr_mask).
3773 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3774 "mrs", "\t$Rd, $mask", []>,
3775 Requires<[IsThumb,IsMClass]> {
3778 let Inst{31-12} = 0b11110011111011111000;
3779 let Inst{11-8} = Rd;
3780 let Inst{19-16} = 0b1111;
3781 let Inst{7-0} = mask;
3785 // Move from ARM core register to Special Register
3789 // No need to have both system and application versions, the encodings are the
3790 // same and the assembly parser has no way to distinguish between them. The mask
3791 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3792 // the mask with the fields to be accessed in the special register.
3793 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3794 NoItinerary, "msr", "\t$mask, $Rn", []>,
3795 Requires<[IsThumb2,IsARClass]> {
3798 let Inst{31-21} = 0b11110011100;
3799 let Inst{20} = mask{4}; // R Bit
3800 let Inst{19-16} = Rn;
3801 let Inst{15-12} = 0b1000;
3802 let Inst{11-8} = mask{3-0};
3808 // Move from ARM core register to Special Register
3809 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3810 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3811 Requires<[IsThumb,IsMClass]> {
3814 let Inst{31-21} = 0b11110011100;
3816 let Inst{19-16} = Rn;
3817 let Inst{15-12} = 0b1000;
3818 let Inst{11-0} = SYSm;
3822 //===----------------------------------------------------------------------===//
3823 // Move between coprocessor and ARM core register
3826 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3828 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3830 let Inst{27-24} = 0b1110;
3831 let Inst{20} = direction;
3841 let Inst{15-12} = Rt;
3842 let Inst{11-8} = cop;
3843 let Inst{23-21} = opc1;
3844 let Inst{7-5} = opc2;
3845 let Inst{3-0} = CRm;
3846 let Inst{19-16} = CRn;
3849 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3850 list<dag> pattern = []>
3852 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3853 opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3854 let Inst{27-24} = 0b1100;
3855 let Inst{23-21} = 0b010;
3856 let Inst{20} = direction;
3864 let Inst{15-12} = Rt;
3865 let Inst{19-16} = Rt2;
3866 let Inst{11-8} = cop;
3867 let Inst{7-4} = opc1;
3868 let Inst{3-0} = CRm;
3871 /* from ARM core register to coprocessor */
3872 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3874 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3875 c_imm:$CRm, imm0_7:$opc2),
3876 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3877 imm:$CRm, imm:$opc2)]>;
3878 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
3879 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3880 c_imm:$CRm, 0, pred:$p)>;
3881 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3882 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3883 c_imm:$CRm, imm0_7:$opc2),
3884 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3885 imm:$CRm, imm:$opc2)]>;
3886 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
3887 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3888 c_imm:$CRm, 0, pred:$p)>;
3890 /* from coprocessor to ARM core register */
3891 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3892 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3893 c_imm:$CRm, imm0_7:$opc2), []>;
3894 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
3895 (t2MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3896 c_imm:$CRm, 0, pred:$p)>;
3898 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3899 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3900 c_imm:$CRm, imm0_7:$opc2), []>;
3901 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
3902 (t2MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3903 c_imm:$CRm, 0, pred:$p)>;
3905 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3906 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3908 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3909 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3912 /* from ARM core register to coprocessor */
3913 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3914 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3916 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3917 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3918 GPR:$Rt2, imm:$CRm)]>;
3919 /* from coprocessor to ARM core register */
3920 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3922 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3924 //===----------------------------------------------------------------------===//
3925 // Other Coprocessor Instructions.
3928 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3929 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3930 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3931 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3932 imm:$CRm, imm:$opc2)]> {
3933 let Inst{27-24} = 0b1110;
3942 let Inst{3-0} = CRm;
3944 let Inst{7-5} = opc2;
3945 let Inst{11-8} = cop;
3946 let Inst{15-12} = CRd;
3947 let Inst{19-16} = CRn;
3948 let Inst{23-20} = opc1;
3951 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3952 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3953 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3954 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3955 imm:$CRm, imm:$opc2)]> {
3956 let Inst{27-24} = 0b1110;
3965 let Inst{3-0} = CRm;
3967 let Inst{7-5} = opc2;
3968 let Inst{11-8} = cop;
3969 let Inst{15-12} = CRd;
3970 let Inst{19-16} = CRn;
3971 let Inst{23-20} = opc1;
3976 //===----------------------------------------------------------------------===//
3977 // Non-Instruction Patterns
3980 // SXT/UXT with no rotate
3981 let AddedComplexity = 16 in {
3982 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3983 Requires<[IsThumb2]>;
3984 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3985 Requires<[IsThumb2]>;
3986 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3987 Requires<[HasT2ExtractPack, IsThumb2]>;
3988 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3989 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3990 Requires<[HasT2ExtractPack, IsThumb2]>;
3991 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3992 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3993 Requires<[HasT2ExtractPack, IsThumb2]>;
3996 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3997 Requires<[IsThumb2]>;
3998 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3999 Requires<[IsThumb2]>;
4000 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4001 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4002 Requires<[HasT2ExtractPack, IsThumb2]>;
4003 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4004 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4005 Requires<[HasT2ExtractPack, IsThumb2]>;
4007 // Atomic load/store patterns
4008 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4009 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4010 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4011 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4012 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4013 (t2LDRBs t2addrmode_so_reg:$addr)>;
4014 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4015 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4016 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4017 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4018 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4019 (t2LDRHs t2addrmode_so_reg:$addr)>;
4020 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4021 (t2LDRi12 t2addrmode_imm12:$addr)>;
4022 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4023 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4024 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4025 (t2LDRs t2addrmode_so_reg:$addr)>;
4026 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4027 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4028 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4029 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4030 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4031 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4032 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4033 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4034 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4035 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4036 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4037 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4038 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4039 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4040 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4041 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4042 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4043 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4046 //===----------------------------------------------------------------------===//
4047 // Assembler aliases
4050 // Aliases for ADC without the ".w" optional width specifier.
4051 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4052 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4053 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4054 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4055 pred:$p, cc_out:$s)>;
4057 // Aliases for SBC without the ".w" optional width specifier.
4058 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4059 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4060 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4061 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4062 pred:$p, cc_out:$s)>;
4064 // Aliases for ADD without the ".w" optional width specifier.
4065 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4066 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4067 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4068 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4069 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4070 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4071 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4072 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4073 pred:$p, cc_out:$s)>;
4074 // ... and with the destination and source register combined.
4075 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4076 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4077 def : t2InstAlias<"add${p} $Rdn, $imm",
4078 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4079 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4080 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4081 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4082 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4083 pred:$p, cc_out:$s)>;
4085 // add w/ negative immediates is just a sub.
4086 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4087 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4089 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4090 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4091 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4092 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4094 def : t2InstAlias<"add${p} $Rdn, $imm",
4095 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4097 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4098 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4100 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4101 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4102 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4103 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4105 def : t2InstAlias<"addw${p} $Rdn, $imm",
4106 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4109 // Aliases for SUB without the ".w" optional width specifier.
4110 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4111 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4112 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4113 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4114 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4115 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4116 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4117 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4118 pred:$p, cc_out:$s)>;
4119 // ... and with the destination and source register combined.
4120 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4121 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4122 def : t2InstAlias<"sub${p} $Rdn, $imm",
4123 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4124 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4125 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4126 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4127 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4128 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4129 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4130 pred:$p, cc_out:$s)>;
4132 // Alias for compares without the ".w" optional width specifier.
4133 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4134 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4135 def : t2InstAlias<"teq${p} $Rn, $Rm",
4136 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4137 def : t2InstAlias<"tst${p} $Rn, $Rm",
4138 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4141 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
4142 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
4143 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
4145 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4147 def : t2InstAlias<"ldr${p} $Rt, $addr",
4148 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4149 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4150 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4151 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4152 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4153 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4154 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4155 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4156 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4158 def : t2InstAlias<"ldr${p} $Rt, $addr",
4159 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4160 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4161 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4162 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4163 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4164 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4165 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4166 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4167 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4169 def : t2InstAlias<"ldr${p} $Rt, $addr",
4170 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4171 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4172 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4173 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4174 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4175 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4176 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4177 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4178 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4180 // Alias for MVN with(out) the ".w" optional width specifier.
4181 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4182 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4183 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4184 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4185 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4186 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4188 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4189 // shift amount is zero (i.e., unspecified).
4190 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4191 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4192 Requires<[HasT2ExtractPack, IsThumb2]>;
4193 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4194 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4195 Requires<[HasT2ExtractPack, IsThumb2]>;
4197 // PUSH/POP aliases for STM/LDM
4198 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4199 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4200 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4201 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4203 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4204 def : t2InstAlias<"stm${p} $Rn, $regs",
4205 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4206 def : t2InstAlias<"stm${p} $Rn!, $regs",
4207 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4209 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4210 def : t2InstAlias<"ldm${p} $Rn, $regs",
4211 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4212 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4213 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4215 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4216 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4217 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4218 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4219 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4221 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4222 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4223 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4224 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4225 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4227 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4228 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4229 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4230 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4233 // Alias for RSB without the ".w" optional width specifier, and with optional
4234 // implied destination register.
4235 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4236 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4237 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4238 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4239 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4240 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4241 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4242 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4245 // SSAT/USAT optional shift operand.
4246 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4247 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4248 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4249 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4251 // STM w/o the .w suffix.
4252 def : t2InstAlias<"stm${p} $Rn, $regs",
4253 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4255 // Alias for STR, STRB, and STRH without the ".w" optional
4257 def : t2InstAlias<"str${p} $Rt, $addr",
4258 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4259 def : t2InstAlias<"strb${p} $Rt, $addr",
4260 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4261 def : t2InstAlias<"strh${p} $Rt, $addr",
4262 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4264 def : t2InstAlias<"str${p} $Rt, $addr",
4265 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4266 def : t2InstAlias<"strb${p} $Rt, $addr",
4267 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4268 def : t2InstAlias<"strh${p} $Rt, $addr",
4269 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4271 // Extend instruction optional rotate operand.
4272 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4273 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4274 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4275 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4276 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4277 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4279 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4280 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4281 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4282 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4283 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4284 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4285 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4286 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4287 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4288 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4290 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4291 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4292 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4293 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4294 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4295 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4296 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4297 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4298 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4299 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4300 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4301 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4303 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4304 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4305 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4306 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4308 // Extend instruction w/o the ".w" optional width specifier.
4309 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4310 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4311 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4312 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4313 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4314 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4316 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4317 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4318 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4319 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4320 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4321 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4324 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4326 def : t2InstAlias<"mov${p} $Rd, $imm",
4327 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4328 def : t2InstAlias<"mvn${p} $Rd, $imm",
4329 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4330 // Same for AND <--> BIC
4331 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4332 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4333 pred:$p, cc_out:$s)>;
4334 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4335 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4336 pred:$p, cc_out:$s)>;
4337 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4338 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4339 pred:$p, cc_out:$s)>;
4340 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4341 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4342 pred:$p, cc_out:$s)>;
4343 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4344 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4345 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4346 pred:$p, cc_out:$s)>;
4347 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4348 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4349 pred:$p, cc_out:$s)>;
4350 // Same for CMP <--> CMN via t2_so_imm_neg
4351 def : t2InstAlias<"cmp${p} $Rd, $imm",
4352 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4353 def : t2InstAlias<"cmn${p} $Rd, $imm",
4354 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4357 // Wide 'mul' encoding can be specified with only two operands.
4358 def : t2InstAlias<"mul${p} $Rn, $Rm",
4359 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4361 // "neg" is and alias for "rsb rd, rn, #0"
4362 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4363 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4365 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4366 // these, unfortunately.
4367 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4368 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4369 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4370 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4372 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4373 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4374 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4375 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4377 // ADR w/o the .w suffix
4378 def : t2InstAlias<"adr${p} $Rd, $addr",
4379 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4381 // LDR(literal) w/ alternate [pc, #imm] syntax.
4382 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4383 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4384 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4385 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4386 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4387 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4388 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4389 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4390 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4391 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4392 // Version w/ the .w suffix.
4393 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4394 (t2LDRpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4395 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4396 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4397 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4398 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4399 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4400 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4401 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4402 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4404 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4405 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;