1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
17 let DecoderMethod = "DecodeITCond";
20 // IT block condition mask
21 def it_mask : Operand<i32> {
22 let PrintMethod = "printThumbITMask";
25 // Shifted operands. No register controlled shifts for Thumb2.
26 // Note: We do not support rrx shifted operands yet.
27 def t2_so_reg : Operand<i32>, // reg imm
28 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
30 let EncoderMethod = "getT2SORegOpValue";
31 let PrintMethod = "printT2SOOperand";
32 let MIOperandInfo = (ops rGPR, i32imm);
33 let DecoderMethod = "DecodeSORegImmOperand";
36 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
37 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
41 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
42 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
43 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
46 // t2_so_imm - Match a 32-bit immediate operand, which is an
47 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
48 // immediate splatted into multiple bytes of the word.
49 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
50 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
51 return ARM_AM::getT2SOImmVal(Imm) != -1;
53 let ParserMatchClass = t2_so_imm_asmoperand;
54 let EncoderMethod = "getT2SOImmOpValue";
55 let DecoderMethod = "DecodeT2SOImm";
58 // t2_so_imm_not - Match an immediate that is a complement
60 def t2_so_imm_not : Operand<i32>,
62 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
63 }], t2_so_imm_not_XFORM>;
65 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
66 def t2_so_imm_neg : Operand<i32>,
68 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
69 }], t2_so_imm_neg_XFORM>;
71 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
72 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{
73 return (int32_t)Imm >= 1 && (int32_t)Imm < 32;
76 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
77 def imm0_4095 : Operand<i32>,
79 return Imm >= 0 && Imm < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 def imm0_255_neg : PatLeaf<(i32 imm), [{
87 return (uint32_t)(-N->getZExtValue()) < 255;
90 def imm0_255_not : PatLeaf<(i32 imm), [{
91 return (uint32_t)(~N->getZExtValue()) < 255;
94 def lo5AllOne : PatLeaf<(i32 imm), [{
95 // Returns true if all low 5-bits are 1.
96 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
99 // Define Thumb2 specific addressing modes.
101 // t2addrmode_imm12 := reg + imm12
102 def t2addrmode_imm12 : Operand<i32>,
103 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
104 let PrintMethod = "printAddrModeImm12Operand";
105 let EncoderMethod = "getAddrModeImm12OpValue";
106 let DecoderMethod = "DecodeT2AddrModeImm12";
107 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
110 // t2ldrlabel := imm12
111 def t2ldrlabel : Operand<i32> {
112 let EncoderMethod = "getAddrModeImm12OpValue";
116 // ADR instruction labels.
117 def t2adrlabel : Operand<i32> {
118 let EncoderMethod = "getT2AdrLabelOpValue";
122 // t2addrmode_imm8 := reg +/- imm8
123 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
124 def t2addrmode_imm8 : Operand<i32>,
125 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
126 let PrintMethod = "printT2AddrModeImm8Operand";
127 let EncoderMethod = "getT2AddrModeImm8OpValue";
128 let DecoderMethod = "DecodeT2AddrModeImm8";
129 let ParserMatchClass = MemImm8OffsetAsmOperand;
130 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
133 def t2am_imm8_offset : Operand<i32>,
134 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
135 [], [SDNPWantRoot]> {
136 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
137 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
138 let DecoderMethod = "DecodeT2Imm8";
141 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
142 def t2addrmode_imm8s4 : Operand<i32> {
143 let PrintMethod = "printT2AddrModeImm8s4Operand";
144 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
145 let DecoderMethod = "DecodeT2AddrModeImm8s4";
146 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
149 def t2am_imm8s4_offset : Operand<i32> {
150 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
151 let DecoderMethod = "DecodeT2Imm8S4";
154 // t2addrmode_so_reg := reg + (reg << imm2)
155 def t2addrmode_so_reg : Operand<i32>,
156 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
157 let PrintMethod = "printT2AddrModeSoRegOperand";
158 let EncoderMethod = "getT2AddrModeSORegOpValue";
159 let DecoderMethod = "DecodeT2AddrModeSOReg";
160 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
163 // t2addrmode_reg := reg
164 // Used by load/store exclusive instructions. Useful to enable right assembly
165 // parsing and printing. Not used for any codegen matching.
167 def t2addrmode_reg : Operand<i32> {
168 let PrintMethod = "printAddrMode7Operand";
169 let DecoderMethod = "DecodeGPRRegisterClass";
170 let MIOperandInfo = (ops GPR);
173 //===----------------------------------------------------------------------===//
174 // Multiclass helpers...
178 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
179 string opc, string asm, list<dag> pattern>
180 : T2I<oops, iops, itin, opc, asm, pattern> {
185 let Inst{26} = imm{11};
186 let Inst{14-12} = imm{10-8};
187 let Inst{7-0} = imm{7-0};
191 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
192 string opc, string asm, list<dag> pattern>
193 : T2sI<oops, iops, itin, opc, asm, pattern> {
199 let Inst{26} = imm{11};
200 let Inst{14-12} = imm{10-8};
201 let Inst{7-0} = imm{7-0};
204 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
205 string opc, string asm, list<dag> pattern>
206 : T2I<oops, iops, itin, opc, asm, pattern> {
210 let Inst{19-16} = Rn;
211 let Inst{26} = imm{11};
212 let Inst{14-12} = imm{10-8};
213 let Inst{7-0} = imm{7-0};
217 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
218 string opc, string asm, list<dag> pattern>
219 : T2I<oops, iops, itin, opc, asm, pattern> {
224 let Inst{3-0} = ShiftedRm{3-0};
225 let Inst{5-4} = ShiftedRm{6-5};
226 let Inst{14-12} = ShiftedRm{11-9};
227 let Inst{7-6} = ShiftedRm{8-7};
230 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
231 string opc, string asm, list<dag> pattern>
232 : T2sI<oops, iops, itin, opc, asm, pattern> {
237 let Inst{3-0} = ShiftedRm{3-0};
238 let Inst{5-4} = ShiftedRm{6-5};
239 let Inst{14-12} = ShiftedRm{11-9};
240 let Inst{7-6} = ShiftedRm{8-7};
243 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
244 string opc, string asm, list<dag> pattern>
245 : T2I<oops, iops, itin, opc, asm, pattern> {
249 let Inst{19-16} = Rn;
250 let Inst{3-0} = ShiftedRm{3-0};
251 let Inst{5-4} = ShiftedRm{6-5};
252 let Inst{14-12} = ShiftedRm{11-9};
253 let Inst{7-6} = ShiftedRm{8-7};
256 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
257 string opc, string asm, list<dag> pattern>
258 : T2I<oops, iops, itin, opc, asm, pattern> {
266 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
267 string opc, string asm, list<dag> pattern>
268 : T2sI<oops, iops, itin, opc, asm, pattern> {
276 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
277 string opc, string asm, list<dag> pattern>
278 : T2I<oops, iops, itin, opc, asm, pattern> {
282 let Inst{19-16} = Rn;
287 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
288 string opc, string asm, list<dag> pattern>
289 : T2I<oops, iops, itin, opc, asm, pattern> {
295 let Inst{19-16} = Rn;
296 let Inst{26} = imm{11};
297 let Inst{14-12} = imm{10-8};
298 let Inst{7-0} = imm{7-0};
301 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
302 string opc, string asm, list<dag> pattern>
303 : T2sI<oops, iops, itin, opc, asm, pattern> {
309 let Inst{19-16} = Rn;
310 let Inst{26} = imm{11};
311 let Inst{14-12} = imm{10-8};
312 let Inst{7-0} = imm{7-0};
315 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
316 string opc, string asm, list<dag> pattern>
317 : T2I<oops, iops, itin, opc, asm, pattern> {
324 let Inst{14-12} = imm{4-2};
325 let Inst{7-6} = imm{1-0};
328 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
329 string opc, string asm, list<dag> pattern>
330 : T2sI<oops, iops, itin, opc, asm, pattern> {
337 let Inst{14-12} = imm{4-2};
338 let Inst{7-6} = imm{1-0};
341 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
342 string opc, string asm, list<dag> pattern>
343 : T2I<oops, iops, itin, opc, asm, pattern> {
349 let Inst{19-16} = Rn;
353 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
354 string opc, string asm, list<dag> pattern>
355 : T2sI<oops, iops, itin, opc, asm, pattern> {
361 let Inst{19-16} = Rn;
365 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
366 string opc, string asm, list<dag> pattern>
367 : T2I<oops, iops, itin, opc, asm, pattern> {
373 let Inst{19-16} = Rn;
374 let Inst{3-0} = ShiftedRm{3-0};
375 let Inst{5-4} = ShiftedRm{6-5};
376 let Inst{14-12} = ShiftedRm{11-9};
377 let Inst{7-6} = ShiftedRm{8-7};
380 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
381 string opc, string asm, list<dag> pattern>
382 : T2sI<oops, iops, itin, opc, asm, pattern> {
388 let Inst{19-16} = Rn;
389 let Inst{3-0} = ShiftedRm{3-0};
390 let Inst{5-4} = ShiftedRm{6-5};
391 let Inst{14-12} = ShiftedRm{11-9};
392 let Inst{7-6} = ShiftedRm{8-7};
395 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
396 string opc, string asm, list<dag> pattern>
397 : T2I<oops, iops, itin, opc, asm, pattern> {
403 let Inst{19-16} = Rn;
404 let Inst{15-12} = Ra;
409 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
410 dag oops, dag iops, InstrItinClass itin,
411 string opc, string asm, list<dag> pattern>
412 : T2I<oops, iops, itin, opc, asm, pattern> {
418 let Inst{31-23} = 0b111110111;
419 let Inst{22-20} = opc22_20;
420 let Inst{19-16} = Rn;
421 let Inst{15-12} = RdLo;
422 let Inst{11-8} = RdHi;
423 let Inst{7-4} = opc7_4;
428 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
429 /// unary operation that produces a value. These are predicable and can be
430 /// changed to modify CPSR.
431 multiclass T2I_un_irs<bits<4> opcod, string opc,
432 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
433 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
435 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
437 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
438 let isAsCheapAsAMove = Cheap;
439 let isReMaterializable = ReMat;
440 let Inst{31-27} = 0b11110;
442 let Inst{24-21} = opcod;
443 let Inst{19-16} = 0b1111; // Rn
447 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
449 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
450 let Inst{31-27} = 0b11101;
451 let Inst{26-25} = 0b01;
452 let Inst{24-21} = opcod;
453 let Inst{19-16} = 0b1111; // Rn
454 let Inst{14-12} = 0b000; // imm3
455 let Inst{7-6} = 0b00; // imm2
456 let Inst{5-4} = 0b00; // type
459 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
460 opc, ".w\t$Rd, $ShiftedRm",
461 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
462 let Inst{31-27} = 0b11101;
463 let Inst{26-25} = 0b01;
464 let Inst{24-21} = opcod;
465 let Inst{19-16} = 0b1111; // Rn
469 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
470 /// binary operation that produces a value. These are predicable and can be
471 /// changed to modify CPSR.
472 multiclass T2I_bin_irs<bits<4> opcod, string opc,
473 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
474 PatFrag opnode, string baseOpc, bit Commutable = 0,
477 def ri : T2sTwoRegImm<
478 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
479 opc, "\t$Rd, $Rn, $imm",
480 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
481 let Inst{31-27} = 0b11110;
483 let Inst{24-21} = opcod;
487 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
488 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
489 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
490 let isCommutable = Commutable;
491 let Inst{31-27} = 0b11101;
492 let Inst{26-25} = 0b01;
493 let Inst{24-21} = opcod;
494 let Inst{14-12} = 0b000; // imm3
495 let Inst{7-6} = 0b00; // imm2
496 let Inst{5-4} = 0b00; // type
499 def rs : T2sTwoRegShiftedReg<
500 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
501 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
502 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
503 let Inst{31-27} = 0b11101;
504 let Inst{26-25} = 0b01;
505 let Inst{24-21} = opcod;
507 // Assembly aliases for optional destination operand when it's the same
508 // as the source operand.
509 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
510 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
511 t2_so_imm:$imm, pred:$p,
513 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
514 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
517 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
518 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
519 t2_so_reg:$shift, pred:$p,
523 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
524 // the ".w" suffix to indicate that they are wide.
525 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
526 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
527 PatFrag opnode, string baseOpc, bit Commutable = 0> :
528 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w">;
530 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
531 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
532 /// it is equivalent to the T2I_bin_irs counterpart.
533 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
535 def ri : T2sTwoRegImm<
536 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
537 opc, ".w\t$Rd, $Rn, $imm",
538 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
539 let Inst{31-27} = 0b11110;
541 let Inst{24-21} = opcod;
545 def rr : T2sThreeReg<
546 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
547 opc, "\t$Rd, $Rn, $Rm",
548 [/* For disassembly only; pattern left blank */]> {
549 let Inst{31-27} = 0b11101;
550 let Inst{26-25} = 0b01;
551 let Inst{24-21} = opcod;
552 let Inst{14-12} = 0b000; // imm3
553 let Inst{7-6} = 0b00; // imm2
554 let Inst{5-4} = 0b00; // type
557 def rs : T2sTwoRegShiftedReg<
558 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
559 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
560 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
561 let Inst{31-27} = 0b11101;
562 let Inst{26-25} = 0b01;
563 let Inst{24-21} = opcod;
567 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
568 /// instruction modifies the CPSR register.
569 let isCodeGenOnly = 1, Defs = [CPSR] in {
570 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
571 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
572 PatFrag opnode, bit Commutable = 0> {
574 def ri : T2TwoRegImm<
575 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
576 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
577 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
578 let Inst{31-27} = 0b11110;
580 let Inst{24-21} = opcod;
581 let Inst{20} = 1; // The S bit.
586 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
587 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
588 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
589 let isCommutable = Commutable;
590 let Inst{31-27} = 0b11101;
591 let Inst{26-25} = 0b01;
592 let Inst{24-21} = opcod;
593 let Inst{20} = 1; // The S bit.
594 let Inst{14-12} = 0b000; // imm3
595 let Inst{7-6} = 0b00; // imm2
596 let Inst{5-4} = 0b00; // type
599 def rs : T2TwoRegShiftedReg<
600 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
601 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
602 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
603 let Inst{31-27} = 0b11101;
604 let Inst{26-25} = 0b01;
605 let Inst{24-21} = opcod;
606 let Inst{20} = 1; // The S bit.
611 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
612 /// patterns for a binary operation that produces a value.
613 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
614 bit Commutable = 0> {
616 // The register-immediate version is re-materializable. This is useful
617 // in particular for taking the address of a local.
618 let isReMaterializable = 1 in {
619 def ri : T2sTwoRegImm<
620 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
621 opc, ".w\t$Rd, $Rn, $imm",
622 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
623 let Inst{31-27} = 0b11110;
626 let Inst{23-21} = op23_21;
632 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
633 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
634 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
638 let Inst{31-27} = 0b11110;
639 let Inst{26} = imm{11};
640 let Inst{25-24} = 0b10;
641 let Inst{23-21} = op23_21;
642 let Inst{20} = 0; // The S bit.
643 let Inst{19-16} = Rn;
645 let Inst{14-12} = imm{10-8};
647 let Inst{7-0} = imm{7-0};
650 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
651 opc, ".w\t$Rd, $Rn, $Rm",
652 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
653 let isCommutable = Commutable;
654 let Inst{31-27} = 0b11101;
655 let Inst{26-25} = 0b01;
657 let Inst{23-21} = op23_21;
658 let Inst{14-12} = 0b000; // imm3
659 let Inst{7-6} = 0b00; // imm2
660 let Inst{5-4} = 0b00; // type
663 def rs : T2sTwoRegShiftedReg<
664 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
665 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
666 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
667 let Inst{31-27} = 0b11101;
668 let Inst{26-25} = 0b01;
670 let Inst{23-21} = op23_21;
674 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
675 /// for a binary operation that produces a value and use the carry
676 /// bit. It's not predicable.
677 let Uses = [CPSR] in {
678 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
679 bit Commutable = 0> {
681 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
682 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
683 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
684 Requires<[IsThumb2]> {
685 let Inst{31-27} = 0b11110;
687 let Inst{24-21} = opcod;
691 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
692 opc, ".w\t$Rd, $Rn, $Rm",
693 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
694 Requires<[IsThumb2]> {
695 let isCommutable = Commutable;
696 let Inst{31-27} = 0b11101;
697 let Inst{26-25} = 0b01;
698 let Inst{24-21} = opcod;
699 let Inst{14-12} = 0b000; // imm3
700 let Inst{7-6} = 0b00; // imm2
701 let Inst{5-4} = 0b00; // type
704 def rs : T2sTwoRegShiftedReg<
705 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
706 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
707 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
708 Requires<[IsThumb2]> {
709 let Inst{31-27} = 0b11101;
710 let Inst{26-25} = 0b01;
711 let Inst{24-21} = opcod;
716 // Carry setting variants
717 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
718 let usesCustomInserter = 1 in {
719 multiclass T2I_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
721 def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
723 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>;
725 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
727 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
728 let isCommutable = Commutable;
731 def rs : t2PseudoInst<
732 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
734 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>;
738 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
739 /// version is not needed since this is only for codegen.
740 let isCodeGenOnly = 1, Defs = [CPSR] in {
741 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
743 def ri : T2TwoRegImm<
744 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
745 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
746 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
747 let Inst{31-27} = 0b11110;
749 let Inst{24-21} = opcod;
750 let Inst{20} = 1; // The S bit.
754 def rs : T2TwoRegShiftedReg<
755 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
756 IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
757 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
758 let Inst{31-27} = 0b11101;
759 let Inst{26-25} = 0b01;
760 let Inst{24-21} = opcod;
761 let Inst{20} = 1; // The S bit.
766 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
767 // rotate operation that produces a value.
768 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
770 def ri : T2sTwoRegShiftImm<
771 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
772 opc, ".w\t$Rd, $Rm, $imm",
773 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
774 let Inst{31-27} = 0b11101;
775 let Inst{26-21} = 0b010010;
776 let Inst{19-16} = 0b1111; // Rn
777 let Inst{5-4} = opcod;
780 def rr : T2sThreeReg<
781 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
782 opc, ".w\t$Rd, $Rn, $Rm",
783 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
784 let Inst{31-27} = 0b11111;
785 let Inst{26-23} = 0b0100;
786 let Inst{22-21} = opcod;
787 let Inst{15-12} = 0b1111;
788 let Inst{7-4} = 0b0000;
792 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
793 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
794 /// a explicit result, only implicitly set CPSR.
795 let isCompare = 1, Defs = [CPSR] in {
796 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
797 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
800 def ri : T2OneRegCmpImm<
801 (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
802 opc, ".w\t$Rn, $imm",
803 [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
804 let Inst{31-27} = 0b11110;
806 let Inst{24-21} = opcod;
807 let Inst{20} = 1; // The S bit.
809 let Inst{11-8} = 0b1111; // Rd
812 def rr : T2TwoRegCmp<
813 (outs), (ins GPR:$Rn, rGPR:$Rm), iir,
815 [(opnode GPR:$Rn, rGPR:$Rm)]> {
816 let Inst{31-27} = 0b11101;
817 let Inst{26-25} = 0b01;
818 let Inst{24-21} = opcod;
819 let Inst{20} = 1; // The S bit.
820 let Inst{14-12} = 0b000; // imm3
821 let Inst{11-8} = 0b1111; // Rd
822 let Inst{7-6} = 0b00; // imm2
823 let Inst{5-4} = 0b00; // type
826 def rs : T2OneRegCmpShiftedReg<
827 (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
828 opc, ".w\t$Rn, $ShiftedRm",
829 [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
830 let Inst{31-27} = 0b11101;
831 let Inst{26-25} = 0b01;
832 let Inst{24-21} = opcod;
833 let Inst{20} = 1; // The S bit.
834 let Inst{11-8} = 0b1111; // Rd
839 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
840 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
841 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
843 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
844 opc, ".w\t$Rt, $addr",
845 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
846 let Inst{31-27} = 0b11111;
847 let Inst{26-25} = 0b00;
848 let Inst{24} = signed;
850 let Inst{22-21} = opcod;
851 let Inst{20} = 1; // load
854 let Inst{15-12} = Rt;
857 let addr{12} = 1; // add = TRUE
858 let Inst{19-16} = addr{16-13}; // Rn
859 let Inst{23} = addr{12}; // U
860 let Inst{11-0} = addr{11-0}; // imm
862 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_imm8:$addr), iii,
864 [(set target:$Rt, (opnode t2addrmode_imm8:$addr))]> {
865 let Inst{31-27} = 0b11111;
866 let Inst{26-25} = 0b00;
867 let Inst{24} = signed;
869 let Inst{22-21} = opcod;
870 let Inst{20} = 1; // load
872 // Offset: index==TRUE, wback==FALSE
873 let Inst{10} = 1; // The P bit.
874 let Inst{8} = 0; // The W bit.
877 let Inst{15-12} = Rt;
880 let Inst{19-16} = addr{12-9}; // Rn
881 let Inst{9} = addr{8}; // U
882 let Inst{7-0} = addr{7-0}; // imm
884 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
885 opc, ".w\t$Rt, $addr",
886 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
887 let Inst{31-27} = 0b11111;
888 let Inst{26-25} = 0b00;
889 let Inst{24} = signed;
891 let Inst{22-21} = opcod;
892 let Inst{20} = 1; // load
893 let Inst{11-6} = 0b000000;
896 let Inst{15-12} = Rt;
899 let Inst{19-16} = addr{9-6}; // Rn
900 let Inst{3-0} = addr{5-2}; // Rm
901 let Inst{5-4} = addr{1-0}; // imm
903 let DecoderMethod = "DecodeT2LoadShift";
906 // FIXME: Is the pci variant actually needed?
907 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
908 opc, ".w\t$Rt, $addr",
909 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
910 let isReMaterializable = 1;
911 let Inst{31-27} = 0b11111;
912 let Inst{26-25} = 0b00;
913 let Inst{24} = signed;
914 let Inst{23} = ?; // add = (U == '1')
915 let Inst{22-21} = opcod;
916 let Inst{20} = 1; // load
917 let Inst{19-16} = 0b1111; // Rn
920 let Inst{15-12} = Rt{3-0};
921 let Inst{11-0} = addr{11-0};
925 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
926 multiclass T2I_st<bits<2> opcod, string opc,
927 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
929 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
930 opc, ".w\t$Rt, $addr",
931 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
932 let Inst{31-27} = 0b11111;
933 let Inst{26-23} = 0b0001;
934 let Inst{22-21} = opcod;
935 let Inst{20} = 0; // !load
938 let Inst{15-12} = Rt;
941 let addr{12} = 1; // add = TRUE
942 let Inst{19-16} = addr{16-13}; // Rn
943 let Inst{23} = addr{12}; // U
944 let Inst{11-0} = addr{11-0}; // imm
946 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_imm8:$addr), iii,
948 [(opnode target:$Rt, t2addrmode_imm8:$addr)]> {
949 let Inst{31-27} = 0b11111;
950 let Inst{26-23} = 0b0000;
951 let Inst{22-21} = opcod;
952 let Inst{20} = 0; // !load
954 // Offset: index==TRUE, wback==FALSE
955 let Inst{10} = 1; // The P bit.
956 let Inst{8} = 0; // The W bit.
959 let Inst{15-12} = Rt;
962 let Inst{19-16} = addr{12-9}; // Rn
963 let Inst{9} = addr{8}; // U
964 let Inst{7-0} = addr{7-0}; // imm
966 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
967 opc, ".w\t$Rt, $addr",
968 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
969 let Inst{31-27} = 0b11111;
970 let Inst{26-23} = 0b0000;
971 let Inst{22-21} = opcod;
972 let Inst{20} = 0; // !load
973 let Inst{11-6} = 0b000000;
976 let Inst{15-12} = Rt;
979 let Inst{19-16} = addr{9-6}; // Rn
980 let Inst{3-0} = addr{5-2}; // Rm
981 let Inst{5-4} = addr{1-0}; // imm
985 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
986 /// register and one whose operand is a register rotated by 8/16/24.
987 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
988 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
989 opc, ".w\t$Rd, $Rm$rot",
990 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
991 Requires<[IsThumb2]> {
992 let Inst{31-27} = 0b11111;
993 let Inst{26-23} = 0b0100;
994 let Inst{22-20} = opcod;
995 let Inst{19-16} = 0b1111; // Rn
996 let Inst{15-12} = 0b1111;
1000 let Inst{5-4} = rot{1-0}; // rotate
1003 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1004 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1005 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1006 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1007 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1008 Requires<[HasT2ExtractPack, IsThumb2]> {
1010 let Inst{31-27} = 0b11111;
1011 let Inst{26-23} = 0b0100;
1012 let Inst{22-20} = opcod;
1013 let Inst{19-16} = 0b1111; // Rn
1014 let Inst{15-12} = 0b1111;
1016 let Inst{5-4} = rot;
1019 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1021 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1022 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1023 opc, "\t$Rd, $Rm$rot", []>,
1024 Requires<[IsThumb2, HasT2ExtractPack]> {
1026 let Inst{31-27} = 0b11111;
1027 let Inst{26-23} = 0b0100;
1028 let Inst{22-20} = opcod;
1029 let Inst{19-16} = 0b1111; // Rn
1030 let Inst{15-12} = 0b1111;
1032 let Inst{5-4} = rot;
1035 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1036 /// register and one whose operand is a register rotated by 8/16/24.
1037 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1038 : T2ThreeReg<(outs rGPR:$Rd),
1039 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1040 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1041 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1042 Requires<[HasT2ExtractPack, IsThumb2]> {
1044 let Inst{31-27} = 0b11111;
1045 let Inst{26-23} = 0b0100;
1046 let Inst{22-20} = opcod;
1047 let Inst{15-12} = 0b1111;
1049 let Inst{5-4} = rot;
1052 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1053 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1054 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1056 let Inst{31-27} = 0b11111;
1057 let Inst{26-23} = 0b0100;
1058 let Inst{22-20} = opcod;
1059 let Inst{15-12} = 0b1111;
1061 let Inst{5-4} = rot;
1064 //===----------------------------------------------------------------------===//
1066 //===----------------------------------------------------------------------===//
1068 //===----------------------------------------------------------------------===//
1069 // Miscellaneous Instructions.
1072 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1073 string asm, list<dag> pattern>
1074 : T2XI<oops, iops, itin, asm, pattern> {
1078 let Inst{11-8} = Rd;
1079 let Inst{26} = label{11};
1080 let Inst{14-12} = label{10-8};
1081 let Inst{7-0} = label{7-0};
1084 // LEApcrel - Load a pc-relative address into a register without offending the
1086 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1087 (ins t2adrlabel:$addr, pred:$p),
1088 IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1089 let Inst{31-27} = 0b11110;
1090 let Inst{25-24} = 0b10;
1091 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1094 let Inst{19-16} = 0b1111; // Rn
1099 let Inst{11-8} = Rd;
1100 let Inst{23} = addr{12};
1101 let Inst{21} = addr{12};
1102 let Inst{26} = addr{11};
1103 let Inst{14-12} = addr{10-8};
1104 let Inst{7-0} = addr{7-0};
1107 let neverHasSideEffects = 1, isReMaterializable = 1 in
1108 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1110 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1111 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1116 //===----------------------------------------------------------------------===//
1117 // Load / store Instructions.
1121 let canFoldAsLoad = 1, isReMaterializable = 1 in
1122 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1123 UnOpFrag<(load node:$Src)>>;
1125 // Loads with zero extension
1126 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1127 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1128 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1129 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1131 // Loads with sign extension
1132 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1133 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1134 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1135 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1137 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1139 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1140 (ins t2addrmode_imm8s4:$addr),
1141 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1142 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1144 // zextload i1 -> zextload i8
1145 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1146 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1147 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1148 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1149 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1150 (t2LDRBs t2addrmode_so_reg:$addr)>;
1151 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1152 (t2LDRBpci tconstpool:$addr)>;
1154 // extload -> zextload
1155 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1157 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1158 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1159 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1160 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1161 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1162 (t2LDRBs t2addrmode_so_reg:$addr)>;
1163 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1164 (t2LDRBpci tconstpool:$addr)>;
1166 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1167 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1168 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1169 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1170 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1171 (t2LDRBs t2addrmode_so_reg:$addr)>;
1172 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1173 (t2LDRBpci tconstpool:$addr)>;
1175 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1176 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1177 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1178 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1179 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1180 (t2LDRHs t2addrmode_so_reg:$addr)>;
1181 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1182 (t2LDRHpci tconstpool:$addr)>;
1184 // FIXME: The destination register of the loads and stores can't be PC, but
1185 // can be SP. We need another regclass (similar to rGPR) to represent
1186 // that. Not a pressing issue since these are selected manually,
1191 let mayLoad = 1, neverHasSideEffects = 1 in {
1192 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1193 (ins t2addrmode_imm8:$addr),
1194 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1195 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1198 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1199 (ins GPR:$base, t2am_imm8_offset:$addr),
1200 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1201 "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1204 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1205 (ins t2addrmode_imm8:$addr),
1206 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1207 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1209 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1210 (ins GPR:$base, t2am_imm8_offset:$addr),
1211 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1212 "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1215 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1216 (ins t2addrmode_imm8:$addr),
1217 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1218 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1220 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1221 (ins GPR:$base, t2am_imm8_offset:$addr),
1222 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1223 "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1226 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1227 (ins t2addrmode_imm8:$addr),
1228 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1229 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1231 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1232 (ins GPR:$base, t2am_imm8_offset:$addr),
1233 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1234 "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1237 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1238 (ins t2addrmode_imm8:$addr),
1239 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1240 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1242 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1243 (ins GPR:$base, t2am_imm8_offset:$addr),
1244 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1245 "ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1247 } // mayLoad = 1, neverHasSideEffects = 1
1249 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1250 // for disassembly only.
1251 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1252 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1253 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1254 "\t$Rt, $addr", []> {
1255 let Inst{31-27} = 0b11111;
1256 let Inst{26-25} = 0b00;
1257 let Inst{24} = signed;
1259 let Inst{22-21} = type;
1260 let Inst{20} = 1; // load
1262 let Inst{10-8} = 0b110; // PUW.
1266 let Inst{15-12} = Rt;
1267 let Inst{19-16} = addr{12-9};
1268 let Inst{7-0} = addr{7-0};
1271 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1272 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1273 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1274 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1275 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1278 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1279 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1280 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1281 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1282 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1283 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1286 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1287 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1288 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1289 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1292 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPRnopc:$base_wb),
1293 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1294 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1295 "str", "\t$Rt, [$Rn, $addr]!",
1296 "$Rn = $base_wb,@earlyclobber $base_wb",
1297 [(set GPRnopc:$base_wb,
1298 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1300 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPRnopc:$base_wb),
1301 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1302 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1303 "str", "\t$Rt, [$Rn], $addr",
1304 "$Rn = $base_wb,@earlyclobber $base_wb",
1305 [(set GPRnopc:$base_wb,
1306 (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1308 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPRnopc:$base_wb),
1309 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1310 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1311 "strh", "\t$Rt, [$Rn, $addr]!",
1312 "$Rn = $base_wb,@earlyclobber $base_wb",
1313 [(set GPRnopc:$base_wb,
1314 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1316 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPRnopc:$base_wb),
1317 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1318 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1319 "strh", "\t$Rt, [$Rn], $addr",
1320 "$Rn = $base_wb,@earlyclobber $base_wb",
1321 [(set GPRnopc:$base_wb,
1322 (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1324 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPRnopc:$base_wb),
1325 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1326 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1327 "strb", "\t$Rt, [$Rn, $addr]!",
1328 "$Rn = $base_wb,@earlyclobber $base_wb",
1329 [(set GPRnopc:$base_wb,
1330 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1332 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPRnopc:$base_wb),
1333 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1334 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1335 "strb", "\t$Rt, [$Rn], $addr",
1336 "$Rn = $base_wb,@earlyclobber $base_wb",
1337 [(set GPRnopc:$base_wb,
1338 (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1340 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1342 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1343 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1344 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1345 "\t$Rt, $addr", []> {
1346 let Inst{31-27} = 0b11111;
1347 let Inst{26-25} = 0b00;
1348 let Inst{24} = 0; // not signed
1350 let Inst{22-21} = type;
1351 let Inst{20} = 0; // store
1353 let Inst{10-8} = 0b110; // PUW
1357 let Inst{15-12} = Rt;
1358 let Inst{19-16} = addr{12-9};
1359 let Inst{7-0} = addr{7-0};
1362 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1363 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1364 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1366 // ldrd / strd pre / post variants
1367 // For disassembly only.
1369 def t2LDRD_PRE : T2Ii8s4Tied<1, 1, 1,
1370 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1371 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1372 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1374 def t2LDRD_POST : T2Ii8s4Tied<0, 1, 1,
1375 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1376 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1377 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1379 def t2STRD_PRE : T2Ii8s4Tied<1, 1, 0, (outs GPR:$wb),
1380 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1381 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1383 def t2STRD_POST : T2Ii8s4Tied<0, 1, 0, (outs GPR:$wb),
1384 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1385 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1387 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1388 // data/instruction access. These are for disassembly only.
1389 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1390 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1391 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1393 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1395 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1396 let Inst{31-25} = 0b1111100;
1397 let Inst{24} = instr;
1399 let Inst{21} = write;
1401 let Inst{15-12} = 0b1111;
1404 let addr{12} = 1; // add = TRUE
1405 let Inst{19-16} = addr{16-13}; // Rn
1406 let Inst{23} = addr{12}; // U
1407 let Inst{11-0} = addr{11-0}; // imm12
1410 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1412 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1413 let Inst{31-25} = 0b1111100;
1414 let Inst{24} = instr;
1415 let Inst{23} = 0; // U = 0
1417 let Inst{21} = write;
1419 let Inst{15-12} = 0b1111;
1420 let Inst{11-8} = 0b1100;
1423 let Inst{19-16} = addr{12-9}; // Rn
1424 let Inst{7-0} = addr{7-0}; // imm8
1427 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1429 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1430 let Inst{31-25} = 0b1111100;
1431 let Inst{24} = instr;
1432 let Inst{23} = 0; // add = TRUE for T1
1434 let Inst{21} = write;
1436 let Inst{15-12} = 0b1111;
1437 let Inst{11-6} = 0000000;
1440 let Inst{19-16} = addr{9-6}; // Rn
1441 let Inst{3-0} = addr{5-2}; // Rm
1442 let Inst{5-4} = addr{1-0}; // imm2
1444 let DecoderMethod = "DecodeT2LoadShift";
1448 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1449 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1450 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1452 //===----------------------------------------------------------------------===//
1453 // Load / store multiple Instructions.
1456 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1457 InstrItinClass itin_upd, bit L_bit> {
1459 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1460 itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1464 let Inst{31-27} = 0b11101;
1465 let Inst{26-25} = 0b00;
1466 let Inst{24-23} = 0b01; // Increment After
1468 let Inst{21} = 0; // No writeback
1469 let Inst{20} = L_bit;
1470 let Inst{19-16} = Rn;
1471 let Inst{15-0} = regs;
1474 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1475 itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1479 let Inst{31-27} = 0b11101;
1480 let Inst{26-25} = 0b00;
1481 let Inst{24-23} = 0b01; // Increment After
1483 let Inst{21} = 1; // Writeback
1484 let Inst{20} = L_bit;
1485 let Inst{19-16} = Rn;
1486 let Inst{15-0} = regs;
1489 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1490 itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1494 let Inst{31-27} = 0b11101;
1495 let Inst{26-25} = 0b00;
1496 let Inst{24-23} = 0b10; // Decrement Before
1498 let Inst{21} = 0; // No writeback
1499 let Inst{20} = L_bit;
1500 let Inst{19-16} = Rn;
1501 let Inst{15-0} = regs;
1504 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1505 itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1509 let Inst{31-27} = 0b11101;
1510 let Inst{26-25} = 0b00;
1511 let Inst{24-23} = 0b10; // Decrement Before
1513 let Inst{21} = 1; // Writeback
1514 let Inst{20} = L_bit;
1515 let Inst{19-16} = Rn;
1516 let Inst{15-0} = regs;
1520 let neverHasSideEffects = 1 in {
1522 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1523 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1525 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1526 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1528 } // neverHasSideEffects
1531 //===----------------------------------------------------------------------===//
1532 // Move Instructions.
1535 let neverHasSideEffects = 1 in
1536 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1537 "mov", ".w\t$Rd, $Rm", []> {
1538 let Inst{31-27} = 0b11101;
1539 let Inst{26-25} = 0b01;
1540 let Inst{24-21} = 0b0010;
1541 let Inst{19-16} = 0b1111; // Rn
1542 let Inst{14-12} = 0b000;
1543 let Inst{7-4} = 0b0000;
1546 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1547 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1548 AddedComplexity = 1 in
1549 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1550 "mov", ".w\t$Rd, $imm",
1551 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1552 let Inst{31-27} = 0b11110;
1554 let Inst{24-21} = 0b0010;
1555 let Inst{19-16} = 0b1111; // Rn
1559 def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1560 pred:$p, cc_out:$s)>;
1562 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1563 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1564 "movw", "\t$Rd, $imm",
1565 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1566 let Inst{31-27} = 0b11110;
1568 let Inst{24-21} = 0b0010;
1569 let Inst{20} = 0; // The S bit.
1575 let Inst{11-8} = Rd;
1576 let Inst{19-16} = imm{15-12};
1577 let Inst{26} = imm{11};
1578 let Inst{14-12} = imm{10-8};
1579 let Inst{7-0} = imm{7-0};
1582 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1583 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1585 let Constraints = "$src = $Rd" in {
1586 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1587 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1588 "movt", "\t$Rd, $imm",
1590 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1591 let Inst{31-27} = 0b11110;
1593 let Inst{24-21} = 0b0110;
1594 let Inst{20} = 0; // The S bit.
1600 let Inst{11-8} = Rd;
1601 let Inst{19-16} = imm{15-12};
1602 let Inst{26} = imm{11};
1603 let Inst{14-12} = imm{10-8};
1604 let Inst{7-0} = imm{7-0};
1607 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1608 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1611 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1613 //===----------------------------------------------------------------------===//
1614 // Extend Instructions.
1619 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1620 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1621 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1622 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1623 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1625 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1626 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1627 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1628 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1629 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1631 // TODO: SXT(A){B|H}16
1635 let AddedComplexity = 16 in {
1636 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1637 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1638 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1639 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1640 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1641 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1643 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1644 // The transformation should probably be done as a combiner action
1645 // instead so we can include a check for masking back in the upper
1646 // eight bits of the source into the lower eight bits of the result.
1647 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1648 // (t2UXTB16 rGPR:$Src, 3)>,
1649 // Requires<[HasT2ExtractPack, IsThumb2]>;
1650 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1651 (t2UXTB16 rGPR:$Src, 1)>,
1652 Requires<[HasT2ExtractPack, IsThumb2]>;
1654 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1655 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1656 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1657 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1658 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1661 //===----------------------------------------------------------------------===//
1662 // Arithmetic Instructions.
1665 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1666 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1667 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1668 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1670 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1671 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1672 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1673 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1674 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1675 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1676 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1678 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1679 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1680 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1681 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1682 defm t2ADCS : T2I_adde_sube_s_irs<BinOpFrag<(adde_live_carry node:$LHS,
1684 defm t2SBCS : T2I_adde_sube_s_irs<BinOpFrag<(sube_live_carry node:$LHS,
1688 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1689 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1690 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1691 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1693 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1694 // The assume-no-carry-in form uses the negation of the input since add/sub
1695 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1696 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1698 // The AddedComplexity preferences the first variant over the others since
1699 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1700 let AddedComplexity = 1 in
1701 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1702 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1703 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1704 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1705 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1706 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1707 let AddedComplexity = 1 in
1708 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1709 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1710 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1711 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1712 // The with-carry-in form matches bitwise not instead of the negation.
1713 // Effectively, the inverse interpretation of the carry flag already accounts
1714 // for part of the negation.
1715 let AddedComplexity = 1 in
1716 def : T2Pat<(adde_dead_carry rGPR:$src, imm0_255_not:$imm),
1717 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1718 def : T2Pat<(adde_dead_carry rGPR:$src, t2_so_imm_not:$imm),
1719 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1720 let AddedComplexity = 1 in
1721 def : T2Pat<(adde_live_carry rGPR:$src, imm0_255_not:$imm),
1722 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1723 def : T2Pat<(adde_live_carry rGPR:$src, t2_so_imm_not:$imm),
1724 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1726 // Select Bytes -- for disassembly only
1728 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1729 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1730 Requires<[IsThumb2, HasThumb2DSP]> {
1731 let Inst{31-27} = 0b11111;
1732 let Inst{26-24} = 0b010;
1734 let Inst{22-20} = 0b010;
1735 let Inst{15-12} = 0b1111;
1737 let Inst{6-4} = 0b000;
1740 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1741 // And Miscellaneous operations -- for disassembly only
1742 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1743 list<dag> pat = [/* For disassembly only; pattern left blank */],
1744 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1745 string asm = "\t$Rd, $Rn, $Rm">
1746 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1747 Requires<[IsThumb2, HasThumb2DSP]> {
1748 let Inst{31-27} = 0b11111;
1749 let Inst{26-23} = 0b0101;
1750 let Inst{22-20} = op22_20;
1751 let Inst{15-12} = 0b1111;
1752 let Inst{7-4} = op7_4;
1758 let Inst{11-8} = Rd;
1759 let Inst{19-16} = Rn;
1763 // Saturating add/subtract -- for disassembly only
1765 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1766 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1767 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1768 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1769 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1770 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1771 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1772 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1773 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1774 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1775 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1776 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1777 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1778 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1779 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1780 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1781 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1782 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1783 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1784 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1785 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1786 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1788 // Signed/Unsigned add/subtract -- for disassembly only
1790 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1791 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1792 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1793 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1794 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1795 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1796 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1797 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1798 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1799 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1800 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1801 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1803 // Signed/Unsigned halving add/subtract -- for disassembly only
1805 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1806 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1807 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1808 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1809 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1810 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1811 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1812 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1813 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1814 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1815 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1816 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1818 // Helper class for disassembly only
1819 // A6.3.16 & A6.3.17
1820 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1821 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1822 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1823 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1824 let Inst{31-27} = 0b11111;
1825 let Inst{26-24} = 0b011;
1826 let Inst{23} = long;
1827 let Inst{22-20} = op22_20;
1828 let Inst{7-4} = op7_4;
1831 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1832 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1833 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1834 let Inst{31-27} = 0b11111;
1835 let Inst{26-24} = 0b011;
1836 let Inst{23} = long;
1837 let Inst{22-20} = op22_20;
1838 let Inst{7-4} = op7_4;
1841 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1843 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1844 (ins rGPR:$Rn, rGPR:$Rm),
1845 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1846 Requires<[IsThumb2, HasThumb2DSP]> {
1847 let Inst{15-12} = 0b1111;
1849 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1850 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1851 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1852 Requires<[IsThumb2, HasThumb2DSP]>;
1854 // Signed/Unsigned saturate -- for disassembly only
1856 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1857 string opc, string asm, list<dag> pattern>
1858 : T2I<oops, iops, itin, opc, asm, pattern> {
1864 let Inst{11-8} = Rd;
1865 let Inst{19-16} = Rn;
1866 let Inst{4-0} = sat_imm;
1867 let Inst{21} = sh{5};
1868 let Inst{14-12} = sh{4-2};
1869 let Inst{7-6} = sh{1-0};
1873 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1874 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1875 [/* For disassembly only; pattern left blank */]> {
1876 let Inst{31-27} = 0b11110;
1877 let Inst{25-22} = 0b1100;
1882 def t2SSAT16: T2SatI<
1883 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
1884 "ssat16", "\t$Rd, $sat_imm, $Rn",
1885 [/* For disassembly only; pattern left blank */]>,
1886 Requires<[IsThumb2, HasThumb2DSP]> {
1887 let Inst{31-27} = 0b11110;
1888 let Inst{25-22} = 0b1100;
1891 let Inst{21} = 1; // sh = '1'
1892 let Inst{14-12} = 0b000; // imm3 = '000'
1893 let Inst{7-6} = 0b00; // imm2 = '00'
1897 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1898 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1899 [/* For disassembly only; pattern left blank */]> {
1900 let Inst{31-27} = 0b11110;
1901 let Inst{25-22} = 0b1110;
1906 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn),
1908 "usat16", "\t$Rd, $sat_imm, $Rn",
1909 [/* For disassembly only; pattern left blank */]>,
1910 Requires<[IsThumb2, HasThumb2DSP]> {
1911 let Inst{31-27} = 0b11110;
1912 let Inst{25-22} = 0b1110;
1915 let Inst{21} = 1; // sh = '1'
1916 let Inst{14-12} = 0b000; // imm3 = '000'
1917 let Inst{7-6} = 0b00; // imm2 = '00'
1920 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1921 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1923 //===----------------------------------------------------------------------===//
1924 // Shift and rotate Instructions.
1927 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1928 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1929 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1930 defm t2ROR : T2I_sh_ir<0b11, "ror", imm1_31, BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1932 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
1933 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
1934 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
1936 let Uses = [CPSR] in {
1937 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1938 "rrx", "\t$Rd, $Rm",
1939 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
1940 let Inst{31-27} = 0b11101;
1941 let Inst{26-25} = 0b01;
1942 let Inst{24-21} = 0b0010;
1943 let Inst{19-16} = 0b1111; // Rn
1944 let Inst{14-12} = 0b000;
1945 let Inst{7-4} = 0b0011;
1949 let isCodeGenOnly = 1, Defs = [CPSR] in {
1950 def t2MOVsrl_flag : T2TwoRegShiftImm<
1951 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1952 "lsrs", ".w\t$Rd, $Rm, #1",
1953 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
1954 let Inst{31-27} = 0b11101;
1955 let Inst{26-25} = 0b01;
1956 let Inst{24-21} = 0b0010;
1957 let Inst{20} = 1; // The S bit.
1958 let Inst{19-16} = 0b1111; // Rn
1959 let Inst{5-4} = 0b01; // Shift type.
1960 // Shift amount = Inst{14-12:7-6} = 1.
1961 let Inst{14-12} = 0b000;
1962 let Inst{7-6} = 0b01;
1964 def t2MOVsra_flag : T2TwoRegShiftImm<
1965 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1966 "asrs", ".w\t$Rd, $Rm, #1",
1967 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
1968 let Inst{31-27} = 0b11101;
1969 let Inst{26-25} = 0b01;
1970 let Inst{24-21} = 0b0010;
1971 let Inst{20} = 1; // The S bit.
1972 let Inst{19-16} = 0b1111; // Rn
1973 let Inst{5-4} = 0b10; // Shift type.
1974 // Shift amount = Inst{14-12:7-6} = 1.
1975 let Inst{14-12} = 0b000;
1976 let Inst{7-6} = 0b01;
1980 //===----------------------------------------------------------------------===//
1981 // Bitwise Instructions.
1984 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1985 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1986 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
1987 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1988 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1989 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
1990 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1991 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1992 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
1994 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1995 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1996 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
1999 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2000 string opc, string asm, list<dag> pattern>
2001 : T2I<oops, iops, itin, opc, asm, pattern> {
2006 let Inst{11-8} = Rd;
2007 let Inst{4-0} = msb{4-0};
2008 let Inst{14-12} = lsb{4-2};
2009 let Inst{7-6} = lsb{1-0};
2012 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2013 string opc, string asm, list<dag> pattern>
2014 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2017 let Inst{19-16} = Rn;
2020 let Constraints = "$src = $Rd" in
2021 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2022 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2023 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2024 let Inst{31-27} = 0b11110;
2025 let Inst{26} = 0; // should be 0.
2027 let Inst{24-20} = 0b10110;
2028 let Inst{19-16} = 0b1111; // Rn
2030 let Inst{5} = 0; // should be 0.
2033 let msb{4-0} = imm{9-5};
2034 let lsb{4-0} = imm{4-0};
2037 def t2SBFX: T2TwoRegBitFI<
2038 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2039 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2040 let Inst{31-27} = 0b11110;
2042 let Inst{24-20} = 0b10100;
2046 def t2UBFX: T2TwoRegBitFI<
2047 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2048 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2049 let Inst{31-27} = 0b11110;
2051 let Inst{24-20} = 0b11100;
2055 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2056 let Constraints = "$src = $Rd" in {
2057 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2058 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2059 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2060 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2061 bf_inv_mask_imm:$imm))]> {
2062 let Inst{31-27} = 0b11110;
2063 let Inst{26} = 0; // should be 0.
2065 let Inst{24-20} = 0b10110;
2067 let Inst{5} = 0; // should be 0.
2070 let msb{4-0} = imm{9-5};
2071 let lsb{4-0} = imm{4-0};
2074 // GNU as only supports this form of bfi (w/ 4 arguments)
2075 let isAsmParserOnly = 1 in
2076 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2077 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2079 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2081 let Inst{31-27} = 0b11110;
2082 let Inst{26} = 0; // should be 0.
2084 let Inst{24-20} = 0b10110;
2086 let Inst{5} = 0; // should be 0.
2090 let msb{4-0} = width; // Custom encoder => lsb+width-1
2091 let lsb{4-0} = lsbit;
2095 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2096 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2097 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2100 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2101 let AddedComplexity = 1 in
2102 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2103 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2104 UnOpFrag<(not node:$Src)>, 1, 1>;
2107 let AddedComplexity = 1 in
2108 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2109 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2111 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2112 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2113 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2114 Requires<[IsThumb2]>;
2116 def : T2Pat<(t2_so_imm_not:$src),
2117 (t2MVNi t2_so_imm_not:$src)>;
2119 //===----------------------------------------------------------------------===//
2120 // Multiply Instructions.
2122 let isCommutable = 1 in
2123 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2124 "mul", "\t$Rd, $Rn, $Rm",
2125 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2126 let Inst{31-27} = 0b11111;
2127 let Inst{26-23} = 0b0110;
2128 let Inst{22-20} = 0b000;
2129 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2130 let Inst{7-4} = 0b0000; // Multiply
2133 def t2MLA: T2FourReg<
2134 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2135 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2136 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2137 let Inst{31-27} = 0b11111;
2138 let Inst{26-23} = 0b0110;
2139 let Inst{22-20} = 0b000;
2140 let Inst{7-4} = 0b0000; // Multiply
2143 def t2MLS: T2FourReg<
2144 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2145 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2146 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2147 let Inst{31-27} = 0b11111;
2148 let Inst{26-23} = 0b0110;
2149 let Inst{22-20} = 0b000;
2150 let Inst{7-4} = 0b0001; // Multiply and Subtract
2153 // Extra precision multiplies with low / high results
2154 let neverHasSideEffects = 1 in {
2155 let isCommutable = 1 in {
2156 def t2SMULL : T2MulLong<0b000, 0b0000,
2157 (outs rGPR:$RdLo, rGPR:$RdHi),
2158 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2159 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2161 def t2UMULL : T2MulLong<0b010, 0b0000,
2162 (outs rGPR:$RdLo, rGPR:$RdHi),
2163 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2164 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2167 // Multiply + accumulate
2168 def t2SMLAL : T2MulLong<0b100, 0b0000,
2169 (outs rGPR:$RdLo, rGPR:$RdHi),
2170 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2171 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2173 def t2UMLAL : T2MulLong<0b110, 0b0000,
2174 (outs rGPR:$RdLo, rGPR:$RdHi),
2175 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2176 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2178 def t2UMAAL : T2MulLong<0b110, 0b0110,
2179 (outs rGPR:$RdLo, rGPR:$RdHi),
2180 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2181 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2182 Requires<[IsThumb2, HasThumb2DSP]>;
2183 } // neverHasSideEffects
2185 // Rounding variants of the below included for disassembly only
2187 // Most significant word multiply
2188 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2189 "smmul", "\t$Rd, $Rn, $Rm",
2190 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2191 Requires<[IsThumb2, HasThumb2DSP]> {
2192 let Inst{31-27} = 0b11111;
2193 let Inst{26-23} = 0b0110;
2194 let Inst{22-20} = 0b101;
2195 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2196 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2199 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2200 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2201 Requires<[IsThumb2, HasThumb2DSP]> {
2202 let Inst{31-27} = 0b11111;
2203 let Inst{26-23} = 0b0110;
2204 let Inst{22-20} = 0b101;
2205 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2206 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2209 def t2SMMLA : T2FourReg<
2210 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2211 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2212 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2213 Requires<[IsThumb2, HasThumb2DSP]> {
2214 let Inst{31-27} = 0b11111;
2215 let Inst{26-23} = 0b0110;
2216 let Inst{22-20} = 0b101;
2217 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2220 def t2SMMLAR: T2FourReg<
2221 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2222 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2223 Requires<[IsThumb2, HasThumb2DSP]> {
2224 let Inst{31-27} = 0b11111;
2225 let Inst{26-23} = 0b0110;
2226 let Inst{22-20} = 0b101;
2227 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2230 def t2SMMLS: T2FourReg<
2231 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2232 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2233 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2234 Requires<[IsThumb2, HasThumb2DSP]> {
2235 let Inst{31-27} = 0b11111;
2236 let Inst{26-23} = 0b0110;
2237 let Inst{22-20} = 0b110;
2238 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2241 def t2SMMLSR:T2FourReg<
2242 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2243 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2244 Requires<[IsThumb2, HasThumb2DSP]> {
2245 let Inst{31-27} = 0b11111;
2246 let Inst{26-23} = 0b0110;
2247 let Inst{22-20} = 0b110;
2248 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2251 multiclass T2I_smul<string opc, PatFrag opnode> {
2252 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2253 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2254 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2255 (sext_inreg rGPR:$Rm, i16)))]>,
2256 Requires<[IsThumb2, HasThumb2DSP]> {
2257 let Inst{31-27} = 0b11111;
2258 let Inst{26-23} = 0b0110;
2259 let Inst{22-20} = 0b001;
2260 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2261 let Inst{7-6} = 0b00;
2262 let Inst{5-4} = 0b00;
2265 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2266 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2267 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2268 (sra rGPR:$Rm, (i32 16))))]>,
2269 Requires<[IsThumb2, HasThumb2DSP]> {
2270 let Inst{31-27} = 0b11111;
2271 let Inst{26-23} = 0b0110;
2272 let Inst{22-20} = 0b001;
2273 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2274 let Inst{7-6} = 0b00;
2275 let Inst{5-4} = 0b01;
2278 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2279 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2280 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2281 (sext_inreg rGPR:$Rm, i16)))]>,
2282 Requires<[IsThumb2, HasThumb2DSP]> {
2283 let Inst{31-27} = 0b11111;
2284 let Inst{26-23} = 0b0110;
2285 let Inst{22-20} = 0b001;
2286 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2287 let Inst{7-6} = 0b00;
2288 let Inst{5-4} = 0b10;
2291 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2292 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2293 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2294 (sra rGPR:$Rm, (i32 16))))]>,
2295 Requires<[IsThumb2, HasThumb2DSP]> {
2296 let Inst{31-27} = 0b11111;
2297 let Inst{26-23} = 0b0110;
2298 let Inst{22-20} = 0b001;
2299 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2300 let Inst{7-6} = 0b00;
2301 let Inst{5-4} = 0b11;
2304 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2305 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2306 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2307 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2308 Requires<[IsThumb2, HasThumb2DSP]> {
2309 let Inst{31-27} = 0b11111;
2310 let Inst{26-23} = 0b0110;
2311 let Inst{22-20} = 0b011;
2312 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2313 let Inst{7-6} = 0b00;
2314 let Inst{5-4} = 0b00;
2317 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2318 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2319 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2320 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2321 Requires<[IsThumb2, HasThumb2DSP]> {
2322 let Inst{31-27} = 0b11111;
2323 let Inst{26-23} = 0b0110;
2324 let Inst{22-20} = 0b011;
2325 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2326 let Inst{7-6} = 0b00;
2327 let Inst{5-4} = 0b01;
2332 multiclass T2I_smla<string opc, PatFrag opnode> {
2334 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2335 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2336 [(set rGPR:$Rd, (add rGPR:$Ra,
2337 (opnode (sext_inreg rGPR:$Rn, i16),
2338 (sext_inreg rGPR:$Rm, i16))))]>,
2339 Requires<[IsThumb2, HasThumb2DSP]> {
2340 let Inst{31-27} = 0b11111;
2341 let Inst{26-23} = 0b0110;
2342 let Inst{22-20} = 0b001;
2343 let Inst{7-6} = 0b00;
2344 let Inst{5-4} = 0b00;
2348 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2349 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2350 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2351 (sra rGPR:$Rm, (i32 16)))))]>,
2352 Requires<[IsThumb2, HasThumb2DSP]> {
2353 let Inst{31-27} = 0b11111;
2354 let Inst{26-23} = 0b0110;
2355 let Inst{22-20} = 0b001;
2356 let Inst{7-6} = 0b00;
2357 let Inst{5-4} = 0b01;
2361 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2362 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2363 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2364 (sext_inreg rGPR:$Rm, i16))))]>,
2365 Requires<[IsThumb2, HasThumb2DSP]> {
2366 let Inst{31-27} = 0b11111;
2367 let Inst{26-23} = 0b0110;
2368 let Inst{22-20} = 0b001;
2369 let Inst{7-6} = 0b00;
2370 let Inst{5-4} = 0b10;
2374 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2375 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2376 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2377 (sra rGPR:$Rm, (i32 16)))))]>,
2378 Requires<[IsThumb2, HasThumb2DSP]> {
2379 let Inst{31-27} = 0b11111;
2380 let Inst{26-23} = 0b0110;
2381 let Inst{22-20} = 0b001;
2382 let Inst{7-6} = 0b00;
2383 let Inst{5-4} = 0b11;
2387 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2388 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2389 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2390 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2391 Requires<[IsThumb2, HasThumb2DSP]> {
2392 let Inst{31-27} = 0b11111;
2393 let Inst{26-23} = 0b0110;
2394 let Inst{22-20} = 0b011;
2395 let Inst{7-6} = 0b00;
2396 let Inst{5-4} = 0b00;
2400 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2401 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2402 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2403 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2404 Requires<[IsThumb2, HasThumb2DSP]> {
2405 let Inst{31-27} = 0b11111;
2406 let Inst{26-23} = 0b0110;
2407 let Inst{22-20} = 0b011;
2408 let Inst{7-6} = 0b00;
2409 let Inst{5-4} = 0b01;
2413 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2414 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2416 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2417 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2418 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2419 [/* For disassembly only; pattern left blank */]>,
2420 Requires<[IsThumb2, HasThumb2DSP]>;
2421 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2422 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2423 [/* For disassembly only; pattern left blank */]>,
2424 Requires<[IsThumb2, HasThumb2DSP]>;
2425 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2426 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2427 [/* For disassembly only; pattern left blank */]>,
2428 Requires<[IsThumb2, HasThumb2DSP]>;
2429 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2430 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2431 [/* For disassembly only; pattern left blank */]>,
2432 Requires<[IsThumb2, HasThumb2DSP]>;
2434 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2435 // These are for disassembly only.
2437 def t2SMUAD: T2ThreeReg_mac<
2438 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2439 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2440 Requires<[IsThumb2, HasThumb2DSP]> {
2441 let Inst{15-12} = 0b1111;
2443 def t2SMUADX:T2ThreeReg_mac<
2444 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2445 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2446 Requires<[IsThumb2, HasThumb2DSP]> {
2447 let Inst{15-12} = 0b1111;
2449 def t2SMUSD: T2ThreeReg_mac<
2450 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2451 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2452 Requires<[IsThumb2, HasThumb2DSP]> {
2453 let Inst{15-12} = 0b1111;
2455 def t2SMUSDX:T2ThreeReg_mac<
2456 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2457 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2458 Requires<[IsThumb2, HasThumb2DSP]> {
2459 let Inst{15-12} = 0b1111;
2461 def t2SMLAD : T2FourReg_mac<
2462 0, 0b010, 0b0000, (outs rGPR:$Rd),
2463 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2464 "\t$Rd, $Rn, $Rm, $Ra", []>,
2465 Requires<[IsThumb2, HasThumb2DSP]>;
2466 def t2SMLADX : T2FourReg_mac<
2467 0, 0b010, 0b0001, (outs rGPR:$Rd),
2468 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2469 "\t$Rd, $Rn, $Rm, $Ra", []>,
2470 Requires<[IsThumb2, HasThumb2DSP]>;
2471 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2472 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2473 "\t$Rd, $Rn, $Rm, $Ra", []>,
2474 Requires<[IsThumb2, HasThumb2DSP]>;
2475 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2476 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2477 "\t$Rd, $Rn, $Rm, $Ra", []>,
2478 Requires<[IsThumb2, HasThumb2DSP]>;
2479 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2480 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2481 "\t$Ra, $Rd, $Rm, $Rn", []>,
2482 Requires<[IsThumb2, HasThumb2DSP]>;
2483 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2484 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2485 "\t$Ra, $Rd, $Rm, $Rn", []>,
2486 Requires<[IsThumb2, HasThumb2DSP]>;
2487 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2488 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2489 "\t$Ra, $Rd, $Rm, $Rn", []>,
2490 Requires<[IsThumb2, HasThumb2DSP]>;
2491 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2492 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2493 "\t$Ra, $Rd, $Rm, $Rn", []>,
2494 Requires<[IsThumb2, HasThumb2DSP]>;
2496 //===----------------------------------------------------------------------===//
2497 // Division Instructions.
2498 // Signed and unsigned division on v7-M
2500 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2501 "sdiv", "\t$Rd, $Rn, $Rm",
2502 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2503 Requires<[HasDivide, IsThumb2]> {
2504 let Inst{31-27} = 0b11111;
2505 let Inst{26-21} = 0b011100;
2507 let Inst{15-12} = 0b1111;
2508 let Inst{7-4} = 0b1111;
2511 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2512 "udiv", "\t$Rd, $Rn, $Rm",
2513 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2514 Requires<[HasDivide, IsThumb2]> {
2515 let Inst{31-27} = 0b11111;
2516 let Inst{26-21} = 0b011101;
2518 let Inst{15-12} = 0b1111;
2519 let Inst{7-4} = 0b1111;
2522 //===----------------------------------------------------------------------===//
2523 // Misc. Arithmetic Instructions.
2526 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2527 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2528 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2529 let Inst{31-27} = 0b11111;
2530 let Inst{26-22} = 0b01010;
2531 let Inst{21-20} = op1;
2532 let Inst{15-12} = 0b1111;
2533 let Inst{7-6} = 0b10;
2534 let Inst{5-4} = op2;
2538 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2539 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2541 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2542 "rbit", "\t$Rd, $Rm",
2543 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2545 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2546 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2548 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2549 "rev16", ".w\t$Rd, $Rm",
2550 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2552 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2553 "revsh", ".w\t$Rd, $Rm",
2554 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2556 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2557 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2558 (t2REVSH rGPR:$Rm)>;
2560 def t2PKHBT : T2ThreeReg<
2561 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2562 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
2563 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2564 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2566 Requires<[HasT2ExtractPack, IsThumb2]> {
2567 let Inst{31-27} = 0b11101;
2568 let Inst{26-25} = 0b01;
2569 let Inst{24-20} = 0b01100;
2570 let Inst{5} = 0; // BT form
2574 let Inst{14-12} = sh{4-2};
2575 let Inst{7-6} = sh{1-0};
2578 // Alternate cases for PKHBT where identities eliminate some nodes.
2579 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2580 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2581 Requires<[HasT2ExtractPack, IsThumb2]>;
2582 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2583 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2584 Requires<[HasT2ExtractPack, IsThumb2]>;
2586 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2587 // will match the pattern below.
2588 def t2PKHTB : T2ThreeReg<
2589 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2590 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
2591 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2592 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2594 Requires<[HasT2ExtractPack, IsThumb2]> {
2595 let Inst{31-27} = 0b11101;
2596 let Inst{26-25} = 0b01;
2597 let Inst{24-20} = 0b01100;
2598 let Inst{5} = 1; // TB form
2602 let Inst{14-12} = sh{4-2};
2603 let Inst{7-6} = sh{1-0};
2606 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2607 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2608 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2609 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2610 Requires<[HasT2ExtractPack, IsThumb2]>;
2611 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2612 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2613 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2614 Requires<[HasT2ExtractPack, IsThumb2]>;
2616 //===----------------------------------------------------------------------===//
2617 // Comparison Instructions...
2619 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2620 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2621 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2623 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
2624 (t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
2625 def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
2626 (t2CMPrr GPR:$lhs, rGPR:$rhs)>;
2627 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
2628 (t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
2630 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2631 // Compare-to-zero still works out, just not the relationals
2632 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2633 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2634 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2635 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2636 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2638 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2639 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2641 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2642 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2644 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2645 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2646 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2647 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2648 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2649 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2651 // Conditional moves
2652 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2653 // a two-value operand where a dag node expects two operands. :(
2654 let neverHasSideEffects = 1 in {
2655 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2656 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2658 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2659 RegConstraint<"$false = $Rd">;
2661 let isMoveImm = 1 in
2662 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2663 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2665 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2666 RegConstraint<"$false = $Rd">;
2668 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2669 let isCodeGenOnly = 1 in {
2670 let isMoveImm = 1 in
2671 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2673 "movw", "\t$Rd, $imm", []>,
2674 RegConstraint<"$false = $Rd"> {
2675 let Inst{31-27} = 0b11110;
2677 let Inst{24-21} = 0b0010;
2678 let Inst{20} = 0; // The S bit.
2684 let Inst{11-8} = Rd;
2685 let Inst{19-16} = imm{15-12};
2686 let Inst{26} = imm{11};
2687 let Inst{14-12} = imm{10-8};
2688 let Inst{7-0} = imm{7-0};
2691 let isMoveImm = 1 in
2692 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2693 (ins rGPR:$false, i32imm:$src, pred:$p),
2694 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2696 let isMoveImm = 1 in
2697 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2698 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2699 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2700 imm:$cc, CCR:$ccr))*/]>,
2701 RegConstraint<"$false = $Rd"> {
2702 let Inst{31-27} = 0b11110;
2704 let Inst{24-21} = 0b0011;
2705 let Inst{20} = 0; // The S bit.
2706 let Inst{19-16} = 0b1111; // Rn
2710 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2711 string opc, string asm, list<dag> pattern>
2712 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2713 let Inst{31-27} = 0b11101;
2714 let Inst{26-25} = 0b01;
2715 let Inst{24-21} = 0b0010;
2716 let Inst{20} = 0; // The S bit.
2717 let Inst{19-16} = 0b1111; // Rn
2718 let Inst{5-4} = opcod; // Shift type.
2720 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2721 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2722 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2723 RegConstraint<"$false = $Rd">;
2724 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2725 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2726 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2727 RegConstraint<"$false = $Rd">;
2728 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2729 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2730 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2731 RegConstraint<"$false = $Rd">;
2732 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2733 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2734 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2735 RegConstraint<"$false = $Rd">;
2736 } // isCodeGenOnly = 1
2737 } // neverHasSideEffects
2739 //===----------------------------------------------------------------------===//
2740 // Atomic operations intrinsics
2743 // memory barriers protect the atomic sequences
2744 let hasSideEffects = 1 in {
2745 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2746 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2747 Requires<[IsThumb, HasDB]> {
2749 let Inst{31-4} = 0xf3bf8f5;
2750 let Inst{3-0} = opt;
2754 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2756 [/* For disassembly only; pattern left blank */]>,
2757 Requires<[IsThumb, HasDB]> {
2759 let Inst{31-4} = 0xf3bf8f4;
2760 let Inst{3-0} = opt;
2763 // ISB has only full system option -- for disassembly only
2764 def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2765 [/* For disassembly only; pattern left blank */]>,
2766 Requires<[IsThumb2, HasV7]> {
2767 let Inst{31-4} = 0xf3bf8f6;
2768 let Inst{3-0} = 0b1111;
2771 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2772 InstrItinClass itin, string opc, string asm, string cstr,
2773 list<dag> pattern, bits<4> rt2 = 0b1111>
2774 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2775 let Inst{31-27} = 0b11101;
2776 let Inst{26-20} = 0b0001101;
2777 let Inst{11-8} = rt2;
2778 let Inst{7-6} = 0b01;
2779 let Inst{5-4} = opcod;
2780 let Inst{3-0} = 0b1111;
2784 let Inst{19-16} = addr;
2785 let Inst{15-12} = Rt;
2787 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2788 InstrItinClass itin, string opc, string asm, string cstr,
2789 list<dag> pattern, bits<4> rt2 = 0b1111>
2790 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2791 let Inst{31-27} = 0b11101;
2792 let Inst{26-20} = 0b0001100;
2793 let Inst{11-8} = rt2;
2794 let Inst{7-6} = 0b01;
2795 let Inst{5-4} = opcod;
2801 let Inst{19-16} = addr;
2802 let Inst{15-12} = Rt;
2805 let mayLoad = 1 in {
2806 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2807 AddrModeNone, 4, NoItinerary,
2808 "ldrexb", "\t$Rt, $addr", "", []>;
2809 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2810 AddrModeNone, 4, NoItinerary,
2811 "ldrexh", "\t$Rt, $addr", "", []>;
2812 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2813 AddrModeNone, 4, NoItinerary,
2814 "ldrex", "\t$Rt, $addr", "", []> {
2815 let Inst{31-27} = 0b11101;
2816 let Inst{26-20} = 0b0000101;
2817 let Inst{11-8} = 0b1111;
2818 let Inst{7-0} = 0b00000000; // imm8 = 0
2822 let Inst{19-16} = addr;
2823 let Inst{15-12} = Rt;
2825 let hasExtraDefRegAllocReq = 1 in
2826 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2827 (ins t2addrmode_reg:$addr),
2828 AddrModeNone, 4, NoItinerary,
2829 "ldrexd", "\t$Rt, $Rt2, $addr", "",
2832 let Inst{11-8} = Rt2;
2836 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2837 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2838 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2839 AddrModeNone, 4, NoItinerary,
2840 "strexb", "\t$Rd, $Rt, $addr", "", []>;
2841 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2842 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2843 AddrModeNone, 4, NoItinerary,
2844 "strexh", "\t$Rd, $Rt, $addr", "", []>;
2845 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2846 AddrModeNone, 4, NoItinerary,
2847 "strex", "\t$Rd, $Rt, $addr", "",
2849 let Inst{31-27} = 0b11101;
2850 let Inst{26-20} = 0b0000100;
2851 let Inst{7-0} = 0b00000000; // imm8 = 0
2856 let Inst{11-8} = Rd;
2857 let Inst{19-16} = addr;
2858 let Inst{15-12} = Rt;
2862 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2863 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2864 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2865 AddrModeNone, 4, NoItinerary,
2866 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2869 let Inst{11-8} = Rt2;
2872 // Clear-Exclusive is for disassembly only.
2873 def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
2874 [/* For disassembly only; pattern left blank */]>,
2875 Requires<[IsThumb2, HasV7]> {
2876 let Inst{31-16} = 0xf3bf;
2877 let Inst{15-14} = 0b10;
2880 let Inst{11-8} = 0b1111;
2881 let Inst{7-4} = 0b0010;
2882 let Inst{3-0} = 0b1111;
2885 //===----------------------------------------------------------------------===//
2886 // SJLJ Exception handling intrinsics
2887 // eh_sjlj_setjmp() is an instruction sequence to store the return
2888 // address and save #0 in R0 for the non-longjmp case.
2889 // Since by its nature we may be coming from some other function to get
2890 // here, and we're using the stack frame for the containing function to
2891 // save/restore registers, we can't keep anything live in regs across
2892 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2893 // when we get here from a longjmp(). We force everything out of registers
2894 // except for our own input by listing the relevant registers in Defs. By
2895 // doing so, we also cause the prologue/epilogue code to actively preserve
2896 // all of the callee-saved resgisters, which is exactly what we want.
2897 // $val is a scratch register for our use.
2899 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
2900 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2901 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2902 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2903 AddrModeNone, 0, NoItinerary, "", "",
2904 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2905 Requires<[IsThumb2, HasVFP2]>;
2909 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
2910 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2911 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2912 AddrModeNone, 0, NoItinerary, "", "",
2913 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2914 Requires<[IsThumb2, NoVFP]>;
2918 //===----------------------------------------------------------------------===//
2919 // Control-Flow Instructions
2922 // FIXME: remove when we have a way to marking a MI with these properties.
2923 // FIXME: Should pc be an implicit operand like PICADD, etc?
2924 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2925 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2926 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2927 reglist:$regs, variable_ops),
2928 4, IIC_iLoad_mBr, [],
2929 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2930 RegConstraint<"$Rn = $wb">;
2932 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2933 let isPredicable = 1 in
2934 def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
2936 [(br bb:$target)]> {
2937 let Inst{31-27} = 0b11110;
2938 let Inst{15-14} = 0b10;
2942 let Inst{26} = target{19};
2943 let Inst{11} = target{18};
2944 let Inst{13} = target{17};
2945 let Inst{21-16} = target{16-11};
2946 let Inst{10-0} = target{10-0};
2949 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2950 def t2BR_JT : t2PseudoInst<(outs),
2951 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
2953 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
2955 // FIXME: Add a non-pc based case that can be predicated.
2956 def t2TBB_JT : t2PseudoInst<(outs),
2957 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2960 def t2TBH_JT : t2PseudoInst<(outs),
2961 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2964 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2965 "tbb", "\t[$Rn, $Rm]", []> {
2968 let Inst{31-20} = 0b111010001101;
2969 let Inst{19-16} = Rn;
2970 let Inst{15-5} = 0b11110000000;
2971 let Inst{4} = 0; // B form
2975 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2976 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
2979 let Inst{31-20} = 0b111010001101;
2980 let Inst{19-16} = Rn;
2981 let Inst{15-5} = 0b11110000000;
2982 let Inst{4} = 1; // H form
2985 } // isNotDuplicable, isIndirectBranch
2987 } // isBranch, isTerminator, isBarrier
2989 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2990 // a two-value operand where a dag node expects two operands. :(
2991 let isBranch = 1, isTerminator = 1 in
2992 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2994 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2995 let Inst{31-27} = 0b11110;
2996 let Inst{15-14} = 0b10;
3000 let Inst{25-22} = p;
3003 let Inst{26} = target{20};
3004 let Inst{11} = target{19};
3005 let Inst{13} = target{18};
3006 let Inst{21-16} = target{17-12};
3007 let Inst{10-0} = target{11-1};
3009 let DecoderMethod = "DecodeThumb2BCCInstruction";
3012 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3014 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3016 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3018 def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
3020 (t2B uncondbrtarget:$dst)>,
3021 Requires<[IsThumb2, IsDarwin]>;
3025 let Defs = [ITSTATE] in
3026 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3027 AddrModeNone, 2, IIC_iALUx,
3028 "it$mask\t$cc", "", []> {
3029 // 16-bit instruction.
3030 let Inst{31-16} = 0x0000;
3031 let Inst{15-8} = 0b10111111;
3036 let Inst{3-0} = mask;
3039 // Branch and Exchange Jazelle -- for disassembly only
3041 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3042 [/* For disassembly only; pattern left blank */]> {
3043 let Inst{31-27} = 0b11110;
3045 let Inst{25-20} = 0b111100;
3046 let Inst{15-14} = 0b10;
3050 let Inst{19-16} = func;
3053 // Compare and branch on zero / non-zero
3054 let isBranch = 1, isTerminator = 1 in {
3055 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3056 "cbz\t$Rn, $target", []>,
3057 T1Misc<{0,0,?,1,?,?,?}>,
3058 Requires<[IsThumb2]> {
3062 let Inst{9} = target{5};
3063 let Inst{7-3} = target{4-0};
3067 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3068 "cbnz\t$Rn, $target", []>,
3069 T1Misc<{1,0,?,1,?,?,?}>,
3070 Requires<[IsThumb2]> {
3074 let Inst{9} = target{5};
3075 let Inst{7-3} = target{4-0};
3081 // Change Processor State is a system instruction -- for disassembly and
3083 // FIXME: Since the asm parser has currently no clean way to handle optional
3084 // operands, create 3 versions of the same instruction. Once there's a clean
3085 // framework to represent optional operands, change this behavior.
3086 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3087 !strconcat("cps", asm_op),
3088 [/* For disassembly only; pattern left blank */]> {
3094 let Inst{31-27} = 0b11110;
3096 let Inst{25-20} = 0b111010;
3097 let Inst{19-16} = 0b1111;
3098 let Inst{15-14} = 0b10;
3100 let Inst{10-9} = imod;
3102 let Inst{7-5} = iflags;
3103 let Inst{4-0} = mode;
3104 let DecoderMethod = "DecodeT2CPSInstruction";
3108 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3109 "$imod.w\t$iflags, $mode">;
3110 let mode = 0, M = 0 in
3111 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3112 "$imod.w\t$iflags">;
3113 let imod = 0, iflags = 0, M = 1 in
3114 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3116 // A6.3.4 Branches and miscellaneous control
3117 // Table A6-14 Change Processor State, and hint instructions
3118 // Helper class for disassembly only.
3119 class T2I_hint<bits<8> op7_0, string opc, string asm>
3120 : T2I<(outs), (ins), NoItinerary, opc, asm,
3121 [/* For disassembly only; pattern left blank */]> {
3122 let Inst{31-20} = 0xf3a;
3123 let Inst{19-16} = 0b1111;
3124 let Inst{15-14} = 0b10;
3126 let Inst{10-8} = 0b000;
3127 let Inst{7-0} = op7_0;
3130 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3131 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3132 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3133 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3134 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3136 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3137 let Inst{31-20} = 0xf3a;
3138 let Inst{15-14} = 0b10;
3140 let Inst{10-8} = 0b000;
3141 let Inst{7-4} = 0b1111;
3144 let Inst{3-0} = opt;
3147 // Secure Monitor Call is a system instruction -- for disassembly only
3148 // Option = Inst{19-16}
3149 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3150 [/* For disassembly only; pattern left blank */]> {
3151 let Inst{31-27} = 0b11110;
3152 let Inst{26-20} = 0b1111111;
3153 let Inst{15-12} = 0b1000;
3156 let Inst{19-16} = opt;
3159 class T2SRS<bits<12> op31_20,
3160 dag oops, dag iops, InstrItinClass itin,
3161 string opc, string asm, list<dag> pattern>
3162 : T2I<oops, iops, itin, opc, asm, pattern> {
3163 let Inst{31-20} = op31_20{11-0};
3166 let Inst{4-0} = mode{4-0};
3169 // Store Return State is a system instruction -- for disassembly only
3170 def t2SRSDBW : T2SRS<0b111010000010,
3171 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3172 [/* For disassembly only; pattern left blank */]>;
3173 def t2SRSDB : T2SRS<0b111010000000,
3174 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3175 [/* For disassembly only; pattern left blank */]>;
3176 def t2SRSIAW : T2SRS<0b111010011010,
3177 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3178 [/* For disassembly only; pattern left blank */]>;
3179 def t2SRSIA : T2SRS<0b111010011000,
3180 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3181 [/* For disassembly only; pattern left blank */]>;
3183 // Return From Exception is a system instruction -- for disassembly only
3185 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3186 string opc, string asm, list<dag> pattern>
3187 : T2I<oops, iops, itin, opc, asm, pattern> {
3188 let Inst{31-20} = op31_20{11-0};
3191 let Inst{19-16} = Rn;
3192 let Inst{15-0} = 0xc000;
3195 def t2RFEDBW : T2RFE<0b111010000011,
3196 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3197 [/* For disassembly only; pattern left blank */]>;
3198 def t2RFEDB : T2RFE<0b111010000001,
3199 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3200 [/* For disassembly only; pattern left blank */]>;
3201 def t2RFEIAW : T2RFE<0b111010011011,
3202 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3203 [/* For disassembly only; pattern left blank */]>;
3204 def t2RFEIA : T2RFE<0b111010011001,
3205 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3206 [/* For disassembly only; pattern left blank */]>;
3208 //===----------------------------------------------------------------------===//
3209 // Non-Instruction Patterns
3212 // 32-bit immediate using movw + movt.
3213 // This is a single pseudo instruction to make it re-materializable.
3214 // FIXME: Remove this when we can do generalized remat.
3215 let isReMaterializable = 1, isMoveImm = 1 in
3216 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3217 [(set rGPR:$dst, (i32 imm:$src))]>,
3218 Requires<[IsThumb, HasV6T2]>;
3220 // Pseudo instruction that combines movw + movt + add pc (if pic).
3221 // It also makes it possible to rematerialize the instructions.
3222 // FIXME: Remove this when we can do generalized remat and when machine licm
3223 // can properly the instructions.
3224 let isReMaterializable = 1 in {
3225 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3227 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3228 Requires<[IsThumb2, UseMovt]>;
3230 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3232 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3233 Requires<[IsThumb2, UseMovt]>;
3236 // ConstantPool, GlobalAddress, and JumpTable
3237 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3238 Requires<[IsThumb2, DontUseMovt]>;
3239 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3240 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3241 Requires<[IsThumb2, UseMovt]>;
3243 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3244 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3246 // Pseudo instruction that combines ldr from constpool and add pc. This should
3247 // be expanded into two instructions late to allow if-conversion and
3249 let canFoldAsLoad = 1, isReMaterializable = 1 in
3250 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3252 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3254 Requires<[IsThumb2]>;
3256 //===----------------------------------------------------------------------===//
3257 // Move between special register and ARM core register -- for disassembly only
3260 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3261 dag oops, dag iops, InstrItinClass itin,
3262 string opc, string asm, list<dag> pattern>
3263 : T2I<oops, iops, itin, opc, asm, pattern> {
3264 let Inst{31-20} = op31_20{11-0};
3265 let Inst{15-14} = op15_14{1-0};
3266 let Inst{12} = op12{0};
3269 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3270 dag oops, dag iops, InstrItinClass itin,
3271 string opc, string asm, list<dag> pattern>
3272 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3274 let Inst{11-8} = Rd;
3275 let Inst{19-16} = 0b1111;
3278 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3279 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3280 [/* For disassembly only; pattern left blank */]>;
3281 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3282 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3283 [/* For disassembly only; pattern left blank */]>;
3285 // Move from ARM core register to Special Register
3287 // No need to have both system and application versions, the encodings are the
3288 // same and the assembly parser has no way to distinguish between them. The mask
3289 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3290 // the mask with the fields to be accessed in the special register.
3291 def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3292 0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3293 NoItinerary, "msr", "\t$mask, $Rn",
3294 [/* For disassembly only; pattern left blank */]> {
3297 let Inst{19-16} = Rn;
3298 let Inst{20} = mask{4}; // R Bit
3300 let Inst{11-8} = mask{3-0};
3303 //===----------------------------------------------------------------------===//
3304 // Move between coprocessor and ARM core register
3307 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3309 : T2Cop<Op, oops, iops,
3310 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3312 let Inst{27-24} = 0b1110;
3313 let Inst{20} = direction;
3323 let Inst{15-12} = Rt;
3324 let Inst{11-8} = cop;
3325 let Inst{23-21} = opc1;
3326 let Inst{7-5} = opc2;
3327 let Inst{3-0} = CRm;
3328 let Inst{19-16} = CRn;
3331 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3332 list<dag> pattern = []>
3334 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3335 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3336 let Inst{27-24} = 0b1100;
3337 let Inst{23-21} = 0b010;
3338 let Inst{20} = direction;
3346 let Inst{15-12} = Rt;
3347 let Inst{19-16} = Rt2;
3348 let Inst{11-8} = cop;
3349 let Inst{7-4} = opc1;
3350 let Inst{3-0} = CRm;
3353 /* from ARM core register to coprocessor */
3354 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3356 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3357 c_imm:$CRm, imm0_7:$opc2),
3358 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3359 imm:$CRm, imm:$opc2)]>;
3360 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3361 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3362 c_imm:$CRm, imm0_7:$opc2),
3363 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3364 imm:$CRm, imm:$opc2)]>;
3366 /* from coprocessor to ARM core register */
3367 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3368 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3369 c_imm:$CRm, imm0_7:$opc2), []>;
3371 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3372 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3373 c_imm:$CRm, imm0_7:$opc2), []>;
3375 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3376 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3378 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3379 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3382 /* from ARM core register to coprocessor */
3383 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3384 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3386 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3387 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3388 GPR:$Rt2, imm:$CRm)]>;
3389 /* from coprocessor to ARM core register */
3390 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3392 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3394 //===----------------------------------------------------------------------===//
3395 // Other Coprocessor Instructions.
3398 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3399 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3400 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3401 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3402 imm:$CRm, imm:$opc2)]> {
3403 let Inst{27-24} = 0b1110;
3412 let Inst{3-0} = CRm;
3414 let Inst{7-5} = opc2;
3415 let Inst{11-8} = cop;
3416 let Inst{15-12} = CRd;
3417 let Inst{19-16} = CRn;
3418 let Inst{23-20} = opc1;
3421 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3422 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3423 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3424 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3425 imm:$CRm, imm:$opc2)]> {
3426 let Inst{27-24} = 0b1110;
3435 let Inst{3-0} = CRm;
3437 let Inst{7-5} = opc2;
3438 let Inst{11-8} = cop;
3439 let Inst{15-12} = CRd;
3440 let Inst{19-16} = CRn;
3441 let Inst{23-20} = opc1;
3446 //===----------------------------------------------------------------------===//
3447 // Non-Instruction Patterns
3450 // SXT/UXT with no rotate
3451 let AddedComplexity = 16 in {
3452 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3453 Requires<[IsThumb2]>;
3454 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3455 Requires<[IsThumb2]>;
3456 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3457 Requires<[HasT2ExtractPack, IsThumb2]>;
3458 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3459 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3460 Requires<[HasT2ExtractPack, IsThumb2]>;
3461 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3462 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3463 Requires<[HasT2ExtractPack, IsThumb2]>;
3466 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3467 Requires<[IsThumb2]>;
3468 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3469 Requires<[IsThumb2]>;
3470 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3471 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3472 Requires<[HasT2ExtractPack, IsThumb2]>;
3473 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3474 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3475 Requires<[HasT2ExtractPack, IsThumb2]>;