1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
53 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 def imm0_255_neg : PatLeaf<(i32 imm), [{
87 return (uint32_t)(-N->getZExtValue()) < 255;
90 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
92 def imm0_65535 : PatLeaf<(i32 imm), [{
93 return (uint32_t)N->getZExtValue() < 65536;
96 /// Split a 32-bit immediate into two 16 bit parts.
97 def t2_lo16 : SDNodeXForm<imm, [{
98 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
102 def t2_hi16 : SDNodeXForm<imm, [{
103 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
106 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
107 // Returns true if all low 16-bits are 0.
108 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
112 // Define Thumb2 specific addressing modes.
114 // t2addrmode_imm12 := reg + imm12
115 def t2addrmode_imm12 : Operand<i32>,
116 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
117 let PrintMethod = "printT2AddrModeImm12Operand";
118 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
121 // t2addrmode_imm8 := reg - imm8
122 def t2addrmode_imm8 : Operand<i32>,
123 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
124 let PrintMethod = "printT2AddrModeImm8Operand";
125 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
128 def t2am_imm8_offset : Operand<i32>,
129 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
130 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
133 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
134 def t2addrmode_imm8s4 : Operand<i32>,
135 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
136 let PrintMethod = "printT2AddrModeImm8s4Operand";
137 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
140 // t2addrmode_so_reg := reg + (reg << imm2)
141 def t2addrmode_so_reg : Operand<i32>,
142 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
143 let PrintMethod = "printT2AddrModeSoRegOperand";
144 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
148 //===----------------------------------------------------------------------===//
149 // Multiclass helpers...
152 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
153 /// unary operation that produces a value. These are predicable and can be
154 /// changed to modify CPSR.
155 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
157 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
159 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
160 let isAsCheapAsAMove = Cheap;
161 let isReMaterializable = ReMat;
164 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
165 opc, ".w $dst, $src",
166 [(set GPR:$dst, (opnode GPR:$src))]>;
168 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
169 opc, ".w $dst, $src",
170 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
173 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
174 // binary operation that produces a value. These are predicable and can be
175 /// changed to modify CPSR.
176 multiclass T2I_bin_irs<string opc, PatFrag opnode,
177 bit Commutable = 0, string wide =""> {
179 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
180 opc, " $dst, $lhs, $rhs",
181 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
183 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
184 opc, !strconcat(wide, " $dst, $lhs, $rhs"),
185 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
186 let isCommutable = Commutable;
189 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
190 opc, !strconcat(wide, " $dst, $lhs, $rhs"),
191 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
194 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
195 // the ".w" prefix to indicate that they are wide.
196 multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> :
197 T2I_bin_irs<opc, opnode, Commutable, ".w">;
199 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
200 /// reversed. It doesn't define the 'rr' form since it's handled by its
201 /// T2I_bin_irs counterpart.
202 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
204 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
205 opc, ".w $dst, $rhs, $lhs",
206 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
208 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
209 opc, " $dst, $rhs, $lhs",
210 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
213 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
214 /// instruction modifies the CPSR register.
215 let Defs = [CPSR] in {
216 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
218 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
219 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
220 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
222 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
223 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
224 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
225 let isCommutable = Commutable;
228 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
229 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
230 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
234 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
235 /// patterns for a binary operation that produces a value.
236 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
238 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
239 opc, ".w $dst, $lhs, $rhs",
240 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
242 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
243 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
244 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
246 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
247 opc, ".w $dst, $lhs, $rhs",
248 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
249 let isCommutable = Commutable;
252 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
253 opc, ".w $dst, $lhs, $rhs",
254 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
257 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
258 /// binary operation that produces a value and use and define the carry bit.
259 /// It's not predicable.
260 let Uses = [CPSR] in {
261 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
263 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
264 opc, " $dst, $lhs, $rhs",
265 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
266 Requires<[IsThumb2, CarryDefIsUnused]>;
268 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
269 opc, ".w $dst, $lhs, $rhs",
270 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
271 Requires<[IsThumb2, CarryDefIsUnused]> {
272 let isCommutable = Commutable;
275 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
276 opc, ".w $dst, $lhs, $rhs",
277 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
278 Requires<[IsThumb2, CarryDefIsUnused]>;
279 // Carry setting variants
281 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
282 !strconcat(opc, "s $dst, $lhs, $rhs"),
283 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
284 Requires<[IsThumb2, CarryDefIsUsed]> {
288 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
289 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
290 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
291 Requires<[IsThumb2, CarryDefIsUsed]> {
293 let isCommutable = Commutable;
296 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
297 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
298 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
299 Requires<[IsThumb2, CarryDefIsUsed]> {
305 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
306 let Defs = [CPSR] in {
307 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
309 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
310 !strconcat(opc, "${s}.w $dst, $rhs, $lhs"),
311 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
313 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
314 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
315 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
319 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
320 // rotate operation that produces a value.
321 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
324 opc, ".w $dst, $lhs, $rhs",
325 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
327 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
328 opc, ".w $dst, $lhs, $rhs",
329 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
332 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
333 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
334 /// a explicit result, only implicitly set CPSR.
335 let Defs = [CPSR] in {
336 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
338 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
339 opc, ".w $lhs, $rhs",
340 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
342 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
343 opc, ".w $lhs, $rhs",
344 [(opnode GPR:$lhs, GPR:$rhs)]>;
346 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
347 opc, ".w $lhs, $rhs",
348 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
352 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
353 multiclass T2I_ld<string opc, PatFrag opnode> {
354 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
355 opc, ".w $dst, $addr",
356 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
357 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
359 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
360 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
361 opc, ".w $dst, $addr",
362 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
363 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
364 opc, ".w $dst, $addr",
365 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
368 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
369 multiclass T2I_st<string opc, PatFrag opnode> {
370 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
371 opc, ".w $src, $addr",
372 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
373 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
375 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
376 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
377 opc, ".w $src, $addr",
378 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
381 /// T2I_picld - Defines the PIC load pattern.
382 class T2I_picld<string opc, PatFrag opnode> :
383 T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
384 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
385 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
387 /// T2I_picst - Defines the PIC store pattern.
388 class T2I_picst<string opc, PatFrag opnode> :
389 T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
390 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
391 [(opnode GPR:$src, addrmodepc:$addr)]>;
394 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
395 /// register and one whose operand is a register rotated by 8/16/24.
396 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
397 def r : T2I<(outs GPR:$dst), (ins GPR:$Src),
398 opc, ".w $dst, $Src",
399 [(set GPR:$dst, (opnode GPR:$Src))]>;
400 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
401 opc, ".w $dst, $Src, ror $rot",
402 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
405 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
406 /// register and one whose operand is a register rotated by 8/16/24.
407 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
408 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
409 opc, " $dst, $LHS, $RHS",
410 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
411 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
412 opc, " $dst, $LHS, $RHS, ror $rot",
413 [(set GPR:$dst, (opnode GPR:$LHS,
414 (rotr GPR:$RHS, rot_imm:$rot)))]>;
417 //===----------------------------------------------------------------------===//
419 //===----------------------------------------------------------------------===//
421 //===----------------------------------------------------------------------===//
422 // Miscellaneous Instructions.
425 let isNotDuplicable = 1 in
426 def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
427 "$cp:\n\tadd.w $dst, $lhs, pc",
428 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
431 // LEApcrel - Load a pc-relative address into a register without offending the
433 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
434 "adr$p.w $dst, #$label", []>;
436 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
437 (ins i32imm:$label, i32imm:$id, pred:$p),
438 "adr$p.w $dst, #${label}_${id:no_hash}", []>;
440 //===----------------------------------------------------------------------===//
441 // Load / store Instructions.
445 let canFoldAsLoad = 1 in
446 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
448 // Loads with zero extension
449 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
450 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
452 // Loads with sign extension
453 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
454 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
458 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
459 "ldrd", " $dst, $addr", []>;
460 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
461 "ldrd", " $dst, $addr", []>;
464 // zextload i1 -> zextload i8
465 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
466 (t2LDRBi12 t2addrmode_imm12:$addr)>;
467 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
468 (t2LDRBi8 t2addrmode_imm8:$addr)>;
469 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
470 (t2LDRBs t2addrmode_so_reg:$addr)>;
471 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
472 (t2LDRBpci tconstpool:$addr)>;
474 // extload -> zextload
475 // FIXME: Reduce the number of patterns by legalizing extload to zextload
477 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
478 (t2LDRBi12 t2addrmode_imm12:$addr)>;
479 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
480 (t2LDRBi8 t2addrmode_imm8:$addr)>;
481 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
482 (t2LDRBs t2addrmode_so_reg:$addr)>;
483 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
484 (t2LDRBpci tconstpool:$addr)>;
486 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
487 (t2LDRBi12 t2addrmode_imm12:$addr)>;
488 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
489 (t2LDRBi8 t2addrmode_imm8:$addr)>;
490 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
491 (t2LDRBs t2addrmode_so_reg:$addr)>;
492 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
493 (t2LDRBpci tconstpool:$addr)>;
495 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
496 (t2LDRHi12 t2addrmode_imm12:$addr)>;
497 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
498 (t2LDRHi8 t2addrmode_imm8:$addr)>;
499 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
500 (t2LDRHs t2addrmode_so_reg:$addr)>;
501 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
502 (t2LDRHpci tconstpool:$addr)>;
506 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
507 (ins t2addrmode_imm8:$addr),
508 AddrModeT2_i8, IndexModePre,
509 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
512 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
513 (ins GPR:$base, t2am_imm8_offset:$offset),
514 AddrModeT2_i8, IndexModePost,
515 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
518 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
519 (ins t2addrmode_imm8:$addr),
520 AddrModeT2_i8, IndexModePre,
521 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
523 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
524 (ins GPR:$base, t2am_imm8_offset:$offset),
525 AddrModeT2_i8, IndexModePost,
526 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
529 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
530 (ins t2addrmode_imm8:$addr),
531 AddrModeT2_i8, IndexModePre,
532 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
534 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
535 (ins GPR:$base, t2am_imm8_offset:$offset),
536 AddrModeT2_i8, IndexModePost,
537 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
540 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
541 (ins t2addrmode_imm8:$addr),
542 AddrModeT2_i8, IndexModePre,
543 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
545 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
546 (ins GPR:$base, t2am_imm8_offset:$offset),
547 AddrModeT2_i8, IndexModePost,
548 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
551 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
552 (ins t2addrmode_imm8:$addr),
553 AddrModeT2_i8, IndexModePre,
554 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
556 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
557 (ins GPR:$base, t2am_imm8_offset:$offset),
558 AddrModeT2_i8, IndexModePost,
559 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
564 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
565 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
566 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
570 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
571 "strd", " $src, $addr", []>;
574 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
575 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
576 AddrModeT2_i8, IndexModePre,
577 "str", " $src, [$base, $offset]!", "$base = $base_wb",
579 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
581 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
582 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
583 AddrModeT2_i8, IndexModePost,
584 "str", " $src, [$base], $offset", "$base = $base_wb",
586 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
588 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
589 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
590 AddrModeT2_i8, IndexModePre,
591 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
593 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
595 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
596 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
597 AddrModeT2_i8, IndexModePost,
598 "strh", " $src, [$base], $offset", "$base = $base_wb",
600 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
602 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
603 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
604 AddrModeT2_i8, IndexModePre,
605 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
607 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
609 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
610 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
611 AddrModeT2_i8, IndexModePost,
612 "strb", " $src, [$base], $offset", "$base = $base_wb",
614 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
617 // FIXME: ldrd / strd pre / post variants
619 //===----------------------------------------------------------------------===//
620 // Load / store multiple Instructions.
624 def t2LDM : T2XI<(outs),
625 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
626 "ldm${addr:submode}${p} $addr, $dst1", []>;
629 def t2STM : T2XI<(outs),
630 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
631 "stm${addr:submode}${p} $addr, $src1", []>;
633 //===----------------------------------------------------------------------===//
634 // Move Instructions.
637 let neverHasSideEffects = 1 in
638 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
639 "mov", ".w $dst, $src", []>;
641 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
642 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
643 "mov", ".w $dst, $src",
644 [(set GPR:$dst, t2_so_imm:$src)]>;
646 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
647 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
648 "movw", " $dst, $src",
649 [(set GPR:$dst, imm0_65535:$src)]>;
651 // FIXME: Also available in ARM mode.
652 let Constraints = "$src = $dst" in
653 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
654 "movt", " $dst, $imm",
656 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
658 //===----------------------------------------------------------------------===//
659 // Extend Instructions.
664 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
665 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
667 defm t2SXTAB : T2I_bin_rrot<"sxtab",
668 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
669 defm t2SXTAH : T2I_bin_rrot<"sxtah",
670 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
672 // TODO: SXT(A){B|H}16
676 let AddedComplexity = 16 in {
677 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
678 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
679 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
681 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
682 (t2UXTB16r_rot GPR:$Src, 24)>;
683 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
684 (t2UXTB16r_rot GPR:$Src, 8)>;
686 defm t2UXTAB : T2I_bin_rrot<"uxtab",
687 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
688 defm t2UXTAH : T2I_bin_rrot<"uxtah",
689 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
692 //===----------------------------------------------------------------------===//
693 // Arithmetic Instructions.
696 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
697 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
699 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
700 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
701 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
703 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
704 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
707 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
708 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
710 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
711 let AddedComplexity = 1 in
712 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
713 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
714 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
715 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
716 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
717 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
720 //===----------------------------------------------------------------------===//
721 // Shift and rotate Instructions.
724 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
725 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
726 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
727 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
729 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
730 "rrx", ".w $dst, $src",
731 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
733 let Defs = [CPSR] in {
734 def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src),
735 "lsrs.w $dst, $src, #1",
736 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
737 def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src),
738 "asrs.w $dst, $src, #1",
739 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
742 //===----------------------------------------------------------------------===//
743 // Bitwise Instructions.
746 defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
747 defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
748 defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
750 defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
752 let Constraints = "$src = $dst" in
753 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
754 "bfc", " $dst, $imm",
755 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
757 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
760 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
762 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
763 def t2ORNri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
764 "orn", " $dst, $lhs, $rhs",
765 [(set GPR:$dst, (or GPR:$lhs, (not t2_so_imm:$rhs)))]>,
766 Requires<[IsThumb2, IsNotDarwin]>;
768 def t2ORNrr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
769 "orn", " $dst, $lhs, $rhs",
770 [(set GPR:$dst, (or GPR:$lhs, (not GPR:$rhs)))]>;
771 def t2ORNrs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
772 "orn", " $dst, $lhs, $rhs",
773 [(set GPR:$dst, (or GPR:$lhs, (not t2_so_reg:$rhs)))]>;
775 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
776 let AddedComplexity = 1 in
777 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
780 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
781 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
783 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
784 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
785 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
786 Requires<[IsThumb2, IsNotDarwin]>;
788 def : T2Pat<(t2_so_imm_not:$src),
789 (t2MVNi t2_so_imm_not:$src)>;
791 //===----------------------------------------------------------------------===//
792 // Multiply Instructions.
794 let isCommutable = 1 in
795 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
796 "mul", " $dst, $a, $b",
797 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
799 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
800 "mla", " $dst, $a, $b, $c",
801 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
803 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
804 "mls", " $dst, $a, $b, $c",
805 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
807 // Extra precision multiplies with low / high results
808 let neverHasSideEffects = 1 in {
809 let isCommutable = 1 in {
810 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
811 "smull", " $ldst, $hdst, $a, $b", []>;
813 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
814 "umull", " $ldst, $hdst, $a, $b", []>;
817 // Multiply + accumulate
818 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
819 "smlal", " $ldst, $hdst, $a, $b", []>;
821 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
822 "umlal", " $ldst, $hdst, $a, $b", []>;
824 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
825 "umaal", " $ldst, $hdst, $a, $b", []>;
826 } // neverHasSideEffects
828 // Most significant word multiply
829 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
830 "smmul", " $dst, $a, $b",
831 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
833 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
834 "smmla", " $dst, $a, $b, $c",
835 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
838 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
839 "smmls", " $dst, $a, $b, $c",
840 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
842 multiclass T2I_smul<string opc, PatFrag opnode> {
843 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
844 !strconcat(opc, "bb"), " $dst, $a, $b",
845 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
846 (sext_inreg GPR:$b, i16)))]>;
848 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
849 !strconcat(opc, "bt"), " $dst, $a, $b",
850 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
851 (sra GPR:$b, (i32 16))))]>;
853 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
854 !strconcat(opc, "tb"), " $dst, $a, $b",
855 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
856 (sext_inreg GPR:$b, i16)))]>;
858 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
859 !strconcat(opc, "tt"), " $dst, $a, $b",
860 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
861 (sra GPR:$b, (i32 16))))]>;
863 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
864 !strconcat(opc, "wb"), " $dst, $a, $b",
865 [(set GPR:$dst, (sra (opnode GPR:$a,
866 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
868 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
869 !strconcat(opc, "wt"), " $dst, $a, $b",
870 [(set GPR:$dst, (sra (opnode GPR:$a,
871 (sra GPR:$b, (i32 16))), (i32 16)))]>;
875 multiclass T2I_smla<string opc, PatFrag opnode> {
876 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
877 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
878 [(set GPR:$dst, (add GPR:$acc,
879 (opnode (sext_inreg GPR:$a, i16),
880 (sext_inreg GPR:$b, i16))))]>;
882 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
883 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
884 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
885 (sra GPR:$b, (i32 16)))))]>;
887 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
888 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
889 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
890 (sext_inreg GPR:$b, i16))))]>;
892 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
893 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
894 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
895 (sra GPR:$b, (i32 16)))))]>;
897 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
898 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
899 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
900 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
902 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
903 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
904 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
905 (sra GPR:$b, (i32 16))), (i32 16))))]>;
908 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
909 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
911 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
912 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
915 //===----------------------------------------------------------------------===//
916 // Misc. Arithmetic Instructions.
919 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
920 "clz", " $dst, $src",
921 [(set GPR:$dst, (ctlz GPR:$src))]>;
923 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
924 "rev", ".w $dst, $src",
925 [(set GPR:$dst, (bswap GPR:$src))]>;
927 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
928 "rev16", ".w $dst, $src",
930 (or (and (srl GPR:$src, (i32 8)), 0xFF),
931 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
932 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
933 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
935 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
936 "revsh", ".w $dst, $src",
939 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
940 (shl GPR:$src, (i32 8))), i16))]>;
942 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
943 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
944 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
945 (and (shl GPR:$src2, (i32 imm:$shamt)),
948 // Alternate cases for PKHBT where identities eliminate some nodes.
949 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
950 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
951 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
952 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
954 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
955 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
956 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
957 (and (sra GPR:$src2, imm16_31:$shamt),
960 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
961 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
962 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
963 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
964 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
965 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
966 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
968 //===----------------------------------------------------------------------===//
969 // Comparison Instructions...
972 defm t2CMP : T2I_cmp_is<"cmp",
973 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
974 defm t2CMPz : T2I_cmp_is<"cmp",
975 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
977 defm t2CMN : T2I_cmp_is<"cmn",
978 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
979 defm t2CMNz : T2I_cmp_is<"cmn",
980 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
982 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
983 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
985 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
986 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
988 defm t2TST : T2I_cmp_is<"tst",
989 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
990 defm t2TEQ : T2I_cmp_is<"teq",
991 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
993 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
994 // Short range conditional branch. Looks awesome for loops. Need to figure
995 // out how to use this one.
999 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1000 // a two-value operand where a dag node expects two operands. :(
1001 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
1002 "mov", ".w $dst, $true",
1003 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1004 RegConstraint<"$false = $dst">;
1006 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1007 "mov", ".w $dst, $true",
1008 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1009 RegConstraint<"$false = $dst">;
1011 def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1012 "lsl", ".w $dst, $true, $rhs", []>,
1013 RegConstraint<"$false = $dst">;
1014 def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1015 "lsr", ".w $dst, $true, $rhs", []>,
1016 RegConstraint<"$false = $dst">;
1017 def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1018 "asr", ".w $dst, $true, $rhs", []>,
1019 RegConstraint<"$false = $dst">;
1020 def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1021 "ror", ".w $dst, $true, $rhs", []>,
1022 RegConstraint<"$false = $dst">;
1024 //===----------------------------------------------------------------------===//
1028 // __aeabi_read_tp preserves the registers r1-r3.
1030 Defs = [R0, R12, LR, CPSR] in {
1031 def t2TPsoft : T2XI<(outs), (ins),
1032 "bl __aeabi_read_tp",
1033 [(set R0, ARMthread_pointer)]>;
1036 //===----------------------------------------------------------------------===//
1037 // Control-Flow Instructions
1040 // FIXME: remove when we have a way to marking a MI with these properties.
1041 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1043 // FIXME: Should pc be an implicit operand like PICADD, etc?
1044 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
1045 def t2LDM_RET : T2XI<(outs),
1046 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
1047 "ldm${addr:submode}${p} $addr, $dst1",
1050 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1051 let isPredicable = 1 in
1052 def t2B : T2XI<(outs), (ins brtarget:$target),
1056 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1059 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
1060 "mov pc, $target\n$jt",
1061 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
1063 // FIXME: Add a non-pc based case that can be predicated.
1066 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1067 "tbb $index\n$jt", []>;
1071 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1072 "tbh $index\n$jt", []>;
1073 } // isNotDuplicable, isIndirectBranch
1075 } // isBranch, isTerminator, isBarrier
1077 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1078 // a two-value operand where a dag node expects two operands. :(
1079 let isBranch = 1, isTerminator = 1 in
1080 def t2Bcc : T2I<(outs), (ins brtarget:$target),
1082 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1086 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1087 AddrModeNone, Size2Bytes,
1088 "it$mask $cc", "", []>;
1090 //===----------------------------------------------------------------------===//
1091 // Non-Instruction Patterns
1094 // ConstantPool, GlobalAddress, and JumpTable
1095 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1096 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1097 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1098 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1100 // Large immediate handling.
1102 def : T2Pat<(i32 imm:$src),
1103 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;