1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let EncoderMethod = "getT2SORegOpValue";
30 let PrintMethod = "printT2SOOperand";
31 let MIOperandInfo = (ops rGPR, i32imm);
34 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
44 // t2_so_imm - Match a 32-bit immediate operand, which is an
45 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46 // immediate splatted into multiple bytes of the word. t2_so_imm values are
47 // represented in the imm field in the same 12-bit form that they are encoded
48 // into t2_so_imm instructions: the 8-bit immediate is the least significant
49 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
50 def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> {
51 let EncoderMethod = "getT2SOImmOpValue";
54 // t2_so_imm_not - Match an immediate that is a complement
56 def t2_so_imm_not : Operand<i32>,
58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
59 }], t2_so_imm_not_XFORM>;
61 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
62 def t2_so_imm_neg : Operand<i32>,
64 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
65 }], t2_so_imm_neg_XFORM>;
67 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
68 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
69 // to get the first/second pieces.
70 def t2_so_imm2part : Operand<i32>,
72 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
76 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
77 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
78 return CurDAG->getTargetConstant(V, MVT::i32);
81 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
87 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
91 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
92 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
93 return CurDAG->getTargetConstant(V, MVT::i32);
96 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
102 def imm1_31 : PatLeaf<(i32 imm), [{
103 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
106 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
107 def imm0_4095 : Operand<i32>,
108 PatLeaf<(i32 imm), [{
109 return (uint32_t)N->getZExtValue() < 4096;
112 def imm0_4095_neg : PatLeaf<(i32 imm), [{
113 return (uint32_t)(-N->getZExtValue()) < 4096;
116 def imm0_255_neg : PatLeaf<(i32 imm), [{
117 return (uint32_t)(-N->getZExtValue()) < 255;
120 def imm0_255_not : PatLeaf<(i32 imm), [{
121 return (uint32_t)(~N->getZExtValue()) < 255;
124 // Define Thumb2 specific addressing modes.
126 // t2addrmode_imm12 := reg + imm12
127 def t2addrmode_imm12 : Operand<i32>,
128 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
129 let PrintMethod = "printAddrModeImm12Operand";
130 let EncoderMethod = "getAddrModeImm12OpValue";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
134 // t2addrmode_imm8 := reg +/- imm8
135 def t2addrmode_imm8 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137 let PrintMethod = "printT2AddrModeImm8Operand";
138 let EncoderMethod = "getT2AddrModeImm8OpValue";
139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
142 def t2am_imm8_offset : Operand<i32>,
143 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
144 [], [SDNPWantRoot]> {
145 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
149 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
150 def t2addrmode_imm8s4 : Operand<i32> {
151 let PrintMethod = "printT2AddrModeImm8s4Operand";
152 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
153 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
156 def t2am_imm8s4_offset : Operand<i32> {
157 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
160 // t2addrmode_so_reg := reg + (reg << imm2)
161 def t2addrmode_so_reg : Operand<i32>,
162 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
163 let PrintMethod = "printT2AddrModeSoRegOperand";
164 let EncoderMethod = "getT2AddrModeSORegOpValue";
165 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
169 //===----------------------------------------------------------------------===//
170 // Multiclass helpers...
174 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
175 string opc, string asm, list<dag> pattern>
176 : T2I<oops, iops, itin, opc, asm, pattern> {
181 let Inst{26} = imm{11};
182 let Inst{14-12} = imm{10-8};
183 let Inst{7-0} = imm{7-0};
187 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
188 string opc, string asm, list<dag> pattern>
189 : T2sI<oops, iops, itin, opc, asm, pattern> {
195 let Inst{26} = imm{11};
196 let Inst{14-12} = imm{10-8};
197 let Inst{7-0} = imm{7-0};
200 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
201 string opc, string asm, list<dag> pattern>
202 : T2I<oops, iops, itin, opc, asm, pattern> {
206 let Inst{19-16} = Rn;
207 let Inst{26} = imm{11};
208 let Inst{14-12} = imm{10-8};
209 let Inst{7-0} = imm{7-0};
213 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
214 string opc, string asm, list<dag> pattern>
215 : T2I<oops, iops, itin, opc, asm, pattern> {
220 let Inst{3-0} = ShiftedRm{3-0};
221 let Inst{5-4} = ShiftedRm{6-5};
222 let Inst{14-12} = ShiftedRm{11-9};
223 let Inst{7-6} = ShiftedRm{8-7};
226 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
227 string opc, string asm, list<dag> pattern>
228 : T2sI<oops, iops, itin, opc, asm, pattern> {
233 let Inst{3-0} = ShiftedRm{3-0};
234 let Inst{5-4} = ShiftedRm{6-5};
235 let Inst{14-12} = ShiftedRm{11-9};
236 let Inst{7-6} = ShiftedRm{8-7};
239 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
240 string opc, string asm, list<dag> pattern>
241 : T2I<oops, iops, itin, opc, asm, pattern> {
245 let Inst{19-16} = Rn;
246 let Inst{3-0} = ShiftedRm{3-0};
247 let Inst{5-4} = ShiftedRm{6-5};
248 let Inst{14-12} = ShiftedRm{11-9};
249 let Inst{7-6} = ShiftedRm{8-7};
252 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
253 string opc, string asm, list<dag> pattern>
254 : T2I<oops, iops, itin, opc, asm, pattern> {
262 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
263 string opc, string asm, list<dag> pattern>
264 : T2sI<oops, iops, itin, opc, asm, pattern> {
272 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
273 string opc, string asm, list<dag> pattern>
274 : T2I<oops, iops, itin, opc, asm, pattern> {
278 let Inst{19-16} = Rn;
283 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
284 string opc, string asm, list<dag> pattern>
285 : T2I<oops, iops, itin, opc, asm, pattern> {
291 let Inst{19-16} = Rn;
292 let Inst{26} = imm{11};
293 let Inst{14-12} = imm{10-8};
294 let Inst{7-0} = imm{7-0};
297 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
298 string opc, string asm, list<dag> pattern>
299 : T2sI<oops, iops, itin, opc, asm, pattern> {
305 let Inst{19-16} = Rn;
306 let Inst{26} = imm{11};
307 let Inst{14-12} = imm{10-8};
308 let Inst{7-0} = imm{7-0};
311 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
312 string opc, string asm, list<dag> pattern>
313 : T2I<oops, iops, itin, opc, asm, pattern> {
320 let Inst{14-12} = imm{4-2};
321 let Inst{7-6} = imm{1-0};
324 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
325 string opc, string asm, list<dag> pattern>
326 : T2sI<oops, iops, itin, opc, asm, pattern> {
333 let Inst{14-12} = imm{4-2};
334 let Inst{7-6} = imm{1-0};
337 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
338 string opc, string asm, list<dag> pattern>
339 : T2I<oops, iops, itin, opc, asm, pattern> {
345 let Inst{19-16} = Rn;
349 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
350 string opc, string asm, list<dag> pattern>
351 : T2sI<oops, iops, itin, opc, asm, pattern> {
357 let Inst{19-16} = Rn;
361 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
362 string opc, string asm, list<dag> pattern>
363 : T2I<oops, iops, itin, opc, asm, pattern> {
369 let Inst{19-16} = Rn;
370 let Inst{3-0} = ShiftedRm{3-0};
371 let Inst{5-4} = ShiftedRm{6-5};
372 let Inst{14-12} = ShiftedRm{11-9};
373 let Inst{7-6} = ShiftedRm{8-7};
376 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
377 string opc, string asm, list<dag> pattern>
378 : T2sI<oops, iops, itin, opc, asm, pattern> {
384 let Inst{19-16} = Rn;
385 let Inst{3-0} = ShiftedRm{3-0};
386 let Inst{5-4} = ShiftedRm{6-5};
387 let Inst{14-12} = ShiftedRm{11-9};
388 let Inst{7-6} = ShiftedRm{8-7};
391 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
392 string opc, string asm, list<dag> pattern>
393 : T2I<oops, iops, itin, opc, asm, pattern> {
399 let Inst{19-16} = Rn;
400 let Inst{15-12} = Ra;
405 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
406 dag oops, dag iops, InstrItinClass itin,
407 string opc, string asm, list<dag> pattern>
408 : T2I<oops, iops, itin, opc, asm, pattern> {
414 let Inst{31-23} = 0b111110111;
415 let Inst{22-20} = opc22_20;
416 let Inst{19-16} = Rn;
417 let Inst{15-12} = RdLo;
418 let Inst{11-8} = RdHi;
419 let Inst{7-4} = opc7_4;
424 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
425 /// unary operation that produces a value. These are predicable and can be
426 /// changed to modify CPSR.
427 multiclass T2I_un_irs<bits<4> opcod, string opc,
428 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
429 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
431 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
433 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
434 let isAsCheapAsAMove = Cheap;
435 let isReMaterializable = ReMat;
436 let Inst{31-27} = 0b11110;
438 let Inst{24-21} = opcod;
439 let Inst{19-16} = 0b1111; // Rn
443 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
445 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
446 let Inst{31-27} = 0b11101;
447 let Inst{26-25} = 0b01;
448 let Inst{24-21} = opcod;
449 let Inst{19-16} = 0b1111; // Rn
450 let Inst{14-12} = 0b000; // imm3
451 let Inst{7-6} = 0b00; // imm2
452 let Inst{5-4} = 0b00; // type
455 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
456 opc, ".w\t$Rd, $ShiftedRm",
457 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
458 let Inst{31-27} = 0b11101;
459 let Inst{26-25} = 0b01;
460 let Inst{24-21} = opcod;
461 let Inst{19-16} = 0b1111; // Rn
465 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
466 /// binary operation that produces a value. These are predicable and can be
467 /// changed to modify CPSR.
468 multiclass T2I_bin_irs<bits<4> opcod, string opc,
469 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
470 PatFrag opnode, bit Commutable = 0, string wide = ""> {
472 def ri : T2sTwoRegImm<
473 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
474 opc, "\t$Rd, $Rn, $imm",
475 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
476 let Inst{31-27} = 0b11110;
478 let Inst{24-21} = opcod;
482 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
483 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
484 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
485 let isCommutable = Commutable;
486 let Inst{31-27} = 0b11101;
487 let Inst{26-25} = 0b01;
488 let Inst{24-21} = opcod;
489 let Inst{14-12} = 0b000; // imm3
490 let Inst{7-6} = 0b00; // imm2
491 let Inst{5-4} = 0b00; // type
494 def rs : T2sTwoRegShiftedReg<
495 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
496 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
497 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
498 let Inst{31-27} = 0b11101;
499 let Inst{26-25} = 0b01;
500 let Inst{24-21} = opcod;
504 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
505 // the ".w" prefix to indicate that they are wide.
506 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
507 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
508 PatFrag opnode, bit Commutable = 0> :
509 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">;
511 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
512 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
513 /// it is equivalent to the T2I_bin_irs counterpart.
514 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
516 def ri : T2sTwoRegImm<
517 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
518 opc, ".w\t$Rd, $Rn, $imm",
519 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
520 let Inst{31-27} = 0b11110;
522 let Inst{24-21} = opcod;
526 def rr : T2sThreeReg<
527 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
528 opc, "\t$Rd, $Rn, $Rm",
529 [/* For disassembly only; pattern left blank */]> {
530 let Inst{31-27} = 0b11101;
531 let Inst{26-25} = 0b01;
532 let Inst{24-21} = opcod;
533 let Inst{14-12} = 0b000; // imm3
534 let Inst{7-6} = 0b00; // imm2
535 let Inst{5-4} = 0b00; // type
538 def rs : T2sTwoRegShiftedReg<
539 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
540 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
541 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
542 let Inst{31-27} = 0b11101;
543 let Inst{26-25} = 0b01;
544 let Inst{24-21} = opcod;
548 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
549 /// instruction modifies the CPSR register.
550 let Defs = [CPSR] in {
551 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
552 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
553 PatFrag opnode, bit Commutable = 0> {
555 def ri : T2TwoRegImm<
556 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
557 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
558 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
559 let Inst{31-27} = 0b11110;
561 let Inst{24-21} = opcod;
562 let Inst{20} = 1; // The S bit.
567 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
568 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
569 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
570 let isCommutable = Commutable;
571 let Inst{31-27} = 0b11101;
572 let Inst{26-25} = 0b01;
573 let Inst{24-21} = opcod;
574 let Inst{20} = 1; // The S bit.
575 let Inst{14-12} = 0b000; // imm3
576 let Inst{7-6} = 0b00; // imm2
577 let Inst{5-4} = 0b00; // type
580 def rs : T2TwoRegShiftedReg<
581 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
582 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
583 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
584 let Inst{31-27} = 0b11101;
585 let Inst{26-25} = 0b01;
586 let Inst{24-21} = opcod;
587 let Inst{20} = 1; // The S bit.
592 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
593 /// patterns for a binary operation that produces a value.
594 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
595 bit Commutable = 0> {
597 // The register-immediate version is re-materializable. This is useful
598 // in particular for taking the address of a local.
599 let isReMaterializable = 1 in {
600 def ri : T2sTwoRegImm<
601 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
602 opc, ".w\t$Rd, $Rn, $imm",
603 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
604 let Inst{31-27} = 0b11110;
607 let Inst{23-21} = op23_21;
613 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
614 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
615 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
619 let Inst{31-27} = 0b11110;
620 let Inst{26} = imm{11};
621 let Inst{25-24} = 0b10;
622 let Inst{23-21} = op23_21;
623 let Inst{20} = 0; // The S bit.
624 let Inst{19-16} = Rn;
626 let Inst{14-12} = imm{10-8};
628 let Inst{7-0} = imm{7-0};
631 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
632 opc, ".w\t$Rd, $Rn, $Rm",
633 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
634 let isCommutable = Commutable;
635 let Inst{31-27} = 0b11101;
636 let Inst{26-25} = 0b01;
638 let Inst{23-21} = op23_21;
639 let Inst{14-12} = 0b000; // imm3
640 let Inst{7-6} = 0b00; // imm2
641 let Inst{5-4} = 0b00; // type
644 def rs : T2sTwoRegShiftedReg<
645 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
646 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
647 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
648 let Inst{31-27} = 0b11101;
649 let Inst{26-25} = 0b01;
651 let Inst{23-21} = op23_21;
655 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
656 /// for a binary operation that produces a value and use the carry
657 /// bit. It's not predicable.
658 let Uses = [CPSR] in {
659 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
660 bit Commutable = 0> {
662 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
663 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
664 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
665 Requires<[IsThumb2]> {
666 let Inst{31-27} = 0b11110;
668 let Inst{24-21} = opcod;
672 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
673 opc, ".w\t$Rd, $Rn, $Rm",
674 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
675 Requires<[IsThumb2]> {
676 let isCommutable = Commutable;
677 let Inst{31-27} = 0b11101;
678 let Inst{26-25} = 0b01;
679 let Inst{24-21} = opcod;
680 let Inst{14-12} = 0b000; // imm3
681 let Inst{7-6} = 0b00; // imm2
682 let Inst{5-4} = 0b00; // type
685 def rs : T2sTwoRegShiftedReg<
686 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
687 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
688 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
689 Requires<[IsThumb2]> {
690 let Inst{31-27} = 0b11101;
691 let Inst{26-25} = 0b01;
692 let Inst{24-21} = opcod;
696 // Carry setting variants
697 let Defs = [CPSR] in {
698 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
699 bit Commutable = 0> {
701 def ri : T2sTwoRegImm<
702 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
703 opc, "\t$Rd, $Rn, $imm",
704 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
705 Requires<[IsThumb2]> {
706 let Inst{31-27} = 0b11110;
708 let Inst{24-21} = opcod;
709 let Inst{20} = 1; // The S bit.
713 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
714 opc, ".w\t$Rd, $Rn, $Rm",
715 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
716 Requires<[IsThumb2]> {
717 let isCommutable = Commutable;
718 let Inst{31-27} = 0b11101;
719 let Inst{26-25} = 0b01;
720 let Inst{24-21} = opcod;
721 let Inst{20} = 1; // The S bit.
722 let Inst{14-12} = 0b000; // imm3
723 let Inst{7-6} = 0b00; // imm2
724 let Inst{5-4} = 0b00; // type
727 def rs : T2sTwoRegShiftedReg<
728 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
729 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
730 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
731 Requires<[IsThumb2]> {
732 let Inst{31-27} = 0b11101;
733 let Inst{26-25} = 0b01;
734 let Inst{24-21} = opcod;
735 let Inst{20} = 1; // The S bit.
741 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
742 /// version is not needed since this is only for codegen.
743 let Defs = [CPSR] in {
744 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
746 def ri : T2TwoRegImm<
747 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
748 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
749 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
750 let Inst{31-27} = 0b11110;
752 let Inst{24-21} = opcod;
753 let Inst{20} = 1; // The S bit.
757 def rs : T2TwoRegShiftedReg<
758 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
759 IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
760 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
761 let Inst{31-27} = 0b11101;
762 let Inst{26-25} = 0b01;
763 let Inst{24-21} = opcod;
764 let Inst{20} = 1; // The S bit.
769 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
770 // rotate operation that produces a value.
771 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
773 def ri : T2sTwoRegShiftImm<
774 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
775 opc, ".w\t$Rd, $Rm, $imm",
776 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
777 let Inst{31-27} = 0b11101;
778 let Inst{26-21} = 0b010010;
779 let Inst{19-16} = 0b1111; // Rn
780 let Inst{5-4} = opcod;
783 def rr : T2sThreeReg<
784 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
785 opc, ".w\t$Rd, $Rn, $Rm",
786 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
787 let Inst{31-27} = 0b11111;
788 let Inst{26-23} = 0b0100;
789 let Inst{22-21} = opcod;
790 let Inst{15-12} = 0b1111;
791 let Inst{7-4} = 0b0000;
795 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
796 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
797 /// a explicit result, only implicitly set CPSR.
798 let isCompare = 1, Defs = [CPSR] in {
799 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
800 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
803 def ri : T2OneRegCmpImm<
804 (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
805 opc, ".w\t$Rn, $imm",
806 [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
807 let Inst{31-27} = 0b11110;
809 let Inst{24-21} = opcod;
810 let Inst{20} = 1; // The S bit.
812 let Inst{11-8} = 0b1111; // Rd
815 def rr : T2TwoRegCmp<
816 (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
817 opc, ".w\t$lhs, $rhs",
818 [(opnode GPR:$lhs, rGPR:$rhs)]> {
819 let Inst{31-27} = 0b11101;
820 let Inst{26-25} = 0b01;
821 let Inst{24-21} = opcod;
822 let Inst{20} = 1; // The S bit.
823 let Inst{14-12} = 0b000; // imm3
824 let Inst{11-8} = 0b1111; // Rd
825 let Inst{7-6} = 0b00; // imm2
826 let Inst{5-4} = 0b00; // type
829 def rs : T2OneRegCmpShiftedReg<
830 (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
831 opc, ".w\t$Rn, $ShiftedRm",
832 [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
833 let Inst{31-27} = 0b11101;
834 let Inst{26-25} = 0b01;
835 let Inst{24-21} = opcod;
836 let Inst{20} = 1; // The S bit.
837 let Inst{11-8} = 0b1111; // Rd
842 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
843 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
844 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
845 def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
846 opc, ".w\t$Rt, $addr",
847 [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
848 let Inst{31-27} = 0b11111;
849 let Inst{26-25} = 0b00;
850 let Inst{24} = signed;
852 let Inst{22-21} = opcod;
853 let Inst{20} = 1; // load
856 let Inst{15-12} = Rt;
859 let Inst{19-16} = addr{16-13}; // Rn
860 let Inst{23} = addr{12}; // U
861 let Inst{11-0} = addr{11-0}; // imm
863 def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
865 [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
866 let Inst{31-27} = 0b11111;
867 let Inst{26-25} = 0b00;
868 let Inst{24} = signed;
870 let Inst{22-21} = opcod;
871 let Inst{20} = 1; // load
873 // Offset: index==TRUE, wback==FALSE
874 let Inst{10} = 1; // The P bit.
875 let Inst{8} = 0; // The W bit.
878 let Inst{15-12} = Rt;
881 let Inst{19-16} = addr{12-9}; // Rn
882 let Inst{9} = addr{8}; // U
883 let Inst{7-0} = addr{7-0}; // imm
885 def s : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
886 opc, ".w\t$Rt, $addr",
887 [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
888 let Inst{31-27} = 0b11111;
889 let Inst{26-25} = 0b00;
890 let Inst{24} = signed;
892 let Inst{22-21} = opcod;
893 let Inst{20} = 1; // load
894 let Inst{11-6} = 0b000000;
897 let Inst{15-12} = Rt;
900 let Inst{19-16} = addr{9-6}; // Rn
901 let Inst{3-0} = addr{5-2}; // Rm
902 let Inst{5-4} = addr{1-0}; // imm
905 def pci : tPseudoInst<(outs GPR:$Rt), (ins i32imm:$addr), Size4Bytes, iis,
906 [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>;
909 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
910 multiclass T2I_st<bits<2> opcod, string opc,
911 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
912 def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
913 opc, ".w\t$Rt, $addr",
914 [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
915 let Inst{31-27} = 0b11111;
916 let Inst{26-23} = 0b0001;
917 let Inst{22-21} = opcod;
918 let Inst{20} = 0; // !load
921 let Inst{15-12} = Rt;
924 let Inst{19-16} = addr{16-13}; // Rn
925 let Inst{23} = addr{12}; // U
926 let Inst{11-0} = addr{11-0}; // imm
928 def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
930 [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
931 let Inst{31-27} = 0b11111;
932 let Inst{26-23} = 0b0000;
933 let Inst{22-21} = opcod;
934 let Inst{20} = 0; // !load
936 // Offset: index==TRUE, wback==FALSE
937 let Inst{10} = 1; // The P bit.
938 let Inst{8} = 0; // The W bit.
941 let Inst{15-12} = Rt;
944 let Inst{19-16} = addr{12-9}; // Rn
945 let Inst{9} = addr{8}; // U
946 let Inst{7-0} = addr{7-0}; // imm
948 def s : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
949 opc, ".w\t$Rt, $addr",
950 [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
951 let Inst{31-27} = 0b11111;
952 let Inst{26-23} = 0b0000;
953 let Inst{22-21} = opcod;
954 let Inst{20} = 0; // !load
955 let Inst{11-6} = 0b000000;
958 let Inst{15-12} = Rt;
961 let Inst{19-16} = addr{9-6}; // Rn
962 let Inst{3-0} = addr{5-2}; // Rm
963 let Inst{5-4} = addr{1-0}; // imm
967 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
968 /// register and one whose operand is a register rotated by 8/16/24.
969 multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
970 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
972 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
973 let Inst{31-27} = 0b11111;
974 let Inst{26-23} = 0b0100;
975 let Inst{22-20} = opcod;
976 let Inst{19-16} = 0b1111; // Rn
977 let Inst{15-12} = 0b1111;
979 let Inst{5-4} = 0b00; // rotate
981 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
982 opc, ".w\t$Rd, $Rm, ror $rot",
983 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
984 let Inst{31-27} = 0b11111;
985 let Inst{26-23} = 0b0100;
986 let Inst{22-20} = opcod;
987 let Inst{19-16} = 0b1111; // Rn
988 let Inst{15-12} = 0b1111;
992 let Inst{5-4} = rot{1-0}; // rotate
996 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
997 multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
998 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1000 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
1001 Requires<[HasT2ExtractPack, IsThumb2]> {
1002 let Inst{31-27} = 0b11111;
1003 let Inst{26-23} = 0b0100;
1004 let Inst{22-20} = opcod;
1005 let Inst{19-16} = 0b1111; // Rn
1006 let Inst{15-12} = 0b1111;
1008 let Inst{5-4} = 0b00; // rotate
1010 def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
1011 IIC_iEXTr, opc, "\t$dst, $Rm, ror $rot",
1012 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1013 Requires<[HasT2ExtractPack, IsThumb2]> {
1014 let Inst{31-27} = 0b11111;
1015 let Inst{26-23} = 0b0100;
1016 let Inst{22-20} = opcod;
1017 let Inst{19-16} = 0b1111; // Rn
1018 let Inst{15-12} = 0b1111;
1022 let Inst{5-4} = rot{1-0}; // rotate
1026 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1028 multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1029 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1030 opc, "\t$Rd, $Rm", []> {
1031 let Inst{31-27} = 0b11111;
1032 let Inst{26-23} = 0b0100;
1033 let Inst{22-20} = opcod;
1034 let Inst{19-16} = 0b1111; // Rn
1035 let Inst{15-12} = 0b1111;
1037 let Inst{5-4} = 0b00; // rotate
1039 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1040 opc, "\t$Rd, $Rm, ror $rot", []> {
1041 let Inst{31-27} = 0b11111;
1042 let Inst{26-23} = 0b0100;
1043 let Inst{22-20} = opcod;
1044 let Inst{19-16} = 0b1111; // Rn
1045 let Inst{15-12} = 0b1111;
1049 let Inst{5-4} = rot{1-0}; // rotate
1053 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1054 /// register and one whose operand is a register rotated by 8/16/24.
1055 multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1056 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1057 opc, "\t$Rd, $Rn, $Rm",
1058 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1059 Requires<[HasT2ExtractPack, IsThumb2]> {
1060 let Inst{31-27} = 0b11111;
1061 let Inst{26-23} = 0b0100;
1062 let Inst{22-20} = opcod;
1063 let Inst{15-12} = 0b1111;
1065 let Inst{5-4} = 0b00; // rotate
1067 def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
1068 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1069 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1070 [(set rGPR:$Rd, (opnode rGPR:$Rn,
1071 (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1072 Requires<[HasT2ExtractPack, IsThumb2]> {
1073 let Inst{31-27} = 0b11111;
1074 let Inst{26-23} = 0b0100;
1075 let Inst{22-20} = opcod;
1076 let Inst{15-12} = 0b1111;
1080 let Inst{5-4} = rot{1-0}; // rotate
1084 // DO variant - disassembly only, no pattern
1086 multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
1087 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1088 opc, "\t$Rd, $Rn, $Rm", []> {
1089 let Inst{31-27} = 0b11111;
1090 let Inst{26-23} = 0b0100;
1091 let Inst{22-20} = opcod;
1092 let Inst{15-12} = 0b1111;
1094 let Inst{5-4} = 0b00; // rotate
1096 def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1097 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
1098 let Inst{31-27} = 0b11111;
1099 let Inst{26-23} = 0b0100;
1100 let Inst{22-20} = opcod;
1101 let Inst{15-12} = 0b1111;
1105 let Inst{5-4} = rot{1-0}; // rotate
1109 //===----------------------------------------------------------------------===//
1111 //===----------------------------------------------------------------------===//
1113 //===----------------------------------------------------------------------===//
1114 // Miscellaneous Instructions.
1117 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1118 string asm, list<dag> pattern>
1119 : T2XI<oops, iops, itin, asm, pattern> {
1123 let Inst{11-8} = Rd;
1124 let Inst{26} = label{11};
1125 let Inst{14-12} = label{10-8};
1126 let Inst{7-0} = label{7-0};
1129 // LEApcrel - Load a pc-relative address into a register without offending the
1131 let neverHasSideEffects = 1 in {
1132 let isReMaterializable = 1 in
1133 def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
1134 "adr${p}.w\t$Rd, #$label", []> {
1135 let Inst{31-27} = 0b11110;
1136 let Inst{25-24} = 0b10;
1137 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1140 let Inst{19-16} = 0b1111; // Rn
1145 } // neverHasSideEffects
1146 def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
1147 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
1148 "adr${p}.w\t$Rd, #${label}_${id}", []> {
1149 let Inst{31-27} = 0b11110;
1150 let Inst{25-24} = 0b10;
1151 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1154 let Inst{19-16} = 0b1111; // Rn
1159 // FIXME: None of these add/sub SP special instructions should be necessary
1160 // at all for thumb2 since they use the same encodings as the generic
1161 // add/sub instructions. In thumb1 we need them since they have dedicated
1162 // encodings. At the least, they should be pseudo instructions.
1163 // ADD r, sp, {so_imm|i12}
1164 let isCodeGenOnly = 1 in {
1165 def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1166 IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> {
1167 let Inst{31-27} = 0b11110;
1169 let Inst{24-21} = 0b1000;
1172 def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1173 IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> {
1174 let Inst{31-27} = 0b11110;
1175 let Inst{25-20} = 0b100000;
1179 // ADD r, sp, so_reg
1180 def t2ADDrSPs : T2sTwoRegShiftedReg<
1181 (outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
1182 IIC_iALUsi, "add", ".w\t$Rd, $Rn, $ShiftedRm", []> {
1183 let Inst{31-27} = 0b11101;
1184 let Inst{26-25} = 0b01;
1185 let Inst{24-21} = 0b1000;
1189 // SUB r, sp, {so_imm|i12}
1190 def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1191 IIC_iALUi, "sub", ".w\t$Rd, $Rn, $imm", []> {
1192 let Inst{31-27} = 0b11110;
1194 let Inst{24-21} = 0b1101;
1197 def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1198 IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> {
1199 let Inst{31-27} = 0b11110;
1200 let Inst{25-20} = 0b101010;
1204 // SUB r, sp, so_reg
1205 def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm),
1207 "sub", "\t$Rd, $Rn, $imm", []> {
1208 let Inst{31-27} = 0b11101;
1209 let Inst{26-25} = 0b01;
1210 let Inst{24-21} = 0b1101;
1211 let Inst{19-16} = 0b1101; // Rn = sp
1214 } // end isCodeGenOnly = 1
1216 // Signed and unsigned division on v7-M
1217 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1218 "sdiv", "\t$Rd, $Rn, $Rm",
1219 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
1220 Requires<[HasDivide, IsThumb2]> {
1221 let Inst{31-27} = 0b11111;
1222 let Inst{26-21} = 0b011100;
1224 let Inst{15-12} = 0b1111;
1225 let Inst{7-4} = 0b1111;
1228 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1229 "udiv", "\t$Rd, $Rn, $Rm",
1230 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
1231 Requires<[HasDivide, IsThumb2]> {
1232 let Inst{31-27} = 0b11111;
1233 let Inst{26-21} = 0b011101;
1235 let Inst{15-12} = 0b1111;
1236 let Inst{7-4} = 0b1111;
1239 //===----------------------------------------------------------------------===//
1240 // Load / store Instructions.
1244 let canFoldAsLoad = 1, isReMaterializable = 1 in
1245 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1246 UnOpFrag<(load node:$Src)>>;
1248 // Loads with zero extension
1249 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1250 UnOpFrag<(zextloadi16 node:$Src)>>;
1251 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1252 UnOpFrag<(zextloadi8 node:$Src)>>;
1254 // Loads with sign extension
1255 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1256 UnOpFrag<(sextloadi16 node:$Src)>>;
1257 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1258 UnOpFrag<(sextloadi8 node:$Src)>>;
1260 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1262 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1263 (ins t2addrmode_imm8s4:$addr),
1264 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1265 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1267 // zextload i1 -> zextload i8
1268 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1269 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1270 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1271 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1272 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1273 (t2LDRBs t2addrmode_so_reg:$addr)>;
1274 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1275 (t2LDRBpci tconstpool:$addr)>;
1277 // extload -> zextload
1278 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1280 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1281 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1282 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1283 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1284 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1285 (t2LDRBs t2addrmode_so_reg:$addr)>;
1286 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1287 (t2LDRBpci tconstpool:$addr)>;
1289 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1290 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1291 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1292 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1293 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1294 (t2LDRBs t2addrmode_so_reg:$addr)>;
1295 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1296 (t2LDRBpci tconstpool:$addr)>;
1298 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1299 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1300 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1301 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1302 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1303 (t2LDRHs t2addrmode_so_reg:$addr)>;
1304 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1305 (t2LDRHpci tconstpool:$addr)>;
1307 // FIXME: The destination register of the loads and stores can't be PC, but
1308 // can be SP. We need another regclass (similar to rGPR) to represent
1309 // that. Not a pressing issue since these are selected manually,
1314 let mayLoad = 1, neverHasSideEffects = 1 in {
1315 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1316 (ins t2addrmode_imm8:$addr),
1317 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1318 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1321 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1322 (ins GPR:$base, t2am_imm8_offset:$addr),
1323 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1324 "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1327 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1328 (ins t2addrmode_imm8:$addr),
1329 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1330 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1332 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1333 (ins GPR:$base, t2am_imm8_offset:$addr),
1334 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1335 "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1338 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1339 (ins t2addrmode_imm8:$addr),
1340 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1341 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1343 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1344 (ins GPR:$base, t2am_imm8_offset:$addr),
1345 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1346 "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1349 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1350 (ins t2addrmode_imm8:$addr),
1351 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1352 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1354 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1355 (ins GPR:$base, t2am_imm8_offset:$addr),
1356 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1357 "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1360 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1361 (ins t2addrmode_imm8:$addr),
1362 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1363 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1365 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
1366 (ins GPR:$base, t2am_imm8_offset:$addr),
1367 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1368 "ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
1370 } // mayLoad = 1, neverHasSideEffects = 1
1372 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1373 // for disassembly only.
1374 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1375 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1376 : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1377 "\t$Rt, $addr", []> {
1378 let Inst{31-27} = 0b11111;
1379 let Inst{26-25} = 0b00;
1380 let Inst{24} = signed;
1382 let Inst{22-21} = type;
1383 let Inst{20} = 1; // load
1385 let Inst{10-8} = 0b110; // PUW.
1389 let Inst{15-12} = Rt;
1390 let Inst{19-16} = addr{12-9};
1391 let Inst{7-0} = addr{7-0};
1394 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1395 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1396 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1397 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1398 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1401 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1402 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1403 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1404 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1405 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1406 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1409 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1410 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1411 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1412 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1415 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1416 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1417 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1418 "str", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1420 (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1422 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1423 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1424 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1425 "str", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1427 (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1429 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1430 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1431 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1432 "strh", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1434 (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1436 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1437 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1438 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1439 "strh", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1441 (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1443 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1444 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1445 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1446 "strb", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1448 (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1450 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1451 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1452 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1453 "strb", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1455 (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1457 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1459 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1460 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1461 : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1462 "\t$Rt, $addr", []> {
1463 let Inst{31-27} = 0b11111;
1464 let Inst{26-25} = 0b00;
1465 let Inst{24} = 0; // not signed
1467 let Inst{22-21} = type;
1468 let Inst{20} = 0; // store
1470 let Inst{10-8} = 0b110; // PUW
1474 let Inst{15-12} = Rt;
1475 let Inst{19-16} = addr{12-9};
1476 let Inst{7-0} = addr{7-0};
1479 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1480 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1481 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1483 // ldrd / strd pre / post variants
1484 // For disassembly only.
1486 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1487 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1488 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1490 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1491 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1492 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1494 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1495 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1496 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1498 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1499 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1500 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1502 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1503 // data/instruction access. These are for disassembly only.
1504 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1505 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1506 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1508 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1510 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1511 let Inst{31-25} = 0b1111100;
1512 let Inst{24} = instr;
1514 let Inst{21} = write;
1516 let Inst{15-12} = 0b1111;
1519 let Inst{19-16} = addr{16-13}; // Rn
1520 let Inst{23} = addr{12}; // U
1521 let Inst{11-0} = addr{11-0}; // imm12
1524 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1526 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1527 let Inst{31-25} = 0b1111100;
1528 let Inst{24} = instr;
1529 let Inst{23} = 0; // U = 0
1531 let Inst{21} = write;
1533 let Inst{15-12} = 0b1111;
1534 let Inst{11-8} = 0b1100;
1537 let Inst{19-16} = addr{12-9}; // Rn
1538 let Inst{7-0} = addr{7-0}; // imm8
1541 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1543 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1544 let Inst{31-25} = 0b1111100;
1545 let Inst{24} = instr;
1546 let Inst{23} = 0; // add = TRUE for T1
1548 let Inst{21} = write;
1550 let Inst{15-12} = 0b1111;
1551 let Inst{11-6} = 0000000;
1554 let Inst{19-16} = addr{9-6}; // Rn
1555 let Inst{3-0} = addr{5-2}; // Rm
1556 let Inst{5-4} = addr{1-0}; // imm2
1560 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1561 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1562 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1564 //===----------------------------------------------------------------------===//
1565 // Load / store multiple Instructions.
1568 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1569 InstrItinClass itin_upd, bit L_bit> {
1571 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1572 itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1576 let Inst{31-27} = 0b11101;
1577 let Inst{26-25} = 0b00;
1578 let Inst{24-23} = 0b01; // Increment After
1580 let Inst{21} = 0; // No writeback
1581 let Inst{20} = L_bit;
1582 let Inst{19-16} = Rn;
1583 let Inst{15-0} = regs;
1586 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1587 itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1591 let Inst{31-27} = 0b11101;
1592 let Inst{26-25} = 0b00;
1593 let Inst{24-23} = 0b01; // Increment After
1595 let Inst{21} = 1; // Writeback
1596 let Inst{20} = L_bit;
1597 let Inst{19-16} = Rn;
1598 let Inst{15-0} = regs;
1601 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1602 itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1606 let Inst{31-27} = 0b11101;
1607 let Inst{26-25} = 0b00;
1608 let Inst{24-23} = 0b10; // Decrement Before
1610 let Inst{21} = 0; // No writeback
1611 let Inst{20} = L_bit;
1612 let Inst{19-16} = Rn;
1613 let Inst{15-0} = regs;
1616 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1617 itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1621 let Inst{31-27} = 0b11101;
1622 let Inst{26-25} = 0b00;
1623 let Inst{24-23} = 0b10; // Decrement Before
1625 let Inst{21} = 1; // Writeback
1626 let Inst{20} = L_bit;
1627 let Inst{19-16} = Rn;
1628 let Inst{15-0} = regs;
1632 let neverHasSideEffects = 1 in {
1634 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1635 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1637 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1638 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1640 } // neverHasSideEffects
1643 //===----------------------------------------------------------------------===//
1644 // Move Instructions.
1647 let neverHasSideEffects = 1 in
1648 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1649 "mov", ".w\t$Rd, $Rm", []> {
1650 let Inst{31-27} = 0b11101;
1651 let Inst{26-25} = 0b01;
1652 let Inst{24-21} = 0b0010;
1653 let Inst{19-16} = 0b1111; // Rn
1654 let Inst{14-12} = 0b000;
1655 let Inst{7-4} = 0b0000;
1658 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1659 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1660 AddedComplexity = 1 in
1661 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1662 "mov", ".w\t$Rd, $imm",
1663 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1664 let Inst{31-27} = 0b11110;
1666 let Inst{24-21} = 0b0010;
1667 let Inst{19-16} = 0b1111; // Rn
1671 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1672 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm:$imm), IIC_iMOVi,
1673 "movw", "\t$Rd, $imm",
1674 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1675 let Inst{31-27} = 0b11110;
1677 let Inst{24-21} = 0b0010;
1678 let Inst{20} = 0; // The S bit.
1684 let Inst{11-8} = Rd;
1685 let Inst{19-16} = imm{15-12};
1686 let Inst{26} = imm{11};
1687 let Inst{14-12} = imm{10-8};
1688 let Inst{7-0} = imm{7-0};
1691 let Constraints = "$src = $Rd" in
1692 def t2MOVTi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1693 "movt", "\t$Rd, $imm",
1695 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1696 let Inst{31-27} = 0b11110;
1698 let Inst{24-21} = 0b0110;
1699 let Inst{20} = 0; // The S bit.
1705 let Inst{11-8} = Rd;
1706 let Inst{19-16} = imm{15-12};
1707 let Inst{26} = imm{11};
1708 let Inst{14-12} = imm{10-8};
1709 let Inst{7-0} = imm{7-0};
1712 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1714 //===----------------------------------------------------------------------===//
1715 // Extend Instructions.
1720 defm t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1721 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1722 defm t2SXTH : T2I_ext_rrot<0b000, "sxth",
1723 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1724 defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1726 defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1727 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1728 defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1729 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1730 defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1732 // TODO: SXT(A){B|H}16 - done for disassembly only
1736 let AddedComplexity = 16 in {
1737 defm t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1738 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1739 defm t2UXTH : T2I_ext_rrot<0b001, "uxth",
1740 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1741 defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1742 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1744 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1745 // The transformation should probably be done as a combiner action
1746 // instead so we can include a check for masking back in the upper
1747 // eight bits of the source into the lower eight bits of the result.
1748 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1749 // (t2UXTB16r_rot rGPR:$Src, 24)>,
1750 // Requires<[HasT2ExtractPack, IsThumb2]>;
1751 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1752 (t2UXTB16r_rot rGPR:$Src, 8)>,
1753 Requires<[HasT2ExtractPack, IsThumb2]>;
1755 defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1756 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1757 defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1758 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1759 defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1762 //===----------------------------------------------------------------------===//
1763 // Arithmetic Instructions.
1766 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1767 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1768 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1769 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1771 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1772 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1773 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1774 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1775 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1776 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1777 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1779 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1780 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1781 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1782 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1783 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1784 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1785 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1786 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1789 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1790 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1791 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1792 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1794 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1795 // The assume-no-carry-in form uses the negation of the input since add/sub
1796 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1797 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1799 // The AddedComplexity preferences the first variant over the others since
1800 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1801 let AddedComplexity = 1 in
1802 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1803 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1804 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1805 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1806 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1807 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1808 let AddedComplexity = 1 in
1809 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1810 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1811 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1812 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1813 // The with-carry-in form matches bitwise not instead of the negation.
1814 // Effectively, the inverse interpretation of the carry flag already accounts
1815 // for part of the negation.
1816 let AddedComplexity = 1 in
1817 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1818 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1819 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1820 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1822 // Select Bytes -- for disassembly only
1824 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1825 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
1826 let Inst{31-27} = 0b11111;
1827 let Inst{26-24} = 0b010;
1829 let Inst{22-20} = 0b010;
1830 let Inst{15-12} = 0b1111;
1832 let Inst{6-4} = 0b000;
1835 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1836 // And Miscellaneous operations -- for disassembly only
1837 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1838 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1839 : T2I<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, opc,
1840 "\t$Rd, $Rn, $Rm", pat> {
1841 let Inst{31-27} = 0b11111;
1842 let Inst{26-23} = 0b0101;
1843 let Inst{22-20} = op22_20;
1844 let Inst{15-12} = 0b1111;
1845 let Inst{7-4} = op7_4;
1851 let Inst{11-8} = Rd;
1852 let Inst{19-16} = Rn;
1856 // Saturating add/subtract -- for disassembly only
1858 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1859 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))]>;
1860 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1861 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1862 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1863 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1864 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1865 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1866 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1867 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))]>;
1868 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1869 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1870 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1871 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1872 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1873 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1874 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1875 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1877 // Signed/Unsigned add/subtract -- for disassembly only
1879 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1880 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1881 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1882 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1883 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1884 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1885 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1886 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1887 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1888 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1889 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1890 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1892 // Signed/Unsigned halving add/subtract -- for disassembly only
1894 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1895 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1896 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1897 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1898 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1899 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1900 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1901 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1902 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1903 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1904 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1905 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1907 // Helper class for disassembly only
1908 // A6.3.16 & A6.3.17
1909 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1910 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1911 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1912 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1913 let Inst{31-27} = 0b11111;
1914 let Inst{26-24} = 0b011;
1915 let Inst{23} = long;
1916 let Inst{22-20} = op22_20;
1917 let Inst{7-4} = op7_4;
1920 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1921 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1922 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1923 let Inst{31-27} = 0b11111;
1924 let Inst{26-24} = 0b011;
1925 let Inst{23} = long;
1926 let Inst{22-20} = op22_20;
1927 let Inst{7-4} = op7_4;
1930 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1932 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1933 (ins rGPR:$Rn, rGPR:$Rm),
1934 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
1935 let Inst{15-12} = 0b1111;
1937 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1938 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1939 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
1941 // Signed/Unsigned saturate -- for disassembly only
1943 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1944 string opc, string asm, list<dag> pattern>
1945 : T2I<oops, iops, itin, opc, asm, pattern> {
1951 let Inst{11-8} = Rd;
1952 let Inst{19-16} = Rn;
1953 let Inst{4-0} = sat_imm{4-0};
1954 let Inst{21} = sh{6};
1955 let Inst{14-12} = sh{4-2};
1956 let Inst{7-6} = sh{1-0};
1960 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1961 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1962 [/* For disassembly only; pattern left blank */]> {
1963 let Inst{31-27} = 0b11110;
1964 let Inst{25-22} = 0b1100;
1969 def t2SSAT16: T2SatI<
1970 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
1971 "ssat16", "\t$Rd, $sat_imm, $Rn",
1972 [/* For disassembly only; pattern left blank */]> {
1973 let Inst{31-27} = 0b11110;
1974 let Inst{25-22} = 0b1100;
1977 let Inst{21} = 1; // sh = '1'
1978 let Inst{14-12} = 0b000; // imm3 = '000'
1979 let Inst{7-6} = 0b00; // imm2 = '00'
1983 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1984 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1985 [/* For disassembly only; pattern left blank */]> {
1986 let Inst{31-27} = 0b11110;
1987 let Inst{25-22} = 0b1110;
1992 def t2USAT16: T2SatI<
1993 (outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
1994 "usat16", "\t$dst, $sat_imm, $Rn",
1995 [/* For disassembly only; pattern left blank */]> {
1996 let Inst{31-27} = 0b11110;
1997 let Inst{25-22} = 0b1110;
2000 let Inst{21} = 1; // sh = '1'
2001 let Inst{14-12} = 0b000; // imm3 = '000'
2002 let Inst{7-6} = 0b00; // imm2 = '00'
2005 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2006 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2008 //===----------------------------------------------------------------------===//
2009 // Shift and rotate Instructions.
2012 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2013 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2014 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2015 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2017 let Uses = [CPSR] in {
2018 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2019 "rrx", "\t$Rd, $Rm",
2020 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2021 let Inst{31-27} = 0b11101;
2022 let Inst{26-25} = 0b01;
2023 let Inst{24-21} = 0b0010;
2024 let Inst{19-16} = 0b1111; // Rn
2025 let Inst{14-12} = 0b000;
2026 let Inst{7-4} = 0b0011;
2030 let Defs = [CPSR] in {
2031 def t2MOVsrl_flag : T2TwoRegShiftImm<
2032 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2033 "lsrs", ".w\t$Rd, $Rm, #1",
2034 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2035 let Inst{31-27} = 0b11101;
2036 let Inst{26-25} = 0b01;
2037 let Inst{24-21} = 0b0010;
2038 let Inst{20} = 1; // The S bit.
2039 let Inst{19-16} = 0b1111; // Rn
2040 let Inst{5-4} = 0b01; // Shift type.
2041 // Shift amount = Inst{14-12:7-6} = 1.
2042 let Inst{14-12} = 0b000;
2043 let Inst{7-6} = 0b01;
2045 def t2MOVsra_flag : T2TwoRegShiftImm<
2046 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2047 "asrs", ".w\t$Rd, $Rm, #1",
2048 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2049 let Inst{31-27} = 0b11101;
2050 let Inst{26-25} = 0b01;
2051 let Inst{24-21} = 0b0010;
2052 let Inst{20} = 1; // The S bit.
2053 let Inst{19-16} = 0b1111; // Rn
2054 let Inst{5-4} = 0b10; // Shift type.
2055 // Shift amount = Inst{14-12:7-6} = 1.
2056 let Inst{14-12} = 0b000;
2057 let Inst{7-6} = 0b01;
2061 //===----------------------------------------------------------------------===//
2062 // Bitwise Instructions.
2065 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2066 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2067 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2068 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2069 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2070 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2071 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2072 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2073 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2075 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2076 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2077 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2079 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2080 string opc, string asm, list<dag> pattern>
2081 : T2I<oops, iops, itin, opc, asm, pattern> {
2086 let Inst{11-8} = Rd;
2087 let Inst{4-0} = msb{4-0};
2088 let Inst{14-12} = lsb{4-2};
2089 let Inst{7-6} = lsb{1-0};
2092 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2093 string opc, string asm, list<dag> pattern>
2094 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2097 let Inst{19-16} = Rn;
2100 let Constraints = "$src = $Rd" in
2101 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2102 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2103 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2104 let Inst{31-27} = 0b11110;
2106 let Inst{24-20} = 0b10110;
2107 let Inst{19-16} = 0b1111; // Rn
2111 let msb{4-0} = imm{9-5};
2112 let lsb{4-0} = imm{4-0};
2115 def t2SBFX: T2TwoRegBitFI<
2116 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2117 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2118 let Inst{31-27} = 0b11110;
2120 let Inst{24-20} = 0b10100;
2124 def t2UBFX: T2TwoRegBitFI<
2125 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2126 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2127 let Inst{31-27} = 0b11110;
2129 let Inst{24-20} = 0b11100;
2133 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2134 let Constraints = "$src = $Rd" in
2135 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2136 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2137 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2138 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2139 bf_inv_mask_imm:$imm))]> {
2140 let Inst{31-27} = 0b11110;
2142 let Inst{24-20} = 0b10110;
2146 let msb{4-0} = imm{9-5};
2147 let lsb{4-0} = imm{4-0};
2150 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2151 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2152 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2154 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2155 let AddedComplexity = 1 in
2156 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2157 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2158 UnOpFrag<(not node:$Src)>, 1, 1>;
2161 let AddedComplexity = 1 in
2162 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2163 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2165 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2166 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2167 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2168 Requires<[IsThumb2]>;
2170 def : T2Pat<(t2_so_imm_not:$src),
2171 (t2MVNi t2_so_imm_not:$src)>;
2173 //===----------------------------------------------------------------------===//
2174 // Multiply Instructions.
2176 let isCommutable = 1 in
2177 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2178 "mul", "\t$Rd, $Rn, $Rm",
2179 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2180 let Inst{31-27} = 0b11111;
2181 let Inst{26-23} = 0b0110;
2182 let Inst{22-20} = 0b000;
2183 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2184 let Inst{7-4} = 0b0000; // Multiply
2187 def t2MLA: T2FourReg<
2188 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2189 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2190 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2191 let Inst{31-27} = 0b11111;
2192 let Inst{26-23} = 0b0110;
2193 let Inst{22-20} = 0b000;
2194 let Inst{7-4} = 0b0000; // Multiply
2197 def t2MLS: T2FourReg<
2198 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2199 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2200 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2201 let Inst{31-27} = 0b11111;
2202 let Inst{26-23} = 0b0110;
2203 let Inst{22-20} = 0b000;
2204 let Inst{7-4} = 0b0001; // Multiply and Subtract
2207 // Extra precision multiplies with low / high results
2208 let neverHasSideEffects = 1 in {
2209 let isCommutable = 1 in {
2210 def t2SMULL : T2MulLong<0b000, 0b0000,
2211 (outs rGPR:$Rd, rGPR:$Ra),
2212 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2213 "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
2215 def t2UMULL : T2MulLong<0b010, 0b0000,
2216 (outs rGPR:$RdLo, rGPR:$RdHi),
2217 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2218 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2221 // Multiply + accumulate
2222 def t2SMLAL : T2MulLong<0b100, 0b0000,
2223 (outs rGPR:$RdLo, rGPR:$RdHi),
2224 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2225 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2227 def t2UMLAL : T2MulLong<0b110, 0b0000,
2228 (outs rGPR:$RdLo, rGPR:$RdHi),
2229 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2230 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2232 def t2UMAAL : T2MulLong<0b110, 0b0110,
2233 (outs rGPR:$RdLo, rGPR:$RdHi),
2234 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2235 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2236 } // neverHasSideEffects
2238 // Rounding variants of the below included for disassembly only
2240 // Most significant word multiply
2241 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2242 "smmul", "\t$Rd, $Rn, $Rm",
2243 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
2244 let Inst{31-27} = 0b11111;
2245 let Inst{26-23} = 0b0110;
2246 let Inst{22-20} = 0b101;
2247 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2248 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2251 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2252 "smmulr", "\t$Rd, $Rn, $Rm", []> {
2253 let Inst{31-27} = 0b11111;
2254 let Inst{26-23} = 0b0110;
2255 let Inst{22-20} = 0b101;
2256 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2257 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2260 def t2SMMLA : T2FourReg<
2261 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2262 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2263 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
2264 let Inst{31-27} = 0b11111;
2265 let Inst{26-23} = 0b0110;
2266 let Inst{22-20} = 0b101;
2267 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2270 def t2SMMLAR: T2FourReg<
2271 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2272 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
2273 let Inst{31-27} = 0b11111;
2274 let Inst{26-23} = 0b0110;
2275 let Inst{22-20} = 0b101;
2276 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2279 def t2SMMLS: T2FourReg<
2280 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2281 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2282 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
2283 let Inst{31-27} = 0b11111;
2284 let Inst{26-23} = 0b0110;
2285 let Inst{22-20} = 0b110;
2286 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2289 def t2SMMLSR:T2FourReg<
2290 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2291 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
2292 let Inst{31-27} = 0b11111;
2293 let Inst{26-23} = 0b0110;
2294 let Inst{22-20} = 0b110;
2295 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2298 multiclass T2I_smul<string opc, PatFrag opnode> {
2299 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2300 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2301 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2302 (sext_inreg rGPR:$Rm, i16)))]> {
2303 let Inst{31-27} = 0b11111;
2304 let Inst{26-23} = 0b0110;
2305 let Inst{22-20} = 0b001;
2306 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2307 let Inst{7-6} = 0b00;
2308 let Inst{5-4} = 0b00;
2311 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2312 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2313 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2314 (sra rGPR:$Rm, (i32 16))))]> {
2315 let Inst{31-27} = 0b11111;
2316 let Inst{26-23} = 0b0110;
2317 let Inst{22-20} = 0b001;
2318 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2319 let Inst{7-6} = 0b00;
2320 let Inst{5-4} = 0b01;
2323 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2324 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2325 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2326 (sext_inreg rGPR:$Rm, i16)))]> {
2327 let Inst{31-27} = 0b11111;
2328 let Inst{26-23} = 0b0110;
2329 let Inst{22-20} = 0b001;
2330 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2331 let Inst{7-6} = 0b00;
2332 let Inst{5-4} = 0b10;
2335 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2336 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2337 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2338 (sra rGPR:$Rm, (i32 16))))]> {
2339 let Inst{31-27} = 0b11111;
2340 let Inst{26-23} = 0b0110;
2341 let Inst{22-20} = 0b001;
2342 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2343 let Inst{7-6} = 0b00;
2344 let Inst{5-4} = 0b11;
2347 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2348 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2349 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2350 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
2351 let Inst{31-27} = 0b11111;
2352 let Inst{26-23} = 0b0110;
2353 let Inst{22-20} = 0b011;
2354 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2355 let Inst{7-6} = 0b00;
2356 let Inst{5-4} = 0b00;
2359 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2360 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2361 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2362 (sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
2363 let Inst{31-27} = 0b11111;
2364 let Inst{26-23} = 0b0110;
2365 let Inst{22-20} = 0b011;
2366 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2367 let Inst{7-6} = 0b00;
2368 let Inst{5-4} = 0b01;
2373 multiclass T2I_smla<string opc, PatFrag opnode> {
2375 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2376 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2377 [(set rGPR:$Rd, (add rGPR:$Ra,
2378 (opnode (sext_inreg rGPR:$Rn, i16),
2379 (sext_inreg rGPR:$Rm, i16))))]> {
2380 let Inst{31-27} = 0b11111;
2381 let Inst{26-23} = 0b0110;
2382 let Inst{22-20} = 0b001;
2383 let Inst{7-6} = 0b00;
2384 let Inst{5-4} = 0b00;
2388 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2389 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2390 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2391 (sra rGPR:$Rm, (i32 16)))))]> {
2392 let Inst{31-27} = 0b11111;
2393 let Inst{26-23} = 0b0110;
2394 let Inst{22-20} = 0b001;
2395 let Inst{7-6} = 0b00;
2396 let Inst{5-4} = 0b01;
2400 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2401 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2402 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2403 (sext_inreg rGPR:$Rm, i16))))]> {
2404 let Inst{31-27} = 0b11111;
2405 let Inst{26-23} = 0b0110;
2406 let Inst{22-20} = 0b001;
2407 let Inst{7-6} = 0b00;
2408 let Inst{5-4} = 0b10;
2412 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2413 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2414 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2415 (sra rGPR:$Rm, (i32 16)))))]> {
2416 let Inst{31-27} = 0b11111;
2417 let Inst{26-23} = 0b0110;
2418 let Inst{22-20} = 0b001;
2419 let Inst{7-6} = 0b00;
2420 let Inst{5-4} = 0b11;
2424 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2425 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2426 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2427 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
2428 let Inst{31-27} = 0b11111;
2429 let Inst{26-23} = 0b0110;
2430 let Inst{22-20} = 0b011;
2431 let Inst{7-6} = 0b00;
2432 let Inst{5-4} = 0b00;
2436 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2437 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2438 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2439 (sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
2440 let Inst{31-27} = 0b11111;
2441 let Inst{26-23} = 0b0110;
2442 let Inst{22-20} = 0b011;
2443 let Inst{7-6} = 0b00;
2444 let Inst{5-4} = 0b01;
2448 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2449 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2451 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2452 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2453 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2454 [/* For disassembly only; pattern left blank */]>;
2455 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2456 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2457 [/* For disassembly only; pattern left blank */]>;
2458 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2459 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2460 [/* For disassembly only; pattern left blank */]>;
2461 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2462 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2463 [/* For disassembly only; pattern left blank */]>;
2465 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2466 // These are for disassembly only.
2468 def t2SMUAD: T2ThreeReg_mac<
2469 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2470 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
2471 let Inst{15-12} = 0b1111;
2473 def t2SMUADX:T2ThreeReg_mac<
2474 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2475 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
2476 let Inst{15-12} = 0b1111;
2478 def t2SMUSD: T2ThreeReg_mac<
2479 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2480 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
2481 let Inst{15-12} = 0b1111;
2483 def t2SMUSDX:T2ThreeReg_mac<
2484 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2485 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
2486 let Inst{15-12} = 0b1111;
2488 def t2SMLAD : T2ThreeReg_mac<
2489 0, 0b010, 0b0000, (outs rGPR:$Rd),
2490 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2491 "\t$Rd, $Rn, $Rm, $Ra", []>;
2492 def t2SMLADX : T2FourReg_mac<
2493 0, 0b010, 0b0001, (outs rGPR:$Rd),
2494 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2495 "\t$Rd, $Rn, $Rm, $Ra", []>;
2496 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2497 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2498 "\t$Rd, $Rn, $Rm, $Ra", []>;
2499 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2500 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2501 "\t$Rd, $Rn, $Rm, $Ra", []>;
2502 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2503 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2504 "\t$Ra, $Rd, $Rm, $Rn", []>;
2505 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2506 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2507 "\t$Ra, $Rd, $Rm, $Rn", []>;
2508 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2509 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2510 "\t$Ra, $Rd, $Rm, $Rn", []>;
2511 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2512 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2513 "\t$Ra, $Rd, $Rm, $Rn", []>;
2515 //===----------------------------------------------------------------------===//
2516 // Misc. Arithmetic Instructions.
2519 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2520 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2521 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2522 let Inst{31-27} = 0b11111;
2523 let Inst{26-22} = 0b01010;
2524 let Inst{21-20} = op1;
2525 let Inst{15-12} = 0b1111;
2526 let Inst{7-6} = 0b10;
2527 let Inst{5-4} = op2;
2531 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2532 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2534 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2535 "rbit", "\t$Rd, $Rm",
2536 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2538 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2539 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2541 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2542 "rev16", ".w\t$Rd, $Rm",
2544 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF),
2545 (or (and (shl rGPR:$Rm, (i32 8)), 0xFF00),
2546 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
2547 (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
2549 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2550 "revsh", ".w\t$Rd, $Rm",
2553 (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
2554 (shl rGPR:$Rm, (i32 8))), i16))]>;
2556 def t2PKHBT : T2ThreeReg<
2557 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2558 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2559 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2560 (and (shl rGPR:$Rm, lsl_amt:$sh),
2562 Requires<[HasT2ExtractPack, IsThumb2]> {
2563 let Inst{31-27} = 0b11101;
2564 let Inst{26-25} = 0b01;
2565 let Inst{24-20} = 0b01100;
2566 let Inst{5} = 0; // BT form
2570 let Inst{14-12} = sh{7-5};
2571 let Inst{7-6} = sh{4-3};
2574 // Alternate cases for PKHBT where identities eliminate some nodes.
2575 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2576 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2577 Requires<[HasT2ExtractPack, IsThumb2]>;
2578 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2579 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2580 Requires<[HasT2ExtractPack, IsThumb2]>;
2582 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2583 // will match the pattern below.
2584 def t2PKHTB : T2ThreeReg<
2585 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2586 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2587 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2588 (and (sra rGPR:$Rm, asr_amt:$sh),
2590 Requires<[HasT2ExtractPack, IsThumb2]> {
2591 let Inst{31-27} = 0b11101;
2592 let Inst{26-25} = 0b01;
2593 let Inst{24-20} = 0b01100;
2594 let Inst{5} = 1; // TB form
2598 let Inst{14-12} = sh{7-5};
2599 let Inst{7-6} = sh{4-3};
2602 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2603 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2604 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2605 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2606 Requires<[HasT2ExtractPack, IsThumb2]>;
2607 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2608 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2609 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2610 Requires<[HasT2ExtractPack, IsThumb2]>;
2612 //===----------------------------------------------------------------------===//
2613 // Comparison Instructions...
2615 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2616 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2617 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2619 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
2620 (t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
2621 def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
2622 (t2CMPrr GPR:$lhs, rGPR:$rhs)>;
2623 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
2624 (t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
2626 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2627 // Compare-to-zero still works out, just not the relationals
2628 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2629 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2630 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2631 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2632 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2634 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2635 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2637 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2638 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2640 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2641 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2642 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2643 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2644 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2645 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2647 // Conditional moves
2648 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2649 // a two-value operand where a dag node expects two operands. :(
2650 let neverHasSideEffects = 1 in {
2651 def t2MOVCCr : T2TwoReg<
2652 (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
2653 "mov", ".w\t$Rd, $Rm",
2654 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2655 RegConstraint<"$false = $Rd"> {
2656 let Inst{31-27} = 0b11101;
2657 let Inst{26-25} = 0b01;
2658 let Inst{24-21} = 0b0010;
2659 let Inst{20} = 0; // The S bit.
2660 let Inst{19-16} = 0b1111; // Rn
2661 let Inst{14-12} = 0b000;
2662 let Inst{7-4} = 0b0000;
2665 let isMoveImm = 1 in
2666 def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2667 IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
2668 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2669 RegConstraint<"$false = $Rd"> {
2670 let Inst{31-27} = 0b11110;
2672 let Inst{24-21} = 0b0010;
2673 let Inst{20} = 0; // The S bit.
2674 let Inst{19-16} = 0b1111; // Rn
2678 let isMoveImm = 1 in
2679 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm:$imm),
2681 "movw", "\t$Rd, $imm", []>,
2682 RegConstraint<"$false = $Rd"> {
2683 let Inst{31-27} = 0b11110;
2685 let Inst{24-21} = 0b0010;
2686 let Inst{20} = 0; // The S bit.
2692 let Inst{11-8} = Rd;
2693 let Inst{19-16} = imm{15-12};
2694 let Inst{26} = imm{11};
2695 let Inst{14-12} = imm{10-8};
2696 let Inst{7-0} = imm{7-0};
2699 let isMoveImm = 1 in
2700 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2701 (ins rGPR:$false, i32imm:$src, pred:$p),
2702 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2704 let isMoveImm = 1 in
2705 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2706 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2707 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2708 imm:$cc, CCR:$ccr))*/]>,
2709 RegConstraint<"$false = $Rd"> {
2710 let Inst{31-27} = 0b11110;
2712 let Inst{24-21} = 0b0011;
2713 let Inst{20} = 0; // The S bit.
2714 let Inst{19-16} = 0b1111; // Rn
2718 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2719 string opc, string asm, list<dag> pattern>
2720 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2721 let Inst{31-27} = 0b11101;
2722 let Inst{26-25} = 0b01;
2723 let Inst{24-21} = 0b0010;
2724 let Inst{20} = 0; // The S bit.
2725 let Inst{19-16} = 0b1111; // Rn
2726 let Inst{5-4} = opcod; // Shift type.
2728 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2729 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2730 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2731 RegConstraint<"$false = $Rd">;
2732 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2733 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2734 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2735 RegConstraint<"$false = $Rd">;
2736 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2737 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2738 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2739 RegConstraint<"$false = $Rd">;
2740 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2741 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2742 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2743 RegConstraint<"$false = $Rd">;
2744 } // neverHasSideEffects
2746 //===----------------------------------------------------------------------===//
2747 // Atomic operations intrinsics
2750 // memory barriers protect the atomic sequences
2751 let hasSideEffects = 1 in {
2752 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2753 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2754 Requires<[IsThumb, HasDB]> {
2756 let Inst{31-4} = 0xf3bf8f5;
2757 let Inst{3-0} = opt;
2761 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2763 [/* For disassembly only; pattern left blank */]>,
2764 Requires<[IsThumb, HasDB]> {
2766 let Inst{31-4} = 0xf3bf8f4;
2767 let Inst{3-0} = opt;
2770 // ISB has only full system option -- for disassembly only
2771 def t2ISB : T2I<(outs), (ins), NoItinerary, "isb", "",
2772 [/* For disassembly only; pattern left blank */]>,
2773 Requires<[IsThumb2, HasV7]> {
2774 let Inst{31-4} = 0xf3bf8f6;
2775 let Inst{3-0} = 0b1111;
2778 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2779 InstrItinClass itin, string opc, string asm, string cstr,
2780 list<dag> pattern, bits<4> rt2 = 0b1111>
2781 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2782 let Inst{31-27} = 0b11101;
2783 let Inst{26-20} = 0b0001101;
2784 let Inst{11-8} = rt2;
2785 let Inst{7-6} = 0b01;
2786 let Inst{5-4} = opcod;
2787 let Inst{3-0} = 0b1111;
2791 let Inst{19-16} = Rn;
2792 let Inst{15-12} = Rt;
2794 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2795 InstrItinClass itin, string opc, string asm, string cstr,
2796 list<dag> pattern, bits<4> rt2 = 0b1111>
2797 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2798 let Inst{31-27} = 0b11101;
2799 let Inst{26-20} = 0b0001100;
2800 let Inst{11-8} = rt2;
2801 let Inst{7-6} = 0b01;
2802 let Inst{5-4} = opcod;
2807 let Inst{11-8} = Rd;
2808 let Inst{19-16} = Rn;
2809 let Inst{15-12} = Rt;
2812 let mayLoad = 1 in {
2813 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2814 Size4Bytes, NoItinerary, "ldrexb", "\t$Rt, [$Rn]",
2816 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2817 Size4Bytes, NoItinerary, "ldrexh", "\t$Rt, [$Rn]",
2819 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2820 Size4Bytes, NoItinerary,
2821 "ldrex", "\t$Rt, [$Rn]", "",
2823 let Inst{31-27} = 0b11101;
2824 let Inst{26-20} = 0b0000101;
2825 let Inst{11-8} = 0b1111;
2826 let Inst{7-0} = 0b00000000; // imm8 = 0
2828 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), (ins rGPR:$Rn),
2829 AddrModeNone, Size4Bytes, NoItinerary,
2830 "ldrexd", "\t$Rt, $Rt2, [$Rn]", "",
2833 let Inst{11-8} = Rt2;
2837 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2838 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2839 AddrModeNone, Size4Bytes, NoItinerary,
2840 "strexb", "\t$Rd, $Rt, [$Rn]", "", []>;
2841 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2842 AddrModeNone, Size4Bytes, NoItinerary,
2843 "strexh", "\t$Rd, $Rt, [$Rn]", "", []>;
2844 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2845 AddrModeNone, Size4Bytes, NoItinerary,
2846 "strex", "\t$Rd, $Rt, [$Rn]", "",
2848 let Inst{31-27} = 0b11101;
2849 let Inst{26-20} = 0b0000100;
2850 let Inst{7-0} = 0b00000000; // imm8 = 0
2852 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2853 (ins rGPR:$Rt, rGPR:$Rt2, rGPR:$Rn),
2854 AddrModeNone, Size4Bytes, NoItinerary,
2855 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]", "", [],
2858 let Inst{11-8} = Rt2;
2862 // Clear-Exclusive is for disassembly only.
2863 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2864 [/* For disassembly only; pattern left blank */]>,
2865 Requires<[IsARM, HasV7]> {
2866 let Inst{31-20} = 0xf3b;
2867 let Inst{15-14} = 0b10;
2869 let Inst{7-4} = 0b0010;
2872 //===----------------------------------------------------------------------===//
2876 // __aeabi_read_tp preserves the registers r1-r3.
2878 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
2879 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2880 "bl\t__aeabi_read_tp",
2881 [(set R0, ARMthread_pointer)]> {
2882 let Inst{31-27} = 0b11110;
2883 let Inst{15-14} = 0b11;
2888 //===----------------------------------------------------------------------===//
2889 // SJLJ Exception handling intrinsics
2890 // eh_sjlj_setjmp() is an instruction sequence to store the return
2891 // address and save #0 in R0 for the non-longjmp case.
2892 // Since by its nature we may be coming from some other function to get
2893 // here, and we're using the stack frame for the containing function to
2894 // save/restore registers, we can't keep anything live in regs across
2895 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2896 // when we get here from a longjmp(). We force everthing out of registers
2897 // except for our own input by listing the relevant registers in Defs. By
2898 // doing so, we also cause the prologue/epilogue code to actively preserve
2899 // all of the callee-saved resgisters, which is exactly what we want.
2900 // $val is a scratch register for our use.
2902 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2903 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2904 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2905 D31 ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2906 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2907 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2908 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2909 Requires<[IsThumb2, HasVFP2]>;
2913 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2914 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2915 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2916 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2917 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2918 Requires<[IsThumb2, NoVFP]>;
2922 //===----------------------------------------------------------------------===//
2923 // Control-Flow Instructions
2926 // FIXME: remove when we have a way to marking a MI with these properties.
2927 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2929 // FIXME: Should pc be an implicit operand like PICADD, etc?
2930 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2931 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2932 def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2933 reglist:$regs, variable_ops),
2935 "ldmia${p}.w\t$Rn!, $regs",
2940 let Inst{31-27} = 0b11101;
2941 let Inst{26-25} = 0b00;
2942 let Inst{24-23} = 0b01; // Increment After
2944 let Inst{21} = 1; // Writeback
2946 let Inst{19-16} = Rn;
2947 let Inst{15-0} = regs;
2950 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2951 let isPredicable = 1 in
2952 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2954 [(br bb:$target)]> {
2955 let Inst{31-27} = 0b11110;
2956 let Inst{15-14} = 0b10;
2960 let Inst{26} = target{19};
2961 let Inst{11} = target{18};
2962 let Inst{13} = target{17};
2963 let Inst{21-16} = target{16-11};
2964 let Inst{10-0} = target{10-0};
2967 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2968 def t2BR_JT : tPseudoInst<(outs),
2969 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
2970 SizeSpecial, IIC_Br,
2971 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
2973 // FIXME: Add a non-pc based case that can be predicated.
2974 def t2TBB_JT : tPseudoInst<(outs),
2975 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2976 SizeSpecial, IIC_Br, []>;
2978 def t2TBH_JT : tPseudoInst<(outs),
2979 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2980 SizeSpecial, IIC_Br, []>;
2982 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2983 "tbb", "\t[$Rn, $Rm]", []> {
2986 let Inst{27-20} = 0b10001101;
2987 let Inst{19-16} = Rn;
2988 let Inst{15-5} = 0b11110000000;
2989 let Inst{4} = 0; // B form
2993 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2994 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
2997 let Inst{27-20} = 0b10001101;
2998 let Inst{19-16} = Rn;
2999 let Inst{15-5} = 0b11110000000;
3000 let Inst{4} = 1; // H form
3003 } // isNotDuplicable, isIndirectBranch
3005 } // isBranch, isTerminator, isBarrier
3007 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3008 // a two-value operand where a dag node expects two operands. :(
3009 let isBranch = 1, isTerminator = 1 in
3010 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3012 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3013 let Inst{31-27} = 0b11110;
3014 let Inst{15-14} = 0b10;
3018 let Inst{25-22} = p;
3021 let Inst{26} = target{20};
3022 let Inst{11} = target{19};
3023 let Inst{13} = target{18};
3024 let Inst{21-16} = target{17-12};
3025 let Inst{10-0} = target{11-1};
3030 let Defs = [ITSTATE] in
3031 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3032 AddrModeNone, Size2Bytes, IIC_iALUx,
3033 "it$mask\t$cc", "", []> {
3034 // 16-bit instruction.
3035 let Inst{31-16} = 0x0000;
3036 let Inst{15-8} = 0b10111111;
3041 let Inst{3-0} = mask;
3044 // Branch and Exchange Jazelle -- for disassembly only
3046 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3047 [/* For disassembly only; pattern left blank */]> {
3048 let Inst{31-27} = 0b11110;
3050 let Inst{25-20} = 0b111100;
3051 let Inst{15-14} = 0b10;
3055 let Inst{19-16} = func;
3058 // Change Processor State is a system instruction -- for disassembly only.
3059 // The singleton $opt operand contains the following information:
3060 // opt{4-0} = mode from Inst{4-0}
3061 // opt{5} = changemode from Inst{17}
3062 // opt{8-6} = AIF from Inst{8-6}
3063 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3064 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
3065 [/* For disassembly only; pattern left blank */]> {
3066 let Inst{31-27} = 0b11110;
3068 let Inst{25-20} = 0b111010;
3069 let Inst{15-14} = 0b10;
3075 let Inst{4-0} = opt{4-0};
3078 let Inst{8} = opt{5};
3081 let Inst{5} = opt{6};
3084 let Inst{6} = opt{7};
3087 let Inst{7} = opt{8};
3090 let Inst{10-9} = opt{10-9};
3093 // A6.3.4 Branches and miscellaneous control
3094 // Table A6-14 Change Processor State, and hint instructions
3095 // Helper class for disassembly only.
3096 class T2I_hint<bits<8> op7_0, string opc, string asm>
3097 : T2I<(outs), (ins), NoItinerary, opc, asm,
3098 [/* For disassembly only; pattern left blank */]> {
3099 let Inst{31-20} = 0xf3a;
3100 let Inst{15-14} = 0b10;
3102 let Inst{10-8} = 0b000;
3103 let Inst{7-0} = op7_0;
3106 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3107 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3108 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3109 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3110 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3112 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
3113 [/* For disassembly only; pattern left blank */]> {
3114 let Inst{31-20} = 0xf3a;
3115 let Inst{15-14} = 0b10;
3117 let Inst{10-8} = 0b000;
3118 let Inst{7-4} = 0b1111;
3121 let Inst{3-0} = opt;
3124 // Secure Monitor Call is a system instruction -- for disassembly only
3125 // Option = Inst{19-16}
3126 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
3127 [/* For disassembly only; pattern left blank */]> {
3128 let Inst{31-27} = 0b11110;
3129 let Inst{26-20} = 0b1111111;
3130 let Inst{15-12} = 0b1000;
3133 let Inst{19-16} = opt;
3136 class T2SRS<bits<12> op31_20,
3137 dag oops, dag iops, InstrItinClass itin,
3138 string opc, string asm, list<dag> pattern>
3139 : T2I<oops, iops, itin, opc, asm, pattern> {
3140 let Inst{31-20} = op31_20{11-0};
3143 let Inst{4-0} = mode{4-0};
3146 // Store Return State is a system instruction -- for disassembly only
3147 def t2SRSDBW : T2SRS<0b111010000010,
3148 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3149 [/* For disassembly only; pattern left blank */]>;
3150 def t2SRSDB : T2SRS<0b111010000000,
3151 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3152 [/* For disassembly only; pattern left blank */]>;
3153 def t2SRSIAW : T2SRS<0b111010011010,
3154 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3155 [/* For disassembly only; pattern left blank */]>;
3156 def t2SRSIA : T2SRS<0b111010011000,
3157 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3158 [/* For disassembly only; pattern left blank */]>;
3160 // Return From Exception is a system instruction -- for disassembly only
3162 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3163 string opc, string asm, list<dag> pattern>
3164 : T2I<oops, iops, itin, opc, asm, pattern> {
3165 let Inst{31-20} = op31_20{11-0};
3168 let Inst{19-16} = Rn;
3171 def t2RFEDBW : T2RFE<0b111010000011,
3172 (outs), (ins rGPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3173 [/* For disassembly only; pattern left blank */]>;
3174 def t2RFEDB : T2RFE<0b111010000001,
3175 (outs), (ins rGPR:$Rn), NoItinerary, "rfeab", "\t$Rn",
3176 [/* For disassembly only; pattern left blank */]>;
3177 def t2RFEIAW : T2RFE<0b111010011011,
3178 (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3179 [/* For disassembly only; pattern left blank */]>;
3180 def t2RFEIA : T2RFE<0b111010011001,
3181 (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3182 [/* For disassembly only; pattern left blank */]>;
3184 //===----------------------------------------------------------------------===//
3185 // Non-Instruction Patterns
3188 // 32-bit immediate using movw + movt.
3189 // This is a single pseudo instruction to make it re-materializable.
3190 // FIXME: Remove this when we can do generalized remat.
3191 let isReMaterializable = 1, isMoveImm = 1 in
3192 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3193 [(set rGPR:$dst, (i32 imm:$src))]>,
3194 Requires<[IsThumb, HasV6T2]>;
3196 // ConstantPool, GlobalAddress, and JumpTable
3197 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3198 Requires<[IsThumb2, DontUseMovt]>;
3199 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3200 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3201 Requires<[IsThumb2, UseMovt]>;
3203 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3204 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3206 // Pseudo instruction that combines ldr from constpool and add pc. This should
3207 // be expanded into two instructions late to allow if-conversion and
3209 let canFoldAsLoad = 1, isReMaterializable = 1 in
3210 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3212 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3214 Requires<[IsThumb2]>;
3216 //===----------------------------------------------------------------------===//
3217 // Move between special register and ARM core register -- for disassembly only
3220 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3221 dag oops, dag iops, InstrItinClass itin,
3222 string opc, string asm, list<dag> pattern>
3223 : T2I<oops, iops, itin, opc, asm, pattern> {
3224 let Inst{31-20} = op31_20{11-0};
3225 let Inst{15-14} = op15_14{1-0};
3226 let Inst{12} = op12{0};
3229 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3230 dag oops, dag iops, InstrItinClass itin,
3231 string opc, string asm, list<dag> pattern>
3232 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3234 let Inst{11-8} = Rd;
3237 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3238 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3239 [/* For disassembly only; pattern left blank */]>;
3240 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3241 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3242 [/* For disassembly only; pattern left blank */]>;
3244 class T2MSR<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3245 dag oops, dag iops, InstrItinClass itin,
3246 string opc, string asm, list<dag> pattern>
3247 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3250 let Inst{19-16} = Rn;
3251 let Inst{11-8} = mask;
3254 def t2MSR : T2MSR<0b111100111000, 0b10, 0,
3255 (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3257 [/* For disassembly only; pattern left blank */]>;
3258 def t2MSRsys : T2MSR<0b111100111001, 0b10, 0,
3259 (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3261 [/* For disassembly only; pattern left blank */]>;