1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectThumb2ShifterOperandReg",
19 let PrintMethod = "printSOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
24 // described for t2_so_imm def below.
25 def t2_so_imm_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(
27 ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
30 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
31 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
32 return CurDAG->getTargetConstant(
33 ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
36 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
37 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(
39 ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
42 // t2_so_imm - Match a 32-bit immediate operand, which is an
43 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
44 // immediate splatted into multiple bytes of the word. t2_so_imm values are
45 // represented in the imm field in the same 12-bit form that they are encoded
46 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
47 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
48 def t2_so_imm : Operand<i32>,
50 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
51 }], t2_so_imm_XFORM> {
52 let PrintMethod = "printT2SOImmOperand";
55 // t2_so_imm_not - Match an immediate that is a complement
57 def t2_so_imm_not : Operand<i32>,
59 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60 }], t2_so_imm_not_XFORM> {
61 let PrintMethod = "printT2SOImmOperand";
64 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65 def t2_so_imm_neg : Operand<i32>,
67 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
68 }], t2_so_imm_neg_XFORM> {
69 let PrintMethod = "printT2SOImmOperand";
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
88 def imm0_65535 : PatLeaf<(i32 imm), [{
89 return (uint32_t)N->getZExtValue() < 65536;
93 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
95 def bf_inv_mask_imm : Operand<i32>,
97 uint32_t v = (uint32_t)N->getZExtValue();
100 // naive checker. should do better, but simple is best for now since it's
101 // more likely to be correct.
102 while (v & 1) v >>= 1; // shift off the leading 1's
105 while (!(v & 1)) v >>=1; // shift off the mask
106 while (v & 1) v >>= 1; // shift off the trailing 1's
108 // if this is a mask for clearing a bitfield, what's left should be zero.
111 let PrintMethod = "printBitfieldInvMaskImmOperand";
114 /// Split a 32-bit immediate into two 16 bit parts.
115 def t2_lo16 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
120 def t2_hi16 : SDNodeXForm<imm, [{
121 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
124 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
125 // Returns true if all low 16-bits are 0.
126 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
129 //===----------------------------------------------------------------------===//
130 // Thumb2 to cover the functionality of the ARM instruction set.
133 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
134 /// unary operation that produces a value. These are predicable and can be
135 /// changed to modify CPSR.
136 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
138 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
140 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
141 let isAsCheapAsAMove = Cheap;
142 let isReMaterializable = ReMat;
145 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
147 [(set GPR:$dst, (opnode GPR:$src))]>;
149 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
151 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
154 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
155 // binary operation that produces a value. These are predicable and can be
156 /// changed to modify CPSR.
157 multiclass T2I_bin_irs<string opc, PatFrag opnode> {
159 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
160 opc, " $dst, $lhs, $rhs",
161 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
163 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
164 opc, " $dst, $lhs, $rhs",
165 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
167 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
168 opc, " $dst, $lhs, $rhs",
169 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
172 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
173 /// reversed. It doesn't define the 'rr' form since it's handled by its
174 /// T2I_bin_irs counterpart.
175 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
177 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
178 opc, " $dst, $rhs, $lhs",
179 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
181 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
182 opc, " $dst, $rhs, $lhs",
183 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
186 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
187 /// instruction modifies the CPSR register.
188 let Defs = [CPSR] in {
189 multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
191 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
192 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
193 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
195 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
196 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
197 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
199 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
200 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
201 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
205 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
206 /// patterns for a binary operation that produces a value.
207 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode> {
209 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
210 opc, " $dst, $lhs, $rhs",
211 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
213 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
214 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
215 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
217 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
218 opc, " $dst, $lhs, $rhs",
219 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
221 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
222 opc, " $dst, $lhs, $rhs",
223 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
226 /// T2I_bin_cs_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
227 /// binary operation that produces a value and use and define the carry bit.
228 /// It's not predicable.
229 let Defs = [CPSR], Uses = [CPSR] in {
230 multiclass T2I_bin_cs_irs<string opc, PatFrag opnode> {
232 def ri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
233 !strconcat(opc, "s $dst, $lhs, $rhs"),
234 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
236 def rr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
237 !strconcat(opc, "s $dst, $lhs, $rhs"),
238 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
240 def rs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
241 !strconcat(opc, "s $dst, $lhs, $rhs"),
242 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
246 /// T2I_rbin_cs_is - Same as T2I_bin_cs_irs except the order of operands are
247 /// reversed. It doesn't define the 'rr' form since it's handled by its
248 /// T2I_bin_cs_irs counterpart.
249 let Defs = [CPSR], Uses = [CPSR] in {
250 multiclass T2I_rbin_cs_is<string opc, PatFrag opnode> {
252 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
253 !strconcat(opc, "s $dst, $rhs, $lhs"),
254 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
256 def rr : T2XI<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
257 !strconcat(opc, "s $dst, $rhs, $lhs"),
258 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
260 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
261 !strconcat(opc, "s $dst, $rhs, $lhs"),
262 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
266 /// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
267 /// reversed. It doesn't define the 'rr' form since it's handled by its
268 /// T2I_bin_s_irs counterpart.
269 let Defs = [CPSR] in {
270 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
272 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
273 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
274 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
276 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
277 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
278 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
282 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
283 // rotate operation that produces a value.
284 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
286 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
287 opc, " $dst, $lhs, $rhs",
288 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
290 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
291 opc, " $dst, $lhs, $rhs",
292 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
295 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
296 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
297 /// a explicit result, only implicitly set CPSR.
298 let Uses = [CPSR] in {
299 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
301 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
303 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
305 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
307 [(opnode GPR:$lhs, GPR:$rhs)]>;
309 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
311 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
315 //===----------------------------------------------------------------------===//
316 // Miscellaneous Instructions.
319 let isNotDuplicable = 1 in
320 def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
321 "$cp:\n\tadd $dst, pc",
322 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
325 // LEApcrel - Load a pc-relative address into a register without offending the
327 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
328 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
329 "${:private}PCRELL${:uid}+8))\n"),
330 !strconcat("${:private}PCRELL${:uid}:\n\t",
331 "add$p $dst, pc, #PCRELV${:uid}")),
334 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
335 (ins i32imm:$label, i32imm:$id, pred:$p),
336 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
337 "${:private}PCRELL${:uid}+8))\n"),
338 !strconcat("${:private}PCRELL${:uid}:\n\t",
339 "add$p $dst, pc, #PCRELV${:uid}")),
342 // ADD rd, sp, #so_imm
343 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
344 "add $dst, $sp, $imm",
347 // ADD rd, sp, #imm12
348 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
349 "addw $dst, $sp, $imm",
352 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
353 "addw $dst, $sp, $rhs",
357 //===----------------------------------------------------------------------===//
358 // Move Instructions.
361 let neverHasSideEffects = 1 in
362 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
363 "mov", " $dst, $src", []>;
365 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
366 def t2MOVi16 : T2sI<(outs GPR:$dst), (ins i32imm:$src),
367 "movw", " $dst, $src",
368 [(set GPR:$dst, imm0_65535:$src)]>;
370 // FIXME: Also available in ARM mode.
371 let Constraints = "$src = $dst" in
372 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
373 "movt", " $dst, $imm",
375 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
377 //===----------------------------------------------------------------------===//
378 // Arithmetic Instructions.
381 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
382 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
384 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
385 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
386 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
388 // FIXME: predication support
389 defm t2ADC : T2I_bin_cs_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
390 defm t2SBC : T2I_bin_cs_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
393 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
394 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
395 defm t2RSC : T2I_rbin_cs_is<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
397 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
398 def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
399 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
400 def : Thumb2Pat<(add GPR:$src, imm0_4095_neg:$imm),
401 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
404 //===----------------------------------------------------------------------===//
405 // Shift and rotate Instructions.
408 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
409 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
410 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
411 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
413 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
414 "mov", " $dst, $src, rrx",
415 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
417 //===----------------------------------------------------------------------===//
418 // Bitwise Instructions.
421 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
422 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
423 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
425 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
427 def : Thumb2Pat<(and GPR:$src, t2_so_imm_not:$imm),
428 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
430 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
432 def : Thumb2Pat<(or GPR:$src, t2_so_imm_not:$imm),
433 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
435 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
437 // A8.6.17 BFC - Bitfield clear
438 // FIXME: Also available in ARM mode.
439 let Constraints = "$src = $dst" in
440 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
441 "bfc", " $dst, $imm",
442 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
444 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
446 //===----------------------------------------------------------------------===//
447 // Multiply Instructions.
449 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
450 "mul", " $dst, $a, $b",
451 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
453 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
454 "mla", " $dst, $a, $b, $c",
455 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
457 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
458 "mls", " $dst, $a, $b, $c",
459 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
461 // FIXME: SMULL, etc.
463 //===----------------------------------------------------------------------===//
464 // Misc. Arithmetic Instructions.
470 // FIXME not firing? but ARM version does...
471 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
472 "clz", " $dst, $src",
473 [(set GPR:$dst, (ctlz GPR:$src))]>;
475 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
476 "rev", " $dst, $src",
477 [(set GPR:$dst, (bswap GPR:$src))]>;
479 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
480 "rev16", " $dst, $src",
482 (or (and (srl GPR:$src, (i32 8)), 0xFF),
483 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
484 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
485 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
490 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
491 "revsh", " $dst, $src",
494 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
495 (shl GPR:$src, (i32 8))), i16))]>;
499 //===----------------------------------------------------------------------===//
500 // Comparison Instructions...
503 defm t2CMP : T2I_cmp_is<"cmp",
504 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
505 defm t2CMPnz : T2I_cmp_is<"cmp",
506 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
508 defm t2CMN : T2I_cmp_is<"cmn",
509 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
510 defm t2CMNnz : T2I_cmp_is<"cmn",
511 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
513 def : Thumb2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
514 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
516 def : Thumb2Pat<(ARMcmpNZ GPR:$src, t2_so_imm_neg:$imm),
517 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
519 // FIXME: TST, TEQ, etc.
521 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
522 // Short range conditional branch. Looks awesome for loops. Need to figure
523 // out how to use this one.
525 // FIXME: Conditional moves
528 //===----------------------------------------------------------------------===//
529 // Non-Instruction Patterns
532 // ConstantPool, GlobalAddress, and JumpTable
533 def : Thumb2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
534 def : Thumb2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
535 def : Thumb2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
536 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
538 // Large immediate handling.
540 def : Thumb2Pat<(i32 imm:$src),
541 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)),
542 (t2_hi16 imm:$src))>;