1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops rGPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]>;
56 // t2_so_imm_not - Match an immediate that is a complement
58 def t2_so_imm_not : Operand<i32>,
60 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
61 }], t2_so_imm_not_XFORM>;
63 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
64 def t2_so_imm_neg : Operand<i32>,
66 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
67 }], t2_so_imm_neg_XFORM>;
69 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
70 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
71 // to get the first/second pieces.
72 def t2_so_imm2part : Operand<i32>,
74 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
78 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
79 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
80 return CurDAG->getTargetConstant(V, MVT::i32);
83 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
84 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
85 return CurDAG->getTargetConstant(V, MVT::i32);
88 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
89 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
93 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
94 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
95 return CurDAG->getTargetConstant(V, MVT::i32);
98 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
99 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
100 return CurDAG->getTargetConstant(V, MVT::i32);
103 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
104 def imm1_31 : PatLeaf<(i32 imm), [{
105 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
108 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
109 def imm0_4095 : Operand<i32>,
110 PatLeaf<(i32 imm), [{
111 return (uint32_t)N->getZExtValue() < 4096;
114 def imm0_4095_neg : PatLeaf<(i32 imm), [{
115 return (uint32_t)(-N->getZExtValue()) < 4096;
118 def imm0_255_neg : PatLeaf<(i32 imm), [{
119 return (uint32_t)(-N->getZExtValue()) < 255;
122 def imm0_255_not : PatLeaf<(i32 imm), [{
123 return (uint32_t)(~N->getZExtValue()) < 255;
126 // Define Thumb2 specific addressing modes.
128 // t2addrmode_imm12 := reg + imm12
129 def t2addrmode_imm12 : Operand<i32>,
130 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
131 let PrintMethod = "printT2AddrModeImm12Operand";
132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
135 // t2addrmode_imm8 := reg +/- imm8
136 def t2addrmode_imm8 : Operand<i32>,
137 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
138 let PrintMethod = "printT2AddrModeImm8Operand";
139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
142 def t2am_imm8_offset : Operand<i32>,
143 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
144 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
147 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
148 def t2addrmode_imm8s4 : Operand<i32>,
149 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
150 let PrintMethod = "printT2AddrModeImm8s4Operand";
151 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
154 def t2am_imm8s4_offset : Operand<i32> {
155 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
158 // t2addrmode_so_reg := reg + (reg << imm2)
159 def t2addrmode_so_reg : Operand<i32>,
160 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
161 let PrintMethod = "printT2AddrModeSoRegOperand";
162 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
166 //===----------------------------------------------------------------------===//
167 // Multiclass helpers...
170 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
171 /// unary operation that produces a value. These are predicable and can be
172 /// changed to modify CPSR.
173 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
174 bit Cheap = 0, bit ReMat = 0> {
176 def i : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
178 [(set rGPR:$dst, (opnode t2_so_imm:$src))]> {
179 let isAsCheapAsAMove = Cheap;
180 let isReMaterializable = ReMat;
181 let Inst{31-27} = 0b11110;
183 let Inst{24-21} = opcod;
184 let Inst{20} = ?; // The S bit.
185 let Inst{19-16} = 0b1111; // Rn
189 def r : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVr,
190 opc, ".w\t$dst, $src",
191 [(set rGPR:$dst, (opnode rGPR:$src))]> {
192 let Inst{31-27} = 0b11101;
193 let Inst{26-25} = 0b01;
194 let Inst{24-21} = opcod;
195 let Inst{20} = ?; // The S bit.
196 let Inst{19-16} = 0b1111; // Rn
197 let Inst{14-12} = 0b000; // imm3
198 let Inst{7-6} = 0b00; // imm2
199 let Inst{5-4} = 0b00; // type
202 def s : T2sI<(outs rGPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
203 opc, ".w\t$dst, $src",
204 [(set rGPR:$dst, (opnode t2_so_reg:$src))]> {
205 let Inst{31-27} = 0b11101;
206 let Inst{26-25} = 0b01;
207 let Inst{24-21} = opcod;
208 let Inst{20} = ?; // The S bit.
209 let Inst{19-16} = 0b1111; // Rn
213 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
214 /// binary operation that produces a value. These are predicable and can be
215 /// changed to modify CPSR.
216 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
217 bit Commutable = 0, string wide =""> {
219 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
220 opc, "\t$dst, $lhs, $rhs",
221 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
222 let Inst{31-27} = 0b11110;
224 let Inst{24-21} = opcod;
225 let Inst{20} = ?; // The S bit.
229 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
230 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
231 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
232 let isCommutable = Commutable;
233 let Inst{31-27} = 0b11101;
234 let Inst{26-25} = 0b01;
235 let Inst{24-21} = opcod;
236 let Inst{20} = ?; // The S bit.
237 let Inst{14-12} = 0b000; // imm3
238 let Inst{7-6} = 0b00; // imm2
239 let Inst{5-4} = 0b00; // type
242 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
243 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
244 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
245 let Inst{31-27} = 0b11101;
246 let Inst{26-25} = 0b01;
247 let Inst{24-21} = opcod;
248 let Inst{20} = ?; // The S bit.
252 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
253 // the ".w" prefix to indicate that they are wide.
254 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
255 bit Commutable = 0> :
256 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
258 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
259 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
260 /// it is equivalent to the T2I_bin_irs counterpart.
261 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
263 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
264 opc, ".w\t$dst, $rhs, $lhs",
265 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
266 let Inst{31-27} = 0b11110;
268 let Inst{24-21} = opcod;
269 let Inst{20} = ?; // The S bit.
273 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr,
274 opc, "\t$dst, $rhs, $lhs",
275 [/* For disassembly only; pattern left blank */]> {
276 let Inst{31-27} = 0b11101;
277 let Inst{26-25} = 0b01;
278 let Inst{24-21} = opcod;
279 let Inst{20} = ?; // The S bit.
280 let Inst{14-12} = 0b000; // imm3
281 let Inst{7-6} = 0b00; // imm2
282 let Inst{5-4} = 0b00; // type
285 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
286 opc, "\t$dst, $rhs, $lhs",
287 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
288 let Inst{31-27} = 0b11101;
289 let Inst{26-25} = 0b01;
290 let Inst{24-21} = opcod;
291 let Inst{20} = ?; // The S bit.
295 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
296 /// instruction modifies the CPSR register.
297 let Defs = [CPSR] in {
298 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
299 bit Commutable = 0> {
301 def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
302 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
303 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
304 let Inst{31-27} = 0b11110;
306 let Inst{24-21} = opcod;
307 let Inst{20} = 1; // The S bit.
311 def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
312 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
313 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
314 let isCommutable = Commutable;
315 let Inst{31-27} = 0b11101;
316 let Inst{26-25} = 0b01;
317 let Inst{24-21} = opcod;
318 let Inst{20} = 1; // The S bit.
319 let Inst{14-12} = 0b000; // imm3
320 let Inst{7-6} = 0b00; // imm2
321 let Inst{5-4} = 0b00; // type
324 def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
325 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
326 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
327 let Inst{31-27} = 0b11101;
328 let Inst{26-25} = 0b01;
329 let Inst{24-21} = opcod;
330 let Inst{20} = 1; // The S bit.
335 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
336 /// patterns for a binary operation that produces a value.
337 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
338 bit Commutable = 0> {
340 def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
341 opc, ".w\t$dst, $lhs, $rhs",
342 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
343 let Inst{31-27} = 0b11110;
346 let Inst{23-21} = op23_21;
347 let Inst{20} = 0; // The S bit.
351 def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
352 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
353 [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
354 let Inst{31-27} = 0b11110;
357 let Inst{23-21} = op23_21;
358 let Inst{20} = 0; // The S bit.
362 def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
363 opc, ".w\t$dst, $lhs, $rhs",
364 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
365 let isCommutable = Commutable;
366 let Inst{31-27} = 0b11101;
367 let Inst{26-25} = 0b01;
369 let Inst{23-21} = op23_21;
370 let Inst{20} = 0; // The S bit.
371 let Inst{14-12} = 0b000; // imm3
372 let Inst{7-6} = 0b00; // imm2
373 let Inst{5-4} = 0b00; // type
376 def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
377 opc, ".w\t$dst, $lhs, $rhs",
378 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
379 let Inst{31-27} = 0b11101;
380 let Inst{26-25} = 0b01;
382 let Inst{23-21} = op23_21;
383 let Inst{20} = 0; // The S bit.
387 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
388 /// for a binary operation that produces a value and use the carry
389 /// bit. It's not predicable.
390 let Uses = [CPSR] in {
391 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
392 bit Commutable = 0> {
394 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
395 opc, "\t$dst, $lhs, $rhs",
396 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
397 Requires<[IsThumb2]> {
398 let Inst{31-27} = 0b11110;
400 let Inst{24-21} = opcod;
401 let Inst{20} = 0; // The S bit.
405 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
406 opc, ".w\t$dst, $lhs, $rhs",
407 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
408 Requires<[IsThumb2]> {
409 let isCommutable = Commutable;
410 let Inst{31-27} = 0b11101;
411 let Inst{26-25} = 0b01;
412 let Inst{24-21} = opcod;
413 let Inst{20} = 0; // The S bit.
414 let Inst{14-12} = 0b000; // imm3
415 let Inst{7-6} = 0b00; // imm2
416 let Inst{5-4} = 0b00; // type
419 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
420 opc, ".w\t$dst, $lhs, $rhs",
421 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
422 Requires<[IsThumb2]> {
423 let Inst{31-27} = 0b11101;
424 let Inst{26-25} = 0b01;
425 let Inst{24-21} = opcod;
426 let Inst{20} = 0; // The S bit.
430 // Carry setting variants
431 let Defs = [CPSR] in {
432 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
433 bit Commutable = 0> {
435 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
436 opc, "\t$dst, $lhs, $rhs",
437 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
438 Requires<[IsThumb2]> {
439 let Inst{31-27} = 0b11110;
441 let Inst{24-21} = opcod;
442 let Inst{20} = 1; // The S bit.
446 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
447 opc, ".w\t$dst, $lhs, $rhs",
448 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
449 Requires<[IsThumb2]> {
450 let isCommutable = Commutable;
451 let Inst{31-27} = 0b11101;
452 let Inst{26-25} = 0b01;
453 let Inst{24-21} = opcod;
454 let Inst{20} = 1; // The S bit.
455 let Inst{14-12} = 0b000; // imm3
456 let Inst{7-6} = 0b00; // imm2
457 let Inst{5-4} = 0b00; // type
460 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
461 opc, ".w\t$dst, $lhs, $rhs",
462 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
463 Requires<[IsThumb2]> {
464 let Inst{31-27} = 0b11101;
465 let Inst{26-25} = 0b01;
466 let Inst{24-21} = opcod;
467 let Inst{20} = 1; // The S bit.
473 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
474 /// version is not needed since this is only for codegen.
475 let Defs = [CPSR] in {
476 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
478 def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
479 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
480 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
481 let Inst{31-27} = 0b11110;
483 let Inst{24-21} = opcod;
484 let Inst{20} = 1; // The S bit.
488 def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
489 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
490 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
491 let Inst{31-27} = 0b11101;
492 let Inst{26-25} = 0b01;
493 let Inst{24-21} = opcod;
494 let Inst{20} = 1; // The S bit.
499 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
500 // rotate operation that produces a value.
501 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
503 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
504 opc, ".w\t$dst, $lhs, $rhs",
505 [(set rGPR:$dst, (opnode rGPR:$lhs, imm1_31:$rhs))]> {
506 let Inst{31-27} = 0b11101;
507 let Inst{26-21} = 0b010010;
508 let Inst{19-16} = 0b1111; // Rn
509 let Inst{5-4} = opcod;
512 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iMOVsr,
513 opc, ".w\t$dst, $lhs, $rhs",
514 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
515 let Inst{31-27} = 0b11111;
516 let Inst{26-23} = 0b0100;
517 let Inst{22-21} = opcod;
518 let Inst{15-12} = 0b1111;
519 let Inst{7-4} = 0b0000;
523 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
524 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
525 /// a explicit result, only implicitly set CPSR.
526 let isCompare = 1, Defs = [CPSR] in {
527 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
529 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
530 opc, ".w\t$lhs, $rhs",
531 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
532 let Inst{31-27} = 0b11110;
534 let Inst{24-21} = opcod;
535 let Inst{20} = 1; // The S bit.
537 let Inst{11-8} = 0b1111; // Rd
540 def rr : T2I<(outs), (ins GPR:$lhs, rGPR:$rhs), IIC_iCMPr,
541 opc, ".w\t$lhs, $rhs",
542 [(opnode GPR:$lhs, rGPR:$rhs)]> {
543 let Inst{31-27} = 0b11101;
544 let Inst{26-25} = 0b01;
545 let Inst{24-21} = opcod;
546 let Inst{20} = 1; // The S bit.
547 let Inst{14-12} = 0b000; // imm3
548 let Inst{11-8} = 0b1111; // Rd
549 let Inst{7-6} = 0b00; // imm2
550 let Inst{5-4} = 0b00; // type
553 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
554 opc, ".w\t$lhs, $rhs",
555 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
556 let Inst{31-27} = 0b11101;
557 let Inst{26-25} = 0b01;
558 let Inst{24-21} = opcod;
559 let Inst{20} = 1; // The S bit.
560 let Inst{11-8} = 0b1111; // Rd
565 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
566 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
567 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
568 opc, ".w\t$dst, $addr",
569 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
570 let Inst{31-27} = 0b11111;
571 let Inst{26-25} = 0b00;
572 let Inst{24} = signed;
574 let Inst{22-21} = opcod;
575 let Inst{20} = 1; // load
577 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
578 opc, "\t$dst, $addr",
579 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
580 let Inst{31-27} = 0b11111;
581 let Inst{26-25} = 0b00;
582 let Inst{24} = signed;
584 let Inst{22-21} = opcod;
585 let Inst{20} = 1; // load
587 // Offset: index==TRUE, wback==FALSE
588 let Inst{10} = 1; // The P bit.
589 let Inst{8} = 0; // The W bit.
591 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
592 opc, ".w\t$dst, $addr",
593 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
594 let Inst{31-27} = 0b11111;
595 let Inst{26-25} = 0b00;
596 let Inst{24} = signed;
598 let Inst{22-21} = opcod;
599 let Inst{20} = 1; // load
600 let Inst{11-6} = 0b000000;
602 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
603 opc, ".w\t$dst, $addr",
604 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
605 let isReMaterializable = 1;
606 let Inst{31-27} = 0b11111;
607 let Inst{26-25} = 0b00;
608 let Inst{24} = signed;
609 let Inst{23} = ?; // add = (U == '1')
610 let Inst{22-21} = opcod;
611 let Inst{20} = 1; // load
612 let Inst{19-16} = 0b1111; // Rn
616 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
617 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
618 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
619 opc, ".w\t$src, $addr",
620 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
621 let Inst{31-27} = 0b11111;
622 let Inst{26-23} = 0b0001;
623 let Inst{22-21} = opcod;
624 let Inst{20} = 0; // !load
626 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
627 opc, "\t$src, $addr",
628 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
629 let Inst{31-27} = 0b11111;
630 let Inst{26-23} = 0b0000;
631 let Inst{22-21} = opcod;
632 let Inst{20} = 0; // !load
634 // Offset: index==TRUE, wback==FALSE
635 let Inst{10} = 1; // The P bit.
636 let Inst{8} = 0; // The W bit.
638 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
639 opc, ".w\t$src, $addr",
640 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
641 let Inst{31-27} = 0b11111;
642 let Inst{26-23} = 0b0000;
643 let Inst{22-21} = opcod;
644 let Inst{20} = 0; // !load
645 let Inst{11-6} = 0b000000;
649 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
650 /// register and one whose operand is a register rotated by 8/16/24.
651 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
652 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
653 opc, ".w\t$dst, $src",
654 [(set rGPR:$dst, (opnode rGPR:$src))]> {
655 let Inst{31-27} = 0b11111;
656 let Inst{26-23} = 0b0100;
657 let Inst{22-20} = opcod;
658 let Inst{19-16} = 0b1111; // Rn
659 let Inst{15-12} = 0b1111;
661 let Inst{5-4} = 0b00; // rotate
663 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
664 opc, ".w\t$dst, $src, ror $rot",
665 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]> {
666 let Inst{31-27} = 0b11111;
667 let Inst{26-23} = 0b0100;
668 let Inst{22-20} = opcod;
669 let Inst{19-16} = 0b1111; // Rn
670 let Inst{15-12} = 0b1111;
672 let Inst{5-4} = {?,?}; // rotate
676 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
677 multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
678 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
680 [(set rGPR:$dst, (opnode rGPR:$src))]>,
681 Requires<[HasT2ExtractPack]> {
682 let Inst{31-27} = 0b11111;
683 let Inst{26-23} = 0b0100;
684 let Inst{22-20} = opcod;
685 let Inst{19-16} = 0b1111; // Rn
686 let Inst{15-12} = 0b1111;
688 let Inst{5-4} = 0b00; // rotate
690 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
691 opc, "\t$dst, $src, ror $rot",
692 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>,
693 Requires<[HasT2ExtractPack]> {
694 let Inst{31-27} = 0b11111;
695 let Inst{26-23} = 0b0100;
696 let Inst{22-20} = opcod;
697 let Inst{19-16} = 0b1111; // Rn
698 let Inst{15-12} = 0b1111;
700 let Inst{5-4} = {?,?}; // rotate
704 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
706 multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> {
707 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
708 opc, "\t$dst, $src", []> {
709 let Inst{31-27} = 0b11111;
710 let Inst{26-23} = 0b0100;
711 let Inst{22-20} = opcod;
712 let Inst{19-16} = 0b1111; // Rn
713 let Inst{15-12} = 0b1111;
715 let Inst{5-4} = 0b00; // rotate
717 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
718 opc, "\t$dst, $src, ror $rot", []> {
719 let Inst{31-27} = 0b11111;
720 let Inst{26-23} = 0b0100;
721 let Inst{22-20} = opcod;
722 let Inst{19-16} = 0b1111; // Rn
723 let Inst{15-12} = 0b1111;
725 let Inst{5-4} = {?,?}; // rotate
729 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
730 /// register and one whose operand is a register rotated by 8/16/24.
731 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
732 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
733 opc, "\t$dst, $LHS, $RHS",
734 [(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>,
735 Requires<[HasT2ExtractPack]> {
736 let Inst{31-27} = 0b11111;
737 let Inst{26-23} = 0b0100;
738 let Inst{22-20} = opcod;
739 let Inst{15-12} = 0b1111;
741 let Inst{5-4} = 0b00; // rotate
743 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
744 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
745 [(set rGPR:$dst, (opnode rGPR:$LHS,
746 (rotr rGPR:$RHS, rot_imm:$rot)))]>,
747 Requires<[HasT2ExtractPack]> {
748 let Inst{31-27} = 0b11111;
749 let Inst{26-23} = 0b0100;
750 let Inst{22-20} = opcod;
751 let Inst{15-12} = 0b1111;
753 let Inst{5-4} = {?,?}; // rotate
757 // DO variant - disassembly only, no pattern
759 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
760 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
761 opc, "\t$dst, $LHS, $RHS", []> {
762 let Inst{31-27} = 0b11111;
763 let Inst{26-23} = 0b0100;
764 let Inst{22-20} = opcod;
765 let Inst{15-12} = 0b1111;
767 let Inst{5-4} = 0b00; // rotate
769 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
770 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
771 let Inst{31-27} = 0b11111;
772 let Inst{26-23} = 0b0100;
773 let Inst{22-20} = opcod;
774 let Inst{15-12} = 0b1111;
776 let Inst{5-4} = {?,?}; // rotate
780 //===----------------------------------------------------------------------===//
782 //===----------------------------------------------------------------------===//
784 //===----------------------------------------------------------------------===//
785 // Miscellaneous Instructions.
788 // LEApcrel - Load a pc-relative address into a register without offending the
790 let neverHasSideEffects = 1 in {
791 let isReMaterializable = 1 in
792 def t2LEApcrel : T2XI<(outs rGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
793 "adr${p}.w\t$dst, #$label", []> {
794 let Inst{31-27} = 0b11110;
795 let Inst{25-24} = 0b10;
796 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
799 let Inst{19-16} = 0b1111; // Rn
802 } // neverHasSideEffects
803 def t2LEApcrelJT : T2XI<(outs rGPR:$dst),
804 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
805 "adr${p}.w\t$dst, #${label}_${id}", []> {
806 let Inst{31-27} = 0b11110;
807 let Inst{25-24} = 0b10;
808 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
811 let Inst{19-16} = 0b1111; // Rn
815 // ADD r, sp, {so_imm|i12}
816 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
817 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
818 let Inst{31-27} = 0b11110;
820 let Inst{24-21} = 0b1000;
821 let Inst{20} = ?; // The S bit.
822 let Inst{19-16} = 0b1101; // Rn = sp
825 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
826 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
827 let Inst{31-27} = 0b11110;
829 let Inst{24-21} = 0b0000;
830 let Inst{20} = 0; // The S bit.
831 let Inst{19-16} = 0b1101; // Rn = sp
836 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
837 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
838 let Inst{31-27} = 0b11101;
839 let Inst{26-25} = 0b01;
840 let Inst{24-21} = 0b1000;
841 let Inst{20} = ?; // The S bit.
842 let Inst{19-16} = 0b1101; // Rn = sp
846 // SUB r, sp, {so_imm|i12}
847 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
848 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
849 let Inst{31-27} = 0b11110;
851 let Inst{24-21} = 0b1101;
852 let Inst{20} = ?; // The S bit.
853 let Inst{19-16} = 0b1101; // Rn = sp
856 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
857 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
858 let Inst{31-27} = 0b11110;
860 let Inst{24-21} = 0b0101;
861 let Inst{20} = 0; // The S bit.
862 let Inst{19-16} = 0b1101; // Rn = sp
867 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
869 "sub", "\t$dst, $sp, $rhs", []> {
870 let Inst{31-27} = 0b11101;
871 let Inst{26-25} = 0b01;
872 let Inst{24-21} = 0b1101;
873 let Inst{20} = ?; // The S bit.
874 let Inst{19-16} = 0b1101; // Rn = sp
878 // Signed and unsigned division on v7-M
879 def t2SDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
880 "sdiv", "\t$dst, $a, $b",
881 [(set rGPR:$dst, (sdiv rGPR:$a, rGPR:$b))]>,
882 Requires<[HasDivide]> {
883 let Inst{31-27} = 0b11111;
884 let Inst{26-21} = 0b011100;
886 let Inst{15-12} = 0b1111;
887 let Inst{7-4} = 0b1111;
890 def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
891 "udiv", "\t$dst, $a, $b",
892 [(set rGPR:$dst, (udiv rGPR:$a, rGPR:$b))]>,
893 Requires<[HasDivide]> {
894 let Inst{31-27} = 0b11111;
895 let Inst{26-21} = 0b011101;
897 let Inst{15-12} = 0b1111;
898 let Inst{7-4} = 0b1111;
901 //===----------------------------------------------------------------------===//
902 // Load / store Instructions.
906 let canFoldAsLoad = 1, isReMaterializable = 1 in
907 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
909 // Loads with zero extension
910 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
911 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
913 // Loads with sign extension
914 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
915 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
917 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
919 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
920 (ins t2addrmode_imm8s4:$addr),
921 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
922 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
923 (ins i32imm:$addr), IIC_iLoadi,
924 "ldrd", "\t$dst1, $addr", []> {
925 let Inst{19-16} = 0b1111; // Rn
927 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
929 // zextload i1 -> zextload i8
930 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
931 (t2LDRBi12 t2addrmode_imm12:$addr)>;
932 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
933 (t2LDRBi8 t2addrmode_imm8:$addr)>;
934 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
935 (t2LDRBs t2addrmode_so_reg:$addr)>;
936 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
937 (t2LDRBpci tconstpool:$addr)>;
939 // extload -> zextload
940 // FIXME: Reduce the number of patterns by legalizing extload to zextload
942 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
943 (t2LDRBi12 t2addrmode_imm12:$addr)>;
944 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
945 (t2LDRBi8 t2addrmode_imm8:$addr)>;
946 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
947 (t2LDRBs t2addrmode_so_reg:$addr)>;
948 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
949 (t2LDRBpci tconstpool:$addr)>;
951 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
952 (t2LDRBi12 t2addrmode_imm12:$addr)>;
953 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
954 (t2LDRBi8 t2addrmode_imm8:$addr)>;
955 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
956 (t2LDRBs t2addrmode_so_reg:$addr)>;
957 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
958 (t2LDRBpci tconstpool:$addr)>;
960 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
961 (t2LDRHi12 t2addrmode_imm12:$addr)>;
962 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
963 (t2LDRHi8 t2addrmode_imm8:$addr)>;
964 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
965 (t2LDRHs t2addrmode_so_reg:$addr)>;
966 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
967 (t2LDRHpci tconstpool:$addr)>;
969 // FIXME: The destination register of the loads and stores can't be PC, but
970 // can be SP. We need another regclass (similar to rGPR) to represent
971 // that. Not a pressing issue since these are selected manually,
975 let mayLoad = 1, neverHasSideEffects = 1 in {
976 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
977 (ins t2addrmode_imm8:$addr),
978 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
979 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
982 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
983 (ins GPR:$base, t2am_imm8_offset:$offset),
984 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
985 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
988 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
989 (ins t2addrmode_imm8:$addr),
990 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
991 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
993 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
994 (ins GPR:$base, t2am_imm8_offset:$offset),
995 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
996 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
999 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1000 (ins t2addrmode_imm8:$addr),
1001 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1002 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
1004 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1005 (ins GPR:$base, t2am_imm8_offset:$offset),
1006 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1007 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
1010 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1011 (ins t2addrmode_imm8:$addr),
1012 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1013 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
1015 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1016 (ins GPR:$base, t2am_imm8_offset:$offset),
1017 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1018 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1021 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1022 (ins t2addrmode_imm8:$addr),
1023 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1024 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1026 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1027 (ins GPR:$base, t2am_imm8_offset:$offset),
1028 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1029 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1031 } // mayLoad = 1, neverHasSideEffects = 1
1033 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1034 // for disassembly only.
1035 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1036 class T2IldT<bit signed, bits<2> type, string opc>
1037 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
1038 "\t$dst, $addr", []> {
1039 let Inst{31-27} = 0b11111;
1040 let Inst{26-25} = 0b00;
1041 let Inst{24} = signed;
1043 let Inst{22-21} = type;
1044 let Inst{20} = 1; // load
1046 let Inst{10-8} = 0b110; // PUW.
1049 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1050 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1051 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1052 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1053 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1056 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1057 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1058 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1061 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1062 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1063 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1064 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1067 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1068 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1069 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1070 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1072 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1074 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1075 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1076 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1077 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1079 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1081 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1082 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1083 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1084 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1086 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1088 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1089 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1090 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1091 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1093 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1095 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1096 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1097 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1098 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1100 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1102 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1103 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1104 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1105 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1107 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1109 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1111 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1112 class T2IstT<bits<2> type, string opc>
1113 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1114 "\t$src, $addr", []> {
1115 let Inst{31-27} = 0b11111;
1116 let Inst{26-25} = 0b00;
1117 let Inst{24} = 0; // not signed
1119 let Inst{22-21} = type;
1120 let Inst{20} = 0; // store
1122 let Inst{10-8} = 0b110; // PUW
1125 def t2STRT : T2IstT<0b10, "strt">;
1126 def t2STRBT : T2IstT<0b00, "strbt">;
1127 def t2STRHT : T2IstT<0b01, "strht">;
1129 // ldrd / strd pre / post variants
1130 // For disassembly only.
1132 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1133 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1134 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1136 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1137 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1138 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1140 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1141 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1142 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1144 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1145 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1146 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>;
1148 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1149 // data/instruction access. These are for disassembly only.
1151 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1152 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1153 multiclass T2Ipl<bit instr, bit write, string opc> {
1155 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc,
1156 "\t[$base, $imm]", []> {
1157 let Inst{31-25} = 0b1111100;
1158 let Inst{24} = instr;
1159 let Inst{23} = 1; // U = 1
1161 let Inst{21} = write;
1163 let Inst{15-12} = 0b1111;
1166 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1167 "\t[$base, $imm]", []> {
1168 let Inst{31-25} = 0b1111100;
1169 let Inst{24} = instr;
1170 let Inst{23} = 0; // U = 0
1172 let Inst{21} = write;
1174 let Inst{15-12} = 0b1111;
1175 let Inst{11-8} = 0b1100;
1178 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1179 "\t[pc, $imm]", []> {
1180 let Inst{31-25} = 0b1111100;
1181 let Inst{24} = instr;
1182 let Inst{23} = ?; // add = (U == 1)
1184 let Inst{21} = write;
1186 let Inst{19-16} = 0b1111; // Rn = 0b1111
1187 let Inst{15-12} = 0b1111;
1190 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc,
1191 "\t[$base, $a]", []> {
1192 let Inst{31-25} = 0b1111100;
1193 let Inst{24} = instr;
1194 let Inst{23} = 0; // add = TRUE for T1
1196 let Inst{21} = write;
1198 let Inst{15-12} = 0b1111;
1199 let Inst{11-6} = 0000000;
1200 let Inst{5-4} = 0b00; // no shift is applied
1203 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc,
1204 "\t[$base, $a, lsl $shamt]", []> {
1205 let Inst{31-25} = 0b1111100;
1206 let Inst{24} = instr;
1207 let Inst{23} = 0; // add = TRUE for T1
1209 let Inst{21} = write;
1211 let Inst{15-12} = 0b1111;
1212 let Inst{11-6} = 0000000;
1216 defm t2PLD : T2Ipl<0, 0, "pld">;
1217 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1218 defm t2PLI : T2Ipl<1, 0, "pli">;
1220 //===----------------------------------------------------------------------===//
1221 // Load / store multiple Instructions.
1224 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1225 def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1226 reglist:$dsts, variable_ops), IIC_iLoadm,
1227 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
1228 let Inst{31-27} = 0b11101;
1229 let Inst{26-25} = 0b00;
1230 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1232 let Inst{21} = 0; // The W bit.
1233 let Inst{20} = 1; // Load
1236 def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1237 reglist:$dsts, variable_ops), IIC_iLoadm,
1238 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
1239 "$addr.addr = $wb", []> {
1240 let Inst{31-27} = 0b11101;
1241 let Inst{26-25} = 0b00;
1242 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1244 let Inst{21} = 1; // The W bit.
1245 let Inst{20} = 1; // Load
1247 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1249 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1250 def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1251 reglist:$srcs, variable_ops), IIC_iStorem,
1252 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
1253 let Inst{31-27} = 0b11101;
1254 let Inst{26-25} = 0b00;
1255 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1257 let Inst{21} = 0; // The W bit.
1258 let Inst{20} = 0; // Store
1261 def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1262 reglist:$srcs, variable_ops),
1264 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
1265 "$addr.addr = $wb", []> {
1266 let Inst{31-27} = 0b11101;
1267 let Inst{26-25} = 0b00;
1268 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1270 let Inst{21} = 1; // The W bit.
1271 let Inst{20} = 0; // Store
1273 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1275 //===----------------------------------------------------------------------===//
1276 // Move Instructions.
1279 let neverHasSideEffects = 1 in
1280 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1281 "mov", ".w\t$dst, $src", []> {
1282 let Inst{31-27} = 0b11101;
1283 let Inst{26-25} = 0b01;
1284 let Inst{24-21} = 0b0010;
1285 let Inst{20} = ?; // The S bit.
1286 let Inst{19-16} = 0b1111; // Rn
1287 let Inst{14-12} = 0b000;
1288 let Inst{7-4} = 0b0000;
1291 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1292 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1293 def t2MOVi : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1294 "mov", ".w\t$dst, $src",
1295 [(set rGPR:$dst, t2_so_imm:$src)]> {
1296 let Inst{31-27} = 0b11110;
1298 let Inst{24-21} = 0b0010;
1299 let Inst{20} = ?; // The S bit.
1300 let Inst{19-16} = 0b1111; // Rn
1304 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1305 def t2MOVi16 : T2I<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1306 "movw", "\t$dst, $src",
1307 [(set rGPR:$dst, imm0_65535:$src)]> {
1308 let Inst{31-27} = 0b11110;
1310 let Inst{24-21} = 0b0010;
1311 let Inst{20} = 0; // The S bit.
1315 let Constraints = "$src = $dst" in
1316 def t2MOVTi16 : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1317 "movt", "\t$dst, $imm",
1319 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1320 let Inst{31-27} = 0b11110;
1322 let Inst{24-21} = 0b0110;
1323 let Inst{20} = 0; // The S bit.
1327 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1329 //===----------------------------------------------------------------------===//
1330 // Extend Instructions.
1335 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1336 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1337 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1338 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1339 defm t2SXTB16 : T2I_unary_rrot_sxtb16<0b010, "sxtb16">;
1341 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1342 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1343 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1344 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1345 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1347 // TODO: SXT(A){B|H}16 - done for disassembly only
1351 let AddedComplexity = 16 in {
1352 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1353 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1354 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1355 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1356 defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16",
1357 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1359 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1360 // The transformation should probably be done as a combiner action
1361 // instead so we can include a check for masking back in the upper
1362 // eight bits of the source into the lower eight bits of the result.
1363 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1364 // (t2UXTB16r_rot rGPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
1365 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1366 (t2UXTB16r_rot rGPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
1368 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1369 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1370 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1371 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1372 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1375 //===----------------------------------------------------------------------===//
1376 // Arithmetic Instructions.
1379 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1380 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1381 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1382 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1384 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1385 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1386 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1387 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1388 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1390 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1391 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1392 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1393 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1394 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1395 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1396 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1397 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1400 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1401 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1402 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1403 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1405 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1406 // The assume-no-carry-in form uses the negation of the input since add/sub
1407 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1408 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1410 // The AddedComplexity preferences the first variant over the others since
1411 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1412 let AddedComplexity = 1 in
1413 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1414 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1415 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1416 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1417 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1418 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1419 let AddedComplexity = 1 in
1420 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1421 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1422 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1423 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1424 // The with-carry-in form matches bitwise not instead of the negation.
1425 // Effectively, the inverse interpretation of the carry flag already accounts
1426 // for part of the negation.
1427 let AddedComplexity = 1 in
1428 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1429 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1430 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1431 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1433 // Select Bytes -- for disassembly only
1435 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1436 "\t$dst, $a, $b", []> {
1437 let Inst{31-27} = 0b11111;
1438 let Inst{26-24} = 0b010;
1440 let Inst{22-20} = 0b010;
1441 let Inst{15-12} = 0b1111;
1443 let Inst{6-4} = 0b000;
1446 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1447 // And Miscellaneous operations -- for disassembly only
1448 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1449 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1450 : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), NoItinerary, opc,
1451 "\t$dst, $a, $b", pat> {
1452 let Inst{31-27} = 0b11111;
1453 let Inst{26-23} = 0b0101;
1454 let Inst{22-20} = op22_20;
1455 let Inst{15-12} = 0b1111;
1456 let Inst{7-4} = op7_4;
1459 // Saturating add/subtract -- for disassembly only
1461 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1462 [(set rGPR:$dst, (int_arm_qadd rGPR:$a, rGPR:$b))]>;
1463 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1464 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1465 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1466 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1467 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1468 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1469 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1470 [(set rGPR:$dst, (int_arm_qsub rGPR:$a, rGPR:$b))]>;
1471 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1472 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1473 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1474 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1475 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1476 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1477 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1478 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1480 // Signed/Unsigned add/subtract -- for disassembly only
1482 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1483 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1484 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1485 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1486 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1487 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1488 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1489 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1490 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1491 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1492 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1493 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1495 // Signed/Unsigned halving add/subtract -- for disassembly only
1497 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1498 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1499 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1500 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1501 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1502 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1503 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1504 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1505 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1506 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1507 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1508 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1510 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1512 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1513 (ins rGPR:$a, rGPR:$b),
1514 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1515 let Inst{15-12} = 0b1111;
1517 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1518 (ins rGPR:$a, rGPR:$b, rGPR:$acc), NoItinerary, "usada8",
1519 "\t$dst, $a, $b, $acc", []>;
1521 // Signed/Unsigned saturate -- for disassembly only
1523 def t2SSAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
1524 NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh",
1525 [/* For disassembly only; pattern left blank */]> {
1526 let Inst{31-27} = 0b11110;
1527 let Inst{25-22} = 0b1100;
1532 def t2SSAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1533 "ssat16", "\t$dst, $bit_pos, $a",
1534 [/* For disassembly only; pattern left blank */]> {
1535 let Inst{31-27} = 0b11110;
1536 let Inst{25-22} = 0b1100;
1539 let Inst{21} = 1; // sh = '1'
1540 let Inst{14-12} = 0b000; // imm3 = '000'
1541 let Inst{7-6} = 0b00; // imm2 = '00'
1544 def t2USAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
1545 NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh",
1546 [/* For disassembly only; pattern left blank */]> {
1547 let Inst{31-27} = 0b11110;
1548 let Inst{25-22} = 0b1110;
1553 def t2USAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1554 "usat16", "\t$dst, $bit_pos, $a",
1555 [/* For disassembly only; pattern left blank */]> {
1556 let Inst{31-27} = 0b11110;
1557 let Inst{25-22} = 0b1110;
1560 let Inst{21} = 1; // sh = '1'
1561 let Inst{14-12} = 0b000; // imm3 = '000'
1562 let Inst{7-6} = 0b00; // imm2 = '00'
1565 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1566 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1568 //===----------------------------------------------------------------------===//
1569 // Shift and rotate Instructions.
1572 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1573 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1574 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1575 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1577 let Uses = [CPSR] in {
1578 def t2MOVrx : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1579 "rrx", "\t$dst, $src",
1580 [(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
1581 let Inst{31-27} = 0b11101;
1582 let Inst{26-25} = 0b01;
1583 let Inst{24-21} = 0b0010;
1584 let Inst{20} = ?; // The S bit.
1585 let Inst{19-16} = 0b1111; // Rn
1586 let Inst{14-12} = 0b000;
1587 let Inst{7-4} = 0b0011;
1591 let Defs = [CPSR] in {
1592 def t2MOVsrl_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1593 "lsrs", ".w\t$dst, $src, #1",
1594 [(set rGPR:$dst, (ARMsrl_flag rGPR:$src))]> {
1595 let Inst{31-27} = 0b11101;
1596 let Inst{26-25} = 0b01;
1597 let Inst{24-21} = 0b0010;
1598 let Inst{20} = 1; // The S bit.
1599 let Inst{19-16} = 0b1111; // Rn
1600 let Inst{5-4} = 0b01; // Shift type.
1601 // Shift amount = Inst{14-12:7-6} = 1.
1602 let Inst{14-12} = 0b000;
1603 let Inst{7-6} = 0b01;
1605 def t2MOVsra_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1606 "asrs", ".w\t$dst, $src, #1",
1607 [(set rGPR:$dst, (ARMsra_flag rGPR:$src))]> {
1608 let Inst{31-27} = 0b11101;
1609 let Inst{26-25} = 0b01;
1610 let Inst{24-21} = 0b0010;
1611 let Inst{20} = 1; // The S bit.
1612 let Inst{19-16} = 0b1111; // Rn
1613 let Inst{5-4} = 0b10; // Shift type.
1614 // Shift amount = Inst{14-12:7-6} = 1.
1615 let Inst{14-12} = 0b000;
1616 let Inst{7-6} = 0b01;
1620 //===----------------------------------------------------------------------===//
1621 // Bitwise Instructions.
1624 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1625 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1626 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1627 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1628 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1629 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1631 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1632 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1634 let Defs = [CPSR] in
1635 defm t2ANDS : T2I_bin_w_irs<0b0000, "and",
1636 BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>;
1638 let Constraints = "$src = $dst" in
1639 def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
1640 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1641 [(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
1642 let Inst{31-27} = 0b11110;
1644 let Inst{24-20} = 0b10110;
1645 let Inst{19-16} = 0b1111; // Rn
1649 def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1650 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1651 let Inst{31-27} = 0b11110;
1653 let Inst{24-20} = 0b10100;
1657 def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1658 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1659 let Inst{31-27} = 0b11110;
1661 let Inst{24-20} = 0b11100;
1665 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1666 let Constraints = "$src = $dst" in
1667 def t2BFI : T2I<(outs rGPR:$dst),
1668 (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm),
1669 IIC_iALUi, "bfi", "\t$dst, $val, $imm",
1670 [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val,
1671 bf_inv_mask_imm:$imm))]> {
1672 let Inst{31-27} = 0b11110;
1674 let Inst{24-20} = 0b10110;
1678 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1681 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1682 let AddedComplexity = 1 in
1683 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1686 let AddedComplexity = 1 in
1687 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
1688 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
1690 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1691 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
1692 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
1693 Requires<[IsThumb2]>;
1695 def : T2Pat<(t2_so_imm_not:$src),
1696 (t2MVNi t2_so_imm_not:$src)>;
1698 //===----------------------------------------------------------------------===//
1699 // Multiply Instructions.
1701 let isCommutable = 1 in
1702 def t2MUL: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1703 "mul", "\t$dst, $a, $b",
1704 [(set rGPR:$dst, (mul rGPR:$a, rGPR:$b))]> {
1705 let Inst{31-27} = 0b11111;
1706 let Inst{26-23} = 0b0110;
1707 let Inst{22-20} = 0b000;
1708 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1709 let Inst{7-4} = 0b0000; // Multiply
1712 def t2MLA: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1713 "mla", "\t$dst, $a, $b, $c",
1714 [(set rGPR:$dst, (add (mul rGPR:$a, rGPR:$b), rGPR:$c))]> {
1715 let Inst{31-27} = 0b11111;
1716 let Inst{26-23} = 0b0110;
1717 let Inst{22-20} = 0b000;
1718 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1719 let Inst{7-4} = 0b0000; // Multiply
1722 def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1723 "mls", "\t$dst, $a, $b, $c",
1724 [(set rGPR:$dst, (sub rGPR:$c, (mul rGPR:$a, rGPR:$b)))]> {
1725 let Inst{31-27} = 0b11111;
1726 let Inst{26-23} = 0b0110;
1727 let Inst{22-20} = 0b000;
1728 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1729 let Inst{7-4} = 0b0001; // Multiply and Subtract
1732 // Extra precision multiplies with low / high results
1733 let neverHasSideEffects = 1 in {
1734 let isCommutable = 1 in {
1735 def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1736 (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1737 "smull", "\t$ldst, $hdst, $a, $b", []> {
1738 let Inst{31-27} = 0b11111;
1739 let Inst{26-23} = 0b0111;
1740 let Inst{22-20} = 0b000;
1741 let Inst{7-4} = 0b0000;
1744 def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1745 (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1746 "umull", "\t$ldst, $hdst, $a, $b", []> {
1747 let Inst{31-27} = 0b11111;
1748 let Inst{26-23} = 0b0111;
1749 let Inst{22-20} = 0b010;
1750 let Inst{7-4} = 0b0000;
1754 // Multiply + accumulate
1755 def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1756 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1757 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1758 let Inst{31-27} = 0b11111;
1759 let Inst{26-23} = 0b0111;
1760 let Inst{22-20} = 0b100;
1761 let Inst{7-4} = 0b0000;
1764 def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1765 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1766 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1767 let Inst{31-27} = 0b11111;
1768 let Inst{26-23} = 0b0111;
1769 let Inst{22-20} = 0b110;
1770 let Inst{7-4} = 0b0000;
1773 def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1774 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1775 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1776 let Inst{31-27} = 0b11111;
1777 let Inst{26-23} = 0b0111;
1778 let Inst{22-20} = 0b110;
1779 let Inst{7-4} = 0b0110;
1781 } // neverHasSideEffects
1783 // Rounding variants of the below included for disassembly only
1785 // Most significant word multiply
1786 def t2SMMUL : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1787 "smmul", "\t$dst, $a, $b",
1788 [(set rGPR:$dst, (mulhs rGPR:$a, rGPR:$b))]> {
1789 let Inst{31-27} = 0b11111;
1790 let Inst{26-23} = 0b0110;
1791 let Inst{22-20} = 0b101;
1792 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1793 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1796 def t2SMMULR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1797 "smmulr", "\t$dst, $a, $b", []> {
1798 let Inst{31-27} = 0b11111;
1799 let Inst{26-23} = 0b0110;
1800 let Inst{22-20} = 0b101;
1801 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1802 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1805 def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1806 "smmla", "\t$dst, $a, $b, $c",
1807 [(set rGPR:$dst, (add (mulhs rGPR:$a, rGPR:$b), rGPR:$c))]> {
1808 let Inst{31-27} = 0b11111;
1809 let Inst{26-23} = 0b0110;
1810 let Inst{22-20} = 0b101;
1811 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1812 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1815 def t2SMMLAR: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1816 "smmlar", "\t$dst, $a, $b, $c", []> {
1817 let Inst{31-27} = 0b11111;
1818 let Inst{26-23} = 0b0110;
1819 let Inst{22-20} = 0b101;
1820 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1821 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1824 def t2SMMLS: T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1825 "smmls", "\t$dst, $a, $b, $c",
1826 [(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
1827 let Inst{31-27} = 0b11111;
1828 let Inst{26-23} = 0b0110;
1829 let Inst{22-20} = 0b110;
1830 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1831 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1834 def t2SMMLSR:T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1835 "smmlsr", "\t$dst, $a, $b, $c", []> {
1836 let Inst{31-27} = 0b11111;
1837 let Inst{26-23} = 0b0110;
1838 let Inst{22-20} = 0b110;
1839 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1840 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1843 multiclass T2I_smul<string opc, PatFrag opnode> {
1844 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1845 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1846 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1847 (sext_inreg rGPR:$b, i16)))]> {
1848 let Inst{31-27} = 0b11111;
1849 let Inst{26-23} = 0b0110;
1850 let Inst{22-20} = 0b001;
1851 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1852 let Inst{7-6} = 0b00;
1853 let Inst{5-4} = 0b00;
1856 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1857 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1858 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1859 (sra rGPR:$b, (i32 16))))]> {
1860 let Inst{31-27} = 0b11111;
1861 let Inst{26-23} = 0b0110;
1862 let Inst{22-20} = 0b001;
1863 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1864 let Inst{7-6} = 0b00;
1865 let Inst{5-4} = 0b01;
1868 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1869 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1870 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1871 (sext_inreg rGPR:$b, i16)))]> {
1872 let Inst{31-27} = 0b11111;
1873 let Inst{26-23} = 0b0110;
1874 let Inst{22-20} = 0b001;
1875 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1876 let Inst{7-6} = 0b00;
1877 let Inst{5-4} = 0b10;
1880 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1881 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1882 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1883 (sra rGPR:$b, (i32 16))))]> {
1884 let Inst{31-27} = 0b11111;
1885 let Inst{26-23} = 0b0110;
1886 let Inst{22-20} = 0b001;
1887 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1888 let Inst{7-6} = 0b00;
1889 let Inst{5-4} = 0b11;
1892 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1893 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1894 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1895 (sext_inreg rGPR:$b, i16)), (i32 16)))]> {
1896 let Inst{31-27} = 0b11111;
1897 let Inst{26-23} = 0b0110;
1898 let Inst{22-20} = 0b011;
1899 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1900 let Inst{7-6} = 0b00;
1901 let Inst{5-4} = 0b00;
1904 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1905 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1906 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1907 (sra rGPR:$b, (i32 16))), (i32 16)))]> {
1908 let Inst{31-27} = 0b11111;
1909 let Inst{26-23} = 0b0110;
1910 let Inst{22-20} = 0b011;
1911 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1912 let Inst{7-6} = 0b00;
1913 let Inst{5-4} = 0b01;
1918 multiclass T2I_smla<string opc, PatFrag opnode> {
1919 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1920 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1921 [(set rGPR:$dst, (add rGPR:$acc,
1922 (opnode (sext_inreg rGPR:$a, i16),
1923 (sext_inreg rGPR:$b, i16))))]> {
1924 let Inst{31-27} = 0b11111;
1925 let Inst{26-23} = 0b0110;
1926 let Inst{22-20} = 0b001;
1927 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1928 let Inst{7-6} = 0b00;
1929 let Inst{5-4} = 0b00;
1932 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1933 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1934 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
1935 (sra rGPR:$b, (i32 16)))))]> {
1936 let Inst{31-27} = 0b11111;
1937 let Inst{26-23} = 0b0110;
1938 let Inst{22-20} = 0b001;
1939 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1940 let Inst{7-6} = 0b00;
1941 let Inst{5-4} = 0b01;
1944 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1945 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1946 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1947 (sext_inreg rGPR:$b, i16))))]> {
1948 let Inst{31-27} = 0b11111;
1949 let Inst{26-23} = 0b0110;
1950 let Inst{22-20} = 0b001;
1951 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1952 let Inst{7-6} = 0b00;
1953 let Inst{5-4} = 0b10;
1956 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1957 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1958 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1959 (sra rGPR:$b, (i32 16)))))]> {
1960 let Inst{31-27} = 0b11111;
1961 let Inst{26-23} = 0b0110;
1962 let Inst{22-20} = 0b001;
1963 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1964 let Inst{7-6} = 0b00;
1965 let Inst{5-4} = 0b11;
1968 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1969 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1970 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1971 (sext_inreg rGPR:$b, i16)), (i32 16))))]> {
1972 let Inst{31-27} = 0b11111;
1973 let Inst{26-23} = 0b0110;
1974 let Inst{22-20} = 0b011;
1975 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1976 let Inst{7-6} = 0b00;
1977 let Inst{5-4} = 0b00;
1980 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1981 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1982 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1983 (sra rGPR:$b, (i32 16))), (i32 16))))]> {
1984 let Inst{31-27} = 0b11111;
1985 let Inst{26-23} = 0b0110;
1986 let Inst{22-20} = 0b011;
1987 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1988 let Inst{7-6} = 0b00;
1989 let Inst{5-4} = 0b01;
1993 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1994 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1996 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
1997 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
1998 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1999 [/* For disassembly only; pattern left blank */]>;
2000 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
2001 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
2002 [/* For disassembly only; pattern left blank */]>;
2003 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
2004 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2005 [/* For disassembly only; pattern left blank */]>;
2006 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
2007 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2008 [/* For disassembly only; pattern left blank */]>;
2010 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2011 // These are for disassembly only.
2013 def t2SMUAD: T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2014 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
2015 let Inst{15-12} = 0b1111;
2017 def t2SMUADX:T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2018 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
2019 let Inst{15-12} = 0b1111;
2021 def t2SMUSD: T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2022 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
2023 let Inst{15-12} = 0b1111;
2025 def t2SMUSDX:T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2026 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2027 let Inst{15-12} = 0b1111;
2029 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
2030 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlad",
2031 "\t$dst, $a, $b, $acc", []>;
2032 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst),
2033 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smladx",
2034 "\t$dst, $a, $b, $acc", []>;
2035 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst),
2036 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsd",
2037 "\t$dst, $a, $b, $acc", []>;
2038 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst),
2039 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsdx",
2040 "\t$dst, $a, $b, $acc", []>;
2041 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2042 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlald",
2043 "\t$ldst, $hdst, $a, $b", []>;
2044 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2045 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaldx",
2046 "\t$ldst, $hdst, $a, $b", []>;
2047 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2048 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsld",
2049 "\t$ldst, $hdst, $a, $b", []>;
2050 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2051 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsldx",
2052 "\t$ldst, $hdst, $a, $b", []>;
2054 //===----------------------------------------------------------------------===//
2055 // Misc. Arithmetic Instructions.
2058 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2059 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2060 : T2I<oops, iops, itin, opc, asm, pattern> {
2061 let Inst{31-27} = 0b11111;
2062 let Inst{26-22} = 0b01010;
2063 let Inst{21-20} = op1;
2064 let Inst{15-12} = 0b1111;
2065 let Inst{7-6} = 0b10;
2066 let Inst{5-4} = op2;
2069 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2070 "clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>;
2072 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2073 "rbit", "\t$dst, $src",
2074 [(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
2076 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2077 "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
2079 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2080 "rev16", ".w\t$dst, $src",
2082 (or (and (srl rGPR:$src, (i32 8)), 0xFF),
2083 (or (and (shl rGPR:$src, (i32 8)), 0xFF00),
2084 (or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
2085 (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
2087 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2088 "revsh", ".w\t$dst, $src",
2091 (or (srl (and rGPR:$src, 0xFF00), (i32 8)),
2092 (shl rGPR:$src, (i32 8))), i16))]>;
2094 def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2095 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2$sh",
2096 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
2097 (and (shl rGPR:$src2, lsl_amt:$sh),
2099 Requires<[HasT2ExtractPack]> {
2100 let Inst{31-27} = 0b11101;
2101 let Inst{26-25} = 0b01;
2102 let Inst{24-20} = 0b01100;
2103 let Inst{5} = 0; // BT form
2107 // Alternate cases for PKHBT where identities eliminate some nodes.
2108 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2109 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2110 Requires<[HasT2ExtractPack]>;
2111 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2112 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2113 Requires<[HasT2ExtractPack]>;
2115 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2116 // will match the pattern below.
2117 def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2118 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2$sh",
2119 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
2120 (and (sra rGPR:$src2, asr_amt:$sh),
2122 Requires<[HasT2ExtractPack]> {
2123 let Inst{31-27} = 0b11101;
2124 let Inst{26-25} = 0b01;
2125 let Inst{24-20} = 0b01100;
2126 let Inst{5} = 1; // TB form
2130 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2131 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2132 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2133 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2134 Requires<[HasT2ExtractPack]>;
2135 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2136 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2137 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2138 Requires<[HasT2ExtractPack]>;
2140 //===----------------------------------------------------------------------===//
2141 // Comparison Instructions...
2143 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2144 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2145 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2146 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2148 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2149 // Compare-to-zero still works out, just not the relationals
2150 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2151 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2152 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2153 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2155 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2156 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2158 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2159 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2161 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2162 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2163 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2164 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2166 // Conditional moves
2167 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2168 // a two-value operand where a dag node expects two operands. :(
2169 let neverHasSideEffects = 1 in {
2170 def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
2171 "mov", ".w\t$dst, $true",
2172 [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
2173 RegConstraint<"$false = $dst"> {
2174 let Inst{31-27} = 0b11101;
2175 let Inst{26-25} = 0b01;
2176 let Inst{24-21} = 0b0010;
2177 let Inst{20} = 0; // The S bit.
2178 let Inst{19-16} = 0b1111; // Rn
2179 let Inst{14-12} = 0b000;
2180 let Inst{7-4} = 0b0000;
2183 def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
2184 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2185 [/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2186 RegConstraint<"$false = $dst"> {
2187 let Inst{31-27} = 0b11110;
2189 let Inst{24-21} = 0b0010;
2190 let Inst{20} = 0; // The S bit.
2191 let Inst{19-16} = 0b1111; // Rn
2195 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2196 string opc, string asm, list<dag> pattern>
2197 : T2I<oops, iops, itin, opc, asm, pattern> {
2198 let Inst{31-27} = 0b11101;
2199 let Inst{26-25} = 0b01;
2200 let Inst{24-21} = 0b0010;
2201 let Inst{20} = 0; // The S bit.
2202 let Inst{19-16} = 0b1111; // Rn
2203 let Inst{5-4} = opcod; // Shift type.
2205 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$dst),
2206 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2207 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2208 RegConstraint<"$false = $dst">;
2209 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$dst),
2210 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2211 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2212 RegConstraint<"$false = $dst">;
2213 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$dst),
2214 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2215 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2216 RegConstraint<"$false = $dst">;
2217 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
2218 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2219 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2220 RegConstraint<"$false = $dst">;
2221 } // neverHasSideEffects
2223 //===----------------------------------------------------------------------===//
2224 // Atomic operations intrinsics
2227 // memory barriers protect the atomic sequences
2228 let hasSideEffects = 1 in {
2229 def t2DMBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dmb", "",
2230 [(ARMMemBarrier)]>, Requires<[IsThumb, HasDB]> {
2231 let Inst{31-4} = 0xF3BF8F5;
2232 // FIXME: add support for options other than a full system DMB
2233 let Inst{3-0} = 0b1111;
2236 def t2DSBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dsb", "",
2237 [(ARMSyncBarrier)]>, Requires<[IsThumb, HasDB]> {
2238 let Inst{31-4} = 0xF3BF8F4;
2239 // FIXME: add support for options other than a full system DSB
2240 let Inst{3-0} = 0b1111;
2244 // Helper class for multiclass T2MemB -- for disassembly only
2245 class T2I_memb<string opc, string asm>
2246 : T2I<(outs), (ins), NoItinerary, opc, asm,
2247 [/* For disassembly only; pattern left blank */]>,
2248 Requires<[IsThumb2, HasV7]> {
2249 let Inst{31-20} = 0xf3b;
2250 let Inst{15-14} = 0b10;
2254 multiclass T2MemB<bits<4> op7_4, string opc> {
2256 def st : T2I_memb<opc, "\tst"> {
2257 let Inst{7-4} = op7_4;
2258 let Inst{3-0} = 0b1110;
2261 def ish : T2I_memb<opc, "\tish"> {
2262 let Inst{7-4} = op7_4;
2263 let Inst{3-0} = 0b1011;
2266 def ishst : T2I_memb<opc, "\tishst"> {
2267 let Inst{7-4} = op7_4;
2268 let Inst{3-0} = 0b1010;
2271 def nsh : T2I_memb<opc, "\tnsh"> {
2272 let Inst{7-4} = op7_4;
2273 let Inst{3-0} = 0b0111;
2276 def nshst : T2I_memb<opc, "\tnshst"> {
2277 let Inst{7-4} = op7_4;
2278 let Inst{3-0} = 0b0110;
2281 def osh : T2I_memb<opc, "\tosh"> {
2282 let Inst{7-4} = op7_4;
2283 let Inst{3-0} = 0b0011;
2286 def oshst : T2I_memb<opc, "\toshst"> {
2287 let Inst{7-4} = op7_4;
2288 let Inst{3-0} = 0b0010;
2292 // These DMB variants are for disassembly only.
2293 defm t2DMB : T2MemB<0b0101, "dmb">;
2295 // These DSB variants are for disassembly only.
2296 defm t2DSB : T2MemB<0b0100, "dsb">;
2298 // ISB has only full system option -- for disassembly only
2299 def t2ISBsy : T2I_memb<"isb", ""> {
2300 let Inst{7-4} = 0b0110;
2301 let Inst{3-0} = 0b1111;
2304 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2305 InstrItinClass itin, string opc, string asm, string cstr,
2306 list<dag> pattern, bits<4> rt2 = 0b1111>
2307 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2308 let Inst{31-27} = 0b11101;
2309 let Inst{26-20} = 0b0001101;
2310 let Inst{11-8} = rt2;
2311 let Inst{7-6} = 0b01;
2312 let Inst{5-4} = opcod;
2313 let Inst{3-0} = 0b1111;
2315 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2316 InstrItinClass itin, string opc, string asm, string cstr,
2317 list<dag> pattern, bits<4> rt2 = 0b1111>
2318 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2319 let Inst{31-27} = 0b11101;
2320 let Inst{26-20} = 0b0001100;
2321 let Inst{11-8} = rt2;
2322 let Inst{7-6} = 0b01;
2323 let Inst{5-4} = opcod;
2326 let mayLoad = 1 in {
2327 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2328 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2330 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2331 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2333 def t2LDREX : Thumb2I<(outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2334 Size4Bytes, NoItinerary,
2335 "ldrex", "\t$dest, [$ptr]", "",
2337 let Inst{31-27} = 0b11101;
2338 let Inst{26-20} = 0b0000101;
2339 let Inst{11-8} = 0b1111;
2340 let Inst{7-0} = 0b00000000; // imm8 = 0
2342 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$dest, rGPR:$dest2), (ins rGPR:$ptr),
2343 AddrModeNone, Size4Bytes, NoItinerary,
2344 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2348 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2349 def t2STREXB : T2I_strex<0b00, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2350 AddrModeNone, Size4Bytes, NoItinerary,
2351 "strexb", "\t$success, $src, [$ptr]", "", []>;
2352 def t2STREXH : T2I_strex<0b01, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2353 AddrModeNone, Size4Bytes, NoItinerary,
2354 "strexh", "\t$success, $src, [$ptr]", "", []>;
2355 def t2STREX : Thumb2I<(outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2356 AddrModeNone, Size4Bytes, NoItinerary,
2357 "strex", "\t$success, $src, [$ptr]", "",
2359 let Inst{31-27} = 0b11101;
2360 let Inst{26-20} = 0b0000100;
2361 let Inst{7-0} = 0b00000000; // imm8 = 0
2363 def t2STREXD : T2I_strex<0b11, (outs rGPR:$success),
2364 (ins rGPR:$src, rGPR:$src2, rGPR:$ptr),
2365 AddrModeNone, Size4Bytes, NoItinerary,
2366 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2370 // Clear-Exclusive is for disassembly only.
2371 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2372 [/* For disassembly only; pattern left blank */]>,
2373 Requires<[IsARM, HasV7]> {
2374 let Inst{31-20} = 0xf3b;
2375 let Inst{15-14} = 0b10;
2377 let Inst{7-4} = 0b0010;
2380 //===----------------------------------------------------------------------===//
2384 // __aeabi_read_tp preserves the registers r1-r3.
2386 Defs = [R0, R12, LR, CPSR] in {
2387 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2388 "bl\t__aeabi_read_tp",
2389 [(set R0, ARMthread_pointer)]> {
2390 let Inst{31-27} = 0b11110;
2391 let Inst{15-14} = 0b11;
2396 //===----------------------------------------------------------------------===//
2397 // SJLJ Exception handling intrinsics
2398 // eh_sjlj_setjmp() is an instruction sequence to store the return
2399 // address and save #0 in R0 for the non-longjmp case.
2400 // Since by its nature we may be coming from some other function to get
2401 // here, and we're using the stack frame for the containing function to
2402 // save/restore registers, we can't keep anything live in regs across
2403 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2404 // when we get here from a longjmp(). We force everthing out of registers
2405 // except for our own input by listing the relevant registers in Defs. By
2406 // doing so, we also cause the prologue/epilogue code to actively preserve
2407 // all of the callee-saved resgisters, which is exactly what we want.
2408 // $val is a scratch register for our use.
2410 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2411 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2412 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2413 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2414 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2415 AddrModeNone, SizeSpecial, NoItinerary,
2416 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2417 "adds\t$val, #7\n\t"
2418 "str\t$val, [$src, #4]\n\t"
2421 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2423 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2424 Requires<[IsThumb2, HasVFP2]>;
2428 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2429 hasSideEffects = 1, isBarrier = 1 in {
2430 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2431 AddrModeNone, SizeSpecial, NoItinerary,
2432 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2433 "adds\t$val, #7\n\t"
2434 "str\t$val, [$src, #4]\n\t"
2437 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2439 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2440 Requires<[IsThumb2, NoVFP]>;
2444 //===----------------------------------------------------------------------===//
2445 // Control-Flow Instructions
2448 // FIXME: remove when we have a way to marking a MI with these properties.
2449 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2451 // FIXME: Should pc be an implicit operand like PICADD, etc?
2452 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2453 hasExtraDefRegAllocReq = 1 in
2454 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
2455 reglist:$dsts, variable_ops), IIC_Br,
2456 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
2457 "$addr.addr = $wb", []> {
2458 let Inst{31-27} = 0b11101;
2459 let Inst{26-25} = 0b00;
2460 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2462 let Inst{21} = 1; // The W bit.
2463 let Inst{20} = 1; // Load
2466 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2467 let isPredicable = 1 in
2468 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2470 [(br bb:$target)]> {
2471 let Inst{31-27} = 0b11110;
2472 let Inst{15-14} = 0b10;
2476 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2479 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2480 IIC_Br, "mov\tpc, $target$jt",
2481 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2482 let Inst{31-27} = 0b11101;
2483 let Inst{26-20} = 0b0100100;
2484 let Inst{19-16} = 0b1111;
2485 let Inst{14-12} = 0b000;
2486 let Inst{11-8} = 0b1111; // Rd = pc
2487 let Inst{7-4} = 0b0000;
2490 // FIXME: Add a non-pc based case that can be predicated.
2493 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2494 IIC_Br, "tbb\t$index$jt", []> {
2495 let Inst{31-27} = 0b11101;
2496 let Inst{26-20} = 0b0001101;
2497 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2498 let Inst{15-8} = 0b11110000;
2499 let Inst{7-4} = 0b0000; // B form
2504 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2505 IIC_Br, "tbh\t$index$jt", []> {
2506 let Inst{31-27} = 0b11101;
2507 let Inst{26-20} = 0b0001101;
2508 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2509 let Inst{15-8} = 0b11110000;
2510 let Inst{7-4} = 0b0001; // H form
2513 // Generic versions of the above two instructions, for disassembly only
2515 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2516 "tbb", "\t[$a, $b]", []>{
2517 let Inst{31-27} = 0b11101;
2518 let Inst{26-20} = 0b0001101;
2519 let Inst{15-8} = 0b11110000;
2520 let Inst{7-4} = 0b0000; // B form
2523 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2524 "tbh", "\t[$a, $b, lsl #1]", []> {
2525 let Inst{31-27} = 0b11101;
2526 let Inst{26-20} = 0b0001101;
2527 let Inst{15-8} = 0b11110000;
2528 let Inst{7-4} = 0b0001; // H form
2530 } // isNotDuplicable, isIndirectBranch
2532 } // isBranch, isTerminator, isBarrier
2534 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2535 // a two-value operand where a dag node expects two operands. :(
2536 let isBranch = 1, isTerminator = 1 in
2537 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2539 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2540 let Inst{31-27} = 0b11110;
2541 let Inst{15-14} = 0b10;
2547 let Defs = [ITSTATE] in
2548 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2549 AddrModeNone, Size2Bytes, IIC_iALUx,
2550 "it$mask\t$cc", "", []> {
2551 // 16-bit instruction.
2552 let Inst{31-16} = 0x0000;
2553 let Inst{15-8} = 0b10111111;
2556 // Branch and Exchange Jazelle -- for disassembly only
2558 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
2559 [/* For disassembly only; pattern left blank */]> {
2560 let Inst{31-27} = 0b11110;
2562 let Inst{25-20} = 0b111100;
2563 let Inst{15-14} = 0b10;
2567 // Change Processor State is a system instruction -- for disassembly only.
2568 // The singleton $opt operand contains the following information:
2569 // opt{4-0} = mode from Inst{4-0}
2570 // opt{5} = changemode from Inst{17}
2571 // opt{8-6} = AIF from Inst{8-6}
2572 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2573 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2574 [/* For disassembly only; pattern left blank */]> {
2575 let Inst{31-27} = 0b11110;
2577 let Inst{25-20} = 0b111010;
2578 let Inst{15-14} = 0b10;
2582 // A6.3.4 Branches and miscellaneous control
2583 // Table A6-14 Change Processor State, and hint instructions
2584 // Helper class for disassembly only.
2585 class T2I_hint<bits<8> op7_0, string opc, string asm>
2586 : T2I<(outs), (ins), NoItinerary, opc, asm,
2587 [/* For disassembly only; pattern left blank */]> {
2588 let Inst{31-20} = 0xf3a;
2589 let Inst{15-14} = 0b10;
2591 let Inst{10-8} = 0b000;
2592 let Inst{7-0} = op7_0;
2595 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2596 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2597 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2598 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2599 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2601 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2602 [/* For disassembly only; pattern left blank */]> {
2603 let Inst{31-20} = 0xf3a;
2604 let Inst{15-14} = 0b10;
2606 let Inst{10-8} = 0b000;
2607 let Inst{7-4} = 0b1111;
2610 // Secure Monitor Call is a system instruction -- for disassembly only
2611 // Option = Inst{19-16}
2612 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2613 [/* For disassembly only; pattern left blank */]> {
2614 let Inst{31-27} = 0b11110;
2615 let Inst{26-20} = 0b1111111;
2616 let Inst{15-12} = 0b1000;
2619 // Store Return State is a system instruction -- for disassembly only
2620 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2621 [/* For disassembly only; pattern left blank */]> {
2622 let Inst{31-27} = 0b11101;
2623 let Inst{26-20} = 0b0000010; // W = 1
2626 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2627 [/* For disassembly only; pattern left blank */]> {
2628 let Inst{31-27} = 0b11101;
2629 let Inst{26-20} = 0b0000000; // W = 0
2632 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2633 [/* For disassembly only; pattern left blank */]> {
2634 let Inst{31-27} = 0b11101;
2635 let Inst{26-20} = 0b0011010; // W = 1
2638 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2639 [/* For disassembly only; pattern left blank */]> {
2640 let Inst{31-27} = 0b11101;
2641 let Inst{26-20} = 0b0011000; // W = 0
2644 // Return From Exception is a system instruction -- for disassembly only
2645 def t2RFEDBW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfedb", "\t$base!",
2646 [/* For disassembly only; pattern left blank */]> {
2647 let Inst{31-27} = 0b11101;
2648 let Inst{26-20} = 0b0000011; // W = 1
2651 def t2RFEDB : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeab", "\t$base",
2652 [/* For disassembly only; pattern left blank */]> {
2653 let Inst{31-27} = 0b11101;
2654 let Inst{26-20} = 0b0000001; // W = 0
2657 def t2RFEIAW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base!",
2658 [/* For disassembly only; pattern left blank */]> {
2659 let Inst{31-27} = 0b11101;
2660 let Inst{26-20} = 0b0011011; // W = 1
2663 def t2RFEIA : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base",
2664 [/* For disassembly only; pattern left blank */]> {
2665 let Inst{31-27} = 0b11101;
2666 let Inst{26-20} = 0b0011001; // W = 0
2669 //===----------------------------------------------------------------------===//
2670 // Non-Instruction Patterns
2673 // Two piece so_imms.
2674 def : T2Pat<(or rGPR:$LHS, t2_so_imm2part:$RHS),
2675 (t2ORRri (t2ORRri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2676 (t2_so_imm2part_2 imm:$RHS))>;
2677 def : T2Pat<(xor rGPR:$LHS, t2_so_imm2part:$RHS),
2678 (t2EORri (t2EORri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2679 (t2_so_imm2part_2 imm:$RHS))>;
2680 def : T2Pat<(add rGPR:$LHS, t2_so_imm2part:$RHS),
2681 (t2ADDri (t2ADDri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2682 (t2_so_imm2part_2 imm:$RHS))>;
2683 def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS),
2684 (t2SUBri (t2SUBri rGPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2685 (t2_so_neg_imm2part_2 imm:$RHS))>;
2687 // 32-bit immediate using movw + movt.
2688 // This is a single pseudo instruction to make it re-materializable. Remove
2689 // when we can do generalized remat.
2690 let isReMaterializable = 1 in
2691 def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2692 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2693 [(set rGPR:$dst, (i32 imm:$src))]>;
2695 // ConstantPool, GlobalAddress, and JumpTable
2696 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2697 Requires<[IsThumb2, DontUseMovt]>;
2698 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2699 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2700 Requires<[IsThumb2, UseMovt]>;
2702 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2703 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2705 // Pseudo instruction that combines ldr from constpool and add pc. This should
2706 // be expanded into two instructions late to allow if-conversion and
2708 let canFoldAsLoad = 1, isReMaterializable = 1 in
2709 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2711 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2712 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2714 Requires<[IsThumb2]>;
2716 //===----------------------------------------------------------------------===//
2717 // Move between special register and ARM core register -- for disassembly only
2721 def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2722 [/* For disassembly only; pattern left blank */]> {
2723 let Inst{31-27} = 0b11110;
2725 let Inst{25-21} = 0b11111;
2726 let Inst{20} = 0; // The R bit.
2727 let Inst{15-14} = 0b10;
2732 def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2733 [/* For disassembly only; pattern left blank */]> {
2734 let Inst{31-27} = 0b11110;
2736 let Inst{25-21} = 0b11111;
2737 let Inst{20} = 1; // The R bit.
2738 let Inst{15-14} = 0b10;
2743 def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2744 "\tcpsr$mask, $src",
2745 [/* For disassembly only; pattern left blank */]> {
2746 let Inst{31-27} = 0b11110;
2748 let Inst{25-21} = 0b11100;
2749 let Inst{20} = 0; // The R bit.
2750 let Inst{15-14} = 0b10;
2755 def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2756 "\tspsr$mask, $src",
2757 [/* For disassembly only; pattern left blank */]> {
2758 let Inst{31-27} = 0b11110;
2760 let Inst{25-21} = 0b11100;
2761 let Inst{20} = 1; // The R bit.
2762 let Inst{15-14} = 0b10;