1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops rGPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]>;
56 // t2_so_imm_not - Match an immediate that is a complement
58 def t2_so_imm_not : Operand<i32>,
60 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
61 }], t2_so_imm_not_XFORM>;
63 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
64 def t2_so_imm_neg : Operand<i32>,
66 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
67 }], t2_so_imm_neg_XFORM>;
69 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
70 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
71 // to get the first/second pieces.
72 def t2_so_imm2part : Operand<i32>,
74 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
78 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
79 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
80 return CurDAG->getTargetConstant(V, MVT::i32);
83 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
84 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
85 return CurDAG->getTargetConstant(V, MVT::i32);
88 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
89 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
93 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
94 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
95 return CurDAG->getTargetConstant(V, MVT::i32);
98 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
99 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
100 return CurDAG->getTargetConstant(V, MVT::i32);
103 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
104 def imm1_31 : PatLeaf<(i32 imm), [{
105 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
108 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
109 def imm0_4095 : Operand<i32>,
110 PatLeaf<(i32 imm), [{
111 return (uint32_t)N->getZExtValue() < 4096;
114 def imm0_4095_neg : PatLeaf<(i32 imm), [{
115 return (uint32_t)(-N->getZExtValue()) < 4096;
118 def imm0_255_neg : PatLeaf<(i32 imm), [{
119 return (uint32_t)(-N->getZExtValue()) < 255;
122 def imm0_255_not : PatLeaf<(i32 imm), [{
123 return (uint32_t)(~N->getZExtValue()) < 255;
126 // Define Thumb2 specific addressing modes.
128 // t2addrmode_imm12 := reg + imm12
129 def t2addrmode_imm12 : Operand<i32>,
130 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
131 let PrintMethod = "printAddrModeImm12Operand";
132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
135 // t2addrmode_imm8 := reg +/- imm8
136 def t2addrmode_imm8 : Operand<i32>,
137 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
138 let PrintMethod = "printT2AddrModeImm8Operand";
139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
142 def t2am_imm8_offset : Operand<i32>,
143 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
144 [], [SDNPWantRoot]> {
145 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
148 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
149 def t2addrmode_imm8s4 : Operand<i32> {
150 let PrintMethod = "printT2AddrModeImm8s4Operand";
151 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
154 def t2am_imm8s4_offset : Operand<i32> {
155 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
158 // t2addrmode_so_reg := reg + (reg << imm2)
159 def t2addrmode_so_reg : Operand<i32>,
160 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
161 let PrintMethod = "printT2AddrModeSoRegOperand";
162 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
166 //===----------------------------------------------------------------------===//
167 // Multiclass helpers...
170 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
171 /// unary operation that produces a value. These are predicable and can be
172 /// changed to modify CPSR.
173 multiclass T2I_un_irs<bits<4> opcod, string opc,
174 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
175 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
177 def i : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), iii,
179 [(set rGPR:$dst, (opnode t2_so_imm:$src))]> {
180 let isAsCheapAsAMove = Cheap;
181 let isReMaterializable = ReMat;
182 let Inst{31-27} = 0b11110;
184 let Inst{24-21} = opcod;
185 let Inst{20} = ?; // The S bit.
186 let Inst{19-16} = 0b1111; // Rn
190 def r : T2sI<(outs rGPR:$dst), (ins rGPR:$src), iir,
191 opc, ".w\t$dst, $src",
192 [(set rGPR:$dst, (opnode rGPR:$src))]> {
193 let Inst{31-27} = 0b11101;
194 let Inst{26-25} = 0b01;
195 let Inst{24-21} = opcod;
196 let Inst{20} = ?; // The S bit.
197 let Inst{19-16} = 0b1111; // Rn
198 let Inst{14-12} = 0b000; // imm3
199 let Inst{7-6} = 0b00; // imm2
200 let Inst{5-4} = 0b00; // type
203 def s : T2sI<(outs rGPR:$dst), (ins t2_so_reg:$src), iis,
204 opc, ".w\t$dst, $src",
205 [(set rGPR:$dst, (opnode t2_so_reg:$src))]> {
206 let Inst{31-27} = 0b11101;
207 let Inst{26-25} = 0b01;
208 let Inst{24-21} = opcod;
209 let Inst{20} = ?; // The S bit.
210 let Inst{19-16} = 0b1111; // Rn
214 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
215 /// binary operation that produces a value. These are predicable and can be
216 /// changed to modify CPSR.
217 multiclass T2I_bin_irs<bits<4> opcod, string opc,
218 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
219 PatFrag opnode, bit Commutable = 0, string wide = ""> {
221 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), iii,
222 opc, "\t$dst, $lhs, $rhs",
223 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
224 let Inst{31-27} = 0b11110;
226 let Inst{24-21} = opcod;
227 let Inst{20} = ?; // The S bit.
231 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), iir,
232 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
233 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
234 let isCommutable = Commutable;
235 let Inst{31-27} = 0b11101;
236 let Inst{26-25} = 0b01;
237 let Inst{24-21} = opcod;
238 let Inst{20} = ?; // The S bit.
239 let Inst{14-12} = 0b000; // imm3
240 let Inst{7-6} = 0b00; // imm2
241 let Inst{5-4} = 0b00; // type
244 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), iis,
245 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
246 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
247 let Inst{31-27} = 0b11101;
248 let Inst{26-25} = 0b01;
249 let Inst{24-21} = opcod;
250 let Inst{20} = ?; // The S bit.
254 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
255 // the ".w" prefix to indicate that they are wide.
256 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
257 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
258 PatFrag opnode, bit Commutable = 0> :
259 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">;
261 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
262 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
263 /// it is equivalent to the T2I_bin_irs counterpart.
264 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
266 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
267 opc, ".w\t$dst, $rhs, $lhs",
268 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
269 let Inst{31-27} = 0b11110;
271 let Inst{24-21} = opcod;
272 let Inst{20} = ?; // The S bit.
276 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr,
277 opc, "\t$dst, $rhs, $lhs",
278 [/* For disassembly only; pattern left blank */]> {
279 let Inst{31-27} = 0b11101;
280 let Inst{26-25} = 0b01;
281 let Inst{24-21} = opcod;
282 let Inst{20} = ?; // The S bit.
283 let Inst{14-12} = 0b000; // imm3
284 let Inst{7-6} = 0b00; // imm2
285 let Inst{5-4} = 0b00; // type
288 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsir,
289 opc, "\t$dst, $rhs, $lhs",
290 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
291 let Inst{31-27} = 0b11101;
292 let Inst{26-25} = 0b01;
293 let Inst{24-21} = opcod;
294 let Inst{20} = ?; // The S bit.
298 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
299 /// instruction modifies the CPSR register.
300 let Defs = [CPSR] in {
301 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
302 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
303 PatFrag opnode, bit Commutable = 0> {
305 def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), iii,
306 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
307 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
308 let Inst{31-27} = 0b11110;
310 let Inst{24-21} = opcod;
311 let Inst{20} = 1; // The S bit.
315 def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), iir,
316 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
317 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
318 let isCommutable = Commutable;
319 let Inst{31-27} = 0b11101;
320 let Inst{26-25} = 0b01;
321 let Inst{24-21} = opcod;
322 let Inst{20} = 1; // The S bit.
323 let Inst{14-12} = 0b000; // imm3
324 let Inst{7-6} = 0b00; // imm2
325 let Inst{5-4} = 0b00; // type
328 def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), iis,
329 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
330 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
331 let Inst{31-27} = 0b11101;
332 let Inst{26-25} = 0b01;
333 let Inst{24-21} = opcod;
334 let Inst{20} = 1; // The S bit.
339 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
340 /// patterns for a binary operation that produces a value.
341 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
342 bit Commutable = 0> {
344 // The register-immediate version is re-materializable. This is useful
345 // in particular for taking the address of a local.
346 let isReMaterializable = 1 in {
347 def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
348 opc, ".w\t$dst, $lhs, $rhs",
349 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
350 let Inst{31-27} = 0b11110;
353 let Inst{23-21} = op23_21;
354 let Inst{20} = 0; // The S bit.
359 def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
360 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
361 [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
362 let Inst{31-27} = 0b11110;
365 let Inst{23-21} = op23_21;
366 let Inst{20} = 0; // The S bit.
370 def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
371 opc, ".w\t$dst, $lhs, $rhs",
372 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
373 let isCommutable = Commutable;
374 let Inst{31-27} = 0b11101;
375 let Inst{26-25} = 0b01;
377 let Inst{23-21} = op23_21;
378 let Inst{20} = 0; // The S bit.
379 let Inst{14-12} = 0b000; // imm3
380 let Inst{7-6} = 0b00; // imm2
381 let Inst{5-4} = 0b00; // type
384 def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
385 opc, ".w\t$dst, $lhs, $rhs",
386 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
387 let Inst{31-27} = 0b11101;
388 let Inst{26-25} = 0b01;
390 let Inst{23-21} = op23_21;
391 let Inst{20} = 0; // The S bit.
395 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
396 /// for a binary operation that produces a value and use the carry
397 /// bit. It's not predicable.
398 let Uses = [CPSR] in {
399 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
400 bit Commutable = 0> {
402 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
403 opc, "\t$dst, $lhs, $rhs",
404 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
405 Requires<[IsThumb2]> {
406 let Inst{31-27} = 0b11110;
408 let Inst{24-21} = opcod;
409 let Inst{20} = 0; // The S bit.
413 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
414 opc, ".w\t$dst, $lhs, $rhs",
415 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
416 Requires<[IsThumb2]> {
417 let isCommutable = Commutable;
418 let Inst{31-27} = 0b11101;
419 let Inst{26-25} = 0b01;
420 let Inst{24-21} = opcod;
421 let Inst{20} = 0; // The S bit.
422 let Inst{14-12} = 0b000; // imm3
423 let Inst{7-6} = 0b00; // imm2
424 let Inst{5-4} = 0b00; // type
427 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
428 opc, ".w\t$dst, $lhs, $rhs",
429 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
430 Requires<[IsThumb2]> {
431 let Inst{31-27} = 0b11101;
432 let Inst{26-25} = 0b01;
433 let Inst{24-21} = opcod;
434 let Inst{20} = 0; // The S bit.
438 // Carry setting variants
439 let Defs = [CPSR] in {
440 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
441 bit Commutable = 0> {
443 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
444 opc, "\t$dst, $lhs, $rhs",
445 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
446 Requires<[IsThumb2]> {
447 let Inst{31-27} = 0b11110;
449 let Inst{24-21} = opcod;
450 let Inst{20} = 1; // The S bit.
454 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
455 opc, ".w\t$dst, $lhs, $rhs",
456 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
457 Requires<[IsThumb2]> {
458 let isCommutable = Commutable;
459 let Inst{31-27} = 0b11101;
460 let Inst{26-25} = 0b01;
461 let Inst{24-21} = opcod;
462 let Inst{20} = 1; // The S bit.
463 let Inst{14-12} = 0b000; // imm3
464 let Inst{7-6} = 0b00; // imm2
465 let Inst{5-4} = 0b00; // type
468 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
469 opc, ".w\t$dst, $lhs, $rhs",
470 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
471 Requires<[IsThumb2]> {
472 let Inst{31-27} = 0b11101;
473 let Inst{26-25} = 0b01;
474 let Inst{24-21} = opcod;
475 let Inst{20} = 1; // The S bit.
481 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
482 /// version is not needed since this is only for codegen.
483 let Defs = [CPSR] in {
484 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
486 def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
487 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
488 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
489 let Inst{31-27} = 0b11110;
491 let Inst{24-21} = opcod;
492 let Inst{20} = 1; // The S bit.
496 def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
497 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
498 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
499 let Inst{31-27} = 0b11101;
500 let Inst{26-25} = 0b01;
501 let Inst{24-21} = opcod;
502 let Inst{20} = 1; // The S bit.
507 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
508 // rotate operation that produces a value.
509 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
511 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
512 opc, ".w\t$dst, $lhs, $rhs",
513 [(set rGPR:$dst, (opnode rGPR:$lhs, imm1_31:$rhs))]> {
514 let Inst{31-27} = 0b11101;
515 let Inst{26-21} = 0b010010;
516 let Inst{19-16} = 0b1111; // Rn
517 let Inst{5-4} = opcod;
520 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iMOVsr,
521 opc, ".w\t$dst, $lhs, $rhs",
522 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
523 let Inst{31-27} = 0b11111;
524 let Inst{26-23} = 0b0100;
525 let Inst{22-21} = opcod;
526 let Inst{15-12} = 0b1111;
527 let Inst{7-4} = 0b0000;
531 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
532 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
533 /// a explicit result, only implicitly set CPSR.
534 let isCompare = 1, Defs = [CPSR] in {
535 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
536 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
539 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), iii,
540 opc, ".w\t$lhs, $rhs",
541 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
542 let Inst{31-27} = 0b11110;
544 let Inst{24-21} = opcod;
545 let Inst{20} = 1; // The S bit.
547 let Inst{11-8} = 0b1111; // Rd
550 def rr : T2I<(outs), (ins GPR:$lhs, rGPR:$rhs), iir,
551 opc, ".w\t$lhs, $rhs",
552 [(opnode GPR:$lhs, rGPR:$rhs)]> {
553 let Inst{31-27} = 0b11101;
554 let Inst{26-25} = 0b01;
555 let Inst{24-21} = opcod;
556 let Inst{20} = 1; // The S bit.
557 let Inst{14-12} = 0b000; // imm3
558 let Inst{11-8} = 0b1111; // Rd
559 let Inst{7-6} = 0b00; // imm2
560 let Inst{5-4} = 0b00; // type
563 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), iis,
564 opc, ".w\t$lhs, $rhs",
565 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
566 let Inst{31-27} = 0b11101;
567 let Inst{26-25} = 0b01;
568 let Inst{24-21} = opcod;
569 let Inst{20} = 1; // The S bit.
570 let Inst{11-8} = 0b1111; // Rd
575 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
576 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
577 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
578 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), iii,
579 opc, ".w\t$dst, $addr",
580 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
581 let Inst{31-27} = 0b11111;
582 let Inst{26-25} = 0b00;
583 let Inst{24} = signed;
585 let Inst{22-21} = opcod;
586 let Inst{20} = 1; // load
588 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), iii,
589 opc, "\t$dst, $addr",
590 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
591 let Inst{31-27} = 0b11111;
592 let Inst{26-25} = 0b00;
593 let Inst{24} = signed;
595 let Inst{22-21} = opcod;
596 let Inst{20} = 1; // load
598 // Offset: index==TRUE, wback==FALSE
599 let Inst{10} = 1; // The P bit.
600 let Inst{8} = 0; // The W bit.
602 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), iis,
603 opc, ".w\t$dst, $addr",
604 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
605 let Inst{31-27} = 0b11111;
606 let Inst{26-25} = 0b00;
607 let Inst{24} = signed;
609 let Inst{22-21} = opcod;
610 let Inst{20} = 1; // load
611 let Inst{11-6} = 0b000000;
613 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), iii,
614 opc, ".w\t$dst, $addr",
615 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
616 let isReMaterializable = 1;
617 let Inst{31-27} = 0b11111;
618 let Inst{26-25} = 0b00;
619 let Inst{24} = signed;
620 let Inst{23} = ?; // add = (U == '1')
621 let Inst{22-21} = opcod;
622 let Inst{20} = 1; // load
623 let Inst{19-16} = 0b1111; // Rn
627 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
628 multiclass T2I_st<bits<2> opcod, string opc,
629 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
630 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), iii,
631 opc, ".w\t$src, $addr",
632 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
633 let Inst{31-27} = 0b11111;
634 let Inst{26-23} = 0b0001;
635 let Inst{22-21} = opcod;
636 let Inst{20} = 0; // !load
638 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), iii,
639 opc, "\t$src, $addr",
640 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
641 let Inst{31-27} = 0b11111;
642 let Inst{26-23} = 0b0000;
643 let Inst{22-21} = opcod;
644 let Inst{20} = 0; // !load
646 // Offset: index==TRUE, wback==FALSE
647 let Inst{10} = 1; // The P bit.
648 let Inst{8} = 0; // The W bit.
650 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), iis,
651 opc, ".w\t$src, $addr",
652 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
653 let Inst{31-27} = 0b11111;
654 let Inst{26-23} = 0b0000;
655 let Inst{22-21} = opcod;
656 let Inst{20} = 0; // !load
657 let Inst{11-6} = 0b000000;
661 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
662 /// register and one whose operand is a register rotated by 8/16/24.
663 multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
664 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iEXTr,
665 opc, ".w\t$dst, $src",
666 [(set rGPR:$dst, (opnode rGPR:$src))]> {
667 let Inst{31-27} = 0b11111;
668 let Inst{26-23} = 0b0100;
669 let Inst{22-20} = opcod;
670 let Inst{19-16} = 0b1111; // Rn
671 let Inst{15-12} = 0b1111;
673 let Inst{5-4} = 0b00; // rotate
675 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iEXTr,
676 opc, ".w\t$dst, $src, ror $rot",
677 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]> {
678 let Inst{31-27} = 0b11111;
679 let Inst{26-23} = 0b0100;
680 let Inst{22-20} = opcod;
681 let Inst{19-16} = 0b1111; // Rn
682 let Inst{15-12} = 0b1111;
684 let Inst{5-4} = {?,?}; // rotate
688 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
689 multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
690 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iEXTr,
692 [(set rGPR:$dst, (opnode rGPR:$src))]>,
693 Requires<[HasT2ExtractPack]> {
694 let Inst{31-27} = 0b11111;
695 let Inst{26-23} = 0b0100;
696 let Inst{22-20} = opcod;
697 let Inst{19-16} = 0b1111; // Rn
698 let Inst{15-12} = 0b1111;
700 let Inst{5-4} = 0b00; // rotate
702 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iEXTr,
703 opc, "\t$dst, $src, ror $rot",
704 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>,
705 Requires<[HasT2ExtractPack]> {
706 let Inst{31-27} = 0b11111;
707 let Inst{26-23} = 0b0100;
708 let Inst{22-20} = opcod;
709 let Inst{19-16} = 0b1111; // Rn
710 let Inst{15-12} = 0b1111;
712 let Inst{5-4} = {?,?}; // rotate
716 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
718 multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
719 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iEXTr,
720 opc, "\t$dst, $src", []> {
721 let Inst{31-27} = 0b11111;
722 let Inst{26-23} = 0b0100;
723 let Inst{22-20} = opcod;
724 let Inst{19-16} = 0b1111; // Rn
725 let Inst{15-12} = 0b1111;
727 let Inst{5-4} = 0b00; // rotate
729 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iEXTr,
730 opc, "\t$dst, $src, ror $rot", []> {
731 let Inst{31-27} = 0b11111;
732 let Inst{26-23} = 0b0100;
733 let Inst{22-20} = opcod;
734 let Inst{19-16} = 0b1111; // Rn
735 let Inst{15-12} = 0b1111;
737 let Inst{5-4} = {?,?}; // rotate
741 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
742 /// register and one whose operand is a register rotated by 8/16/24.
743 multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
744 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iEXTAr,
745 opc, "\t$dst, $LHS, $RHS",
746 [(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>,
747 Requires<[HasT2ExtractPack]> {
748 let Inst{31-27} = 0b11111;
749 let Inst{26-23} = 0b0100;
750 let Inst{22-20} = opcod;
751 let Inst{15-12} = 0b1111;
753 let Inst{5-4} = 0b00; // rotate
755 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
756 IIC_iEXTAsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
757 [(set rGPR:$dst, (opnode rGPR:$LHS,
758 (rotr rGPR:$RHS, rot_imm:$rot)))]>,
759 Requires<[HasT2ExtractPack]> {
760 let Inst{31-27} = 0b11111;
761 let Inst{26-23} = 0b0100;
762 let Inst{22-20} = opcod;
763 let Inst{15-12} = 0b1111;
765 let Inst{5-4} = {?,?}; // rotate
769 // DO variant - disassembly only, no pattern
771 multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
772 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iEXTAr,
773 opc, "\t$dst, $LHS, $RHS", []> {
774 let Inst{31-27} = 0b11111;
775 let Inst{26-23} = 0b0100;
776 let Inst{22-20} = opcod;
777 let Inst{15-12} = 0b1111;
779 let Inst{5-4} = 0b00; // rotate
781 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
782 IIC_iEXTAsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
783 let Inst{31-27} = 0b11111;
784 let Inst{26-23} = 0b0100;
785 let Inst{22-20} = opcod;
786 let Inst{15-12} = 0b1111;
788 let Inst{5-4} = {?,?}; // rotate
792 //===----------------------------------------------------------------------===//
794 //===----------------------------------------------------------------------===//
796 //===----------------------------------------------------------------------===//
797 // Miscellaneous Instructions.
800 // LEApcrel - Load a pc-relative address into a register without offending the
802 let neverHasSideEffects = 1 in {
803 let isReMaterializable = 1 in
804 def t2LEApcrel : T2XI<(outs rGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
805 "adr${p}.w\t$dst, #$label", []> {
806 let Inst{31-27} = 0b11110;
807 let Inst{25-24} = 0b10;
808 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
811 let Inst{19-16} = 0b1111; // Rn
814 } // neverHasSideEffects
815 def t2LEApcrelJT : T2XI<(outs rGPR:$dst),
816 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
817 "adr${p}.w\t$dst, #${label}_${id}", []> {
818 let Inst{31-27} = 0b11110;
819 let Inst{25-24} = 0b10;
820 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
823 let Inst{19-16} = 0b1111; // Rn
827 // ADD r, sp, {so_imm|i12}
828 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
829 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
830 let Inst{31-27} = 0b11110;
832 let Inst{24-21} = 0b1000;
833 let Inst{20} = ?; // The S bit.
834 let Inst{19-16} = 0b1101; // Rn = sp
837 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
838 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
839 let Inst{31-27} = 0b11110;
841 let Inst{24-21} = 0b0000;
842 let Inst{20} = 0; // The S bit.
843 let Inst{19-16} = 0b1101; // Rn = sp
848 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
849 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
850 let Inst{31-27} = 0b11101;
851 let Inst{26-25} = 0b01;
852 let Inst{24-21} = 0b1000;
853 let Inst{20} = ?; // The S bit.
854 let Inst{19-16} = 0b1101; // Rn = sp
858 // SUB r, sp, {so_imm|i12}
859 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
860 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
861 let Inst{31-27} = 0b11110;
863 let Inst{24-21} = 0b1101;
864 let Inst{20} = ?; // The S bit.
865 let Inst{19-16} = 0b1101; // Rn = sp
868 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
869 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
870 let Inst{31-27} = 0b11110;
872 let Inst{24-21} = 0b0101;
873 let Inst{20} = 0; // The S bit.
874 let Inst{19-16} = 0b1101; // Rn = sp
879 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
881 "sub", "\t$dst, $sp, $rhs", []> {
882 let Inst{31-27} = 0b11101;
883 let Inst{26-25} = 0b01;
884 let Inst{24-21} = 0b1101;
885 let Inst{20} = ?; // The S bit.
886 let Inst{19-16} = 0b1101; // Rn = sp
890 // Signed and unsigned division on v7-M
891 def t2SDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
892 "sdiv", "\t$dst, $a, $b",
893 [(set rGPR:$dst, (sdiv rGPR:$a, rGPR:$b))]>,
894 Requires<[HasDivide]> {
895 let Inst{31-27} = 0b11111;
896 let Inst{26-21} = 0b011100;
898 let Inst{15-12} = 0b1111;
899 let Inst{7-4} = 0b1111;
902 def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
903 "udiv", "\t$dst, $a, $b",
904 [(set rGPR:$dst, (udiv rGPR:$a, rGPR:$b))]>,
905 Requires<[HasDivide]> {
906 let Inst{31-27} = 0b11111;
907 let Inst{26-21} = 0b011101;
909 let Inst{15-12} = 0b1111;
910 let Inst{7-4} = 0b1111;
913 //===----------------------------------------------------------------------===//
914 // Load / store Instructions.
918 let canFoldAsLoad = 1, isReMaterializable = 1 in
919 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
920 UnOpFrag<(load node:$Src)>>;
922 // Loads with zero extension
923 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
924 UnOpFrag<(zextloadi16 node:$Src)>>;
925 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
926 UnOpFrag<(zextloadi8 node:$Src)>>;
928 // Loads with sign extension
929 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
930 UnOpFrag<(sextloadi16 node:$Src)>>;
931 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
932 UnOpFrag<(sextloadi8 node:$Src)>>;
934 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
936 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
937 (ins t2addrmode_imm8s4:$addr),
938 IIC_iLoad_d_i, "ldrd", "\t$dst1, $addr", []>;
939 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
940 (ins i32imm:$addr), IIC_iLoad_d_i,
941 "ldrd", "\t$dst1, $addr", []> {
942 let Inst{19-16} = 0b1111; // Rn
944 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
946 // zextload i1 -> zextload i8
947 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
948 (t2LDRBi12 t2addrmode_imm12:$addr)>;
949 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
950 (t2LDRBi8 t2addrmode_imm8:$addr)>;
951 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
952 (t2LDRBs t2addrmode_so_reg:$addr)>;
953 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
954 (t2LDRBpci tconstpool:$addr)>;
956 // extload -> zextload
957 // FIXME: Reduce the number of patterns by legalizing extload to zextload
959 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
960 (t2LDRBi12 t2addrmode_imm12:$addr)>;
961 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
962 (t2LDRBi8 t2addrmode_imm8:$addr)>;
963 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
964 (t2LDRBs t2addrmode_so_reg:$addr)>;
965 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
966 (t2LDRBpci tconstpool:$addr)>;
968 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
969 (t2LDRBi12 t2addrmode_imm12:$addr)>;
970 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
971 (t2LDRBi8 t2addrmode_imm8:$addr)>;
972 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
973 (t2LDRBs t2addrmode_so_reg:$addr)>;
974 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
975 (t2LDRBpci tconstpool:$addr)>;
977 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
978 (t2LDRHi12 t2addrmode_imm12:$addr)>;
979 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
980 (t2LDRHi8 t2addrmode_imm8:$addr)>;
981 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
982 (t2LDRHs t2addrmode_so_reg:$addr)>;
983 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
984 (t2LDRHpci tconstpool:$addr)>;
986 // FIXME: The destination register of the loads and stores can't be PC, but
987 // can be SP. We need another regclass (similar to rGPR) to represent
988 // that. Not a pressing issue since these are selected manually,
992 let mayLoad = 1, neverHasSideEffects = 1 in {
993 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
994 (ins t2addrmode_imm8:$addr),
995 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
996 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
999 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1000 (ins GPR:$base, t2am_imm8_offset:$offset),
1001 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1002 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
1005 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1006 (ins t2addrmode_imm8:$addr),
1007 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1008 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
1010 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1011 (ins GPR:$base, t2am_imm8_offset:$offset),
1012 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1013 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
1016 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1017 (ins t2addrmode_imm8:$addr),
1018 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1019 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
1021 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1022 (ins GPR:$base, t2am_imm8_offset:$offset),
1023 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1024 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
1027 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1028 (ins t2addrmode_imm8:$addr),
1029 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1030 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
1032 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1033 (ins GPR:$base, t2am_imm8_offset:$offset),
1034 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1035 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1038 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1039 (ins t2addrmode_imm8:$addr),
1040 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1041 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1043 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1044 (ins GPR:$base, t2am_imm8_offset:$offset),
1045 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1046 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1048 } // mayLoad = 1, neverHasSideEffects = 1
1050 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1051 // for disassembly only.
1052 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1053 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1054 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), ii, opc,
1055 "\t$dst, $addr", []> {
1056 let Inst{31-27} = 0b11111;
1057 let Inst{26-25} = 0b00;
1058 let Inst{24} = signed;
1060 let Inst{22-21} = type;
1061 let Inst{20} = 1; // load
1063 let Inst{10-8} = 0b110; // PUW.
1066 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1067 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1068 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1069 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1070 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1073 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1074 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1075 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1076 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1077 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1078 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1081 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1082 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1083 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1084 IIC_iStore_d_r, "strd", "\t$src1, $addr", []>;
1087 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1088 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1089 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1090 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1092 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1094 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1095 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1096 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1097 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1099 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1101 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1102 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1103 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1104 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1106 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1108 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1109 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1110 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1111 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1113 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1115 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1116 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1117 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1118 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1120 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1122 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1123 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1124 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1125 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1127 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1129 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1131 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1132 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1133 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), ii, opc,
1134 "\t$src, $addr", []> {
1135 let Inst{31-27} = 0b11111;
1136 let Inst{26-25} = 0b00;
1137 let Inst{24} = 0; // not signed
1139 let Inst{22-21} = type;
1140 let Inst{20} = 0; // store
1142 let Inst{10-8} = 0b110; // PUW
1145 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1146 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1147 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1149 // ldrd / strd pre / post variants
1150 // For disassembly only.
1152 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1153 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1154 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1156 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1157 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1158 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1160 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1161 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1162 IIC_iStore_d_ru, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1164 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1165 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1166 IIC_iStore_d_ru, "strd", "\t$src1, $src2, [$base], $imm", []>;
1168 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1169 // data/instruction access. These are for disassembly only.
1171 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1172 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1173 multiclass T2Ipl<bit instr, bit write, string opc> {
1175 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoad_i, opc,
1176 "\t[$base, $imm]", []> {
1177 let Inst{31-25} = 0b1111100;
1178 let Inst{24} = instr;
1179 let Inst{23} = 1; // U = 1
1181 let Inst{21} = write;
1183 let Inst{15-12} = 0b1111;
1186 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoad_i, opc,
1187 "\t[$base, $imm]", []> {
1188 let Inst{31-25} = 0b1111100;
1189 let Inst{24} = instr;
1190 let Inst{23} = 0; // U = 0
1192 let Inst{21} = write;
1194 let Inst{15-12} = 0b1111;
1195 let Inst{11-8} = 0b1100;
1198 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoad_i, opc,
1199 "\t[pc, $imm]", []> {
1200 let Inst{31-25} = 0b1111100;
1201 let Inst{24} = instr;
1202 let Inst{23} = ?; // add = (U == 1)
1204 let Inst{21} = write;
1206 let Inst{19-16} = 0b1111; // Rn = 0b1111
1207 let Inst{15-12} = 0b1111;
1210 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoad_i, opc,
1211 "\t[$base, $a]", []> {
1212 let Inst{31-25} = 0b1111100;
1213 let Inst{24} = instr;
1214 let Inst{23} = 0; // add = TRUE for T1
1216 let Inst{21} = write;
1218 let Inst{15-12} = 0b1111;
1219 let Inst{11-6} = 0000000;
1220 let Inst{5-4} = 0b00; // no shift is applied
1223 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoad_i, opc,
1224 "\t[$base, $a, lsl $shamt]", []> {
1225 let Inst{31-25} = 0b1111100;
1226 let Inst{24} = instr;
1227 let Inst{23} = 0; // add = TRUE for T1
1229 let Inst{21} = write;
1231 let Inst{15-12} = 0b1111;
1232 let Inst{11-6} = 0000000;
1236 defm t2PLD : T2Ipl<0, 0, "pld">;
1237 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1238 defm t2PLI : T2Ipl<1, 0, "pli">;
1240 //===----------------------------------------------------------------------===//
1241 // Load / store multiple Instructions.
1244 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1245 isCodeGenOnly = 1 in {
1246 def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1247 reglist:$dsts, variable_ops), IIC_iLoad_m,
1248 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
1249 let Inst{31-27} = 0b11101;
1250 let Inst{26-25} = 0b00;
1251 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1253 let Inst{21} = 0; // The W bit.
1254 let Inst{20} = 1; // Load
1257 def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1258 reglist:$dsts, variable_ops),
1260 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
1261 "$addr.addr = $wb", []> {
1262 let Inst{31-27} = 0b11101;
1263 let Inst{26-25} = 0b00;
1264 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1266 let Inst{21} = 1; // The W bit.
1267 let Inst{20} = 1; // Load
1269 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1271 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1272 isCodeGenOnly = 1 in {
1273 def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1274 reglist:$srcs, variable_ops), IIC_iStore_m,
1275 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
1276 let Inst{31-27} = 0b11101;
1277 let Inst{26-25} = 0b00;
1278 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1280 let Inst{21} = 0; // The W bit.
1281 let Inst{20} = 0; // Store
1284 def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1285 reglist:$srcs, variable_ops),
1287 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
1288 "$addr.addr = $wb", []> {
1289 let Inst{31-27} = 0b11101;
1290 let Inst{26-25} = 0b00;
1291 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1293 let Inst{21} = 1; // The W bit.
1294 let Inst{20} = 0; // Store
1296 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1298 //===----------------------------------------------------------------------===//
1299 // Move Instructions.
1302 let neverHasSideEffects = 1 in
1303 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1304 "mov", ".w\t$dst, $src", []> {
1305 let Inst{31-27} = 0b11101;
1306 let Inst{26-25} = 0b01;
1307 let Inst{24-21} = 0b0010;
1308 let Inst{20} = ?; // The S bit.
1309 let Inst{19-16} = 0b1111; // Rn
1310 let Inst{14-12} = 0b000;
1311 let Inst{7-4} = 0b0000;
1314 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1315 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1316 def t2MOVi : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1317 "mov", ".w\t$dst, $src",
1318 [(set rGPR:$dst, t2_so_imm:$src)]> {
1319 let Inst{31-27} = 0b11110;
1321 let Inst{24-21} = 0b0010;
1322 let Inst{20} = ?; // The S bit.
1323 let Inst{19-16} = 0b1111; // Rn
1327 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1328 def t2MOVi16 : T2I<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1329 "movw", "\t$dst, $src",
1330 [(set rGPR:$dst, imm0_65535:$src)]> {
1331 let Inst{31-27} = 0b11110;
1333 let Inst{24-21} = 0b0010;
1334 let Inst{20} = 0; // The S bit.
1338 let Constraints = "$src = $dst" in
1339 def t2MOVTi16 : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1340 "movt", "\t$dst, $imm",
1342 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1343 let Inst{31-27} = 0b11110;
1345 let Inst{24-21} = 0b0110;
1346 let Inst{20} = 0; // The S bit.
1350 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1352 //===----------------------------------------------------------------------===//
1353 // Extend Instructions.
1358 defm t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1359 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1360 defm t2SXTH : T2I_ext_rrot<0b000, "sxth",
1361 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1362 defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1364 defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1365 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1366 defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1367 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1368 defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1370 // TODO: SXT(A){B|H}16 - done for disassembly only
1374 let AddedComplexity = 16 in {
1375 defm t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1376 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1377 defm t2UXTH : T2I_ext_rrot<0b001, "uxth",
1378 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1379 defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1380 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1382 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1383 // The transformation should probably be done as a combiner action
1384 // instead so we can include a check for masking back in the upper
1385 // eight bits of the source into the lower eight bits of the result.
1386 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1387 // (t2UXTB16r_rot rGPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
1388 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1389 (t2UXTB16r_rot rGPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
1391 defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1392 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1393 defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1394 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1395 defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1398 //===----------------------------------------------------------------------===//
1399 // Arithmetic Instructions.
1402 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1403 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1404 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1405 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1407 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1408 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1409 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1410 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1411 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1412 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1413 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1415 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1416 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1417 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1418 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1419 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1420 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1421 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1422 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1425 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1426 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1427 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1428 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1430 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1431 // The assume-no-carry-in form uses the negation of the input since add/sub
1432 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1433 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1435 // The AddedComplexity preferences the first variant over the others since
1436 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1437 let AddedComplexity = 1 in
1438 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1439 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1440 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1441 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1442 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1443 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1444 let AddedComplexity = 1 in
1445 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1446 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1447 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1448 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1449 // The with-carry-in form matches bitwise not instead of the negation.
1450 // Effectively, the inverse interpretation of the carry flag already accounts
1451 // for part of the negation.
1452 let AddedComplexity = 1 in
1453 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1454 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1455 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1456 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1458 // Select Bytes -- for disassembly only
1460 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1461 "\t$dst, $a, $b", []> {
1462 let Inst{31-27} = 0b11111;
1463 let Inst{26-24} = 0b010;
1465 let Inst{22-20} = 0b010;
1466 let Inst{15-12} = 0b1111;
1468 let Inst{6-4} = 0b000;
1471 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1472 // And Miscellaneous operations -- for disassembly only
1473 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1474 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1475 : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), NoItinerary, opc,
1476 "\t$dst, $a, $b", pat> {
1477 let Inst{31-27} = 0b11111;
1478 let Inst{26-23} = 0b0101;
1479 let Inst{22-20} = op22_20;
1480 let Inst{15-12} = 0b1111;
1481 let Inst{7-4} = op7_4;
1484 // Saturating add/subtract -- for disassembly only
1486 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1487 [(set rGPR:$dst, (int_arm_qadd rGPR:$a, rGPR:$b))]>;
1488 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1489 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1490 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1491 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1492 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1493 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1494 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1495 [(set rGPR:$dst, (int_arm_qsub rGPR:$a, rGPR:$b))]>;
1496 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1497 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1498 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1499 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1500 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1501 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1502 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1503 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1505 // Signed/Unsigned add/subtract -- for disassembly only
1507 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1508 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1509 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1510 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1511 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1512 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1513 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1514 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1515 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1516 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1517 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1518 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1520 // Signed/Unsigned halving add/subtract -- for disassembly only
1522 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1523 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1524 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1525 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1526 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1527 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1528 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1529 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1530 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1531 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1532 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1533 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1535 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1537 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1538 (ins rGPR:$a, rGPR:$b),
1539 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1540 let Inst{15-12} = 0b1111;
1542 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1543 (ins rGPR:$a, rGPR:$b, rGPR:$acc), NoItinerary, "usada8",
1544 "\t$dst, $a, $b, $acc", []>;
1546 // Signed/Unsigned saturate -- for disassembly only
1548 def t2SSAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
1549 NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh",
1550 [/* For disassembly only; pattern left blank */]> {
1551 let Inst{31-27} = 0b11110;
1552 let Inst{25-22} = 0b1100;
1557 def t2SSAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1558 "ssat16", "\t$dst, $bit_pos, $a",
1559 [/* For disassembly only; pattern left blank */]> {
1560 let Inst{31-27} = 0b11110;
1561 let Inst{25-22} = 0b1100;
1564 let Inst{21} = 1; // sh = '1'
1565 let Inst{14-12} = 0b000; // imm3 = '000'
1566 let Inst{7-6} = 0b00; // imm2 = '00'
1569 def t2USAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
1570 NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh",
1571 [/* For disassembly only; pattern left blank */]> {
1572 let Inst{31-27} = 0b11110;
1573 let Inst{25-22} = 0b1110;
1578 def t2USAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1579 "usat16", "\t$dst, $bit_pos, $a",
1580 [/* For disassembly only; pattern left blank */]> {
1581 let Inst{31-27} = 0b11110;
1582 let Inst{25-22} = 0b1110;
1585 let Inst{21} = 1; // sh = '1'
1586 let Inst{14-12} = 0b000; // imm3 = '000'
1587 let Inst{7-6} = 0b00; // imm2 = '00'
1590 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1591 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1593 //===----------------------------------------------------------------------===//
1594 // Shift and rotate Instructions.
1597 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1598 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1599 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1600 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1602 let Uses = [CPSR] in {
1603 def t2RRX : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1604 "rrx", "\t$dst, $src",
1605 [(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
1606 let Inst{31-27} = 0b11101;
1607 let Inst{26-25} = 0b01;
1608 let Inst{24-21} = 0b0010;
1609 let Inst{20} = ?; // The S bit.
1610 let Inst{19-16} = 0b1111; // Rn
1611 let Inst{14-12} = 0b000;
1612 let Inst{7-4} = 0b0011;
1616 let Defs = [CPSR] in {
1617 def t2MOVsrl_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1618 "lsrs", ".w\t$dst, $src, #1",
1619 [(set rGPR:$dst, (ARMsrl_flag rGPR:$src))]> {
1620 let Inst{31-27} = 0b11101;
1621 let Inst{26-25} = 0b01;
1622 let Inst{24-21} = 0b0010;
1623 let Inst{20} = 1; // The S bit.
1624 let Inst{19-16} = 0b1111; // Rn
1625 let Inst{5-4} = 0b01; // Shift type.
1626 // Shift amount = Inst{14-12:7-6} = 1.
1627 let Inst{14-12} = 0b000;
1628 let Inst{7-6} = 0b01;
1630 def t2MOVsra_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1631 "asrs", ".w\t$dst, $src, #1",
1632 [(set rGPR:$dst, (ARMsra_flag rGPR:$src))]> {
1633 let Inst{31-27} = 0b11101;
1634 let Inst{26-25} = 0b01;
1635 let Inst{24-21} = 0b0010;
1636 let Inst{20} = 1; // The S bit.
1637 let Inst{19-16} = 0b1111; // Rn
1638 let Inst{5-4} = 0b10; // Shift type.
1639 // Shift amount = Inst{14-12:7-6} = 1.
1640 let Inst{14-12} = 0b000;
1641 let Inst{7-6} = 0b01;
1645 //===----------------------------------------------------------------------===//
1646 // Bitwise Instructions.
1649 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1650 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1651 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1652 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1653 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1654 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1655 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1656 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1657 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1659 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1660 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1661 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1663 let Constraints = "$src = $dst" in
1664 def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
1665 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1666 [(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
1667 let Inst{31-27} = 0b11110;
1669 let Inst{24-20} = 0b10110;
1670 let Inst{19-16} = 0b1111; // Rn
1674 def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1675 IIC_iUNAsi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1676 let Inst{31-27} = 0b11110;
1678 let Inst{24-20} = 0b10100;
1682 def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1683 IIC_iUNAsi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1684 let Inst{31-27} = 0b11110;
1686 let Inst{24-20} = 0b11100;
1690 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1691 let Constraints = "$src = $dst" in
1692 def t2BFI : T2I<(outs rGPR:$dst),
1693 (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm),
1694 IIC_iBITi, "bfi", "\t$dst, $val, $imm",
1695 [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val,
1696 bf_inv_mask_imm:$imm))]> {
1697 let Inst{31-27} = 0b11110;
1699 let Inst{24-20} = 0b10110;
1703 defm t2ORN : T2I_bin_irs<0b0011, "orn",
1704 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1705 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
1707 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1708 let AddedComplexity = 1 in
1709 defm t2MVN : T2I_un_irs <0b0011, "mvn",
1710 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
1711 UnOpFrag<(not node:$Src)>, 1, 1>;
1714 let AddedComplexity = 1 in
1715 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
1716 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
1718 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1719 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
1720 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
1721 Requires<[IsThumb2]>;
1723 def : T2Pat<(t2_so_imm_not:$src),
1724 (t2MVNi t2_so_imm_not:$src)>;
1726 //===----------------------------------------------------------------------===//
1727 // Multiply Instructions.
1729 let isCommutable = 1 in
1730 def t2MUL: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1731 "mul", "\t$dst, $a, $b",
1732 [(set rGPR:$dst, (mul rGPR:$a, rGPR:$b))]> {
1733 let Inst{31-27} = 0b11111;
1734 let Inst{26-23} = 0b0110;
1735 let Inst{22-20} = 0b000;
1736 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1737 let Inst{7-4} = 0b0000; // Multiply
1740 def t2MLA: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1741 "mla", "\t$dst, $a, $b, $c",
1742 [(set rGPR:$dst, (add (mul rGPR:$a, rGPR:$b), rGPR:$c))]> {
1743 let Inst{31-27} = 0b11111;
1744 let Inst{26-23} = 0b0110;
1745 let Inst{22-20} = 0b000;
1746 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1747 let Inst{7-4} = 0b0000; // Multiply
1750 def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1751 "mls", "\t$dst, $a, $b, $c",
1752 [(set rGPR:$dst, (sub rGPR:$c, (mul rGPR:$a, rGPR:$b)))]> {
1753 let Inst{31-27} = 0b11111;
1754 let Inst{26-23} = 0b0110;
1755 let Inst{22-20} = 0b000;
1756 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1757 let Inst{7-4} = 0b0001; // Multiply and Subtract
1760 // Extra precision multiplies with low / high results
1761 let neverHasSideEffects = 1 in {
1762 let isCommutable = 1 in {
1763 def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1764 (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1765 "smull", "\t$ldst, $hdst, $a, $b", []> {
1766 let Inst{31-27} = 0b11111;
1767 let Inst{26-23} = 0b0111;
1768 let Inst{22-20} = 0b000;
1769 let Inst{7-4} = 0b0000;
1772 def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1773 (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1774 "umull", "\t$ldst, $hdst, $a, $b", []> {
1775 let Inst{31-27} = 0b11111;
1776 let Inst{26-23} = 0b0111;
1777 let Inst{22-20} = 0b010;
1778 let Inst{7-4} = 0b0000;
1782 // Multiply + accumulate
1783 def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1784 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1785 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1786 let Inst{31-27} = 0b11111;
1787 let Inst{26-23} = 0b0111;
1788 let Inst{22-20} = 0b100;
1789 let Inst{7-4} = 0b0000;
1792 def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1793 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1794 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1795 let Inst{31-27} = 0b11111;
1796 let Inst{26-23} = 0b0111;
1797 let Inst{22-20} = 0b110;
1798 let Inst{7-4} = 0b0000;
1801 def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1802 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1803 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1804 let Inst{31-27} = 0b11111;
1805 let Inst{26-23} = 0b0111;
1806 let Inst{22-20} = 0b110;
1807 let Inst{7-4} = 0b0110;
1809 } // neverHasSideEffects
1811 // Rounding variants of the below included for disassembly only
1813 // Most significant word multiply
1814 def t2SMMUL : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1815 "smmul", "\t$dst, $a, $b",
1816 [(set rGPR:$dst, (mulhs rGPR:$a, rGPR:$b))]> {
1817 let Inst{31-27} = 0b11111;
1818 let Inst{26-23} = 0b0110;
1819 let Inst{22-20} = 0b101;
1820 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1821 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1824 def t2SMMULR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1825 "smmulr", "\t$dst, $a, $b", []> {
1826 let Inst{31-27} = 0b11111;
1827 let Inst{26-23} = 0b0110;
1828 let Inst{22-20} = 0b101;
1829 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1830 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1833 def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1834 "smmla", "\t$dst, $a, $b, $c",
1835 [(set rGPR:$dst, (add (mulhs rGPR:$a, rGPR:$b), rGPR:$c))]> {
1836 let Inst{31-27} = 0b11111;
1837 let Inst{26-23} = 0b0110;
1838 let Inst{22-20} = 0b101;
1839 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1840 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1843 def t2SMMLAR: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1844 "smmlar", "\t$dst, $a, $b, $c", []> {
1845 let Inst{31-27} = 0b11111;
1846 let Inst{26-23} = 0b0110;
1847 let Inst{22-20} = 0b101;
1848 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1849 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1852 def t2SMMLS: T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1853 "smmls", "\t$dst, $a, $b, $c",
1854 [(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
1855 let Inst{31-27} = 0b11111;
1856 let Inst{26-23} = 0b0110;
1857 let Inst{22-20} = 0b110;
1858 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1859 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1862 def t2SMMLSR:T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1863 "smmlsr", "\t$dst, $a, $b, $c", []> {
1864 let Inst{31-27} = 0b11111;
1865 let Inst{26-23} = 0b0110;
1866 let Inst{22-20} = 0b110;
1867 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1868 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1871 multiclass T2I_smul<string opc, PatFrag opnode> {
1872 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1873 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1874 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1875 (sext_inreg rGPR:$b, i16)))]> {
1876 let Inst{31-27} = 0b11111;
1877 let Inst{26-23} = 0b0110;
1878 let Inst{22-20} = 0b001;
1879 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1880 let Inst{7-6} = 0b00;
1881 let Inst{5-4} = 0b00;
1884 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1885 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1886 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1887 (sra rGPR:$b, (i32 16))))]> {
1888 let Inst{31-27} = 0b11111;
1889 let Inst{26-23} = 0b0110;
1890 let Inst{22-20} = 0b001;
1891 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1892 let Inst{7-6} = 0b00;
1893 let Inst{5-4} = 0b01;
1896 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1897 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1898 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1899 (sext_inreg rGPR:$b, i16)))]> {
1900 let Inst{31-27} = 0b11111;
1901 let Inst{26-23} = 0b0110;
1902 let Inst{22-20} = 0b001;
1903 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1904 let Inst{7-6} = 0b00;
1905 let Inst{5-4} = 0b10;
1908 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1909 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1910 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1911 (sra rGPR:$b, (i32 16))))]> {
1912 let Inst{31-27} = 0b11111;
1913 let Inst{26-23} = 0b0110;
1914 let Inst{22-20} = 0b001;
1915 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1916 let Inst{7-6} = 0b00;
1917 let Inst{5-4} = 0b11;
1920 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1921 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1922 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1923 (sext_inreg rGPR:$b, i16)), (i32 16)))]> {
1924 let Inst{31-27} = 0b11111;
1925 let Inst{26-23} = 0b0110;
1926 let Inst{22-20} = 0b011;
1927 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1928 let Inst{7-6} = 0b00;
1929 let Inst{5-4} = 0b00;
1932 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1933 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1934 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1935 (sra rGPR:$b, (i32 16))), (i32 16)))]> {
1936 let Inst{31-27} = 0b11111;
1937 let Inst{26-23} = 0b0110;
1938 let Inst{22-20} = 0b011;
1939 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1940 let Inst{7-6} = 0b00;
1941 let Inst{5-4} = 0b01;
1946 multiclass T2I_smla<string opc, PatFrag opnode> {
1947 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1948 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1949 [(set rGPR:$dst, (add rGPR:$acc,
1950 (opnode (sext_inreg rGPR:$a, i16),
1951 (sext_inreg rGPR:$b, i16))))]> {
1952 let Inst{31-27} = 0b11111;
1953 let Inst{26-23} = 0b0110;
1954 let Inst{22-20} = 0b001;
1955 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1956 let Inst{7-6} = 0b00;
1957 let Inst{5-4} = 0b00;
1960 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1961 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1962 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
1963 (sra rGPR:$b, (i32 16)))))]> {
1964 let Inst{31-27} = 0b11111;
1965 let Inst{26-23} = 0b0110;
1966 let Inst{22-20} = 0b001;
1967 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1968 let Inst{7-6} = 0b00;
1969 let Inst{5-4} = 0b01;
1972 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1973 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1974 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1975 (sext_inreg rGPR:$b, i16))))]> {
1976 let Inst{31-27} = 0b11111;
1977 let Inst{26-23} = 0b0110;
1978 let Inst{22-20} = 0b001;
1979 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1980 let Inst{7-6} = 0b00;
1981 let Inst{5-4} = 0b10;
1984 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1985 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1986 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1987 (sra rGPR:$b, (i32 16)))))]> {
1988 let Inst{31-27} = 0b11111;
1989 let Inst{26-23} = 0b0110;
1990 let Inst{22-20} = 0b001;
1991 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1992 let Inst{7-6} = 0b00;
1993 let Inst{5-4} = 0b11;
1996 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1997 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1998 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
1999 (sext_inreg rGPR:$b, i16)), (i32 16))))]> {
2000 let Inst{31-27} = 0b11111;
2001 let Inst{26-23} = 0b0110;
2002 let Inst{22-20} = 0b011;
2003 let Inst{15-12} = {?, ?, ?, ?}; // Ra
2004 let Inst{7-6} = 0b00;
2005 let Inst{5-4} = 0b00;
2008 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
2009 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
2010 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
2011 (sra rGPR:$b, (i32 16))), (i32 16))))]> {
2012 let Inst{31-27} = 0b11111;
2013 let Inst{26-23} = 0b0110;
2014 let Inst{22-20} = 0b011;
2015 let Inst{15-12} = {?, ?, ?, ?}; // Ra
2016 let Inst{7-6} = 0b00;
2017 let Inst{5-4} = 0b01;
2021 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2022 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2024 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2025 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
2026 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
2027 [/* For disassembly only; pattern left blank */]>;
2028 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
2029 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
2030 [/* For disassembly only; pattern left blank */]>;
2031 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
2032 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2033 [/* For disassembly only; pattern left blank */]>;
2034 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
2035 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2036 [/* For disassembly only; pattern left blank */]>;
2038 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2039 // These are for disassembly only.
2041 def t2SMUAD: T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2042 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
2043 let Inst{15-12} = 0b1111;
2045 def t2SMUADX:T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2046 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
2047 let Inst{15-12} = 0b1111;
2049 def t2SMUSD: T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2050 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
2051 let Inst{15-12} = 0b1111;
2053 def t2SMUSDX:T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2054 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2055 let Inst{15-12} = 0b1111;
2057 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
2058 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlad",
2059 "\t$dst, $a, $b, $acc", []>;
2060 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst),
2061 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smladx",
2062 "\t$dst, $a, $b, $acc", []>;
2063 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst),
2064 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsd",
2065 "\t$dst, $a, $b, $acc", []>;
2066 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst),
2067 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsdx",
2068 "\t$dst, $a, $b, $acc", []>;
2069 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2070 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlald",
2071 "\t$ldst, $hdst, $a, $b", []>;
2072 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2073 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaldx",
2074 "\t$ldst, $hdst, $a, $b", []>;
2075 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2076 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsld",
2077 "\t$ldst, $hdst, $a, $b", []>;
2078 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2079 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsldx",
2080 "\t$ldst, $hdst, $a, $b", []>;
2082 //===----------------------------------------------------------------------===//
2083 // Misc. Arithmetic Instructions.
2086 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2087 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2088 : T2I<oops, iops, itin, opc, asm, pattern> {
2089 let Inst{31-27} = 0b11111;
2090 let Inst{26-22} = 0b01010;
2091 let Inst{21-20} = op1;
2092 let Inst{15-12} = 0b1111;
2093 let Inst{7-6} = 0b10;
2094 let Inst{5-4} = op2;
2097 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2098 "clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>;
2100 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2101 "rbit", "\t$dst, $src",
2102 [(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
2104 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2105 "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
2107 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2108 "rev16", ".w\t$dst, $src",
2110 (or (and (srl rGPR:$src, (i32 8)), 0xFF),
2111 (or (and (shl rGPR:$src, (i32 8)), 0xFF00),
2112 (or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
2113 (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
2115 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2116 "revsh", ".w\t$dst, $src",
2119 (or (srl (and rGPR:$src, 0xFF00), (i32 8)),
2120 (shl rGPR:$src, (i32 8))), i16))]>;
2122 def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2123 IIC_iBITsi, "pkhbt", "\t$dst, $src1, $src2$sh",
2124 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
2125 (and (shl rGPR:$src2, lsl_amt:$sh),
2127 Requires<[HasT2ExtractPack]> {
2128 let Inst{31-27} = 0b11101;
2129 let Inst{26-25} = 0b01;
2130 let Inst{24-20} = 0b01100;
2131 let Inst{5} = 0; // BT form
2135 // Alternate cases for PKHBT where identities eliminate some nodes.
2136 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2137 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2138 Requires<[HasT2ExtractPack]>;
2139 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2140 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2141 Requires<[HasT2ExtractPack]>;
2143 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2144 // will match the pattern below.
2145 def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2146 IIC_iBITsi, "pkhtb", "\t$dst, $src1, $src2$sh",
2147 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
2148 (and (sra rGPR:$src2, asr_amt:$sh),
2150 Requires<[HasT2ExtractPack]> {
2151 let Inst{31-27} = 0b11101;
2152 let Inst{26-25} = 0b01;
2153 let Inst{24-20} = 0b01100;
2154 let Inst{5} = 1; // TB form
2158 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2159 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2160 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2161 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2162 Requires<[HasT2ExtractPack]>;
2163 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2164 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2165 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2166 Requires<[HasT2ExtractPack]>;
2168 //===----------------------------------------------------------------------===//
2169 // Comparison Instructions...
2171 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2172 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2173 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2174 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2175 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2176 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2178 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2179 // Compare-to-zero still works out, just not the relationals
2180 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2181 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2182 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2183 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2184 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2186 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2187 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2189 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2190 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2192 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2193 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2194 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2195 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2196 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2197 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2199 // Conditional moves
2200 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2201 // a two-value operand where a dag node expects two operands. :(
2202 let neverHasSideEffects = 1 in {
2203 def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
2204 "mov", ".w\t$dst, $true",
2205 [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
2206 RegConstraint<"$false = $dst"> {
2207 let Inst{31-27} = 0b11101;
2208 let Inst{26-25} = 0b01;
2209 let Inst{24-21} = 0b0010;
2210 let Inst{20} = 0; // The S bit.
2211 let Inst{19-16} = 0b1111; // Rn
2212 let Inst{14-12} = 0b000;
2213 let Inst{7-4} = 0b0000;
2216 def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
2217 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2218 [/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2219 RegConstraint<"$false = $dst"> {
2220 let Inst{31-27} = 0b11110;
2222 let Inst{24-21} = 0b0010;
2223 let Inst{20} = 0; // The S bit.
2224 let Inst{19-16} = 0b1111; // Rn
2228 def t2MOVCCi16 : T2I<(outs rGPR:$dst), (ins rGPR:$false, i32imm:$src),
2230 "movw", "\t$dst, $src", []>,
2231 RegConstraint<"$false = $dst"> {
2232 let Inst{31-27} = 0b11110;
2234 let Inst{24-21} = 0b0010;
2235 let Inst{20} = 0; // The S bit.
2239 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2240 string opc, string asm, list<dag> pattern>
2241 : T2I<oops, iops, itin, opc, asm, pattern> {
2242 let Inst{31-27} = 0b11101;
2243 let Inst{26-25} = 0b01;
2244 let Inst{24-21} = 0b0010;
2245 let Inst{20} = 0; // The S bit.
2246 let Inst{19-16} = 0b1111; // Rn
2247 let Inst{5-4} = opcod; // Shift type.
2249 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$dst),
2250 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2251 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2252 RegConstraint<"$false = $dst">;
2253 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$dst),
2254 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2255 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2256 RegConstraint<"$false = $dst">;
2257 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$dst),
2258 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2259 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2260 RegConstraint<"$false = $dst">;
2261 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
2262 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2263 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2264 RegConstraint<"$false = $dst">;
2265 } // neverHasSideEffects
2267 //===----------------------------------------------------------------------===//
2268 // Atomic operations intrinsics
2271 // memory barriers protect the atomic sequences
2272 let hasSideEffects = 1 in {
2273 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2274 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2275 Requires<[IsThumb, HasDB]> {
2277 let Inst{31-4} = 0xf3bf8f5;
2278 let Inst{3-0} = opt;
2282 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2284 [/* For disassembly only; pattern left blank */]>,
2285 Requires<[IsThumb, HasDB]> {
2287 let Inst{31-4} = 0xf3bf8f4;
2288 let Inst{3-0} = opt;
2291 // ISB has only full system option -- for disassembly only
2292 def t2ISB : T2I<(outs), (ins), NoItinerary, "isb", "",
2293 [/* For disassembly only; pattern left blank */]>,
2294 Requires<[IsThumb2, HasV7]> {
2295 let Inst{31-4} = 0xf3bf8f6;
2296 let Inst{3-0} = 0b1111;
2299 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2300 InstrItinClass itin, string opc, string asm, string cstr,
2301 list<dag> pattern, bits<4> rt2 = 0b1111>
2302 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2303 let Inst{31-27} = 0b11101;
2304 let Inst{26-20} = 0b0001101;
2305 let Inst{11-8} = rt2;
2306 let Inst{7-6} = 0b01;
2307 let Inst{5-4} = opcod;
2308 let Inst{3-0} = 0b1111;
2310 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2311 InstrItinClass itin, string opc, string asm, string cstr,
2312 list<dag> pattern, bits<4> rt2 = 0b1111>
2313 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2314 let Inst{31-27} = 0b11101;
2315 let Inst{26-20} = 0b0001100;
2316 let Inst{11-8} = rt2;
2317 let Inst{7-6} = 0b01;
2318 let Inst{5-4} = opcod;
2321 let mayLoad = 1 in {
2322 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2323 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2325 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2326 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2328 def t2LDREX : Thumb2I<(outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2329 Size4Bytes, NoItinerary,
2330 "ldrex", "\t$dest, [$ptr]", "",
2332 let Inst{31-27} = 0b11101;
2333 let Inst{26-20} = 0b0000101;
2334 let Inst{11-8} = 0b1111;
2335 let Inst{7-0} = 0b00000000; // imm8 = 0
2337 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$dest, rGPR:$dest2), (ins rGPR:$ptr),
2338 AddrModeNone, Size4Bytes, NoItinerary,
2339 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2343 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2344 def t2STREXB : T2I_strex<0b00, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2345 AddrModeNone, Size4Bytes, NoItinerary,
2346 "strexb", "\t$success, $src, [$ptr]", "", []>;
2347 def t2STREXH : T2I_strex<0b01, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2348 AddrModeNone, Size4Bytes, NoItinerary,
2349 "strexh", "\t$success, $src, [$ptr]", "", []>;
2350 def t2STREX : Thumb2I<(outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2351 AddrModeNone, Size4Bytes, NoItinerary,
2352 "strex", "\t$success, $src, [$ptr]", "",
2354 let Inst{31-27} = 0b11101;
2355 let Inst{26-20} = 0b0000100;
2356 let Inst{7-0} = 0b00000000; // imm8 = 0
2358 def t2STREXD : T2I_strex<0b11, (outs rGPR:$success),
2359 (ins rGPR:$src, rGPR:$src2, rGPR:$ptr),
2360 AddrModeNone, Size4Bytes, NoItinerary,
2361 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2365 // Clear-Exclusive is for disassembly only.
2366 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2367 [/* For disassembly only; pattern left blank */]>,
2368 Requires<[IsARM, HasV7]> {
2369 let Inst{31-20} = 0xf3b;
2370 let Inst{15-14} = 0b10;
2372 let Inst{7-4} = 0b0010;
2375 //===----------------------------------------------------------------------===//
2379 // __aeabi_read_tp preserves the registers r1-r3.
2381 Defs = [R0, R12, LR, CPSR] in {
2382 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2383 "bl\t__aeabi_read_tp",
2384 [(set R0, ARMthread_pointer)]> {
2385 let Inst{31-27} = 0b11110;
2386 let Inst{15-14} = 0b11;
2391 //===----------------------------------------------------------------------===//
2392 // SJLJ Exception handling intrinsics
2393 // eh_sjlj_setjmp() is an instruction sequence to store the return
2394 // address and save #0 in R0 for the non-longjmp case.
2395 // Since by its nature we may be coming from some other function to get
2396 // here, and we're using the stack frame for the containing function to
2397 // save/restore registers, we can't keep anything live in regs across
2398 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2399 // when we get here from a longjmp(). We force everthing out of registers
2400 // except for our own input by listing the relevant registers in Defs. By
2401 // doing so, we also cause the prologue/epilogue code to actively preserve
2402 // all of the callee-saved resgisters, which is exactly what we want.
2403 // $val is a scratch register for our use.
2405 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2406 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2407 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2408 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2409 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2410 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2411 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2412 Requires<[IsThumb2, HasVFP2]>;
2416 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2417 hasSideEffects = 1, isBarrier = 1 in {
2418 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2419 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2420 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2421 Requires<[IsThumb2, NoVFP]>;
2425 //===----------------------------------------------------------------------===//
2426 // Control-Flow Instructions
2429 // FIXME: remove when we have a way to marking a MI with these properties.
2430 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2432 // FIXME: Should pc be an implicit operand like PICADD, etc?
2433 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2434 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2435 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
2436 reglist:$dsts, variable_ops),
2438 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
2439 "$addr.addr = $wb", []> {
2440 let Inst{31-27} = 0b11101;
2441 let Inst{26-25} = 0b00;
2442 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2444 let Inst{21} = 1; // The W bit.
2445 let Inst{20} = 1; // Load
2448 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2449 let isPredicable = 1 in
2450 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2452 [(br bb:$target)]> {
2453 let Inst{31-27} = 0b11110;
2454 let Inst{15-14} = 0b10;
2458 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2461 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2462 IIC_Br, "mov\tpc, $target$jt",
2463 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2464 let Inst{31-27} = 0b11101;
2465 let Inst{26-20} = 0b0100100;
2466 let Inst{19-16} = 0b1111;
2467 let Inst{14-12} = 0b000;
2468 let Inst{11-8} = 0b1111; // Rd = pc
2469 let Inst{7-4} = 0b0000;
2472 // FIXME: Add a non-pc based case that can be predicated.
2475 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2476 IIC_Br, "tbb\t$index$jt", []> {
2477 let Inst{31-27} = 0b11101;
2478 let Inst{26-20} = 0b0001101;
2479 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2480 let Inst{15-8} = 0b11110000;
2481 let Inst{7-4} = 0b0000; // B form
2486 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2487 IIC_Br, "tbh\t$index$jt", []> {
2488 let Inst{31-27} = 0b11101;
2489 let Inst{26-20} = 0b0001101;
2490 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2491 let Inst{15-8} = 0b11110000;
2492 let Inst{7-4} = 0b0001; // H form
2495 // Generic versions of the above two instructions, for disassembly only
2497 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2498 "tbb", "\t[$a, $b]", []>{
2499 let Inst{31-27} = 0b11101;
2500 let Inst{26-20} = 0b0001101;
2501 let Inst{15-8} = 0b11110000;
2502 let Inst{7-4} = 0b0000; // B form
2505 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2506 "tbh", "\t[$a, $b, lsl #1]", []> {
2507 let Inst{31-27} = 0b11101;
2508 let Inst{26-20} = 0b0001101;
2509 let Inst{15-8} = 0b11110000;
2510 let Inst{7-4} = 0b0001; // H form
2512 } // isNotDuplicable, isIndirectBranch
2514 } // isBranch, isTerminator, isBarrier
2516 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2517 // a two-value operand where a dag node expects two operands. :(
2518 let isBranch = 1, isTerminator = 1 in
2519 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2521 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2522 let Inst{31-27} = 0b11110;
2523 let Inst{15-14} = 0b10;
2529 let Defs = [ITSTATE] in
2530 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2531 AddrModeNone, Size2Bytes, IIC_iALUx,
2532 "it$mask\t$cc", "", []> {
2533 // 16-bit instruction.
2534 let Inst{31-16} = 0x0000;
2535 let Inst{15-8} = 0b10111111;
2538 // Branch and Exchange Jazelle -- for disassembly only
2540 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
2541 [/* For disassembly only; pattern left blank */]> {
2542 let Inst{31-27} = 0b11110;
2544 let Inst{25-20} = 0b111100;
2545 let Inst{15-14} = 0b10;
2549 // Change Processor State is a system instruction -- for disassembly only.
2550 // The singleton $opt operand contains the following information:
2551 // opt{4-0} = mode from Inst{4-0}
2552 // opt{5} = changemode from Inst{17}
2553 // opt{8-6} = AIF from Inst{8-6}
2554 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2555 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2556 [/* For disassembly only; pattern left blank */]> {
2557 let Inst{31-27} = 0b11110;
2559 let Inst{25-20} = 0b111010;
2560 let Inst{15-14} = 0b10;
2564 // A6.3.4 Branches and miscellaneous control
2565 // Table A6-14 Change Processor State, and hint instructions
2566 // Helper class for disassembly only.
2567 class T2I_hint<bits<8> op7_0, string opc, string asm>
2568 : T2I<(outs), (ins), NoItinerary, opc, asm,
2569 [/* For disassembly only; pattern left blank */]> {
2570 let Inst{31-20} = 0xf3a;
2571 let Inst{15-14} = 0b10;
2573 let Inst{10-8} = 0b000;
2574 let Inst{7-0} = op7_0;
2577 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2578 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2579 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2580 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2581 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2583 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2584 [/* For disassembly only; pattern left blank */]> {
2585 let Inst{31-20} = 0xf3a;
2586 let Inst{15-14} = 0b10;
2588 let Inst{10-8} = 0b000;
2589 let Inst{7-4} = 0b1111;
2592 // Secure Monitor Call is a system instruction -- for disassembly only
2593 // Option = Inst{19-16}
2594 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2595 [/* For disassembly only; pattern left blank */]> {
2596 let Inst{31-27} = 0b11110;
2597 let Inst{26-20} = 0b1111111;
2598 let Inst{15-12} = 0b1000;
2601 // Store Return State is a system instruction -- for disassembly only
2602 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2603 [/* For disassembly only; pattern left blank */]> {
2604 let Inst{31-27} = 0b11101;
2605 let Inst{26-20} = 0b0000010; // W = 1
2608 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2609 [/* For disassembly only; pattern left blank */]> {
2610 let Inst{31-27} = 0b11101;
2611 let Inst{26-20} = 0b0000000; // W = 0
2614 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2615 [/* For disassembly only; pattern left blank */]> {
2616 let Inst{31-27} = 0b11101;
2617 let Inst{26-20} = 0b0011010; // W = 1
2620 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2621 [/* For disassembly only; pattern left blank */]> {
2622 let Inst{31-27} = 0b11101;
2623 let Inst{26-20} = 0b0011000; // W = 0
2626 // Return From Exception is a system instruction -- for disassembly only
2627 def t2RFEDBW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfedb", "\t$base!",
2628 [/* For disassembly only; pattern left blank */]> {
2629 let Inst{31-27} = 0b11101;
2630 let Inst{26-20} = 0b0000011; // W = 1
2633 def t2RFEDB : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeab", "\t$base",
2634 [/* For disassembly only; pattern left blank */]> {
2635 let Inst{31-27} = 0b11101;
2636 let Inst{26-20} = 0b0000001; // W = 0
2639 def t2RFEIAW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base!",
2640 [/* For disassembly only; pattern left blank */]> {
2641 let Inst{31-27} = 0b11101;
2642 let Inst{26-20} = 0b0011011; // W = 1
2645 def t2RFEIA : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base",
2646 [/* For disassembly only; pattern left blank */]> {
2647 let Inst{31-27} = 0b11101;
2648 let Inst{26-20} = 0b0011001; // W = 0
2651 //===----------------------------------------------------------------------===//
2652 // Non-Instruction Patterns
2655 // Two piece so_imms.
2656 def : T2Pat<(or rGPR:$LHS, t2_so_imm2part:$RHS),
2657 (t2ORRri (t2ORRri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2658 (t2_so_imm2part_2 imm:$RHS))>;
2659 def : T2Pat<(xor rGPR:$LHS, t2_so_imm2part:$RHS),
2660 (t2EORri (t2EORri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2661 (t2_so_imm2part_2 imm:$RHS))>;
2662 def : T2Pat<(add rGPR:$LHS, t2_so_imm2part:$RHS),
2663 (t2ADDri (t2ADDri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2664 (t2_so_imm2part_2 imm:$RHS))>;
2665 def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS),
2666 (t2SUBri (t2SUBri rGPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2667 (t2_so_neg_imm2part_2 imm:$RHS))>;
2669 // 32-bit immediate using movw + movt.
2670 // This is a single pseudo instruction to make it re-materializable.
2671 // FIXME: Remove this when we can do generalized remat.
2672 let isReMaterializable = 1 in
2673 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
2674 "", [(set rGPR:$dst, (i32 imm:$src))]>,
2675 Requires<[IsThumb, HasV6T2]>;
2677 // ConstantPool, GlobalAddress, and JumpTable
2678 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2679 Requires<[IsThumb2, DontUseMovt]>;
2680 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2681 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2682 Requires<[IsThumb2, UseMovt]>;
2684 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2685 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2687 // Pseudo instruction that combines ldr from constpool and add pc. This should
2688 // be expanded into two instructions late to allow if-conversion and
2690 let canFoldAsLoad = 1, isReMaterializable = 1 in
2691 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2693 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2695 Requires<[IsThumb2]>;
2697 //===----------------------------------------------------------------------===//
2698 // Move between special register and ARM core register -- for disassembly only
2702 def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2703 [/* For disassembly only; pattern left blank */]> {
2704 let Inst{31-27} = 0b11110;
2706 let Inst{25-21} = 0b11111;
2707 let Inst{20} = 0; // The R bit.
2708 let Inst{15-14} = 0b10;
2713 def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2714 [/* For disassembly only; pattern left blank */]> {
2715 let Inst{31-27} = 0b11110;
2717 let Inst{25-21} = 0b11111;
2718 let Inst{20} = 1; // The R bit.
2719 let Inst{15-14} = 0b10;
2724 def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2725 "\tcpsr$mask, $src",
2726 [/* For disassembly only; pattern left blank */]> {
2727 let Inst{31-27} = 0b11110;
2729 let Inst{25-21} = 0b11100;
2730 let Inst{20} = 0; // The R bit.
2731 let Inst{15-14} = 0b10;
2736 def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2737 "\tspsr$mask, $src",
2738 [/* For disassembly only; pattern left blank */]> {
2739 let Inst{31-27} = 0b11110;
2741 let Inst{25-21} = 0b11100;
2742 let Inst{20} = 1; // The R bit.
2743 let Inst{15-14} = 0b10;