1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let EncoderMethod = "getT2SORegOpValue";
30 let PrintMethod = "printT2SOOperand";
31 let MIOperandInfo = (ops rGPR, i32imm);
34 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
44 // t2_so_imm - Match a 32-bit immediate operand, which is an
45 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46 // immediate splatted into multiple bytes of the word.
47 def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> {
48 let EncoderMethod = "getT2SOImmOpValue";
51 // t2_so_imm_not - Match an immediate that is a complement
53 def t2_so_imm_not : Operand<i32>,
55 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
56 }], t2_so_imm_not_XFORM>;
58 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
59 def t2_so_imm_neg : Operand<i32>,
61 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
62 }], t2_so_imm_neg_XFORM>;
64 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
65 def imm1_31 : PatLeaf<(i32 imm), [{
66 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
69 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
70 def imm0_4095 : Operand<i32>,
72 return (uint32_t)N->getZExtValue() < 4096;
75 def imm0_4095_neg : PatLeaf<(i32 imm), [{
76 return (uint32_t)(-N->getZExtValue()) < 4096;
79 def imm0_255_neg : PatLeaf<(i32 imm), [{
80 return (uint32_t)(-N->getZExtValue()) < 255;
83 def imm0_255_not : PatLeaf<(i32 imm), [{
84 return (uint32_t)(~N->getZExtValue()) < 255;
87 // Define Thumb2 specific addressing modes.
89 // t2addrmode_imm12 := reg + imm12
90 def t2addrmode_imm12 : Operand<i32>,
91 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
92 let PrintMethod = "printAddrModeImm12Operand";
93 let EncoderMethod = "getAddrModeImm12OpValue";
94 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
95 let ParserMatchClass = MemMode5AsmOperand;
98 // t2ldrlabel := imm12
99 def t2ldrlabel : Operand<i32> {
100 let EncoderMethod = "getAddrModeImm12OpValue";
104 // ADR instruction labels.
105 def t2adrlabel : Operand<i32> {
106 let EncoderMethod = "getT2AdrLabelOpValue";
110 // t2addrmode_imm8 := reg +/- imm8
111 def t2addrmode_imm8 : Operand<i32>,
112 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
113 let PrintMethod = "printT2AddrModeImm8Operand";
114 let EncoderMethod = "getT2AddrModeImm8OpValue";
115 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
116 let ParserMatchClass = MemMode5AsmOperand;
119 def t2am_imm8_offset : Operand<i32>,
120 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
121 [], [SDNPWantRoot]> {
122 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
123 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
124 let ParserMatchClass = MemMode5AsmOperand;
127 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
128 def t2addrmode_imm8s4 : Operand<i32> {
129 let PrintMethod = "printT2AddrModeImm8s4Operand";
130 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
132 let ParserMatchClass = MemMode5AsmOperand;
135 def t2am_imm8s4_offset : Operand<i32> {
136 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
139 // t2addrmode_so_reg := reg + (reg << imm2)
140 def t2addrmode_so_reg : Operand<i32>,
141 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
142 let PrintMethod = "printT2AddrModeSoRegOperand";
143 let EncoderMethod = "getT2AddrModeSORegOpValue";
144 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
145 let ParserMatchClass = MemMode5AsmOperand;
148 // t2addrmode_reg := reg
149 // Used by load/store exclusive instructions. Useful to enable right assembly
150 // parsing and printing. Not used for any codegen matching.
152 def t2addrmode_reg : Operand<i32> {
153 let PrintMethod = "printAddrMode7Operand";
154 let MIOperandInfo = (ops tGPR);
155 let ParserMatchClass = MemMode7AsmOperand;
158 //===----------------------------------------------------------------------===//
159 // Multiclass helpers...
163 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
164 string opc, string asm, list<dag> pattern>
165 : T2I<oops, iops, itin, opc, asm, pattern> {
170 let Inst{26} = imm{11};
171 let Inst{14-12} = imm{10-8};
172 let Inst{7-0} = imm{7-0};
176 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
177 string opc, string asm, list<dag> pattern>
178 : T2sI<oops, iops, itin, opc, asm, pattern> {
184 let Inst{26} = imm{11};
185 let Inst{14-12} = imm{10-8};
186 let Inst{7-0} = imm{7-0};
189 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
190 string opc, string asm, list<dag> pattern>
191 : T2I<oops, iops, itin, opc, asm, pattern> {
195 let Inst{19-16} = Rn;
196 let Inst{26} = imm{11};
197 let Inst{14-12} = imm{10-8};
198 let Inst{7-0} = imm{7-0};
202 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
203 string opc, string asm, list<dag> pattern>
204 : T2I<oops, iops, itin, opc, asm, pattern> {
209 let Inst{3-0} = ShiftedRm{3-0};
210 let Inst{5-4} = ShiftedRm{6-5};
211 let Inst{14-12} = ShiftedRm{11-9};
212 let Inst{7-6} = ShiftedRm{8-7};
215 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
216 string opc, string asm, list<dag> pattern>
217 : T2sI<oops, iops, itin, opc, asm, pattern> {
222 let Inst{3-0} = ShiftedRm{3-0};
223 let Inst{5-4} = ShiftedRm{6-5};
224 let Inst{14-12} = ShiftedRm{11-9};
225 let Inst{7-6} = ShiftedRm{8-7};
228 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
229 string opc, string asm, list<dag> pattern>
230 : T2I<oops, iops, itin, opc, asm, pattern> {
234 let Inst{19-16} = Rn;
235 let Inst{3-0} = ShiftedRm{3-0};
236 let Inst{5-4} = ShiftedRm{6-5};
237 let Inst{14-12} = ShiftedRm{11-9};
238 let Inst{7-6} = ShiftedRm{8-7};
241 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
242 string opc, string asm, list<dag> pattern>
243 : T2I<oops, iops, itin, opc, asm, pattern> {
251 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
252 string opc, string asm, list<dag> pattern>
253 : T2sI<oops, iops, itin, opc, asm, pattern> {
261 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
262 string opc, string asm, list<dag> pattern>
263 : T2I<oops, iops, itin, opc, asm, pattern> {
267 let Inst{19-16} = Rn;
272 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
273 string opc, string asm, list<dag> pattern>
274 : T2I<oops, iops, itin, opc, asm, pattern> {
280 let Inst{19-16} = Rn;
281 let Inst{26} = imm{11};
282 let Inst{14-12} = imm{10-8};
283 let Inst{7-0} = imm{7-0};
286 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
287 string opc, string asm, list<dag> pattern>
288 : T2sI<oops, iops, itin, opc, asm, pattern> {
294 let Inst{19-16} = Rn;
295 let Inst{26} = imm{11};
296 let Inst{14-12} = imm{10-8};
297 let Inst{7-0} = imm{7-0};
300 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
301 string opc, string asm, list<dag> pattern>
302 : T2I<oops, iops, itin, opc, asm, pattern> {
309 let Inst{14-12} = imm{4-2};
310 let Inst{7-6} = imm{1-0};
313 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
314 string opc, string asm, list<dag> pattern>
315 : T2sI<oops, iops, itin, opc, asm, pattern> {
322 let Inst{14-12} = imm{4-2};
323 let Inst{7-6} = imm{1-0};
326 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
327 string opc, string asm, list<dag> pattern>
328 : T2I<oops, iops, itin, opc, asm, pattern> {
334 let Inst{19-16} = Rn;
338 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
339 string opc, string asm, list<dag> pattern>
340 : T2sI<oops, iops, itin, opc, asm, pattern> {
346 let Inst{19-16} = Rn;
350 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
351 string opc, string asm, list<dag> pattern>
352 : T2I<oops, iops, itin, opc, asm, pattern> {
358 let Inst{19-16} = Rn;
359 let Inst{3-0} = ShiftedRm{3-0};
360 let Inst{5-4} = ShiftedRm{6-5};
361 let Inst{14-12} = ShiftedRm{11-9};
362 let Inst{7-6} = ShiftedRm{8-7};
365 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
366 string opc, string asm, list<dag> pattern>
367 : T2sI<oops, iops, itin, opc, asm, pattern> {
373 let Inst{19-16} = Rn;
374 let Inst{3-0} = ShiftedRm{3-0};
375 let Inst{5-4} = ShiftedRm{6-5};
376 let Inst{14-12} = ShiftedRm{11-9};
377 let Inst{7-6} = ShiftedRm{8-7};
380 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
381 string opc, string asm, list<dag> pattern>
382 : T2I<oops, iops, itin, opc, asm, pattern> {
388 let Inst{19-16} = Rn;
389 let Inst{15-12} = Ra;
394 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
395 dag oops, dag iops, InstrItinClass itin,
396 string opc, string asm, list<dag> pattern>
397 : T2I<oops, iops, itin, opc, asm, pattern> {
403 let Inst{31-23} = 0b111110111;
404 let Inst{22-20} = opc22_20;
405 let Inst{19-16} = Rn;
406 let Inst{15-12} = RdLo;
407 let Inst{11-8} = RdHi;
408 let Inst{7-4} = opc7_4;
413 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
414 /// unary operation that produces a value. These are predicable and can be
415 /// changed to modify CPSR.
416 multiclass T2I_un_irs<bits<4> opcod, string opc,
417 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
418 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
420 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
422 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
423 let isAsCheapAsAMove = Cheap;
424 let isReMaterializable = ReMat;
425 let Inst{31-27} = 0b11110;
427 let Inst{24-21} = opcod;
428 let Inst{19-16} = 0b1111; // Rn
432 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
434 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
435 let Inst{31-27} = 0b11101;
436 let Inst{26-25} = 0b01;
437 let Inst{24-21} = opcod;
438 let Inst{19-16} = 0b1111; // Rn
439 let Inst{14-12} = 0b000; // imm3
440 let Inst{7-6} = 0b00; // imm2
441 let Inst{5-4} = 0b00; // type
444 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
445 opc, ".w\t$Rd, $ShiftedRm",
446 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
447 let Inst{31-27} = 0b11101;
448 let Inst{26-25} = 0b01;
449 let Inst{24-21} = opcod;
450 let Inst{19-16} = 0b1111; // Rn
454 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
455 /// binary operation that produces a value. These are predicable and can be
456 /// changed to modify CPSR.
457 multiclass T2I_bin_irs<bits<4> opcod, string opc,
458 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
459 PatFrag opnode, bit Commutable = 0, string wide = ""> {
461 def ri : T2sTwoRegImm<
462 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
463 opc, "\t$Rd, $Rn, $imm",
464 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
465 let Inst{31-27} = 0b11110;
467 let Inst{24-21} = opcod;
471 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
472 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
473 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
474 let isCommutable = Commutable;
475 let Inst{31-27} = 0b11101;
476 let Inst{26-25} = 0b01;
477 let Inst{24-21} = opcod;
478 let Inst{14-12} = 0b000; // imm3
479 let Inst{7-6} = 0b00; // imm2
480 let Inst{5-4} = 0b00; // type
483 def rs : T2sTwoRegShiftedReg<
484 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
485 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
486 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
487 let Inst{31-27} = 0b11101;
488 let Inst{26-25} = 0b01;
489 let Inst{24-21} = opcod;
493 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
494 // the ".w" prefix to indicate that they are wide.
495 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
496 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
497 PatFrag opnode, bit Commutable = 0> :
498 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">;
500 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
501 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
502 /// it is equivalent to the T2I_bin_irs counterpart.
503 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
505 def ri : T2sTwoRegImm<
506 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
507 opc, ".w\t$Rd, $Rn, $imm",
508 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
509 let Inst{31-27} = 0b11110;
511 let Inst{24-21} = opcod;
515 def rr : T2sThreeReg<
516 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
517 opc, "\t$Rd, $Rn, $Rm",
518 [/* For disassembly only; pattern left blank */]> {
519 let Inst{31-27} = 0b11101;
520 let Inst{26-25} = 0b01;
521 let Inst{24-21} = opcod;
522 let Inst{14-12} = 0b000; // imm3
523 let Inst{7-6} = 0b00; // imm2
524 let Inst{5-4} = 0b00; // type
527 def rs : T2sTwoRegShiftedReg<
528 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
529 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
530 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
531 let Inst{31-27} = 0b11101;
532 let Inst{26-25} = 0b01;
533 let Inst{24-21} = opcod;
537 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
538 /// instruction modifies the CPSR register.
539 let isCodeGenOnly = 1, Defs = [CPSR] in {
540 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
541 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
542 PatFrag opnode, bit Commutable = 0> {
544 def ri : T2TwoRegImm<
545 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
546 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
547 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
548 let Inst{31-27} = 0b11110;
550 let Inst{24-21} = opcod;
551 let Inst{20} = 1; // The S bit.
556 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
557 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
558 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
559 let isCommutable = Commutable;
560 let Inst{31-27} = 0b11101;
561 let Inst{26-25} = 0b01;
562 let Inst{24-21} = opcod;
563 let Inst{20} = 1; // The S bit.
564 let Inst{14-12} = 0b000; // imm3
565 let Inst{7-6} = 0b00; // imm2
566 let Inst{5-4} = 0b00; // type
569 def rs : T2TwoRegShiftedReg<
570 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
571 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
572 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
573 let Inst{31-27} = 0b11101;
574 let Inst{26-25} = 0b01;
575 let Inst{24-21} = opcod;
576 let Inst{20} = 1; // The S bit.
581 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
582 /// patterns for a binary operation that produces a value.
583 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
584 bit Commutable = 0> {
586 // The register-immediate version is re-materializable. This is useful
587 // in particular for taking the address of a local.
588 let isReMaterializable = 1 in {
589 def ri : T2sTwoRegImm<
590 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
591 opc, ".w\t$Rd, $Rn, $imm",
592 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
593 let Inst{31-27} = 0b11110;
596 let Inst{23-21} = op23_21;
602 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
603 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
604 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
608 let Inst{31-27} = 0b11110;
609 let Inst{26} = imm{11};
610 let Inst{25-24} = 0b10;
611 let Inst{23-21} = op23_21;
612 let Inst{20} = 0; // The S bit.
613 let Inst{19-16} = Rn;
615 let Inst{14-12} = imm{10-8};
617 let Inst{7-0} = imm{7-0};
620 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
621 opc, ".w\t$Rd, $Rn, $Rm",
622 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
623 let isCommutable = Commutable;
624 let Inst{31-27} = 0b11101;
625 let Inst{26-25} = 0b01;
627 let Inst{23-21} = op23_21;
628 let Inst{14-12} = 0b000; // imm3
629 let Inst{7-6} = 0b00; // imm2
630 let Inst{5-4} = 0b00; // type
633 def rs : T2sTwoRegShiftedReg<
634 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
635 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
636 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
637 let Inst{31-27} = 0b11101;
638 let Inst{26-25} = 0b01;
640 let Inst{23-21} = op23_21;
644 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
645 /// for a binary operation that produces a value and use the carry
646 /// bit. It's not predicable.
647 let Uses = [CPSR] in {
648 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
649 bit Commutable = 0> {
651 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
652 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
653 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
654 Requires<[IsThumb2]> {
655 let Inst{31-27} = 0b11110;
657 let Inst{24-21} = opcod;
661 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
662 opc, ".w\t$Rd, $Rn, $Rm",
663 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
664 Requires<[IsThumb2]> {
665 let isCommutable = Commutable;
666 let Inst{31-27} = 0b11101;
667 let Inst{26-25} = 0b01;
668 let Inst{24-21} = opcod;
669 let Inst{14-12} = 0b000; // imm3
670 let Inst{7-6} = 0b00; // imm2
671 let Inst{5-4} = 0b00; // type
674 def rs : T2sTwoRegShiftedReg<
675 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
676 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
677 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
678 Requires<[IsThumb2]> {
679 let Inst{31-27} = 0b11101;
680 let Inst{26-25} = 0b01;
681 let Inst{24-21} = opcod;
685 // Carry setting variants
686 let isCodeGenOnly = 1, Defs = [CPSR] in {
687 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
688 bit Commutable = 0> {
690 def ri : T2sTwoRegImm<
691 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
692 opc, "\t$Rd, $Rn, $imm",
693 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
694 Requires<[IsThumb2]> {
695 let Inst{31-27} = 0b11110;
697 let Inst{24-21} = opcod;
698 let Inst{20} = 1; // The S bit.
702 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
703 opc, ".w\t$Rd, $Rn, $Rm",
704 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
705 Requires<[IsThumb2]> {
706 let isCommutable = Commutable;
707 let Inst{31-27} = 0b11101;
708 let Inst{26-25} = 0b01;
709 let Inst{24-21} = opcod;
710 let Inst{20} = 1; // The S bit.
711 let Inst{14-12} = 0b000; // imm3
712 let Inst{7-6} = 0b00; // imm2
713 let Inst{5-4} = 0b00; // type
716 def rs : T2sTwoRegShiftedReg<
717 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
718 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
719 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
720 Requires<[IsThumb2]> {
721 let Inst{31-27} = 0b11101;
722 let Inst{26-25} = 0b01;
723 let Inst{24-21} = opcod;
724 let Inst{20} = 1; // The S bit.
730 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
731 /// version is not needed since this is only for codegen.
732 let isCodeGenOnly = 1, Defs = [CPSR] in {
733 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
735 def ri : T2TwoRegImm<
736 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
737 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
738 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
739 let Inst{31-27} = 0b11110;
741 let Inst{24-21} = opcod;
742 let Inst{20} = 1; // The S bit.
746 def rs : T2TwoRegShiftedReg<
747 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
748 IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
749 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
750 let Inst{31-27} = 0b11101;
751 let Inst{26-25} = 0b01;
752 let Inst{24-21} = opcod;
753 let Inst{20} = 1; // The S bit.
758 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
759 // rotate operation that produces a value.
760 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
762 def ri : T2sTwoRegShiftImm<
763 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
764 opc, ".w\t$Rd, $Rm, $imm",
765 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
766 let Inst{31-27} = 0b11101;
767 let Inst{26-21} = 0b010010;
768 let Inst{19-16} = 0b1111; // Rn
769 let Inst{5-4} = opcod;
772 def rr : T2sThreeReg<
773 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
774 opc, ".w\t$Rd, $Rn, $Rm",
775 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
776 let Inst{31-27} = 0b11111;
777 let Inst{26-23} = 0b0100;
778 let Inst{22-21} = opcod;
779 let Inst{15-12} = 0b1111;
780 let Inst{7-4} = 0b0000;
784 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
785 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
786 /// a explicit result, only implicitly set CPSR.
787 let isCompare = 1, Defs = [CPSR] in {
788 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
789 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
792 def ri : T2OneRegCmpImm<
793 (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
794 opc, ".w\t$Rn, $imm",
795 [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
796 let Inst{31-27} = 0b11110;
798 let Inst{24-21} = opcod;
799 let Inst{20} = 1; // The S bit.
801 let Inst{11-8} = 0b1111; // Rd
804 def rr : T2TwoRegCmp<
805 (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
806 opc, ".w\t$lhs, $rhs",
807 [(opnode GPR:$lhs, rGPR:$rhs)]> {
808 let Inst{31-27} = 0b11101;
809 let Inst{26-25} = 0b01;
810 let Inst{24-21} = opcod;
811 let Inst{20} = 1; // The S bit.
812 let Inst{14-12} = 0b000; // imm3
813 let Inst{11-8} = 0b1111; // Rd
814 let Inst{7-6} = 0b00; // imm2
815 let Inst{5-4} = 0b00; // type
818 def rs : T2OneRegCmpShiftedReg<
819 (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
820 opc, ".w\t$Rn, $ShiftedRm",
821 [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
822 let Inst{31-27} = 0b11101;
823 let Inst{26-25} = 0b01;
824 let Inst{24-21} = opcod;
825 let Inst{20} = 1; // The S bit.
826 let Inst{11-8} = 0b1111; // Rd
831 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
832 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
833 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
834 def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
835 opc, ".w\t$Rt, $addr",
836 [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
837 let Inst{31-27} = 0b11111;
838 let Inst{26-25} = 0b00;
839 let Inst{24} = signed;
841 let Inst{22-21} = opcod;
842 let Inst{20} = 1; // load
845 let Inst{15-12} = Rt;
848 let addr{12} = 1; // add = TRUE
849 let Inst{19-16} = addr{16-13}; // Rn
850 let Inst{23} = addr{12}; // U
851 let Inst{11-0} = addr{11-0}; // imm
853 def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
855 [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
856 let Inst{31-27} = 0b11111;
857 let Inst{26-25} = 0b00;
858 let Inst{24} = signed;
860 let Inst{22-21} = opcod;
861 let Inst{20} = 1; // load
863 // Offset: index==TRUE, wback==FALSE
864 let Inst{10} = 1; // The P bit.
865 let Inst{8} = 0; // The W bit.
868 let Inst{15-12} = Rt;
871 let Inst{19-16} = addr{12-9}; // Rn
872 let Inst{9} = addr{8}; // U
873 let Inst{7-0} = addr{7-0}; // imm
875 def s : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
876 opc, ".w\t$Rt, $addr",
877 [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
878 let Inst{31-27} = 0b11111;
879 let Inst{26-25} = 0b00;
880 let Inst{24} = signed;
882 let Inst{22-21} = opcod;
883 let Inst{20} = 1; // load
884 let Inst{11-6} = 0b000000;
887 let Inst{15-12} = Rt;
890 let Inst{19-16} = addr{9-6}; // Rn
891 let Inst{3-0} = addr{5-2}; // Rm
892 let Inst{5-4} = addr{1-0}; // imm
895 // FIXME: Is the pci variant actually needed?
896 def pci : T2Ipc <(outs GPR:$Rt), (ins t2ldrlabel:$addr), iii,
897 opc, ".w\t$Rt, $addr",
898 [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
899 let isReMaterializable = 1;
900 let Inst{31-27} = 0b11111;
901 let Inst{26-25} = 0b00;
902 let Inst{24} = signed;
903 let Inst{23} = ?; // add = (U == '1')
904 let Inst{22-21} = opcod;
905 let Inst{20} = 1; // load
906 let Inst{19-16} = 0b1111; // Rn
909 let Inst{15-12} = Rt{3-0};
910 let Inst{11-0} = addr{11-0};
914 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
915 multiclass T2I_st<bits<2> opcod, string opc,
916 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
917 def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
918 opc, ".w\t$Rt, $addr",
919 [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
920 let Inst{31-27} = 0b11111;
921 let Inst{26-23} = 0b0001;
922 let Inst{22-21} = opcod;
923 let Inst{20} = 0; // !load
926 let Inst{15-12} = Rt;
929 let addr{12} = 1; // add = TRUE
930 let Inst{19-16} = addr{16-13}; // Rn
931 let Inst{23} = addr{12}; // U
932 let Inst{11-0} = addr{11-0}; // imm
934 def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
936 [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
937 let Inst{31-27} = 0b11111;
938 let Inst{26-23} = 0b0000;
939 let Inst{22-21} = opcod;
940 let Inst{20} = 0; // !load
942 // Offset: index==TRUE, wback==FALSE
943 let Inst{10} = 1; // The P bit.
944 let Inst{8} = 0; // The W bit.
947 let Inst{15-12} = Rt;
950 let Inst{19-16} = addr{12-9}; // Rn
951 let Inst{9} = addr{8}; // U
952 let Inst{7-0} = addr{7-0}; // imm
954 def s : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
955 opc, ".w\t$Rt, $addr",
956 [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
957 let Inst{31-27} = 0b11111;
958 let Inst{26-23} = 0b0000;
959 let Inst{22-21} = opcod;
960 let Inst{20} = 0; // !load
961 let Inst{11-6} = 0b000000;
964 let Inst{15-12} = Rt;
967 let Inst{19-16} = addr{9-6}; // Rn
968 let Inst{3-0} = addr{5-2}; // Rm
969 let Inst{5-4} = addr{1-0}; // imm
973 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
974 /// register and one whose operand is a register rotated by 8/16/24.
975 multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
976 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
978 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
979 let Inst{31-27} = 0b11111;
980 let Inst{26-23} = 0b0100;
981 let Inst{22-20} = opcod;
982 let Inst{19-16} = 0b1111; // Rn
983 let Inst{15-12} = 0b1111;
985 let Inst{5-4} = 0b00; // rotate
987 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
988 opc, ".w\t$Rd, $Rm, ror $rot",
989 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
990 let Inst{31-27} = 0b11111;
991 let Inst{26-23} = 0b0100;
992 let Inst{22-20} = opcod;
993 let Inst{19-16} = 0b1111; // Rn
994 let Inst{15-12} = 0b1111;
998 let Inst{5-4} = rot{1-0}; // rotate
1002 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1003 multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
1004 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1006 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
1007 Requires<[HasT2ExtractPack, IsThumb2]> {
1008 let Inst{31-27} = 0b11111;
1009 let Inst{26-23} = 0b0100;
1010 let Inst{22-20} = opcod;
1011 let Inst{19-16} = 0b1111; // Rn
1012 let Inst{15-12} = 0b1111;
1014 let Inst{5-4} = 0b00; // rotate
1016 def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
1017 IIC_iEXTr, opc, "\t$dst, $Rm, ror $rot",
1018 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1019 Requires<[HasT2ExtractPack, IsThumb2]> {
1020 let Inst{31-27} = 0b11111;
1021 let Inst{26-23} = 0b0100;
1022 let Inst{22-20} = opcod;
1023 let Inst{19-16} = 0b1111; // Rn
1024 let Inst{15-12} = 0b1111;
1028 let Inst{5-4} = rot{1-0}; // rotate
1032 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1034 multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1035 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1036 opc, "\t$Rd, $Rm", []> {
1037 let Inst{31-27} = 0b11111;
1038 let Inst{26-23} = 0b0100;
1039 let Inst{22-20} = opcod;
1040 let Inst{19-16} = 0b1111; // Rn
1041 let Inst{15-12} = 0b1111;
1043 let Inst{5-4} = 0b00; // rotate
1045 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1046 opc, "\t$Rd, $Rm, ror $rot", []> {
1047 let Inst{31-27} = 0b11111;
1048 let Inst{26-23} = 0b0100;
1049 let Inst{22-20} = opcod;
1050 let Inst{19-16} = 0b1111; // Rn
1051 let Inst{15-12} = 0b1111;
1055 let Inst{5-4} = rot{1-0}; // rotate
1059 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1060 /// register and one whose operand is a register rotated by 8/16/24.
1061 multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1062 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1063 opc, "\t$Rd, $Rn, $Rm",
1064 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1065 Requires<[HasT2ExtractPack, IsThumb2]> {
1066 let Inst{31-27} = 0b11111;
1067 let Inst{26-23} = 0b0100;
1068 let Inst{22-20} = opcod;
1069 let Inst{15-12} = 0b1111;
1071 let Inst{5-4} = 0b00; // rotate
1073 def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
1074 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1075 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1076 [(set rGPR:$Rd, (opnode rGPR:$Rn,
1077 (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1078 Requires<[HasT2ExtractPack, IsThumb2]> {
1079 let Inst{31-27} = 0b11111;
1080 let Inst{26-23} = 0b0100;
1081 let Inst{22-20} = opcod;
1082 let Inst{15-12} = 0b1111;
1086 let Inst{5-4} = rot{1-0}; // rotate
1090 // DO variant - disassembly only, no pattern
1092 multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
1093 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1094 opc, "\t$Rd, $Rn, $Rm", []> {
1095 let Inst{31-27} = 0b11111;
1096 let Inst{26-23} = 0b0100;
1097 let Inst{22-20} = opcod;
1098 let Inst{15-12} = 0b1111;
1100 let Inst{5-4} = 0b00; // rotate
1102 def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1103 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
1104 let Inst{31-27} = 0b11111;
1105 let Inst{26-23} = 0b0100;
1106 let Inst{22-20} = opcod;
1107 let Inst{15-12} = 0b1111;
1111 let Inst{5-4} = rot{1-0}; // rotate
1115 //===----------------------------------------------------------------------===//
1117 //===----------------------------------------------------------------------===//
1119 //===----------------------------------------------------------------------===//
1120 // Miscellaneous Instructions.
1123 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1124 string asm, list<dag> pattern>
1125 : T2XI<oops, iops, itin, asm, pattern> {
1129 let Inst{11-8} = Rd;
1130 let Inst{26} = label{11};
1131 let Inst{14-12} = label{10-8};
1132 let Inst{7-0} = label{7-0};
1135 // LEApcrel - Load a pc-relative address into a register without offending the
1137 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1138 (ins t2adrlabel:$addr, pred:$p),
1139 IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1140 let Inst{31-27} = 0b11110;
1141 let Inst{25-24} = 0b10;
1142 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1145 let Inst{19-16} = 0b1111; // Rn
1150 let Inst{11-8} = Rd;
1151 let Inst{23} = addr{12};
1152 let Inst{21} = addr{12};
1153 let Inst{26} = addr{11};
1154 let Inst{14-12} = addr{10-8};
1155 let Inst{7-0} = addr{7-0};
1158 let neverHasSideEffects = 1, isReMaterializable = 1 in
1159 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1160 Size4Bytes, IIC_iALUi, []>;
1161 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1162 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1163 Size4Bytes, IIC_iALUi,
1167 // FIXME: None of these add/sub SP special instructions should be necessary
1168 // at all for thumb2 since they use the same encodings as the generic
1169 // add/sub instructions. In thumb1 we need them since they have dedicated
1170 // encodings. At the least, they should be pseudo instructions.
1171 // ADD r, sp, {so_imm|i12}
1172 let isCodeGenOnly = 1 in {
1173 def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1174 IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> {
1175 let Inst{31-27} = 0b11110;
1177 let Inst{24-21} = 0b1000;
1180 def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1181 IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> {
1182 let Inst{31-27} = 0b11110;
1183 let Inst{25-20} = 0b100000;
1187 // ADD r, sp, so_reg
1188 def t2ADDrSPs : T2sTwoRegShiftedReg<
1189 (outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
1190 IIC_iALUsi, "add", ".w\t$Rd, $Rn, $ShiftedRm", []> {
1191 let Inst{31-27} = 0b11101;
1192 let Inst{26-25} = 0b01;
1193 let Inst{24-21} = 0b1000;
1197 // SUB r, sp, {so_imm|i12}
1198 def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1199 IIC_iALUi, "sub", ".w\t$Rd, $Rn, $imm", []> {
1200 let Inst{31-27} = 0b11110;
1202 let Inst{24-21} = 0b1101;
1205 def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1206 IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> {
1207 let Inst{31-27} = 0b11110;
1208 let Inst{25-20} = 0b101010;
1212 // SUB r, sp, so_reg
1213 def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm),
1215 "sub", "\t$Rd, $Rn, $imm", []> {
1216 let Inst{31-27} = 0b11101;
1217 let Inst{26-25} = 0b01;
1218 let Inst{24-21} = 0b1101;
1219 let Inst{19-16} = 0b1101; // Rn = sp
1222 } // end isCodeGenOnly = 1
1224 // Signed and unsigned division on v7-M
1225 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1226 "sdiv", "\t$Rd, $Rn, $Rm",
1227 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
1228 Requires<[HasDivide, IsThumb2]> {
1229 let Inst{31-27} = 0b11111;
1230 let Inst{26-21} = 0b011100;
1232 let Inst{15-12} = 0b1111;
1233 let Inst{7-4} = 0b1111;
1236 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1237 "udiv", "\t$Rd, $Rn, $Rm",
1238 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
1239 Requires<[HasDivide, IsThumb2]> {
1240 let Inst{31-27} = 0b11111;
1241 let Inst{26-21} = 0b011101;
1243 let Inst{15-12} = 0b1111;
1244 let Inst{7-4} = 0b1111;
1247 //===----------------------------------------------------------------------===//
1248 // Load / store Instructions.
1252 let canFoldAsLoad = 1, isReMaterializable = 1 in
1253 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1254 UnOpFrag<(load node:$Src)>>;
1256 // Loads with zero extension
1257 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1258 UnOpFrag<(zextloadi16 node:$Src)>>;
1259 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1260 UnOpFrag<(zextloadi8 node:$Src)>>;
1262 // Loads with sign extension
1263 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1264 UnOpFrag<(sextloadi16 node:$Src)>>;
1265 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1266 UnOpFrag<(sextloadi8 node:$Src)>>;
1268 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1270 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1271 (ins t2addrmode_imm8s4:$addr),
1272 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1273 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1275 // zextload i1 -> zextload i8
1276 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1277 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1278 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1279 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1280 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1281 (t2LDRBs t2addrmode_so_reg:$addr)>;
1282 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1283 (t2LDRBpci tconstpool:$addr)>;
1285 // extload -> zextload
1286 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1288 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1289 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1290 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1291 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1292 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1293 (t2LDRBs t2addrmode_so_reg:$addr)>;
1294 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1295 (t2LDRBpci tconstpool:$addr)>;
1297 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1298 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1299 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1300 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1301 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1302 (t2LDRBs t2addrmode_so_reg:$addr)>;
1303 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1304 (t2LDRBpci tconstpool:$addr)>;
1306 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1307 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1308 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1309 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1310 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1311 (t2LDRHs t2addrmode_so_reg:$addr)>;
1312 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1313 (t2LDRHpci tconstpool:$addr)>;
1315 // FIXME: The destination register of the loads and stores can't be PC, but
1316 // can be SP. We need another regclass (similar to rGPR) to represent
1317 // that. Not a pressing issue since these are selected manually,
1322 let mayLoad = 1, neverHasSideEffects = 1 in {
1323 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1324 (ins t2addrmode_imm8:$addr),
1325 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1326 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1329 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1330 (ins GPR:$base, t2am_imm8_offset:$addr),
1331 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1332 "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1335 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1336 (ins t2addrmode_imm8:$addr),
1337 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1338 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1340 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1341 (ins GPR:$base, t2am_imm8_offset:$addr),
1342 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1343 "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1346 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1347 (ins t2addrmode_imm8:$addr),
1348 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1349 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1351 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1352 (ins GPR:$base, t2am_imm8_offset:$addr),
1353 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1354 "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1357 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1358 (ins t2addrmode_imm8:$addr),
1359 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1360 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1362 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1363 (ins GPR:$base, t2am_imm8_offset:$addr),
1364 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1365 "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1368 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1369 (ins t2addrmode_imm8:$addr),
1370 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1371 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1373 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
1374 (ins GPR:$base, t2am_imm8_offset:$addr),
1375 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1376 "ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
1378 } // mayLoad = 1, neverHasSideEffects = 1
1380 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1381 // for disassembly only.
1382 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1383 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1384 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1385 "\t$Rt, $addr", []> {
1386 let Inst{31-27} = 0b11111;
1387 let Inst{26-25} = 0b00;
1388 let Inst{24} = signed;
1390 let Inst{22-21} = type;
1391 let Inst{20} = 1; // load
1393 let Inst{10-8} = 0b110; // PUW.
1397 let Inst{15-12} = Rt;
1398 let Inst{19-16} = addr{12-9};
1399 let Inst{7-0} = addr{7-0};
1402 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1403 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1404 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1405 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1406 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1409 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1410 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1411 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1412 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1413 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1414 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1417 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1418 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1419 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1420 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1423 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1424 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1425 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1426 "str", "\t$Rt, [$Rn, $addr]!",
1427 "$Rn = $base_wb,@earlyclobber $base_wb",
1429 (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1431 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1432 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1433 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1434 "str", "\t$Rt, [$Rn], $addr",
1435 "$Rn = $base_wb,@earlyclobber $base_wb",
1437 (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1439 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1440 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1441 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1442 "strh", "\t$Rt, [$Rn, $addr]!",
1443 "$Rn = $base_wb,@earlyclobber $base_wb",
1445 (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1447 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1448 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1449 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1450 "strh", "\t$Rt, [$Rn], $addr",
1451 "$Rn = $base_wb,@earlyclobber $base_wb",
1453 (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1455 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1456 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1457 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1458 "strb", "\t$Rt, [$Rn, $addr]!",
1459 "$Rn = $base_wb,@earlyclobber $base_wb",
1461 (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1463 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1464 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1465 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1466 "strb", "\t$Rt, [$Rn], $addr",
1467 "$Rn = $base_wb,@earlyclobber $base_wb",
1469 (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1471 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1473 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1474 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1475 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1476 "\t$Rt, $addr", []> {
1477 let Inst{31-27} = 0b11111;
1478 let Inst{26-25} = 0b00;
1479 let Inst{24} = 0; // not signed
1481 let Inst{22-21} = type;
1482 let Inst{20} = 0; // store
1484 let Inst{10-8} = 0b110; // PUW
1488 let Inst{15-12} = Rt;
1489 let Inst{19-16} = addr{12-9};
1490 let Inst{7-0} = addr{7-0};
1493 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1494 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1495 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1497 // ldrd / strd pre / post variants
1498 // For disassembly only.
1500 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1501 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1502 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1504 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1505 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1506 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1508 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1509 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1510 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1512 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1513 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1514 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1516 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1517 // data/instruction access. These are for disassembly only.
1518 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1519 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1520 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1522 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1524 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1525 let Inst{31-25} = 0b1111100;
1526 let Inst{24} = instr;
1528 let Inst{21} = write;
1530 let Inst{15-12} = 0b1111;
1533 let addr{12} = 1; // add = TRUE
1534 let Inst{19-16} = addr{16-13}; // Rn
1535 let Inst{23} = addr{12}; // U
1536 let Inst{11-0} = addr{11-0}; // imm12
1539 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1541 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1542 let Inst{31-25} = 0b1111100;
1543 let Inst{24} = instr;
1544 let Inst{23} = 0; // U = 0
1546 let Inst{21} = write;
1548 let Inst{15-12} = 0b1111;
1549 let Inst{11-8} = 0b1100;
1552 let Inst{19-16} = addr{12-9}; // Rn
1553 let Inst{7-0} = addr{7-0}; // imm8
1556 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1558 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1559 let Inst{31-25} = 0b1111100;
1560 let Inst{24} = instr;
1561 let Inst{23} = 0; // add = TRUE for T1
1563 let Inst{21} = write;
1565 let Inst{15-12} = 0b1111;
1566 let Inst{11-6} = 0000000;
1569 let Inst{19-16} = addr{9-6}; // Rn
1570 let Inst{3-0} = addr{5-2}; // Rm
1571 let Inst{5-4} = addr{1-0}; // imm2
1575 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1576 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1577 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1579 //===----------------------------------------------------------------------===//
1580 // Load / store multiple Instructions.
1583 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1584 InstrItinClass itin_upd, bit L_bit> {
1586 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1587 itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1591 let Inst{31-27} = 0b11101;
1592 let Inst{26-25} = 0b00;
1593 let Inst{24-23} = 0b01; // Increment After
1595 let Inst{21} = 0; // No writeback
1596 let Inst{20} = L_bit;
1597 let Inst{19-16} = Rn;
1598 let Inst{15-0} = regs;
1601 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1602 itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1606 let Inst{31-27} = 0b11101;
1607 let Inst{26-25} = 0b00;
1608 let Inst{24-23} = 0b01; // Increment After
1610 let Inst{21} = 1; // Writeback
1611 let Inst{20} = L_bit;
1612 let Inst{19-16} = Rn;
1613 let Inst{15-0} = regs;
1616 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1617 itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1621 let Inst{31-27} = 0b11101;
1622 let Inst{26-25} = 0b00;
1623 let Inst{24-23} = 0b10; // Decrement Before
1625 let Inst{21} = 0; // No writeback
1626 let Inst{20} = L_bit;
1627 let Inst{19-16} = Rn;
1628 let Inst{15-0} = regs;
1631 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1632 itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1636 let Inst{31-27} = 0b11101;
1637 let Inst{26-25} = 0b00;
1638 let Inst{24-23} = 0b10; // Decrement Before
1640 let Inst{21} = 1; // Writeback
1641 let Inst{20} = L_bit;
1642 let Inst{19-16} = Rn;
1643 let Inst{15-0} = regs;
1647 let neverHasSideEffects = 1 in {
1649 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1650 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1652 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1653 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1655 } // neverHasSideEffects
1658 //===----------------------------------------------------------------------===//
1659 // Move Instructions.
1662 let neverHasSideEffects = 1 in
1663 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1664 "mov", ".w\t$Rd, $Rm", []> {
1665 let Inst{31-27} = 0b11101;
1666 let Inst{26-25} = 0b01;
1667 let Inst{24-21} = 0b0010;
1668 let Inst{19-16} = 0b1111; // Rn
1669 let Inst{14-12} = 0b000;
1670 let Inst{7-4} = 0b0000;
1673 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1674 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1675 AddedComplexity = 1 in
1676 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1677 "mov", ".w\t$Rd, $imm",
1678 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1679 let Inst{31-27} = 0b11110;
1681 let Inst{24-21} = 0b0010;
1682 let Inst{19-16} = 0b1111; // Rn
1686 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1687 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi,
1688 "movw", "\t$Rd, $imm",
1689 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1690 let Inst{31-27} = 0b11110;
1692 let Inst{24-21} = 0b0010;
1693 let Inst{20} = 0; // The S bit.
1699 let Inst{11-8} = Rd;
1700 let Inst{19-16} = imm{15-12};
1701 let Inst{26} = imm{11};
1702 let Inst{14-12} = imm{10-8};
1703 let Inst{7-0} = imm{7-0};
1706 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1707 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1709 let Constraints = "$src = $Rd" in {
1710 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1711 (ins rGPR:$src, i32imm_hilo16:$imm), IIC_iMOVi,
1712 "movt", "\t$Rd, $imm",
1714 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1715 let Inst{31-27} = 0b11110;
1717 let Inst{24-21} = 0b0110;
1718 let Inst{20} = 0; // The S bit.
1724 let Inst{11-8} = Rd;
1725 let Inst{19-16} = imm{15-12};
1726 let Inst{26} = imm{11};
1727 let Inst{14-12} = imm{10-8};
1728 let Inst{7-0} = imm{7-0};
1731 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1732 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1735 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1737 //===----------------------------------------------------------------------===//
1738 // Extend Instructions.
1743 defm t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1744 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1745 defm t2SXTH : T2I_ext_rrot<0b000, "sxth",
1746 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1747 defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1749 defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1750 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1751 defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1752 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1753 defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1755 // TODO: SXT(A){B|H}16 - done for disassembly only
1759 let AddedComplexity = 16 in {
1760 defm t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1761 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1762 defm t2UXTH : T2I_ext_rrot<0b001, "uxth",
1763 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1764 defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1765 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1767 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1768 // The transformation should probably be done as a combiner action
1769 // instead so we can include a check for masking back in the upper
1770 // eight bits of the source into the lower eight bits of the result.
1771 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1772 // (t2UXTB16r_rot rGPR:$Src, 24)>,
1773 // Requires<[HasT2ExtractPack, IsThumb2]>;
1774 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1775 (t2UXTB16r_rot rGPR:$Src, 8)>,
1776 Requires<[HasT2ExtractPack, IsThumb2]>;
1778 defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1779 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1780 defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1781 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1782 defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1785 //===----------------------------------------------------------------------===//
1786 // Arithmetic Instructions.
1789 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1790 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1791 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1792 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1794 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1795 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1796 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1797 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1798 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1799 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1800 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1802 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1803 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1804 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1805 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1806 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1807 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1808 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1809 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1812 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1813 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1814 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1815 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1817 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1818 // The assume-no-carry-in form uses the negation of the input since add/sub
1819 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1820 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1822 // The AddedComplexity preferences the first variant over the others since
1823 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1824 let AddedComplexity = 1 in
1825 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1826 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1827 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1828 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1829 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1830 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1831 let AddedComplexity = 1 in
1832 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1833 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1834 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1835 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1836 // The with-carry-in form matches bitwise not instead of the negation.
1837 // Effectively, the inverse interpretation of the carry flag already accounts
1838 // for part of the negation.
1839 let AddedComplexity = 1 in
1840 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1841 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1842 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1843 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1845 // Select Bytes -- for disassembly only
1847 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1848 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
1849 let Inst{31-27} = 0b11111;
1850 let Inst{26-24} = 0b010;
1852 let Inst{22-20} = 0b010;
1853 let Inst{15-12} = 0b1111;
1855 let Inst{6-4} = 0b000;
1858 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1859 // And Miscellaneous operations -- for disassembly only
1860 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1861 list<dag> pat = [/* For disassembly only; pattern left blank */],
1862 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1863 string asm = "\t$Rd, $Rn, $Rm">
1864 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat> {
1865 let Inst{31-27} = 0b11111;
1866 let Inst{26-23} = 0b0101;
1867 let Inst{22-20} = op22_20;
1868 let Inst{15-12} = 0b1111;
1869 let Inst{7-4} = op7_4;
1875 let Inst{11-8} = Rd;
1876 let Inst{19-16} = Rn;
1880 // Saturating add/subtract -- for disassembly only
1882 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1883 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1884 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1885 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1886 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1887 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1888 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1889 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1890 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1891 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1892 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1893 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1894 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1895 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1896 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1897 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1898 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1899 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1900 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1901 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1902 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1903 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1905 // Signed/Unsigned add/subtract -- for disassembly only
1907 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1908 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1909 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1910 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1911 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1912 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1913 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1914 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1915 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1916 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1917 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1918 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1920 // Signed/Unsigned halving add/subtract -- for disassembly only
1922 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1923 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1924 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1925 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1926 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1927 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1928 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1929 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1930 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1931 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1932 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1933 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1935 // Helper class for disassembly only
1936 // A6.3.16 & A6.3.17
1937 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1938 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1939 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1940 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1941 let Inst{31-27} = 0b11111;
1942 let Inst{26-24} = 0b011;
1943 let Inst{23} = long;
1944 let Inst{22-20} = op22_20;
1945 let Inst{7-4} = op7_4;
1948 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1949 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1950 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1951 let Inst{31-27} = 0b11111;
1952 let Inst{26-24} = 0b011;
1953 let Inst{23} = long;
1954 let Inst{22-20} = op22_20;
1955 let Inst{7-4} = op7_4;
1958 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1960 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1961 (ins rGPR:$Rn, rGPR:$Rm),
1962 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
1963 let Inst{15-12} = 0b1111;
1965 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1966 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1967 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
1969 // Signed/Unsigned saturate -- for disassembly only
1971 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1972 string opc, string asm, list<dag> pattern>
1973 : T2I<oops, iops, itin, opc, asm, pattern> {
1979 let Inst{11-8} = Rd;
1980 let Inst{19-16} = Rn;
1981 let Inst{4-0} = sat_imm{4-0};
1982 let Inst{21} = sh{6};
1983 let Inst{14-12} = sh{4-2};
1984 let Inst{7-6} = sh{1-0};
1988 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1989 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1990 [/* For disassembly only; pattern left blank */]> {
1991 let Inst{31-27} = 0b11110;
1992 let Inst{25-22} = 0b1100;
1997 def t2SSAT16: T2SatI<
1998 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
1999 "ssat16", "\t$Rd, $sat_imm, $Rn",
2000 [/* For disassembly only; pattern left blank */]> {
2001 let Inst{31-27} = 0b11110;
2002 let Inst{25-22} = 0b1100;
2005 let Inst{21} = 1; // sh = '1'
2006 let Inst{14-12} = 0b000; // imm3 = '000'
2007 let Inst{7-6} = 0b00; // imm2 = '00'
2011 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2012 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
2013 [/* For disassembly only; pattern left blank */]> {
2014 let Inst{31-27} = 0b11110;
2015 let Inst{25-22} = 0b1110;
2020 def t2USAT16: T2SatI<
2021 (outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
2022 "usat16", "\t$dst, $sat_imm, $Rn",
2023 [/* For disassembly only; pattern left blank */]> {
2024 let Inst{31-27} = 0b11110;
2025 let Inst{25-22} = 0b1110;
2028 let Inst{21} = 1; // sh = '1'
2029 let Inst{14-12} = 0b000; // imm3 = '000'
2030 let Inst{7-6} = 0b00; // imm2 = '00'
2033 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2034 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2036 //===----------------------------------------------------------------------===//
2037 // Shift and rotate Instructions.
2040 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2041 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2042 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2043 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2045 let Uses = [CPSR] in {
2046 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2047 "rrx", "\t$Rd, $Rm",
2048 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2049 let Inst{31-27} = 0b11101;
2050 let Inst{26-25} = 0b01;
2051 let Inst{24-21} = 0b0010;
2052 let Inst{19-16} = 0b1111; // Rn
2053 let Inst{14-12} = 0b000;
2054 let Inst{7-4} = 0b0011;
2058 let isCodeGenOnly = 1, Defs = [CPSR] in {
2059 def t2MOVsrl_flag : T2TwoRegShiftImm<
2060 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2061 "lsrs", ".w\t$Rd, $Rm, #1",
2062 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2063 let Inst{31-27} = 0b11101;
2064 let Inst{26-25} = 0b01;
2065 let Inst{24-21} = 0b0010;
2066 let Inst{20} = 1; // The S bit.
2067 let Inst{19-16} = 0b1111; // Rn
2068 let Inst{5-4} = 0b01; // Shift type.
2069 // Shift amount = Inst{14-12:7-6} = 1.
2070 let Inst{14-12} = 0b000;
2071 let Inst{7-6} = 0b01;
2073 def t2MOVsra_flag : T2TwoRegShiftImm<
2074 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2075 "asrs", ".w\t$Rd, $Rm, #1",
2076 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2077 let Inst{31-27} = 0b11101;
2078 let Inst{26-25} = 0b01;
2079 let Inst{24-21} = 0b0010;
2080 let Inst{20} = 1; // The S bit.
2081 let Inst{19-16} = 0b1111; // Rn
2082 let Inst{5-4} = 0b10; // Shift type.
2083 // Shift amount = Inst{14-12:7-6} = 1.
2084 let Inst{14-12} = 0b000;
2085 let Inst{7-6} = 0b01;
2089 //===----------------------------------------------------------------------===//
2090 // Bitwise Instructions.
2093 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2094 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2095 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2096 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2097 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2098 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2099 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2100 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2101 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2103 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2104 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2105 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2107 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2108 string opc, string asm, list<dag> pattern>
2109 : T2I<oops, iops, itin, opc, asm, pattern> {
2114 let Inst{11-8} = Rd;
2115 let Inst{4-0} = msb{4-0};
2116 let Inst{14-12} = lsb{4-2};
2117 let Inst{7-6} = lsb{1-0};
2120 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2121 string opc, string asm, list<dag> pattern>
2122 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2125 let Inst{19-16} = Rn;
2128 let Constraints = "$src = $Rd" in
2129 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2130 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2131 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2132 let Inst{31-27} = 0b11110;
2133 let Inst{26} = 0; // should be 0.
2135 let Inst{24-20} = 0b10110;
2136 let Inst{19-16} = 0b1111; // Rn
2138 let Inst{5} = 0; // should be 0.
2141 let msb{4-0} = imm{9-5};
2142 let lsb{4-0} = imm{4-0};
2145 def t2SBFX: T2TwoRegBitFI<
2146 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2147 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2148 let Inst{31-27} = 0b11110;
2150 let Inst{24-20} = 0b10100;
2154 def t2UBFX: T2TwoRegBitFI<
2155 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2156 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2157 let Inst{31-27} = 0b11110;
2159 let Inst{24-20} = 0b11100;
2163 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2164 let Constraints = "$src = $Rd" in {
2165 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2166 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2167 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2168 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2169 bf_inv_mask_imm:$imm))]> {
2170 let Inst{31-27} = 0b11110;
2171 let Inst{26} = 0; // should be 0.
2173 let Inst{24-20} = 0b10110;
2175 let Inst{5} = 0; // should be 0.
2178 let msb{4-0} = imm{9-5};
2179 let lsb{4-0} = imm{4-0};
2182 // GNU as only supports this form of bfi (w/ 4 arguments)
2183 let isAsmParserOnly = 1 in
2184 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2185 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2187 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2189 let Inst{31-27} = 0b11110;
2190 let Inst{26} = 0; // should be 0.
2192 let Inst{24-20} = 0b10110;
2194 let Inst{5} = 0; // should be 0.
2198 let msb{4-0} = width; // Custom encoder => lsb+width-1
2199 let lsb{4-0} = lsbit;
2203 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2204 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2205 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2207 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2208 let AddedComplexity = 1 in
2209 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2210 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2211 UnOpFrag<(not node:$Src)>, 1, 1>;
2214 let AddedComplexity = 1 in
2215 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2216 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2218 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2219 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2220 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2221 Requires<[IsThumb2]>;
2223 def : T2Pat<(t2_so_imm_not:$src),
2224 (t2MVNi t2_so_imm_not:$src)>;
2226 //===----------------------------------------------------------------------===//
2227 // Multiply Instructions.
2229 let isCommutable = 1 in
2230 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2231 "mul", "\t$Rd, $Rn, $Rm",
2232 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2233 let Inst{31-27} = 0b11111;
2234 let Inst{26-23} = 0b0110;
2235 let Inst{22-20} = 0b000;
2236 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2237 let Inst{7-4} = 0b0000; // Multiply
2240 def t2MLA: T2FourReg<
2241 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2242 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2243 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2244 let Inst{31-27} = 0b11111;
2245 let Inst{26-23} = 0b0110;
2246 let Inst{22-20} = 0b000;
2247 let Inst{7-4} = 0b0000; // Multiply
2250 def t2MLS: T2FourReg<
2251 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2252 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2253 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2254 let Inst{31-27} = 0b11111;
2255 let Inst{26-23} = 0b0110;
2256 let Inst{22-20} = 0b000;
2257 let Inst{7-4} = 0b0001; // Multiply and Subtract
2260 // Extra precision multiplies with low / high results
2261 let neverHasSideEffects = 1 in {
2262 let isCommutable = 1 in {
2263 def t2SMULL : T2MulLong<0b000, 0b0000,
2264 (outs rGPR:$Rd, rGPR:$Ra),
2265 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2266 "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
2268 def t2UMULL : T2MulLong<0b010, 0b0000,
2269 (outs rGPR:$RdLo, rGPR:$RdHi),
2270 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2271 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2274 // Multiply + accumulate
2275 def t2SMLAL : T2MulLong<0b100, 0b0000,
2276 (outs rGPR:$RdLo, rGPR:$RdHi),
2277 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2278 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2280 def t2UMLAL : T2MulLong<0b110, 0b0000,
2281 (outs rGPR:$RdLo, rGPR:$RdHi),
2282 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2283 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2285 def t2UMAAL : T2MulLong<0b110, 0b0110,
2286 (outs rGPR:$RdLo, rGPR:$RdHi),
2287 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2288 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2289 } // neverHasSideEffects
2291 // Rounding variants of the below included for disassembly only
2293 // Most significant word multiply
2294 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2295 "smmul", "\t$Rd, $Rn, $Rm",
2296 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
2297 let Inst{31-27} = 0b11111;
2298 let Inst{26-23} = 0b0110;
2299 let Inst{22-20} = 0b101;
2300 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2301 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2304 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2305 "smmulr", "\t$Rd, $Rn, $Rm", []> {
2306 let Inst{31-27} = 0b11111;
2307 let Inst{26-23} = 0b0110;
2308 let Inst{22-20} = 0b101;
2309 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2310 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2313 def t2SMMLA : T2FourReg<
2314 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2315 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2316 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
2317 let Inst{31-27} = 0b11111;
2318 let Inst{26-23} = 0b0110;
2319 let Inst{22-20} = 0b101;
2320 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2323 def t2SMMLAR: T2FourReg<
2324 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2325 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
2326 let Inst{31-27} = 0b11111;
2327 let Inst{26-23} = 0b0110;
2328 let Inst{22-20} = 0b101;
2329 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2332 def t2SMMLS: T2FourReg<
2333 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2334 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2335 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
2336 let Inst{31-27} = 0b11111;
2337 let Inst{26-23} = 0b0110;
2338 let Inst{22-20} = 0b110;
2339 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2342 def t2SMMLSR:T2FourReg<
2343 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2344 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
2345 let Inst{31-27} = 0b11111;
2346 let Inst{26-23} = 0b0110;
2347 let Inst{22-20} = 0b110;
2348 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2351 multiclass T2I_smul<string opc, PatFrag opnode> {
2352 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2353 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2354 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2355 (sext_inreg rGPR:$Rm, i16)))]> {
2356 let Inst{31-27} = 0b11111;
2357 let Inst{26-23} = 0b0110;
2358 let Inst{22-20} = 0b001;
2359 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2360 let Inst{7-6} = 0b00;
2361 let Inst{5-4} = 0b00;
2364 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2365 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2366 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2367 (sra rGPR:$Rm, (i32 16))))]> {
2368 let Inst{31-27} = 0b11111;
2369 let Inst{26-23} = 0b0110;
2370 let Inst{22-20} = 0b001;
2371 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2372 let Inst{7-6} = 0b00;
2373 let Inst{5-4} = 0b01;
2376 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2377 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2378 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2379 (sext_inreg rGPR:$Rm, i16)))]> {
2380 let Inst{31-27} = 0b11111;
2381 let Inst{26-23} = 0b0110;
2382 let Inst{22-20} = 0b001;
2383 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2384 let Inst{7-6} = 0b00;
2385 let Inst{5-4} = 0b10;
2388 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2389 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2390 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2391 (sra rGPR:$Rm, (i32 16))))]> {
2392 let Inst{31-27} = 0b11111;
2393 let Inst{26-23} = 0b0110;
2394 let Inst{22-20} = 0b001;
2395 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2396 let Inst{7-6} = 0b00;
2397 let Inst{5-4} = 0b11;
2400 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2401 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2402 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2403 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
2404 let Inst{31-27} = 0b11111;
2405 let Inst{26-23} = 0b0110;
2406 let Inst{22-20} = 0b011;
2407 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2408 let Inst{7-6} = 0b00;
2409 let Inst{5-4} = 0b00;
2412 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2413 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2414 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2415 (sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
2416 let Inst{31-27} = 0b11111;
2417 let Inst{26-23} = 0b0110;
2418 let Inst{22-20} = 0b011;
2419 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2420 let Inst{7-6} = 0b00;
2421 let Inst{5-4} = 0b01;
2426 multiclass T2I_smla<string opc, PatFrag opnode> {
2428 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2429 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2430 [(set rGPR:$Rd, (add rGPR:$Ra,
2431 (opnode (sext_inreg rGPR:$Rn, i16),
2432 (sext_inreg rGPR:$Rm, i16))))]> {
2433 let Inst{31-27} = 0b11111;
2434 let Inst{26-23} = 0b0110;
2435 let Inst{22-20} = 0b001;
2436 let Inst{7-6} = 0b00;
2437 let Inst{5-4} = 0b00;
2441 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2442 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2443 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2444 (sra rGPR:$Rm, (i32 16)))))]> {
2445 let Inst{31-27} = 0b11111;
2446 let Inst{26-23} = 0b0110;
2447 let Inst{22-20} = 0b001;
2448 let Inst{7-6} = 0b00;
2449 let Inst{5-4} = 0b01;
2453 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2454 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2455 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2456 (sext_inreg rGPR:$Rm, i16))))]> {
2457 let Inst{31-27} = 0b11111;
2458 let Inst{26-23} = 0b0110;
2459 let Inst{22-20} = 0b001;
2460 let Inst{7-6} = 0b00;
2461 let Inst{5-4} = 0b10;
2465 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2466 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2467 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2468 (sra rGPR:$Rm, (i32 16)))))]> {
2469 let Inst{31-27} = 0b11111;
2470 let Inst{26-23} = 0b0110;
2471 let Inst{22-20} = 0b001;
2472 let Inst{7-6} = 0b00;
2473 let Inst{5-4} = 0b11;
2477 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2478 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2479 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2480 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
2481 let Inst{31-27} = 0b11111;
2482 let Inst{26-23} = 0b0110;
2483 let Inst{22-20} = 0b011;
2484 let Inst{7-6} = 0b00;
2485 let Inst{5-4} = 0b00;
2489 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2490 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2491 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2492 (sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
2493 let Inst{31-27} = 0b11111;
2494 let Inst{26-23} = 0b0110;
2495 let Inst{22-20} = 0b011;
2496 let Inst{7-6} = 0b00;
2497 let Inst{5-4} = 0b01;
2501 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2502 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2504 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2505 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2506 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2507 [/* For disassembly only; pattern left blank */]>;
2508 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2509 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2510 [/* For disassembly only; pattern left blank */]>;
2511 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2512 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2513 [/* For disassembly only; pattern left blank */]>;
2514 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2515 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2516 [/* For disassembly only; pattern left blank */]>;
2518 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2519 // These are for disassembly only.
2521 def t2SMUAD: T2ThreeReg_mac<
2522 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2523 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
2524 let Inst{15-12} = 0b1111;
2526 def t2SMUADX:T2ThreeReg_mac<
2527 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2528 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
2529 let Inst{15-12} = 0b1111;
2531 def t2SMUSD: T2ThreeReg_mac<
2532 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2533 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
2534 let Inst{15-12} = 0b1111;
2536 def t2SMUSDX:T2ThreeReg_mac<
2537 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2538 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
2539 let Inst{15-12} = 0b1111;
2541 def t2SMLAD : T2ThreeReg_mac<
2542 0, 0b010, 0b0000, (outs rGPR:$Rd),
2543 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2544 "\t$Rd, $Rn, $Rm, $Ra", []>;
2545 def t2SMLADX : T2FourReg_mac<
2546 0, 0b010, 0b0001, (outs rGPR:$Rd),
2547 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2548 "\t$Rd, $Rn, $Rm, $Ra", []>;
2549 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2550 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2551 "\t$Rd, $Rn, $Rm, $Ra", []>;
2552 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2553 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2554 "\t$Rd, $Rn, $Rm, $Ra", []>;
2555 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2556 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2557 "\t$Ra, $Rd, $Rm, $Rn", []>;
2558 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2559 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2560 "\t$Ra, $Rd, $Rm, $Rn", []>;
2561 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2562 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2563 "\t$Ra, $Rd, $Rm, $Rn", []>;
2564 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2565 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2566 "\t$Ra, $Rd, $Rm, $Rn", []>;
2568 //===----------------------------------------------------------------------===//
2569 // Misc. Arithmetic Instructions.
2572 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2573 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2574 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2575 let Inst{31-27} = 0b11111;
2576 let Inst{26-22} = 0b01010;
2577 let Inst{21-20} = op1;
2578 let Inst{15-12} = 0b1111;
2579 let Inst{7-6} = 0b10;
2580 let Inst{5-4} = op2;
2584 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2585 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2587 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2588 "rbit", "\t$Rd, $Rm",
2589 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2591 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2592 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2594 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2595 "rev16", ".w\t$Rd, $Rm",
2597 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF),
2598 (or (and (shl rGPR:$Rm, (i32 8)), 0xFF00),
2599 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
2600 (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
2602 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2603 "revsh", ".w\t$Rd, $Rm",
2606 (or (srl rGPR:$Rm, (i32 8)),
2607 (shl rGPR:$Rm, (i32 8))), i16))]>;
2609 def : T2Pat<(sext_inreg (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
2610 (shl rGPR:$Rm, (i32 8))), i16),
2611 (t2REVSH rGPR:$Rm)>;
2613 def : T2Pat<(sra (bswap rGPR:$Rm), (i32 16)), (t2REVSH rGPR:$Rm)>;
2615 def t2PKHBT : T2ThreeReg<
2616 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2617 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2618 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2619 (and (shl rGPR:$Rm, lsl_amt:$sh),
2621 Requires<[HasT2ExtractPack, IsThumb2]> {
2622 let Inst{31-27} = 0b11101;
2623 let Inst{26-25} = 0b01;
2624 let Inst{24-20} = 0b01100;
2625 let Inst{5} = 0; // BT form
2629 let Inst{14-12} = sh{7-5};
2630 let Inst{7-6} = sh{4-3};
2633 // Alternate cases for PKHBT where identities eliminate some nodes.
2634 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2635 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2636 Requires<[HasT2ExtractPack, IsThumb2]>;
2637 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2638 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2639 Requires<[HasT2ExtractPack, IsThumb2]>;
2641 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2642 // will match the pattern below.
2643 def t2PKHTB : T2ThreeReg<
2644 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2645 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2646 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2647 (and (sra rGPR:$Rm, asr_amt:$sh),
2649 Requires<[HasT2ExtractPack, IsThumb2]> {
2650 let Inst{31-27} = 0b11101;
2651 let Inst{26-25} = 0b01;
2652 let Inst{24-20} = 0b01100;
2653 let Inst{5} = 1; // TB form
2657 let Inst{14-12} = sh{7-5};
2658 let Inst{7-6} = sh{4-3};
2661 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2662 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2663 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2664 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2665 Requires<[HasT2ExtractPack, IsThumb2]>;
2666 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2667 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2668 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2669 Requires<[HasT2ExtractPack, IsThumb2]>;
2671 //===----------------------------------------------------------------------===//
2672 // Comparison Instructions...
2674 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2675 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2676 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2678 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
2679 (t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
2680 def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
2681 (t2CMPrr GPR:$lhs, rGPR:$rhs)>;
2682 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
2683 (t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
2685 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2686 // Compare-to-zero still works out, just not the relationals
2687 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2688 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2689 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2690 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2691 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2693 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2694 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2696 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2697 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2699 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2700 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2701 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2702 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2703 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2704 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2706 // Conditional moves
2707 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2708 // a two-value operand where a dag node expects two operands. :(
2709 let neverHasSideEffects = 1 in {
2710 def t2MOVCCr : T2TwoReg<
2711 (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
2712 "mov", ".w\t$Rd, $Rm",
2713 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2714 RegConstraint<"$false = $Rd"> {
2715 let Inst{31-27} = 0b11101;
2716 let Inst{26-25} = 0b01;
2717 let Inst{24-21} = 0b0010;
2718 let Inst{20} = 0; // The S bit.
2719 let Inst{19-16} = 0b1111; // Rn
2720 let Inst{14-12} = 0b000;
2721 let Inst{7-4} = 0b0000;
2724 let isMoveImm = 1 in
2725 def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2726 IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
2727 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2728 RegConstraint<"$false = $Rd"> {
2729 let Inst{31-27} = 0b11110;
2731 let Inst{24-21} = 0b0010;
2732 let Inst{20} = 0; // The S bit.
2733 let Inst{19-16} = 0b1111; // Rn
2737 let isMoveImm = 1 in
2738 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm_hilo16:$imm),
2740 "movw", "\t$Rd, $imm", []>,
2741 RegConstraint<"$false = $Rd"> {
2742 let Inst{31-27} = 0b11110;
2744 let Inst{24-21} = 0b0010;
2745 let Inst{20} = 0; // The S bit.
2751 let Inst{11-8} = Rd;
2752 let Inst{19-16} = imm{15-12};
2753 let Inst{26} = imm{11};
2754 let Inst{14-12} = imm{10-8};
2755 let Inst{7-0} = imm{7-0};
2758 let isMoveImm = 1 in
2759 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2760 (ins rGPR:$false, i32imm:$src, pred:$p),
2761 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2763 let isMoveImm = 1 in
2764 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2765 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2766 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2767 imm:$cc, CCR:$ccr))*/]>,
2768 RegConstraint<"$false = $Rd"> {
2769 let Inst{31-27} = 0b11110;
2771 let Inst{24-21} = 0b0011;
2772 let Inst{20} = 0; // The S bit.
2773 let Inst{19-16} = 0b1111; // Rn
2777 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2778 string opc, string asm, list<dag> pattern>
2779 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2780 let Inst{31-27} = 0b11101;
2781 let Inst{26-25} = 0b01;
2782 let Inst{24-21} = 0b0010;
2783 let Inst{20} = 0; // The S bit.
2784 let Inst{19-16} = 0b1111; // Rn
2785 let Inst{5-4} = opcod; // Shift type.
2787 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2788 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2789 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2790 RegConstraint<"$false = $Rd">;
2791 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2792 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2793 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2794 RegConstraint<"$false = $Rd">;
2795 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2796 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2797 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2798 RegConstraint<"$false = $Rd">;
2799 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2800 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2801 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2802 RegConstraint<"$false = $Rd">;
2803 } // neverHasSideEffects
2805 //===----------------------------------------------------------------------===//
2806 // Atomic operations intrinsics
2809 // memory barriers protect the atomic sequences
2810 let hasSideEffects = 1 in {
2811 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2812 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2813 Requires<[IsThumb, HasDB]> {
2815 let Inst{31-4} = 0xf3bf8f5;
2816 let Inst{3-0} = opt;
2820 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2822 [/* For disassembly only; pattern left blank */]>,
2823 Requires<[IsThumb, HasDB]> {
2825 let Inst{31-4} = 0xf3bf8f4;
2826 let Inst{3-0} = opt;
2829 // ISB has only full system option -- for disassembly only
2830 def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2831 [/* For disassembly only; pattern left blank */]>,
2832 Requires<[IsThumb2, HasV7]> {
2833 let Inst{31-4} = 0xf3bf8f6;
2834 let Inst{3-0} = 0b1111;
2837 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2838 InstrItinClass itin, string opc, string asm, string cstr,
2839 list<dag> pattern, bits<4> rt2 = 0b1111>
2840 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2841 let Inst{31-27} = 0b11101;
2842 let Inst{26-20} = 0b0001101;
2843 let Inst{11-8} = rt2;
2844 let Inst{7-6} = 0b01;
2845 let Inst{5-4} = opcod;
2846 let Inst{3-0} = 0b1111;
2850 let Inst{19-16} = addr;
2851 let Inst{15-12} = Rt;
2853 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2854 InstrItinClass itin, string opc, string asm, string cstr,
2855 list<dag> pattern, bits<4> rt2 = 0b1111>
2856 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2857 let Inst{31-27} = 0b11101;
2858 let Inst{26-20} = 0b0001100;
2859 let Inst{11-8} = rt2;
2860 let Inst{7-6} = 0b01;
2861 let Inst{5-4} = opcod;
2867 let Inst{19-16} = addr;
2868 let Inst{15-12} = Rt;
2871 let mayLoad = 1 in {
2872 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr), AddrModeNone,
2873 Size4Bytes, NoItinerary, "ldrexb", "\t$Rt, $addr",
2875 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr), AddrModeNone,
2876 Size4Bytes, NoItinerary, "ldrexh", "\t$Rt, $addr",
2878 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr), AddrModeNone,
2879 Size4Bytes, NoItinerary,
2880 "ldrex", "\t$Rt, $addr", "",
2882 let Inst{31-27} = 0b11101;
2883 let Inst{26-20} = 0b0000101;
2884 let Inst{11-8} = 0b1111;
2885 let Inst{7-0} = 0b00000000; // imm8 = 0
2889 let Inst{19-16} = addr;
2890 let Inst{15-12} = Rt;
2892 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), (ins t2addrmode_reg:$addr),
2893 AddrModeNone, Size4Bytes, NoItinerary,
2894 "ldrexd", "\t$Rt, $Rt2, $addr", "",
2897 let Inst{11-8} = Rt2;
2901 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2902 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2903 AddrModeNone, Size4Bytes, NoItinerary,
2904 "strexb", "\t$Rd, $Rt, $addr", "", []>;
2905 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2906 AddrModeNone, Size4Bytes, NoItinerary,
2907 "strexh", "\t$Rd, $Rt, $addr", "", []>;
2908 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2909 AddrModeNone, Size4Bytes, NoItinerary,
2910 "strex", "\t$Rd, $Rt, $addr", "",
2912 let Inst{31-27} = 0b11101;
2913 let Inst{26-20} = 0b0000100;
2914 let Inst{7-0} = 0b00000000; // imm8 = 0
2919 let Inst{11-8} = Rd;
2920 let Inst{19-16} = addr;
2921 let Inst{15-12} = Rt;
2923 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2924 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2925 AddrModeNone, Size4Bytes, NoItinerary,
2926 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2929 let Inst{11-8} = Rt2;
2933 // Clear-Exclusive is for disassembly only.
2934 def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
2935 [/* For disassembly only; pattern left blank */]>,
2936 Requires<[IsThumb2, HasV7]> {
2937 let Inst{31-16} = 0xf3bf;
2938 let Inst{15-14} = 0b10;
2941 let Inst{11-8} = 0b1111;
2942 let Inst{7-4} = 0b0010;
2943 let Inst{3-0} = 0b1111;
2946 //===----------------------------------------------------------------------===//
2950 // __aeabi_read_tp preserves the registers r1-r3.
2952 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
2953 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2954 "bl\t__aeabi_read_tp",
2955 [(set R0, ARMthread_pointer)]> {
2956 let Inst{31-27} = 0b11110;
2957 let Inst{15-14} = 0b11;
2962 //===----------------------------------------------------------------------===//
2963 // SJLJ Exception handling intrinsics
2964 // eh_sjlj_setjmp() is an instruction sequence to store the return
2965 // address and save #0 in R0 for the non-longjmp case.
2966 // Since by its nature we may be coming from some other function to get
2967 // here, and we're using the stack frame for the containing function to
2968 // save/restore registers, we can't keep anything live in regs across
2969 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2970 // when we get here from a longjmp(). We force everything out of registers
2971 // except for our own input by listing the relevant registers in Defs. By
2972 // doing so, we also cause the prologue/epilogue code to actively preserve
2973 // all of the callee-saved resgisters, which is exactly what we want.
2974 // $val is a scratch register for our use.
2976 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2977 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2978 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2979 D31 ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2980 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2981 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2982 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2983 Requires<[IsThumb2, HasVFP2]>;
2987 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2988 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2989 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2990 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2991 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2992 Requires<[IsThumb2, NoVFP]>;
2996 //===----------------------------------------------------------------------===//
2997 // Control-Flow Instructions
3000 // FIXME: remove when we have a way to marking a MI with these properties.
3001 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
3003 // FIXME: Should pc be an implicit operand like PICADD, etc?
3004 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3005 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3006 def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3007 reglist:$regs, variable_ops),
3009 "ldmia${p}.w\t$Rn!, $regs",
3014 let Inst{31-27} = 0b11101;
3015 let Inst{26-25} = 0b00;
3016 let Inst{24-23} = 0b01; // Increment After
3018 let Inst{21} = 1; // Writeback
3020 let Inst{19-16} = Rn;
3021 let Inst{15-0} = regs;
3024 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3025 let isPredicable = 1 in
3026 def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
3028 [(br bb:$target)]> {
3029 let Inst{31-27} = 0b11110;
3030 let Inst{15-14} = 0b10;
3034 let Inst{26} = target{19};
3035 let Inst{11} = target{18};
3036 let Inst{13} = target{17};
3037 let Inst{21-16} = target{16-11};
3038 let Inst{10-0} = target{10-0};
3041 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3042 def t2BR_JT : t2PseudoInst<(outs),
3043 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3044 SizeSpecial, IIC_Br,
3045 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3047 // FIXME: Add a non-pc based case that can be predicated.
3048 def t2TBB_JT : t2PseudoInst<(outs),
3049 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3050 SizeSpecial, IIC_Br, []>;
3052 def t2TBH_JT : t2PseudoInst<(outs),
3053 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3054 SizeSpecial, IIC_Br, []>;
3056 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3057 "tbb", "\t[$Rn, $Rm]", []> {
3060 let Inst{31-20} = 0b111010001101;
3061 let Inst{19-16} = Rn;
3062 let Inst{15-5} = 0b11110000000;
3063 let Inst{4} = 0; // B form
3067 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3068 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3071 let Inst{31-20} = 0b111010001101;
3072 let Inst{19-16} = Rn;
3073 let Inst{15-5} = 0b11110000000;
3074 let Inst{4} = 1; // H form
3077 } // isNotDuplicable, isIndirectBranch
3079 } // isBranch, isTerminator, isBarrier
3081 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3082 // a two-value operand where a dag node expects two operands. :(
3083 let isBranch = 1, isTerminator = 1 in
3084 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3086 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3087 let Inst{31-27} = 0b11110;
3088 let Inst{15-14} = 0b10;
3092 let Inst{25-22} = p;
3095 let Inst{26} = target{20};
3096 let Inst{11} = target{19};
3097 let Inst{13} = target{18};
3098 let Inst{21-16} = target{17-12};
3099 let Inst{10-0} = target{11-1};
3104 let Defs = [ITSTATE] in
3105 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3106 AddrModeNone, Size2Bytes, IIC_iALUx,
3107 "it$mask\t$cc", "", []> {
3108 // 16-bit instruction.
3109 let Inst{31-16} = 0x0000;
3110 let Inst{15-8} = 0b10111111;
3115 let Inst{3-0} = mask;
3118 // Branch and Exchange Jazelle -- for disassembly only
3120 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3121 [/* For disassembly only; pattern left blank */]> {
3122 let Inst{31-27} = 0b11110;
3124 let Inst{25-20} = 0b111100;
3125 let Inst{15-14} = 0b10;
3129 let Inst{19-16} = func;
3132 // Change Processor State is a system instruction -- for disassembly and
3134 // FIXME: Since the asm parser has currently no clean way to handle optional
3135 // operands, create 3 versions of the same instruction. Once there's a clean
3136 // framework to represent optional operands, change this behavior.
3137 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3138 !strconcat("cps", asm_op),
3139 [/* For disassembly only; pattern left blank */]> {
3145 let Inst{31-27} = 0b11110;
3147 let Inst{25-20} = 0b111010;
3148 let Inst{19-16} = 0b1111;
3149 let Inst{15-14} = 0b10;
3151 let Inst{10-9} = imod;
3153 let Inst{7-5} = iflags;
3154 let Inst{4-0} = mode;
3158 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3159 "$imod.w\t$iflags, $mode">;
3160 let mode = 0, M = 0 in
3161 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3162 "$imod.w\t$iflags">;
3163 let imod = 0, iflags = 0, M = 1 in
3164 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3166 // A6.3.4 Branches and miscellaneous control
3167 // Table A6-14 Change Processor State, and hint instructions
3168 // Helper class for disassembly only.
3169 class T2I_hint<bits<8> op7_0, string opc, string asm>
3170 : T2I<(outs), (ins), NoItinerary, opc, asm,
3171 [/* For disassembly only; pattern left blank */]> {
3172 let Inst{31-20} = 0xf3a;
3173 let Inst{19-16} = 0b1111;
3174 let Inst{15-14} = 0b10;
3176 let Inst{10-8} = 0b000;
3177 let Inst{7-0} = op7_0;
3180 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3181 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3182 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3183 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3184 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3186 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
3187 [/* For disassembly only; pattern left blank */]> {
3188 let Inst{31-20} = 0xf3a;
3189 let Inst{15-14} = 0b10;
3191 let Inst{10-8} = 0b000;
3192 let Inst{7-4} = 0b1111;
3195 let Inst{3-0} = opt;
3198 // Secure Monitor Call is a system instruction -- for disassembly only
3199 // Option = Inst{19-16}
3200 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
3201 [/* For disassembly only; pattern left blank */]> {
3202 let Inst{31-27} = 0b11110;
3203 let Inst{26-20} = 0b1111111;
3204 let Inst{15-12} = 0b1000;
3207 let Inst{19-16} = opt;
3210 class T2SRS<bits<12> op31_20,
3211 dag oops, dag iops, InstrItinClass itin,
3212 string opc, string asm, list<dag> pattern>
3213 : T2I<oops, iops, itin, opc, asm, pattern> {
3214 let Inst{31-20} = op31_20{11-0};
3217 let Inst{4-0} = mode{4-0};
3220 // Store Return State is a system instruction -- for disassembly only
3221 def t2SRSDBW : T2SRS<0b111010000010,
3222 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3223 [/* For disassembly only; pattern left blank */]>;
3224 def t2SRSDB : T2SRS<0b111010000000,
3225 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3226 [/* For disassembly only; pattern left blank */]>;
3227 def t2SRSIAW : T2SRS<0b111010011010,
3228 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3229 [/* For disassembly only; pattern left blank */]>;
3230 def t2SRSIA : T2SRS<0b111010011000,
3231 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3232 [/* For disassembly only; pattern left blank */]>;
3234 // Return From Exception is a system instruction -- for disassembly only
3236 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3237 string opc, string asm, list<dag> pattern>
3238 : T2I<oops, iops, itin, opc, asm, pattern> {
3239 let Inst{31-20} = op31_20{11-0};
3242 let Inst{19-16} = Rn;
3243 let Inst{15-0} = 0xc000;
3246 def t2RFEDBW : T2RFE<0b111010000011,
3247 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3248 [/* For disassembly only; pattern left blank */]>;
3249 def t2RFEDB : T2RFE<0b111010000001,
3250 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3251 [/* For disassembly only; pattern left blank */]>;
3252 def t2RFEIAW : T2RFE<0b111010011011,
3253 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3254 [/* For disassembly only; pattern left blank */]>;
3255 def t2RFEIA : T2RFE<0b111010011001,
3256 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3257 [/* For disassembly only; pattern left blank */]>;
3259 //===----------------------------------------------------------------------===//
3260 // Non-Instruction Patterns
3263 // 32-bit immediate using movw + movt.
3264 // This is a single pseudo instruction to make it re-materializable.
3265 // FIXME: Remove this when we can do generalized remat.
3266 let isReMaterializable = 1, isMoveImm = 1 in
3267 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3268 [(set rGPR:$dst, (i32 imm:$src))]>,
3269 Requires<[IsThumb, HasV6T2]>;
3271 // Pseudo instruction that combines movw + movt + add pc (if pic).
3272 // It also makes it possible to rematerialize the instructions.
3273 // FIXME: Remove this when we can do generalized remat and when machine licm
3274 // can properly the instructions.
3275 let isReMaterializable = 1 in {
3276 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3278 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3279 Requires<[IsThumb2, UseMovt]>;
3281 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3283 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3284 Requires<[IsThumb2, UseMovt]>;
3287 // ConstantPool, GlobalAddress, and JumpTable
3288 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3289 Requires<[IsThumb2, DontUseMovt]>;
3290 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3291 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3292 Requires<[IsThumb2, UseMovt]>;
3294 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3295 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3297 // Pseudo instruction that combines ldr from constpool and add pc. This should
3298 // be expanded into two instructions late to allow if-conversion and
3300 let canFoldAsLoad = 1, isReMaterializable = 1 in
3301 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3303 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3305 Requires<[IsThumb2]>;
3307 //===----------------------------------------------------------------------===//
3308 // Move between special register and ARM core register -- for disassembly only
3311 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3312 dag oops, dag iops, InstrItinClass itin,
3313 string opc, string asm, list<dag> pattern>
3314 : T2I<oops, iops, itin, opc, asm, pattern> {
3315 let Inst{31-20} = op31_20{11-0};
3316 let Inst{15-14} = op15_14{1-0};
3317 let Inst{12} = op12{0};
3320 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3321 dag oops, dag iops, InstrItinClass itin,
3322 string opc, string asm, list<dag> pattern>
3323 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3325 let Inst{11-8} = Rd;
3326 let Inst{19-16} = 0b1111;
3329 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3330 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3331 [/* For disassembly only; pattern left blank */]>;
3332 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3333 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3334 [/* For disassembly only; pattern left blank */]>;
3336 // Move from ARM core register to Special Register
3338 // No need to have both system and application versions, the encodings are the
3339 // same and the assembly parser has no way to distinguish between them. The mask
3340 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3341 // the mask with the fields to be accessed in the special register.
3342 def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3343 0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3344 NoItinerary, "msr", "\t$mask, $Rn",
3345 [/* For disassembly only; pattern left blank */]> {
3348 let Inst{19-16} = Rn;
3349 let Inst{20} = mask{4}; // R Bit
3351 let Inst{11-8} = mask{3-0};
3354 //===----------------------------------------------------------------------===//
3355 // Move between coprocessor and ARM core register -- for disassembly only
3358 class t2MovRCopro<string opc, bit direction, dag oops, dag iops>
3359 : T2Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3360 [/* For disassembly only; pattern left blank */]> {
3361 let Inst{27-24} = 0b1110;
3362 let Inst{20} = direction;
3372 let Inst{15-12} = Rt;
3373 let Inst{11-8} = cop;
3374 let Inst{23-21} = opc1;
3375 let Inst{7-5} = opc2;
3376 let Inst{3-0} = CRm;
3377 let Inst{19-16} = CRn;
3380 def t2MCR2 : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */,
3381 (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3382 c_imm:$CRm, i32imm:$opc2)>;
3383 def t2MRC2 : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */,
3384 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
3385 c_imm:$CRm, i32imm:$opc2)>;
3387 class t2MovRRCopro<string opc, bit direction>
3388 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3389 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3390 [/* For disassembly only; pattern left blank */]> {
3391 let Inst{27-24} = 0b1100;
3392 let Inst{23-21} = 0b010;
3393 let Inst{20} = direction;
3401 let Inst{15-12} = Rt;
3402 let Inst{19-16} = Rt2;
3403 let Inst{11-8} = cop;
3404 let Inst{7-4} = opc1;
3405 let Inst{3-0} = CRm;
3408 def t2MCRR2 : t2MovRRCopro<"mcrr2",
3409 0 /* from ARM core register to coprocessor */>;
3410 def t2MRRC2 : t2MovRRCopro<"mrrc2",
3411 1 /* from coprocessor to ARM core register */>;
3413 //===----------------------------------------------------------------------===//
3414 // Other Coprocessor Instructions. For disassembly only.
3417 def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
3418 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3419 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3420 [/* For disassembly only; pattern left blank */]> {
3421 let Inst{27-24} = 0b1110;
3430 let Inst{3-0} = CRm;
3432 let Inst{7-5} = opc2;
3433 let Inst{11-8} = cop;
3434 let Inst{15-12} = CRd;
3435 let Inst{19-16} = CRn;
3436 let Inst{23-20} = opc1;