1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // t2_so_imm - Match a 32-bit immediate operand, which is an
66 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
67 // immediate splatted into multiple bytes of the word.
68 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
69 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
70 return ARM_AM::getT2SOImmVal(Imm) != -1;
72 let ParserMatchClass = t2_so_imm_asmoperand;
73 let EncoderMethod = "getT2SOImmOpValue";
74 let DecoderMethod = "DecodeT2SOImm";
77 // t2_so_imm_not - Match an immediate that is a complement
79 // Note: this pattern doesn't require an encoder method and such, as it's
80 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
81 // is handled by the destination instructions, which use t2_so_imm.
82 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
83 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
84 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
85 }], t2_so_imm_not_XFORM> {
86 let ParserMatchClass = t2_so_imm_not_asmoperand;
89 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
90 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
91 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
93 }], t2_so_imm_neg_XFORM> {
94 let ParserMatchClass = t2_so_imm_neg_asmoperand;
97 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
98 def imm0_4095 : Operand<i32>,
100 return Imm >= 0 && Imm < 4096;
103 def imm0_4095_neg : PatLeaf<(i32 imm), [{
104 return (uint32_t)(-N->getZExtValue()) < 4096;
107 def imm0_255_neg : PatLeaf<(i32 imm), [{
108 return (uint32_t)(-N->getZExtValue()) < 255;
111 def imm0_255_not : PatLeaf<(i32 imm), [{
112 return (uint32_t)(~N->getZExtValue()) < 255;
115 def lo5AllOne : PatLeaf<(i32 imm), [{
116 // Returns true if all low 5-bits are 1.
117 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
120 // Define Thumb2 specific addressing modes.
122 // t2addrmode_imm12 := reg + imm12
123 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
124 def t2addrmode_imm12 : Operand<i32>,
125 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
126 let PrintMethod = "printAddrModeImm12Operand";
127 let EncoderMethod = "getAddrModeImm12OpValue";
128 let DecoderMethod = "DecodeT2AddrModeImm12";
129 let ParserMatchClass = t2addrmode_imm12_asmoperand;
130 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
133 // t2ldrlabel := imm12
134 def t2ldrlabel : Operand<i32> {
135 let EncoderMethod = "getAddrModeImm12OpValue";
136 let PrintMethod = "printT2LdrLabelOperand";
139 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
140 def t2ldr_pcrel_imm12 : Operand<i32> {
141 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
142 // used for assembler pseudo instruction and maps to t2ldrlabel, so
143 // doesn't need encoder or print methods of its own.
146 // ADR instruction labels.
147 def t2adrlabel : Operand<i32> {
148 let EncoderMethod = "getT2AdrLabelOpValue";
152 // t2addrmode_posimm8 := reg + imm8
153 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
154 def t2addrmode_posimm8 : Operand<i32> {
155 let PrintMethod = "printT2AddrModeImm8Operand";
156 let EncoderMethod = "getT2AddrModeImm8OpValue";
157 let DecoderMethod = "DecodeT2AddrModeImm8";
158 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
159 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
162 // t2addrmode_negimm8 := reg - imm8
163 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
164 def t2addrmode_negimm8 : Operand<i32>,
165 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
166 let PrintMethod = "printT2AddrModeImm8Operand";
167 let EncoderMethod = "getT2AddrModeImm8OpValue";
168 let DecoderMethod = "DecodeT2AddrModeImm8";
169 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
170 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
173 // t2addrmode_imm8 := reg +/- imm8
174 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
175 def t2addrmode_imm8 : Operand<i32>,
176 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
177 let PrintMethod = "printT2AddrModeImm8Operand";
178 let EncoderMethod = "getT2AddrModeImm8OpValue";
179 let DecoderMethod = "DecodeT2AddrModeImm8";
180 let ParserMatchClass = MemImm8OffsetAsmOperand;
181 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
184 def t2am_imm8_offset : Operand<i32>,
185 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
186 [], [SDNPWantRoot]> {
187 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
188 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
189 let DecoderMethod = "DecodeT2Imm8";
192 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
193 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
194 def t2addrmode_imm8s4 : Operand<i32> {
195 let PrintMethod = "printT2AddrModeImm8s4Operand";
196 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
197 let DecoderMethod = "DecodeT2AddrModeImm8s4";
198 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
199 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
202 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
203 def t2am_imm8s4_offset : Operand<i32> {
204 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
205 let EncoderMethod = "getT2Imm8s4OpValue";
206 let DecoderMethod = "DecodeT2Imm8S4";
209 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
210 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
211 let Name = "MemImm0_1020s4Offset";
213 def t2addrmode_imm0_1020s4 : Operand<i32> {
214 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
215 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
216 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
217 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
218 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
221 // t2addrmode_so_reg := reg + (reg << imm2)
222 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
223 def t2addrmode_so_reg : Operand<i32>,
224 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
225 let PrintMethod = "printT2AddrModeSoRegOperand";
226 let EncoderMethod = "getT2AddrModeSORegOpValue";
227 let DecoderMethod = "DecodeT2AddrModeSOReg";
228 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
229 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
232 // Addresses for the TBB/TBH instructions.
233 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
234 def addrmode_tbb : Operand<i32> {
235 let PrintMethod = "printAddrModeTBB";
236 let ParserMatchClass = addrmode_tbb_asmoperand;
237 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
239 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
240 def addrmode_tbh : Operand<i32> {
241 let PrintMethod = "printAddrModeTBH";
242 let ParserMatchClass = addrmode_tbh_asmoperand;
243 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
246 //===----------------------------------------------------------------------===//
247 // Multiclass helpers...
251 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
252 string opc, string asm, list<dag> pattern>
253 : T2I<oops, iops, itin, opc, asm, pattern> {
258 let Inst{26} = imm{11};
259 let Inst{14-12} = imm{10-8};
260 let Inst{7-0} = imm{7-0};
264 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
265 string opc, string asm, list<dag> pattern>
266 : T2sI<oops, iops, itin, opc, asm, pattern> {
272 let Inst{26} = imm{11};
273 let Inst{14-12} = imm{10-8};
274 let Inst{7-0} = imm{7-0};
277 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
278 string opc, string asm, list<dag> pattern>
279 : T2I<oops, iops, itin, opc, asm, pattern> {
283 let Inst{19-16} = Rn;
284 let Inst{26} = imm{11};
285 let Inst{14-12} = imm{10-8};
286 let Inst{7-0} = imm{7-0};
290 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
291 string opc, string asm, list<dag> pattern>
292 : T2I<oops, iops, itin, opc, asm, pattern> {
297 let Inst{3-0} = ShiftedRm{3-0};
298 let Inst{5-4} = ShiftedRm{6-5};
299 let Inst{14-12} = ShiftedRm{11-9};
300 let Inst{7-6} = ShiftedRm{8-7};
303 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
304 string opc, string asm, list<dag> pattern>
305 : T2sI<oops, iops, itin, opc, asm, pattern> {
310 let Inst{3-0} = ShiftedRm{3-0};
311 let Inst{5-4} = ShiftedRm{6-5};
312 let Inst{14-12} = ShiftedRm{11-9};
313 let Inst{7-6} = ShiftedRm{8-7};
316 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
317 string opc, string asm, list<dag> pattern>
318 : T2I<oops, iops, itin, opc, asm, pattern> {
322 let Inst{19-16} = Rn;
323 let Inst{3-0} = ShiftedRm{3-0};
324 let Inst{5-4} = ShiftedRm{6-5};
325 let Inst{14-12} = ShiftedRm{11-9};
326 let Inst{7-6} = ShiftedRm{8-7};
329 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
330 string opc, string asm, list<dag> pattern>
331 : T2I<oops, iops, itin, opc, asm, pattern> {
339 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
340 string opc, string asm, list<dag> pattern>
341 : T2sI<oops, iops, itin, opc, asm, pattern> {
349 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
350 string opc, string asm, list<dag> pattern>
351 : T2I<oops, iops, itin, opc, asm, pattern> {
355 let Inst{19-16} = Rn;
360 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : T2I<oops, iops, itin, opc, asm, pattern> {
368 let Inst{19-16} = Rn;
369 let Inst{26} = imm{11};
370 let Inst{14-12} = imm{10-8};
371 let Inst{7-0} = imm{7-0};
374 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
375 string opc, string asm, list<dag> pattern>
376 : T2sI<oops, iops, itin, opc, asm, pattern> {
382 let Inst{19-16} = Rn;
383 let Inst{26} = imm{11};
384 let Inst{14-12} = imm{10-8};
385 let Inst{7-0} = imm{7-0};
388 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
389 string opc, string asm, list<dag> pattern>
390 : T2I<oops, iops, itin, opc, asm, pattern> {
397 let Inst{14-12} = imm{4-2};
398 let Inst{7-6} = imm{1-0};
401 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
402 string opc, string asm, list<dag> pattern>
403 : T2sI<oops, iops, itin, opc, asm, pattern> {
410 let Inst{14-12} = imm{4-2};
411 let Inst{7-6} = imm{1-0};
414 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
415 string opc, string asm, list<dag> pattern>
416 : T2I<oops, iops, itin, opc, asm, pattern> {
422 let Inst{19-16} = Rn;
426 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
427 string opc, string asm, list<dag> pattern>
428 : T2sI<oops, iops, itin, opc, asm, pattern> {
434 let Inst{19-16} = Rn;
438 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
439 string opc, string asm, list<dag> pattern>
440 : T2I<oops, iops, itin, opc, asm, pattern> {
446 let Inst{19-16} = Rn;
447 let Inst{3-0} = ShiftedRm{3-0};
448 let Inst{5-4} = ShiftedRm{6-5};
449 let Inst{14-12} = ShiftedRm{11-9};
450 let Inst{7-6} = ShiftedRm{8-7};
453 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
454 string opc, string asm, list<dag> pattern>
455 : T2sI<oops, iops, itin, opc, asm, pattern> {
461 let Inst{19-16} = Rn;
462 let Inst{3-0} = ShiftedRm{3-0};
463 let Inst{5-4} = ShiftedRm{6-5};
464 let Inst{14-12} = ShiftedRm{11-9};
465 let Inst{7-6} = ShiftedRm{8-7};
468 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : T2I<oops, iops, itin, opc, asm, pattern> {
476 let Inst{19-16} = Rn;
477 let Inst{15-12} = Ra;
482 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
483 dag oops, dag iops, InstrItinClass itin,
484 string opc, string asm, list<dag> pattern>
485 : T2I<oops, iops, itin, opc, asm, pattern> {
491 let Inst{31-23} = 0b111110111;
492 let Inst{22-20} = opc22_20;
493 let Inst{19-16} = Rn;
494 let Inst{15-12} = RdLo;
495 let Inst{11-8} = RdHi;
496 let Inst{7-4} = opc7_4;
501 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
502 /// binary operation that produces a value. These are predicable and can be
503 /// changed to modify CPSR.
504 multiclass T2I_bin_irs<bits<4> opcod, string opc,
505 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
506 PatFrag opnode, string baseOpc, bit Commutable = 0,
509 def ri : T2sTwoRegImm<
510 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
511 opc, "\t$Rd, $Rn, $imm",
512 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
513 let Inst{31-27} = 0b11110;
515 let Inst{24-21} = opcod;
519 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
520 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
521 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
522 let isCommutable = Commutable;
523 let Inst{31-27} = 0b11101;
524 let Inst{26-25} = 0b01;
525 let Inst{24-21} = opcod;
526 let Inst{14-12} = 0b000; // imm3
527 let Inst{7-6} = 0b00; // imm2
528 let Inst{5-4} = 0b00; // type
531 def rs : T2sTwoRegShiftedReg<
532 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
533 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
534 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
535 let Inst{31-27} = 0b11101;
536 let Inst{26-25} = 0b01;
537 let Inst{24-21} = opcod;
539 // Assembly aliases for optional destination operand when it's the same
540 // as the source operand.
541 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
542 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
543 t2_so_imm:$imm, pred:$p,
545 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
546 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
549 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
550 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
551 t2_so_reg:$shift, pred:$p,
555 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
556 // the ".w" suffix to indicate that they are wide.
557 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
558 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
559 PatFrag opnode, string baseOpc, bit Commutable = 0> :
560 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
561 // Assembler aliases w/ the ".w" suffix.
562 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
563 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
564 t2_so_imm:$imm, pred:$p,
566 // Assembler aliases w/o the ".w" suffix.
567 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
568 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
571 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
572 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
573 t2_so_reg:$shift, pred:$p,
576 // and with the optional destination operand, too.
577 def : t2InstAlias<!strconcat(opc, "${s}${p}.ri", " $Rdn, $imm"),
578 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
579 t2_so_imm:$imm, pred:$p,
581 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
582 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
585 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
586 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
587 t2_so_reg:$shift, pred:$p,
591 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
592 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
593 /// it is equivalent to the T2I_bin_irs counterpart.
594 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
596 def ri : T2sTwoRegImm<
597 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
598 opc, ".w\t$Rd, $Rn, $imm",
599 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
600 let Inst{31-27} = 0b11110;
602 let Inst{24-21} = opcod;
606 def rr : T2sThreeReg<
607 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
608 opc, "\t$Rd, $Rn, $Rm",
609 [/* For disassembly only; pattern left blank */]> {
610 let Inst{31-27} = 0b11101;
611 let Inst{26-25} = 0b01;
612 let Inst{24-21} = opcod;
613 let Inst{14-12} = 0b000; // imm3
614 let Inst{7-6} = 0b00; // imm2
615 let Inst{5-4} = 0b00; // type
618 def rs : T2sTwoRegShiftedReg<
619 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
620 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
621 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
622 let Inst{31-27} = 0b11101;
623 let Inst{26-25} = 0b01;
624 let Inst{24-21} = opcod;
628 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
629 /// instruction modifies the CPSR register.
631 /// These opcodes will be converted to the real non-S opcodes by
632 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
633 let hasPostISelHook = 1, Defs = [CPSR] in {
634 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
635 InstrItinClass iis, PatFrag opnode,
636 bit Commutable = 0> {
638 def ri : t2PseudoInst<(outs rGPR:$Rd),
639 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
641 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
644 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
646 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
648 let isCommutable = Commutable;
651 def rs : t2PseudoInst<(outs rGPR:$Rd),
652 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
654 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
655 t2_so_reg:$ShiftedRm))]>;
659 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
660 /// operands are reversed.
661 let hasPostISelHook = 1, Defs = [CPSR] in {
662 multiclass T2I_rbin_s_is<PatFrag opnode> {
664 def ri : t2PseudoInst<(outs rGPR:$Rd),
665 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
667 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
670 def rs : t2PseudoInst<(outs rGPR:$Rd),
671 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
673 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
678 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
679 /// patterns for a binary operation that produces a value.
680 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
681 bit Commutable = 0> {
683 // The register-immediate version is re-materializable. This is useful
684 // in particular for taking the address of a local.
685 let isReMaterializable = 1 in {
686 def ri : T2sTwoRegImm<
687 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
688 opc, ".w\t$Rd, $Rn, $imm",
689 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
690 let Inst{31-27} = 0b11110;
693 let Inst{23-21} = op23_21;
699 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
700 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
701 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
705 let Inst{31-27} = 0b11110;
706 let Inst{26} = imm{11};
707 let Inst{25-24} = 0b10;
708 let Inst{23-21} = op23_21;
709 let Inst{20} = 0; // The S bit.
710 let Inst{19-16} = Rn;
712 let Inst{14-12} = imm{10-8};
714 let Inst{7-0} = imm{7-0};
717 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
718 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
719 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
720 let isCommutable = Commutable;
721 let Inst{31-27} = 0b11101;
722 let Inst{26-25} = 0b01;
724 let Inst{23-21} = op23_21;
725 let Inst{14-12} = 0b000; // imm3
726 let Inst{7-6} = 0b00; // imm2
727 let Inst{5-4} = 0b00; // type
730 def rs : T2sTwoRegShiftedReg<
731 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
732 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
733 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
734 let Inst{31-27} = 0b11101;
735 let Inst{26-25} = 0b01;
737 let Inst{23-21} = op23_21;
741 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
742 /// for a binary operation that produces a value and use the carry
743 /// bit. It's not predicable.
744 let Defs = [CPSR], Uses = [CPSR] in {
745 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
746 bit Commutable = 0> {
748 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
749 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
750 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
751 Requires<[IsThumb2]> {
752 let Inst{31-27} = 0b11110;
754 let Inst{24-21} = opcod;
758 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
759 opc, ".w\t$Rd, $Rn, $Rm",
760 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
761 Requires<[IsThumb2]> {
762 let isCommutable = Commutable;
763 let Inst{31-27} = 0b11101;
764 let Inst{26-25} = 0b01;
765 let Inst{24-21} = opcod;
766 let Inst{14-12} = 0b000; // imm3
767 let Inst{7-6} = 0b00; // imm2
768 let Inst{5-4} = 0b00; // type
771 def rs : T2sTwoRegShiftedReg<
772 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
773 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
774 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
775 Requires<[IsThumb2]> {
776 let Inst{31-27} = 0b11101;
777 let Inst{26-25} = 0b01;
778 let Inst{24-21} = opcod;
783 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
784 // rotate operation that produces a value.
785 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
788 def ri : T2sTwoRegShiftImm<
789 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
790 opc, ".w\t$Rd, $Rm, $imm",
791 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
792 let Inst{31-27} = 0b11101;
793 let Inst{26-21} = 0b010010;
794 let Inst{19-16} = 0b1111; // Rn
795 let Inst{5-4} = opcod;
798 def rr : T2sThreeReg<
799 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
800 opc, ".w\t$Rd, $Rn, $Rm",
801 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
802 let Inst{31-27} = 0b11111;
803 let Inst{26-23} = 0b0100;
804 let Inst{22-21} = opcod;
805 let Inst{15-12} = 0b1111;
806 let Inst{7-4} = 0b0000;
809 // Optional destination register
810 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
811 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
814 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
815 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
819 // Assembler aliases w/o the ".w" suffix.
820 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
821 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
824 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
825 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
829 // and with the optional destination operand, too.
830 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
831 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
834 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
835 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
840 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
841 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
842 /// a explicit result, only implicitly set CPSR.
843 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
844 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
845 PatFrag opnode, string baseOpc> {
846 let isCompare = 1, Defs = [CPSR] in {
848 def ri : T2OneRegCmpImm<
849 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
850 opc, ".w\t$Rn, $imm",
851 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
852 let Inst{31-27} = 0b11110;
854 let Inst{24-21} = opcod;
855 let Inst{20} = 1; // The S bit.
857 let Inst{11-8} = 0b1111; // Rd
860 def rr : T2TwoRegCmp<
861 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
863 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
864 let Inst{31-27} = 0b11101;
865 let Inst{26-25} = 0b01;
866 let Inst{24-21} = opcod;
867 let Inst{20} = 1; // The S bit.
868 let Inst{14-12} = 0b000; // imm3
869 let Inst{11-8} = 0b1111; // Rd
870 let Inst{7-6} = 0b00; // imm2
871 let Inst{5-4} = 0b00; // type
874 def rs : T2OneRegCmpShiftedReg<
875 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
876 opc, ".w\t$Rn, $ShiftedRm",
877 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
878 let Inst{31-27} = 0b11101;
879 let Inst{26-25} = 0b01;
880 let Inst{24-21} = opcod;
881 let Inst{20} = 1; // The S bit.
882 let Inst{11-8} = 0b1111; // Rd
886 // Assembler aliases w/o the ".w" suffix.
887 // No alias here for 'rr' version as not all instantiations of this
888 // multiclass want one (CMP in particular, does not).
889 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
890 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
891 t2_so_imm:$imm, pred:$p)>;
892 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
893 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
898 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
899 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
900 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
902 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
903 opc, ".w\t$Rt, $addr",
904 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
907 let Inst{31-25} = 0b1111100;
908 let Inst{24} = signed;
910 let Inst{22-21} = opcod;
911 let Inst{20} = 1; // load
912 let Inst{19-16} = addr{16-13}; // Rn
913 let Inst{15-12} = Rt;
914 let Inst{11-0} = addr{11-0}; // imm
916 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
918 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
921 let Inst{31-27} = 0b11111;
922 let Inst{26-25} = 0b00;
923 let Inst{24} = signed;
925 let Inst{22-21} = opcod;
926 let Inst{20} = 1; // load
927 let Inst{19-16} = addr{12-9}; // Rn
928 let Inst{15-12} = Rt;
930 // Offset: index==TRUE, wback==FALSE
931 let Inst{10} = 1; // The P bit.
932 let Inst{9} = addr{8}; // U
933 let Inst{8} = 0; // The W bit.
934 let Inst{7-0} = addr{7-0}; // imm
936 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
937 opc, ".w\t$Rt, $addr",
938 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
939 let Inst{31-27} = 0b11111;
940 let Inst{26-25} = 0b00;
941 let Inst{24} = signed;
943 let Inst{22-21} = opcod;
944 let Inst{20} = 1; // load
945 let Inst{11-6} = 0b000000;
948 let Inst{15-12} = Rt;
951 let Inst{19-16} = addr{9-6}; // Rn
952 let Inst{3-0} = addr{5-2}; // Rm
953 let Inst{5-4} = addr{1-0}; // imm
955 let DecoderMethod = "DecodeT2LoadShift";
958 // pci variant is very similar to i12, but supports negative offsets
960 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
961 opc, ".w\t$Rt, $addr",
962 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
963 let isReMaterializable = 1;
964 let Inst{31-27} = 0b11111;
965 let Inst{26-25} = 0b00;
966 let Inst{24} = signed;
967 let Inst{23} = ?; // add = (U == '1')
968 let Inst{22-21} = opcod;
969 let Inst{20} = 1; // load
970 let Inst{19-16} = 0b1111; // Rn
973 let Inst{15-12} = Rt{3-0};
974 let Inst{11-0} = addr{11-0};
978 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
979 multiclass T2I_st<bits<2> opcod, string opc,
980 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
982 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
983 opc, ".w\t$Rt, $addr",
984 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
985 let Inst{31-27} = 0b11111;
986 let Inst{26-23} = 0b0001;
987 let Inst{22-21} = opcod;
988 let Inst{20} = 0; // !load
991 let Inst{15-12} = Rt;
994 let addr{12} = 1; // add = TRUE
995 let Inst{19-16} = addr{16-13}; // Rn
996 let Inst{23} = addr{12}; // U
997 let Inst{11-0} = addr{11-0}; // imm
999 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1000 opc, "\t$Rt, $addr",
1001 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1002 let Inst{31-27} = 0b11111;
1003 let Inst{26-23} = 0b0000;
1004 let Inst{22-21} = opcod;
1005 let Inst{20} = 0; // !load
1007 // Offset: index==TRUE, wback==FALSE
1008 let Inst{10} = 1; // The P bit.
1009 let Inst{8} = 0; // The W bit.
1012 let Inst{15-12} = Rt;
1015 let Inst{19-16} = addr{12-9}; // Rn
1016 let Inst{9} = addr{8}; // U
1017 let Inst{7-0} = addr{7-0}; // imm
1019 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1020 opc, ".w\t$Rt, $addr",
1021 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1022 let Inst{31-27} = 0b11111;
1023 let Inst{26-23} = 0b0000;
1024 let Inst{22-21} = opcod;
1025 let Inst{20} = 0; // !load
1026 let Inst{11-6} = 0b000000;
1029 let Inst{15-12} = Rt;
1032 let Inst{19-16} = addr{9-6}; // Rn
1033 let Inst{3-0} = addr{5-2}; // Rm
1034 let Inst{5-4} = addr{1-0}; // imm
1038 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1039 /// register and one whose operand is a register rotated by 8/16/24.
1040 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1041 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1042 opc, ".w\t$Rd, $Rm$rot",
1043 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1044 Requires<[IsThumb2]> {
1045 let Inst{31-27} = 0b11111;
1046 let Inst{26-23} = 0b0100;
1047 let Inst{22-20} = opcod;
1048 let Inst{19-16} = 0b1111; // Rn
1049 let Inst{15-12} = 0b1111;
1053 let Inst{5-4} = rot{1-0}; // rotate
1056 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1057 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1058 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1059 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1060 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1061 Requires<[HasT2ExtractPack, IsThumb2]> {
1063 let Inst{31-27} = 0b11111;
1064 let Inst{26-23} = 0b0100;
1065 let Inst{22-20} = opcod;
1066 let Inst{19-16} = 0b1111; // Rn
1067 let Inst{15-12} = 0b1111;
1069 let Inst{5-4} = rot;
1072 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1074 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1075 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1076 opc, "\t$Rd, $Rm$rot", []>,
1077 Requires<[IsThumb2, HasT2ExtractPack]> {
1079 let Inst{31-27} = 0b11111;
1080 let Inst{26-23} = 0b0100;
1081 let Inst{22-20} = opcod;
1082 let Inst{19-16} = 0b1111; // Rn
1083 let Inst{15-12} = 0b1111;
1085 let Inst{5-4} = rot;
1088 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1089 /// register and one whose operand is a register rotated by 8/16/24.
1090 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1091 : T2ThreeReg<(outs rGPR:$Rd),
1092 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1093 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1094 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1095 Requires<[HasT2ExtractPack, IsThumb2]> {
1097 let Inst{31-27} = 0b11111;
1098 let Inst{26-23} = 0b0100;
1099 let Inst{22-20} = opcod;
1100 let Inst{15-12} = 0b1111;
1102 let Inst{5-4} = rot;
1105 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1106 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1107 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1109 let Inst{31-27} = 0b11111;
1110 let Inst{26-23} = 0b0100;
1111 let Inst{22-20} = opcod;
1112 let Inst{15-12} = 0b1111;
1114 let Inst{5-4} = rot;
1117 //===----------------------------------------------------------------------===//
1119 //===----------------------------------------------------------------------===//
1121 //===----------------------------------------------------------------------===//
1122 // Miscellaneous Instructions.
1125 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1126 string asm, list<dag> pattern>
1127 : T2XI<oops, iops, itin, asm, pattern> {
1131 let Inst{11-8} = Rd;
1132 let Inst{26} = label{11};
1133 let Inst{14-12} = label{10-8};
1134 let Inst{7-0} = label{7-0};
1137 // LEApcrel - Load a pc-relative address into a register without offending the
1139 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1140 (ins t2adrlabel:$addr, pred:$p),
1141 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1142 let Inst{31-27} = 0b11110;
1143 let Inst{25-24} = 0b10;
1144 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1147 let Inst{19-16} = 0b1111; // Rn
1152 let Inst{11-8} = Rd;
1153 let Inst{23} = addr{12};
1154 let Inst{21} = addr{12};
1155 let Inst{26} = addr{11};
1156 let Inst{14-12} = addr{10-8};
1157 let Inst{7-0} = addr{7-0};
1159 let DecoderMethod = "DecodeT2Adr";
1162 let neverHasSideEffects = 1, isReMaterializable = 1 in
1163 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1165 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1166 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1171 //===----------------------------------------------------------------------===//
1172 // Load / store Instructions.
1176 let canFoldAsLoad = 1, isReMaterializable = 1 in
1177 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1178 UnOpFrag<(load node:$Src)>>;
1180 // Loads with zero extension
1181 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1182 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1183 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1184 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1186 // Loads with sign extension
1187 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1188 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1189 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1190 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1192 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1194 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1195 (ins t2addrmode_imm8s4:$addr),
1196 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1197 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1199 // zextload i1 -> zextload i8
1200 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1201 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1202 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1203 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1204 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1205 (t2LDRBs t2addrmode_so_reg:$addr)>;
1206 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1207 (t2LDRBpci tconstpool:$addr)>;
1209 // extload -> zextload
1210 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1212 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1213 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1214 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1215 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1216 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1217 (t2LDRBs t2addrmode_so_reg:$addr)>;
1218 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1219 (t2LDRBpci tconstpool:$addr)>;
1221 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1222 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1223 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1224 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1225 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1226 (t2LDRBs t2addrmode_so_reg:$addr)>;
1227 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1228 (t2LDRBpci tconstpool:$addr)>;
1230 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1231 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1232 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1233 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1234 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1235 (t2LDRHs t2addrmode_so_reg:$addr)>;
1236 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1237 (t2LDRHpci tconstpool:$addr)>;
1239 // FIXME: The destination register of the loads and stores can't be PC, but
1240 // can be SP. We need another regclass (similar to rGPR) to represent
1241 // that. Not a pressing issue since these are selected manually,
1246 let mayLoad = 1, neverHasSideEffects = 1 in {
1247 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1248 (ins t2addrmode_imm8:$addr),
1249 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1250 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1252 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1255 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1256 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1257 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1258 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1260 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1261 (ins t2addrmode_imm8:$addr),
1262 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1263 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1265 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1267 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1268 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1269 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1270 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1272 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1273 (ins t2addrmode_imm8:$addr),
1274 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1275 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1277 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1279 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1280 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1281 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1282 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1284 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1285 (ins t2addrmode_imm8:$addr),
1286 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1287 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1289 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1291 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1292 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1293 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1294 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1296 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1297 (ins t2addrmode_imm8:$addr),
1298 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1299 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1301 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1303 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1304 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1305 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1306 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1307 } // mayLoad = 1, neverHasSideEffects = 1
1309 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1310 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1311 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1312 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1313 "\t$Rt, $addr", []> {
1316 let Inst{31-27} = 0b11111;
1317 let Inst{26-25} = 0b00;
1318 let Inst{24} = signed;
1320 let Inst{22-21} = type;
1321 let Inst{20} = 1; // load
1322 let Inst{19-16} = addr{12-9};
1323 let Inst{15-12} = Rt;
1325 let Inst{10-8} = 0b110; // PUW.
1326 let Inst{7-0} = addr{7-0};
1329 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1330 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1331 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1332 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1333 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1336 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1337 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1338 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1339 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1340 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1341 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1344 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1345 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1346 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1347 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1351 let mayStore = 1, neverHasSideEffects = 1 in {
1352 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1353 (ins GPRnopc:$Rt, t2addrmode_imm8:$addr),
1354 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1355 "str", "\t$Rt, $addr!",
1356 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1357 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1359 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1360 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1361 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1362 "strh", "\t$Rt, $addr!",
1363 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1364 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1367 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1368 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1369 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1370 "strb", "\t$Rt, $addr!",
1371 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1372 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1374 } // mayStore = 1, neverHasSideEffects = 1
1376 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1377 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1378 t2am_imm8_offset:$offset),
1379 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1380 "str", "\t$Rt, $Rn$offset",
1381 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1382 [(set GPRnopc:$Rn_wb,
1383 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1384 t2am_imm8_offset:$offset))]>;
1386 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1387 (ins rGPR:$Rt, addr_offset_none:$Rn,
1388 t2am_imm8_offset:$offset),
1389 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1390 "strh", "\t$Rt, $Rn$offset",
1391 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1392 [(set GPRnopc:$Rn_wb,
1393 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1394 t2am_imm8_offset:$offset))]>;
1396 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1397 (ins rGPR:$Rt, addr_offset_none:$Rn,
1398 t2am_imm8_offset:$offset),
1399 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1400 "strb", "\t$Rt, $Rn$offset",
1401 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1402 [(set GPRnopc:$Rn_wb,
1403 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1404 t2am_imm8_offset:$offset))]>;
1406 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1407 // put the patterns on the instruction definitions directly as ISel wants
1408 // the address base and offset to be separate operands, not a single
1409 // complex operand like we represent the instructions themselves. The
1410 // pseudos map between the two.
1411 let usesCustomInserter = 1,
1412 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1413 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1414 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1416 [(set GPRnopc:$Rn_wb,
1417 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1418 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1419 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1421 [(set GPRnopc:$Rn_wb,
1422 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1423 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1424 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1426 [(set GPRnopc:$Rn_wb,
1427 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1430 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1432 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1433 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1434 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1435 "\t$Rt, $addr", []> {
1436 let Inst{31-27} = 0b11111;
1437 let Inst{26-25} = 0b00;
1438 let Inst{24} = 0; // not signed
1440 let Inst{22-21} = type;
1441 let Inst{20} = 0; // store
1443 let Inst{10-8} = 0b110; // PUW
1447 let Inst{15-12} = Rt;
1448 let Inst{19-16} = addr{12-9};
1449 let Inst{7-0} = addr{7-0};
1452 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1453 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1454 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1456 // ldrd / strd pre / post variants
1457 // For disassembly only.
1459 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1460 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1461 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1462 let AsmMatchConverter = "cvtT2LdrdPre";
1463 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1466 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1467 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1468 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1469 "$addr.base = $wb", []>;
1471 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1472 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1473 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1474 "$addr.base = $wb", []> {
1475 let AsmMatchConverter = "cvtT2StrdPre";
1476 let DecoderMethod = "DecodeT2STRDPreInstruction";
1479 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1480 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1481 t2am_imm8s4_offset:$imm),
1482 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1483 "$addr.base = $wb", []>;
1485 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1486 // data/instruction access.
1487 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1488 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1489 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1491 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1493 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1494 let Inst{31-25} = 0b1111100;
1495 let Inst{24} = instr;
1497 let Inst{21} = write;
1499 let Inst{15-12} = 0b1111;
1502 let addr{12} = 1; // add = TRUE
1503 let Inst{19-16} = addr{16-13}; // Rn
1504 let Inst{23} = addr{12}; // U
1505 let Inst{11-0} = addr{11-0}; // imm12
1508 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1510 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1511 let Inst{31-25} = 0b1111100;
1512 let Inst{24} = instr;
1513 let Inst{23} = 0; // U = 0
1515 let Inst{21} = write;
1517 let Inst{15-12} = 0b1111;
1518 let Inst{11-8} = 0b1100;
1521 let Inst{19-16} = addr{12-9}; // Rn
1522 let Inst{7-0} = addr{7-0}; // imm8
1525 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1527 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1528 let Inst{31-25} = 0b1111100;
1529 let Inst{24} = instr;
1530 let Inst{23} = 0; // add = TRUE for T1
1532 let Inst{21} = write;
1534 let Inst{15-12} = 0b1111;
1535 let Inst{11-6} = 0000000;
1538 let Inst{19-16} = addr{9-6}; // Rn
1539 let Inst{3-0} = addr{5-2}; // Rm
1540 let Inst{5-4} = addr{1-0}; // imm2
1542 let DecoderMethod = "DecodeT2LoadShift";
1544 // FIXME: We should have a separate 'pci' variant here. As-is we represent
1545 // it via the i12 variant, which it's related to, but that means we can
1546 // represent negative immediates, which aren't legal for anything except
1547 // the 'pci' case (Rn == 15).
1550 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1551 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1552 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1554 //===----------------------------------------------------------------------===//
1555 // Load / store multiple Instructions.
1558 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1559 InstrItinClass itin_upd, bit L_bit> {
1561 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1562 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1566 let Inst{31-27} = 0b11101;
1567 let Inst{26-25} = 0b00;
1568 let Inst{24-23} = 0b01; // Increment After
1570 let Inst{21} = 0; // No writeback
1571 let Inst{20} = L_bit;
1572 let Inst{19-16} = Rn;
1573 let Inst{15-0} = regs;
1576 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1577 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1581 let Inst{31-27} = 0b11101;
1582 let Inst{26-25} = 0b00;
1583 let Inst{24-23} = 0b01; // Increment After
1585 let Inst{21} = 1; // Writeback
1586 let Inst{20} = L_bit;
1587 let Inst{19-16} = Rn;
1588 let Inst{15-0} = regs;
1591 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1592 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1596 let Inst{31-27} = 0b11101;
1597 let Inst{26-25} = 0b00;
1598 let Inst{24-23} = 0b10; // Decrement Before
1600 let Inst{21} = 0; // No writeback
1601 let Inst{20} = L_bit;
1602 let Inst{19-16} = Rn;
1603 let Inst{15-0} = regs;
1606 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1607 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1611 let Inst{31-27} = 0b11101;
1612 let Inst{26-25} = 0b00;
1613 let Inst{24-23} = 0b10; // Decrement Before
1615 let Inst{21} = 1; // Writeback
1616 let Inst{20} = L_bit;
1617 let Inst{19-16} = Rn;
1618 let Inst{15-0} = regs;
1622 let neverHasSideEffects = 1 in {
1624 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1625 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1627 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1628 InstrItinClass itin_upd, bit L_bit> {
1630 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1631 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1635 let Inst{31-27} = 0b11101;
1636 let Inst{26-25} = 0b00;
1637 let Inst{24-23} = 0b01; // Increment After
1639 let Inst{21} = 0; // No writeback
1640 let Inst{20} = L_bit;
1641 let Inst{19-16} = Rn;
1643 let Inst{14} = regs{14};
1645 let Inst{12-0} = regs{12-0};
1648 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1649 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1653 let Inst{31-27} = 0b11101;
1654 let Inst{26-25} = 0b00;
1655 let Inst{24-23} = 0b01; // Increment After
1657 let Inst{21} = 1; // Writeback
1658 let Inst{20} = L_bit;
1659 let Inst{19-16} = Rn;
1661 let Inst{14} = regs{14};
1663 let Inst{12-0} = regs{12-0};
1666 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1667 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1671 let Inst{31-27} = 0b11101;
1672 let Inst{26-25} = 0b00;
1673 let Inst{24-23} = 0b10; // Decrement Before
1675 let Inst{21} = 0; // No writeback
1676 let Inst{20} = L_bit;
1677 let Inst{19-16} = Rn;
1679 let Inst{14} = regs{14};
1681 let Inst{12-0} = regs{12-0};
1684 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1685 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1689 let Inst{31-27} = 0b11101;
1690 let Inst{26-25} = 0b00;
1691 let Inst{24-23} = 0b10; // Decrement Before
1693 let Inst{21} = 1; // Writeback
1694 let Inst{20} = L_bit;
1695 let Inst{19-16} = Rn;
1697 let Inst{14} = regs{14};
1699 let Inst{12-0} = regs{12-0};
1704 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1705 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1707 } // neverHasSideEffects
1710 //===----------------------------------------------------------------------===//
1711 // Move Instructions.
1714 let neverHasSideEffects = 1 in
1715 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1716 "mov", ".w\t$Rd, $Rm", []> {
1717 let Inst{31-27} = 0b11101;
1718 let Inst{26-25} = 0b01;
1719 let Inst{24-21} = 0b0010;
1720 let Inst{19-16} = 0b1111; // Rn
1721 let Inst{14-12} = 0b000;
1722 let Inst{7-4} = 0b0000;
1724 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1725 pred:$p, zero_reg)>;
1726 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1728 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1731 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1732 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1733 AddedComplexity = 1 in
1734 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1735 "mov", ".w\t$Rd, $imm",
1736 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1737 let Inst{31-27} = 0b11110;
1739 let Inst{24-21} = 0b0010;
1740 let Inst{19-16} = 0b1111; // Rn
1744 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1745 // Use aliases to get that to play nice here.
1746 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1748 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1751 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1752 pred:$p, zero_reg)>;
1753 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1754 pred:$p, zero_reg)>;
1756 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1757 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1758 "movw", "\t$Rd, $imm",
1759 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1760 let Inst{31-27} = 0b11110;
1762 let Inst{24-21} = 0b0010;
1763 let Inst{20} = 0; // The S bit.
1769 let Inst{11-8} = Rd;
1770 let Inst{19-16} = imm{15-12};
1771 let Inst{26} = imm{11};
1772 let Inst{14-12} = imm{10-8};
1773 let Inst{7-0} = imm{7-0};
1774 let DecoderMethod = "DecodeT2MOVTWInstruction";
1777 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1778 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1780 let Constraints = "$src = $Rd" in {
1781 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1782 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1783 "movt", "\t$Rd, $imm",
1785 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1786 let Inst{31-27} = 0b11110;
1788 let Inst{24-21} = 0b0110;
1789 let Inst{20} = 0; // The S bit.
1795 let Inst{11-8} = Rd;
1796 let Inst{19-16} = imm{15-12};
1797 let Inst{26} = imm{11};
1798 let Inst{14-12} = imm{10-8};
1799 let Inst{7-0} = imm{7-0};
1800 let DecoderMethod = "DecodeT2MOVTWInstruction";
1803 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1804 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1807 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1809 //===----------------------------------------------------------------------===//
1810 // Extend Instructions.
1815 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1816 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1817 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1818 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1819 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1821 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1822 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1823 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1824 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1825 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1829 let AddedComplexity = 16 in {
1830 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1831 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1832 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1833 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1834 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1835 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1837 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1838 // The transformation should probably be done as a combiner action
1839 // instead so we can include a check for masking back in the upper
1840 // eight bits of the source into the lower eight bits of the result.
1841 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1842 // (t2UXTB16 rGPR:$Src, 3)>,
1843 // Requires<[HasT2ExtractPack, IsThumb2]>;
1844 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1845 (t2UXTB16 rGPR:$Src, 1)>,
1846 Requires<[HasT2ExtractPack, IsThumb2]>;
1848 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1849 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1850 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1851 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1852 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1855 //===----------------------------------------------------------------------===//
1856 // Arithmetic Instructions.
1859 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1860 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1861 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1862 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1864 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1866 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1867 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1868 // AdjustInstrPostInstrSelection where we determine whether or not to
1869 // set the "s" bit based on CPSR liveness.
1871 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1872 // support for an optional CPSR definition that corresponds to the DAG
1873 // node's second value. We can then eliminate the implicit def of CPSR.
1874 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1875 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1876 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1877 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1879 let hasPostISelHook = 1 in {
1880 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1881 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1882 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1883 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1887 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1888 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1890 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1891 // CPSR and the implicit def of CPSR is not needed.
1892 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1894 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1895 // The assume-no-carry-in form uses the negation of the input since add/sub
1896 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1897 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1899 // The AddedComplexity preferences the first variant over the others since
1900 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1901 let AddedComplexity = 1 in
1902 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1903 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1904 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1905 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1906 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1907 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1908 let AddedComplexity = 1 in
1909 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1910 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1911 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1912 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1913 // The with-carry-in form matches bitwise not instead of the negation.
1914 // Effectively, the inverse interpretation of the carry flag already accounts
1915 // for part of the negation.
1916 let AddedComplexity = 1 in
1917 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1918 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1919 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1920 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1922 // Select Bytes -- for disassembly only
1924 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1925 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1926 Requires<[IsThumb2, HasThumb2DSP]> {
1927 let Inst{31-27} = 0b11111;
1928 let Inst{26-24} = 0b010;
1930 let Inst{22-20} = 0b010;
1931 let Inst{15-12} = 0b1111;
1933 let Inst{6-4} = 0b000;
1936 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1937 // And Miscellaneous operations -- for disassembly only
1938 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1939 list<dag> pat = [/* For disassembly only; pattern left blank */],
1940 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1941 string asm = "\t$Rd, $Rn, $Rm">
1942 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1943 Requires<[IsThumb2, HasThumb2DSP]> {
1944 let Inst{31-27} = 0b11111;
1945 let Inst{26-23} = 0b0101;
1946 let Inst{22-20} = op22_20;
1947 let Inst{15-12} = 0b1111;
1948 let Inst{7-4} = op7_4;
1954 let Inst{11-8} = Rd;
1955 let Inst{19-16} = Rn;
1959 // Saturating add/subtract -- for disassembly only
1961 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1962 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1963 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1964 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1965 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1966 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1967 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1968 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1969 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1970 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1971 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1972 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1973 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1974 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1975 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1976 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1977 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1978 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1979 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1980 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1981 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1982 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1984 // Signed/Unsigned add/subtract -- for disassembly only
1986 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1987 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1988 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1989 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1990 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1991 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1992 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1993 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1994 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1995 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1996 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1997 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1999 // Signed/Unsigned halving add/subtract -- for disassembly only
2001 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2002 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2003 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2004 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2005 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2006 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2007 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2008 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2009 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2010 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2011 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2012 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2014 // Helper class for disassembly only
2015 // A6.3.16 & A6.3.17
2016 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2017 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2018 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2019 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2020 let Inst{31-27} = 0b11111;
2021 let Inst{26-24} = 0b011;
2022 let Inst{23} = long;
2023 let Inst{22-20} = op22_20;
2024 let Inst{7-4} = op7_4;
2027 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2028 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2029 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2030 let Inst{31-27} = 0b11111;
2031 let Inst{26-24} = 0b011;
2032 let Inst{23} = long;
2033 let Inst{22-20} = op22_20;
2034 let Inst{7-4} = op7_4;
2037 // Unsigned Sum of Absolute Differences [and Accumulate].
2038 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2039 (ins rGPR:$Rn, rGPR:$Rm),
2040 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2041 Requires<[IsThumb2, HasThumb2DSP]> {
2042 let Inst{15-12} = 0b1111;
2044 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2045 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2046 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2047 Requires<[IsThumb2, HasThumb2DSP]>;
2049 // Signed/Unsigned saturate.
2050 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2051 string opc, string asm, list<dag> pattern>
2052 : T2I<oops, iops, itin, opc, asm, pattern> {
2058 let Inst{11-8} = Rd;
2059 let Inst{19-16} = Rn;
2060 let Inst{4-0} = sat_imm;
2061 let Inst{21} = sh{5};
2062 let Inst{14-12} = sh{4-2};
2063 let Inst{7-6} = sh{1-0};
2068 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2069 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2070 let Inst{31-27} = 0b11110;
2071 let Inst{25-22} = 0b1100;
2077 def t2SSAT16: T2SatI<
2078 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2079 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2080 Requires<[IsThumb2, HasThumb2DSP]> {
2081 let Inst{31-27} = 0b11110;
2082 let Inst{25-22} = 0b1100;
2085 let Inst{21} = 1; // sh = '1'
2086 let Inst{14-12} = 0b000; // imm3 = '000'
2087 let Inst{7-6} = 0b00; // imm2 = '00'
2088 let Inst{5-4} = 0b00;
2093 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2094 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2095 let Inst{31-27} = 0b11110;
2096 let Inst{25-22} = 0b1110;
2101 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2103 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2104 Requires<[IsThumb2, HasThumb2DSP]> {
2105 let Inst{31-22} = 0b1111001110;
2108 let Inst{21} = 1; // sh = '1'
2109 let Inst{14-12} = 0b000; // imm3 = '000'
2110 let Inst{7-6} = 0b00; // imm2 = '00'
2111 let Inst{5-4} = 0b00;
2114 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2115 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2117 //===----------------------------------------------------------------------===//
2118 // Shift and rotate Instructions.
2121 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2122 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2123 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2124 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2125 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2126 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2127 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2128 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2130 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2131 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2132 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2134 let Uses = [CPSR] in {
2135 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2136 "rrx", "\t$Rd, $Rm",
2137 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2138 let Inst{31-27} = 0b11101;
2139 let Inst{26-25} = 0b01;
2140 let Inst{24-21} = 0b0010;
2141 let Inst{19-16} = 0b1111; // Rn
2142 let Inst{14-12} = 0b000;
2143 let Inst{7-4} = 0b0011;
2147 let isCodeGenOnly = 1, Defs = [CPSR] in {
2148 def t2MOVsrl_flag : T2TwoRegShiftImm<
2149 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2150 "lsrs", ".w\t$Rd, $Rm, #1",
2151 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2152 let Inst{31-27} = 0b11101;
2153 let Inst{26-25} = 0b01;
2154 let Inst{24-21} = 0b0010;
2155 let Inst{20} = 1; // The S bit.
2156 let Inst{19-16} = 0b1111; // Rn
2157 let Inst{5-4} = 0b01; // Shift type.
2158 // Shift amount = Inst{14-12:7-6} = 1.
2159 let Inst{14-12} = 0b000;
2160 let Inst{7-6} = 0b01;
2162 def t2MOVsra_flag : T2TwoRegShiftImm<
2163 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2164 "asrs", ".w\t$Rd, $Rm, #1",
2165 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2166 let Inst{31-27} = 0b11101;
2167 let Inst{26-25} = 0b01;
2168 let Inst{24-21} = 0b0010;
2169 let Inst{20} = 1; // The S bit.
2170 let Inst{19-16} = 0b1111; // Rn
2171 let Inst{5-4} = 0b10; // Shift type.
2172 // Shift amount = Inst{14-12:7-6} = 1.
2173 let Inst{14-12} = 0b000;
2174 let Inst{7-6} = 0b01;
2178 //===----------------------------------------------------------------------===//
2179 // Bitwise Instructions.
2182 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2183 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2184 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2185 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2186 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2187 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2188 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2189 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2190 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2192 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2193 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2194 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2197 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2198 string opc, string asm, list<dag> pattern>
2199 : T2I<oops, iops, itin, opc, asm, pattern> {
2204 let Inst{11-8} = Rd;
2205 let Inst{4-0} = msb{4-0};
2206 let Inst{14-12} = lsb{4-2};
2207 let Inst{7-6} = lsb{1-0};
2210 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2211 string opc, string asm, list<dag> pattern>
2212 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2215 let Inst{19-16} = Rn;
2218 let Constraints = "$src = $Rd" in
2219 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2220 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2221 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2222 let Inst{31-27} = 0b11110;
2223 let Inst{26} = 0; // should be 0.
2225 let Inst{24-20} = 0b10110;
2226 let Inst{19-16} = 0b1111; // Rn
2228 let Inst{5} = 0; // should be 0.
2231 let msb{4-0} = imm{9-5};
2232 let lsb{4-0} = imm{4-0};
2235 def t2SBFX: T2TwoRegBitFI<
2236 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2237 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2238 let Inst{31-27} = 0b11110;
2240 let Inst{24-20} = 0b10100;
2244 def t2UBFX: T2TwoRegBitFI<
2245 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2246 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2247 let Inst{31-27} = 0b11110;
2249 let Inst{24-20} = 0b11100;
2253 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2254 let Constraints = "$src = $Rd" in {
2255 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2256 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2257 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2258 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2259 bf_inv_mask_imm:$imm))]> {
2260 let Inst{31-27} = 0b11110;
2261 let Inst{26} = 0; // should be 0.
2263 let Inst{24-20} = 0b10110;
2265 let Inst{5} = 0; // should be 0.
2268 let msb{4-0} = imm{9-5};
2269 let lsb{4-0} = imm{4-0};
2273 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2274 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2275 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2278 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2279 /// unary operation that produces a value. These are predicable and can be
2280 /// changed to modify CPSR.
2281 multiclass T2I_un_irs<bits<4> opcod, string opc,
2282 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2283 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2285 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2287 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2288 let isAsCheapAsAMove = Cheap;
2289 let isReMaterializable = ReMat;
2290 let Inst{31-27} = 0b11110;
2292 let Inst{24-21} = opcod;
2293 let Inst{19-16} = 0b1111; // Rn
2297 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2298 opc, ".w\t$Rd, $Rm",
2299 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2300 let Inst{31-27} = 0b11101;
2301 let Inst{26-25} = 0b01;
2302 let Inst{24-21} = opcod;
2303 let Inst{19-16} = 0b1111; // Rn
2304 let Inst{14-12} = 0b000; // imm3
2305 let Inst{7-6} = 0b00; // imm2
2306 let Inst{5-4} = 0b00; // type
2309 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2310 opc, ".w\t$Rd, $ShiftedRm",
2311 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2312 let Inst{31-27} = 0b11101;
2313 let Inst{26-25} = 0b01;
2314 let Inst{24-21} = opcod;
2315 let Inst{19-16} = 0b1111; // Rn
2319 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2320 let AddedComplexity = 1 in
2321 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2322 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2323 UnOpFrag<(not node:$Src)>, 1, 1>;
2325 let AddedComplexity = 1 in
2326 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2327 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2329 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2330 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2331 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2332 Requires<[IsThumb2]>;
2334 def : T2Pat<(t2_so_imm_not:$src),
2335 (t2MVNi t2_so_imm_not:$src)>;
2337 //===----------------------------------------------------------------------===//
2338 // Multiply Instructions.
2340 let isCommutable = 1 in
2341 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2342 "mul", "\t$Rd, $Rn, $Rm",
2343 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2344 let Inst{31-27} = 0b11111;
2345 let Inst{26-23} = 0b0110;
2346 let Inst{22-20} = 0b000;
2347 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2348 let Inst{7-4} = 0b0000; // Multiply
2351 def t2MLA: T2FourReg<
2352 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2353 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2354 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2355 let Inst{31-27} = 0b11111;
2356 let Inst{26-23} = 0b0110;
2357 let Inst{22-20} = 0b000;
2358 let Inst{7-4} = 0b0000; // Multiply
2361 def t2MLS: T2FourReg<
2362 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2363 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2364 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2365 let Inst{31-27} = 0b11111;
2366 let Inst{26-23} = 0b0110;
2367 let Inst{22-20} = 0b000;
2368 let Inst{7-4} = 0b0001; // Multiply and Subtract
2371 // Extra precision multiplies with low / high results
2372 let neverHasSideEffects = 1 in {
2373 let isCommutable = 1 in {
2374 def t2SMULL : T2MulLong<0b000, 0b0000,
2375 (outs rGPR:$RdLo, rGPR:$RdHi),
2376 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2377 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2379 def t2UMULL : T2MulLong<0b010, 0b0000,
2380 (outs rGPR:$RdLo, rGPR:$RdHi),
2381 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2382 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2385 // Multiply + accumulate
2386 def t2SMLAL : T2MulLong<0b100, 0b0000,
2387 (outs rGPR:$RdLo, rGPR:$RdHi),
2388 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2389 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2391 def t2UMLAL : T2MulLong<0b110, 0b0000,
2392 (outs rGPR:$RdLo, rGPR:$RdHi),
2393 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2394 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2396 def t2UMAAL : T2MulLong<0b110, 0b0110,
2397 (outs rGPR:$RdLo, rGPR:$RdHi),
2398 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2399 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2400 Requires<[IsThumb2, HasThumb2DSP]>;
2401 } // neverHasSideEffects
2403 // Rounding variants of the below included for disassembly only
2405 // Most significant word multiply
2406 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2407 "smmul", "\t$Rd, $Rn, $Rm",
2408 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2409 Requires<[IsThumb2, HasThumb2DSP]> {
2410 let Inst{31-27} = 0b11111;
2411 let Inst{26-23} = 0b0110;
2412 let Inst{22-20} = 0b101;
2413 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2414 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2417 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2418 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2419 Requires<[IsThumb2, HasThumb2DSP]> {
2420 let Inst{31-27} = 0b11111;
2421 let Inst{26-23} = 0b0110;
2422 let Inst{22-20} = 0b101;
2423 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2424 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2427 def t2SMMLA : T2FourReg<
2428 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2429 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2430 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2431 Requires<[IsThumb2, HasThumb2DSP]> {
2432 let Inst{31-27} = 0b11111;
2433 let Inst{26-23} = 0b0110;
2434 let Inst{22-20} = 0b101;
2435 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2438 def t2SMMLAR: T2FourReg<
2439 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2440 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2441 Requires<[IsThumb2, HasThumb2DSP]> {
2442 let Inst{31-27} = 0b11111;
2443 let Inst{26-23} = 0b0110;
2444 let Inst{22-20} = 0b101;
2445 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2448 def t2SMMLS: T2FourReg<
2449 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2450 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2451 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2452 Requires<[IsThumb2, HasThumb2DSP]> {
2453 let Inst{31-27} = 0b11111;
2454 let Inst{26-23} = 0b0110;
2455 let Inst{22-20} = 0b110;
2456 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2459 def t2SMMLSR:T2FourReg<
2460 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2461 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2462 Requires<[IsThumb2, HasThumb2DSP]> {
2463 let Inst{31-27} = 0b11111;
2464 let Inst{26-23} = 0b0110;
2465 let Inst{22-20} = 0b110;
2466 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2469 multiclass T2I_smul<string opc, PatFrag opnode> {
2470 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2471 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2472 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2473 (sext_inreg rGPR:$Rm, i16)))]>,
2474 Requires<[IsThumb2, HasThumb2DSP]> {
2475 let Inst{31-27} = 0b11111;
2476 let Inst{26-23} = 0b0110;
2477 let Inst{22-20} = 0b001;
2478 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2479 let Inst{7-6} = 0b00;
2480 let Inst{5-4} = 0b00;
2483 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2484 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2485 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2486 (sra rGPR:$Rm, (i32 16))))]>,
2487 Requires<[IsThumb2, HasThumb2DSP]> {
2488 let Inst{31-27} = 0b11111;
2489 let Inst{26-23} = 0b0110;
2490 let Inst{22-20} = 0b001;
2491 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2492 let Inst{7-6} = 0b00;
2493 let Inst{5-4} = 0b01;
2496 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2497 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2498 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2499 (sext_inreg rGPR:$Rm, i16)))]>,
2500 Requires<[IsThumb2, HasThumb2DSP]> {
2501 let Inst{31-27} = 0b11111;
2502 let Inst{26-23} = 0b0110;
2503 let Inst{22-20} = 0b001;
2504 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2505 let Inst{7-6} = 0b00;
2506 let Inst{5-4} = 0b10;
2509 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2510 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2511 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2512 (sra rGPR:$Rm, (i32 16))))]>,
2513 Requires<[IsThumb2, HasThumb2DSP]> {
2514 let Inst{31-27} = 0b11111;
2515 let Inst{26-23} = 0b0110;
2516 let Inst{22-20} = 0b001;
2517 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2518 let Inst{7-6} = 0b00;
2519 let Inst{5-4} = 0b11;
2522 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2523 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2524 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2525 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2526 Requires<[IsThumb2, HasThumb2DSP]> {
2527 let Inst{31-27} = 0b11111;
2528 let Inst{26-23} = 0b0110;
2529 let Inst{22-20} = 0b011;
2530 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2531 let Inst{7-6} = 0b00;
2532 let Inst{5-4} = 0b00;
2535 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2536 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2537 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2538 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2539 Requires<[IsThumb2, HasThumb2DSP]> {
2540 let Inst{31-27} = 0b11111;
2541 let Inst{26-23} = 0b0110;
2542 let Inst{22-20} = 0b011;
2543 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2544 let Inst{7-6} = 0b00;
2545 let Inst{5-4} = 0b01;
2550 multiclass T2I_smla<string opc, PatFrag opnode> {
2552 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2553 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2554 [(set rGPR:$Rd, (add rGPR:$Ra,
2555 (opnode (sext_inreg rGPR:$Rn, i16),
2556 (sext_inreg rGPR:$Rm, i16))))]>,
2557 Requires<[IsThumb2, HasThumb2DSP]> {
2558 let Inst{31-27} = 0b11111;
2559 let Inst{26-23} = 0b0110;
2560 let Inst{22-20} = 0b001;
2561 let Inst{7-6} = 0b00;
2562 let Inst{5-4} = 0b00;
2566 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2567 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2568 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2569 (sra rGPR:$Rm, (i32 16)))))]>,
2570 Requires<[IsThumb2, HasThumb2DSP]> {
2571 let Inst{31-27} = 0b11111;
2572 let Inst{26-23} = 0b0110;
2573 let Inst{22-20} = 0b001;
2574 let Inst{7-6} = 0b00;
2575 let Inst{5-4} = 0b01;
2579 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2580 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2581 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2582 (sext_inreg rGPR:$Rm, i16))))]>,
2583 Requires<[IsThumb2, HasThumb2DSP]> {
2584 let Inst{31-27} = 0b11111;
2585 let Inst{26-23} = 0b0110;
2586 let Inst{22-20} = 0b001;
2587 let Inst{7-6} = 0b00;
2588 let Inst{5-4} = 0b10;
2592 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2593 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2594 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2595 (sra rGPR:$Rm, (i32 16)))))]>,
2596 Requires<[IsThumb2, HasThumb2DSP]> {
2597 let Inst{31-27} = 0b11111;
2598 let Inst{26-23} = 0b0110;
2599 let Inst{22-20} = 0b001;
2600 let Inst{7-6} = 0b00;
2601 let Inst{5-4} = 0b11;
2605 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2606 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2607 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2608 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2609 Requires<[IsThumb2, HasThumb2DSP]> {
2610 let Inst{31-27} = 0b11111;
2611 let Inst{26-23} = 0b0110;
2612 let Inst{22-20} = 0b011;
2613 let Inst{7-6} = 0b00;
2614 let Inst{5-4} = 0b00;
2618 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2619 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2620 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2621 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2622 Requires<[IsThumb2, HasThumb2DSP]> {
2623 let Inst{31-27} = 0b11111;
2624 let Inst{26-23} = 0b0110;
2625 let Inst{22-20} = 0b011;
2626 let Inst{7-6} = 0b00;
2627 let Inst{5-4} = 0b01;
2631 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2632 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2634 // Halfword multiple accumulate long: SMLAL<x><y>
2635 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2636 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2637 [/* For disassembly only; pattern left blank */]>,
2638 Requires<[IsThumb2, HasThumb2DSP]>;
2639 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2640 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2641 [/* For disassembly only; pattern left blank */]>,
2642 Requires<[IsThumb2, HasThumb2DSP]>;
2643 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2644 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2645 [/* For disassembly only; pattern left blank */]>,
2646 Requires<[IsThumb2, HasThumb2DSP]>;
2647 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2648 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2649 [/* For disassembly only; pattern left blank */]>,
2650 Requires<[IsThumb2, HasThumb2DSP]>;
2652 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2653 def t2SMUAD: T2ThreeReg_mac<
2654 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2655 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2656 Requires<[IsThumb2, HasThumb2DSP]> {
2657 let Inst{15-12} = 0b1111;
2659 def t2SMUADX:T2ThreeReg_mac<
2660 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2661 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2662 Requires<[IsThumb2, HasThumb2DSP]> {
2663 let Inst{15-12} = 0b1111;
2665 def t2SMUSD: T2ThreeReg_mac<
2666 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2667 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2668 Requires<[IsThumb2, HasThumb2DSP]> {
2669 let Inst{15-12} = 0b1111;
2671 def t2SMUSDX:T2ThreeReg_mac<
2672 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2673 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2674 Requires<[IsThumb2, HasThumb2DSP]> {
2675 let Inst{15-12} = 0b1111;
2677 def t2SMLAD : T2FourReg_mac<
2678 0, 0b010, 0b0000, (outs rGPR:$Rd),
2679 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2680 "\t$Rd, $Rn, $Rm, $Ra", []>,
2681 Requires<[IsThumb2, HasThumb2DSP]>;
2682 def t2SMLADX : T2FourReg_mac<
2683 0, 0b010, 0b0001, (outs rGPR:$Rd),
2684 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2685 "\t$Rd, $Rn, $Rm, $Ra", []>,
2686 Requires<[IsThumb2, HasThumb2DSP]>;
2687 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2688 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2689 "\t$Rd, $Rn, $Rm, $Ra", []>,
2690 Requires<[IsThumb2, HasThumb2DSP]>;
2691 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2692 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2693 "\t$Rd, $Rn, $Rm, $Ra", []>,
2694 Requires<[IsThumb2, HasThumb2DSP]>;
2695 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2696 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2697 "\t$Ra, $Rd, $Rn, $Rm", []>,
2698 Requires<[IsThumb2, HasThumb2DSP]>;
2699 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2700 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2701 "\t$Ra, $Rd, $Rn, $Rm", []>,
2702 Requires<[IsThumb2, HasThumb2DSP]>;
2703 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2704 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2705 "\t$Ra, $Rd, $Rn, $Rm", []>,
2706 Requires<[IsThumb2, HasThumb2DSP]>;
2707 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2708 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2709 "\t$Ra, $Rd, $Rn, $Rm", []>,
2710 Requires<[IsThumb2, HasThumb2DSP]>;
2712 //===----------------------------------------------------------------------===//
2713 // Division Instructions.
2714 // Signed and unsigned division on v7-M
2716 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2717 "sdiv", "\t$Rd, $Rn, $Rm",
2718 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2719 Requires<[HasDivide, IsThumb2]> {
2720 let Inst{31-27} = 0b11111;
2721 let Inst{26-21} = 0b011100;
2723 let Inst{15-12} = 0b1111;
2724 let Inst{7-4} = 0b1111;
2727 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2728 "udiv", "\t$Rd, $Rn, $Rm",
2729 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2730 Requires<[HasDivide, IsThumb2]> {
2731 let Inst{31-27} = 0b11111;
2732 let Inst{26-21} = 0b011101;
2734 let Inst{15-12} = 0b1111;
2735 let Inst{7-4} = 0b1111;
2738 //===----------------------------------------------------------------------===//
2739 // Misc. Arithmetic Instructions.
2742 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2743 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2744 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2745 let Inst{31-27} = 0b11111;
2746 let Inst{26-22} = 0b01010;
2747 let Inst{21-20} = op1;
2748 let Inst{15-12} = 0b1111;
2749 let Inst{7-6} = 0b10;
2750 let Inst{5-4} = op2;
2754 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2755 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2757 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2758 "rbit", "\t$Rd, $Rm",
2759 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2761 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2762 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2764 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2765 "rev16", ".w\t$Rd, $Rm",
2766 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2768 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2769 "revsh", ".w\t$Rd, $Rm",
2770 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2772 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2773 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2774 (t2REVSH rGPR:$Rm)>;
2776 def t2PKHBT : T2ThreeReg<
2777 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2778 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2779 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2780 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2782 Requires<[HasT2ExtractPack, IsThumb2]> {
2783 let Inst{31-27} = 0b11101;
2784 let Inst{26-25} = 0b01;
2785 let Inst{24-20} = 0b01100;
2786 let Inst{5} = 0; // BT form
2790 let Inst{14-12} = sh{4-2};
2791 let Inst{7-6} = sh{1-0};
2794 // Alternate cases for PKHBT where identities eliminate some nodes.
2795 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2796 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2797 Requires<[HasT2ExtractPack, IsThumb2]>;
2798 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2799 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2800 Requires<[HasT2ExtractPack, IsThumb2]>;
2802 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2803 // will match the pattern below.
2804 def t2PKHTB : T2ThreeReg<
2805 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2806 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2807 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2808 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2810 Requires<[HasT2ExtractPack, IsThumb2]> {
2811 let Inst{31-27} = 0b11101;
2812 let Inst{26-25} = 0b01;
2813 let Inst{24-20} = 0b01100;
2814 let Inst{5} = 1; // TB form
2818 let Inst{14-12} = sh{4-2};
2819 let Inst{7-6} = sh{1-0};
2822 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2823 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2824 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2825 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2826 Requires<[HasT2ExtractPack, IsThumb2]>;
2827 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2828 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2829 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2830 Requires<[HasT2ExtractPack, IsThumb2]>;
2832 //===----------------------------------------------------------------------===//
2833 // Comparison Instructions...
2835 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2836 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2837 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2839 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2840 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2841 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2842 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2843 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2844 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2846 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2847 // Compare-to-zero still works out, just not the relationals
2848 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2849 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2850 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2851 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2852 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2855 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2856 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2858 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2859 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2861 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2862 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2863 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2865 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2866 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2867 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2870 // Conditional moves
2871 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2872 // a two-value operand where a dag node expects two operands. :(
2873 let neverHasSideEffects = 1 in {
2874 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2875 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2877 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2878 RegConstraint<"$false = $Rd">;
2880 let isMoveImm = 1 in
2881 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2882 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2884 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2885 RegConstraint<"$false = $Rd">;
2887 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2888 let isCodeGenOnly = 1 in {
2889 let isMoveImm = 1 in
2890 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2892 "movw", "\t$Rd, $imm", []>,
2893 RegConstraint<"$false = $Rd"> {
2894 let Inst{31-27} = 0b11110;
2896 let Inst{24-21} = 0b0010;
2897 let Inst{20} = 0; // The S bit.
2903 let Inst{11-8} = Rd;
2904 let Inst{19-16} = imm{15-12};
2905 let Inst{26} = imm{11};
2906 let Inst{14-12} = imm{10-8};
2907 let Inst{7-0} = imm{7-0};
2910 let isMoveImm = 1 in
2911 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2912 (ins rGPR:$false, i32imm:$src, pred:$p),
2913 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2915 let isMoveImm = 1 in
2916 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2917 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
2918 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2919 imm:$cc, CCR:$ccr))*/]>,
2920 RegConstraint<"$false = $Rd"> {
2921 let Inst{31-27} = 0b11110;
2923 let Inst{24-21} = 0b0011;
2924 let Inst{20} = 0; // The S bit.
2925 let Inst{19-16} = 0b1111; // Rn
2929 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2930 string opc, string asm, list<dag> pattern>
2931 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2932 let Inst{31-27} = 0b11101;
2933 let Inst{26-25} = 0b01;
2934 let Inst{24-21} = 0b0010;
2935 let Inst{20} = 0; // The S bit.
2936 let Inst{19-16} = 0b1111; // Rn
2937 let Inst{5-4} = opcod; // Shift type.
2939 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2940 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2941 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2942 RegConstraint<"$false = $Rd">;
2943 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2944 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2945 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2946 RegConstraint<"$false = $Rd">;
2947 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2948 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2949 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2950 RegConstraint<"$false = $Rd">;
2951 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2952 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2953 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2954 RegConstraint<"$false = $Rd">;
2956 multiclass T2I_bincc_irs<bits<4> opcod, string opc,
2957 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
2959 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
2960 iii, opc, ".w\t$Rd, $Rn, $imm", []>,
2961 RegConstraint<"$Rn = $Rd"> {
2962 let Inst{31-27} = 0b11110;
2964 let Inst{24-21} = opcod;
2968 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2969 iir, opc, ".w\t$Rd, $Rn, $Rm", []>,
2970 RegConstraint<"$Rn = $Rd"> {
2971 let Inst{31-27} = 0b11101;
2972 let Inst{26-25} = 0b01;
2973 let Inst{24-21} = opcod;
2974 let Inst{14-12} = 0b000; // imm3
2975 let Inst{7-6} = 0b00; // imm2
2976 let Inst{5-4} = 0b00; // type
2979 def rs : T2sTwoRegShiftedReg<(outs rGPR:$Rd),
2980 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
2981 iis, opc, ".w\t$Rd, $Rn, $ShiftedRm", []>,
2982 RegConstraint<"$Rn = $Rd"> {
2983 let Inst{31-27} = 0b11101;
2984 let Inst{26-25} = 0b01;
2985 let Inst{24-21} = opcod;
2989 defm t2ANDCC : T2I_bincc_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
2990 defm t2ORRCC : T2I_bincc_irs<0b0010, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
2991 defm t2EORCC : T2I_bincc_irs<0b0100, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
2993 } // isCodeGenOnly = 1
2994 } // neverHasSideEffects
2996 //===----------------------------------------------------------------------===//
2997 // Atomic operations intrinsics
3000 // memory barriers protect the atomic sequences
3001 let hasSideEffects = 1 in {
3002 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3003 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3004 Requires<[IsThumb, HasDB]> {
3006 let Inst{31-4} = 0xf3bf8f5;
3007 let Inst{3-0} = opt;
3011 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3012 "dsb", "\t$opt", []>,
3013 Requires<[IsThumb, HasDB]> {
3015 let Inst{31-4} = 0xf3bf8f4;
3016 let Inst{3-0} = opt;
3019 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3021 []>, Requires<[IsThumb2, HasDB]> {
3023 let Inst{31-4} = 0xf3bf8f6;
3024 let Inst{3-0} = opt;
3027 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3028 InstrItinClass itin, string opc, string asm, string cstr,
3029 list<dag> pattern, bits<4> rt2 = 0b1111>
3030 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3031 let Inst{31-27} = 0b11101;
3032 let Inst{26-20} = 0b0001101;
3033 let Inst{11-8} = rt2;
3034 let Inst{7-6} = 0b01;
3035 let Inst{5-4} = opcod;
3036 let Inst{3-0} = 0b1111;
3040 let Inst{19-16} = addr;
3041 let Inst{15-12} = Rt;
3043 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3044 InstrItinClass itin, string opc, string asm, string cstr,
3045 list<dag> pattern, bits<4> rt2 = 0b1111>
3046 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3047 let Inst{31-27} = 0b11101;
3048 let Inst{26-20} = 0b0001100;
3049 let Inst{11-8} = rt2;
3050 let Inst{7-6} = 0b01;
3051 let Inst{5-4} = opcod;
3057 let Inst{19-16} = addr;
3058 let Inst{15-12} = Rt;
3061 let mayLoad = 1 in {
3062 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3063 AddrModeNone, 4, NoItinerary,
3064 "ldrexb", "\t$Rt, $addr", "", []>;
3065 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3066 AddrModeNone, 4, NoItinerary,
3067 "ldrexh", "\t$Rt, $addr", "", []>;
3068 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3069 AddrModeNone, 4, NoItinerary,
3070 "ldrex", "\t$Rt, $addr", "", []> {
3073 let Inst{31-27} = 0b11101;
3074 let Inst{26-20} = 0b0000101;
3075 let Inst{19-16} = addr{11-8};
3076 let Inst{15-12} = Rt;
3077 let Inst{11-8} = 0b1111;
3078 let Inst{7-0} = addr{7-0};
3080 let hasExtraDefRegAllocReq = 1 in
3081 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3082 (ins addr_offset_none:$addr),
3083 AddrModeNone, 4, NoItinerary,
3084 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3087 let Inst{11-8} = Rt2;
3091 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3092 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3093 (ins rGPR:$Rt, addr_offset_none:$addr),
3094 AddrModeNone, 4, NoItinerary,
3095 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3096 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3097 (ins rGPR:$Rt, addr_offset_none:$addr),
3098 AddrModeNone, 4, NoItinerary,
3099 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3100 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3101 t2addrmode_imm0_1020s4:$addr),
3102 AddrModeNone, 4, NoItinerary,
3103 "strex", "\t$Rd, $Rt, $addr", "",
3108 let Inst{31-27} = 0b11101;
3109 let Inst{26-20} = 0b0000100;
3110 let Inst{19-16} = addr{11-8};
3111 let Inst{15-12} = Rt;
3112 let Inst{11-8} = Rd;
3113 let Inst{7-0} = addr{7-0};
3115 let hasExtraSrcRegAllocReq = 1 in
3116 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3117 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3118 AddrModeNone, 4, NoItinerary,
3119 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3122 let Inst{11-8} = Rt2;
3126 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3127 Requires<[IsThumb2, HasV7]> {
3128 let Inst{31-16} = 0xf3bf;
3129 let Inst{15-14} = 0b10;
3132 let Inst{11-8} = 0b1111;
3133 let Inst{7-4} = 0b0010;
3134 let Inst{3-0} = 0b1111;
3137 //===----------------------------------------------------------------------===//
3138 // SJLJ Exception handling intrinsics
3139 // eh_sjlj_setjmp() is an instruction sequence to store the return
3140 // address and save #0 in R0 for the non-longjmp case.
3141 // Since by its nature we may be coming from some other function to get
3142 // here, and we're using the stack frame for the containing function to
3143 // save/restore registers, we can't keep anything live in regs across
3144 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3145 // when we get here from a longjmp(). We force everything out of registers
3146 // except for our own input by listing the relevant registers in Defs. By
3147 // doing so, we also cause the prologue/epilogue code to actively preserve
3148 // all of the callee-saved resgisters, which is exactly what we want.
3149 // $val is a scratch register for our use.
3151 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3152 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3153 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3154 usesCustomInserter = 1 in {
3155 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3156 AddrModeNone, 0, NoItinerary, "", "",
3157 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3158 Requires<[IsThumb2, HasVFP2]>;
3162 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3163 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3164 usesCustomInserter = 1 in {
3165 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3166 AddrModeNone, 0, NoItinerary, "", "",
3167 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3168 Requires<[IsThumb2, NoVFP]>;
3172 //===----------------------------------------------------------------------===//
3173 // Control-Flow Instructions
3176 // FIXME: remove when we have a way to marking a MI with these properties.
3177 // FIXME: Should pc be an implicit operand like PICADD, etc?
3178 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3179 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3180 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3181 reglist:$regs, variable_ops),
3182 4, IIC_iLoad_mBr, [],
3183 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3184 RegConstraint<"$Rn = $wb">;
3186 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3187 let isPredicable = 1 in
3188 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3190 [(br bb:$target)]> {
3191 let Inst{31-27} = 0b11110;
3192 let Inst{15-14} = 0b10;
3196 let Inst{26} = target{19};
3197 let Inst{11} = target{18};
3198 let Inst{13} = target{17};
3199 let Inst{21-16} = target{16-11};
3200 let Inst{10-0} = target{10-0};
3203 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3204 def t2BR_JT : t2PseudoInst<(outs),
3205 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3207 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3209 // FIXME: Add a non-pc based case that can be predicated.
3210 def t2TBB_JT : t2PseudoInst<(outs),
3211 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3213 def t2TBH_JT : t2PseudoInst<(outs),
3214 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3216 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3217 "tbb", "\t$addr", []> {
3220 let Inst{31-20} = 0b111010001101;
3221 let Inst{19-16} = Rn;
3222 let Inst{15-5} = 0b11110000000;
3223 let Inst{4} = 0; // B form
3226 let DecoderMethod = "DecodeThumbTableBranch";
3229 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3230 "tbh", "\t$addr", []> {
3233 let Inst{31-20} = 0b111010001101;
3234 let Inst{19-16} = Rn;
3235 let Inst{15-5} = 0b11110000000;
3236 let Inst{4} = 1; // H form
3239 let DecoderMethod = "DecodeThumbTableBranch";
3241 } // isNotDuplicable, isIndirectBranch
3243 } // isBranch, isTerminator, isBarrier
3245 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3246 // a two-value operand where a dag node expects ", "two operands. :(
3247 let isBranch = 1, isTerminator = 1 in
3248 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3250 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3251 let Inst{31-27} = 0b11110;
3252 let Inst{15-14} = 0b10;
3256 let Inst{25-22} = p;
3259 let Inst{26} = target{20};
3260 let Inst{11} = target{19};
3261 let Inst{13} = target{18};
3262 let Inst{21-16} = target{17-12};
3263 let Inst{10-0} = target{11-1};
3265 let DecoderMethod = "DecodeThumb2BCCInstruction";
3268 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3270 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3273 def tTAILJMPd: tPseudoExpand<(outs),
3274 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3276 (t2B uncondbrtarget:$dst, pred:$p)>,
3277 Requires<[IsThumb2, IsIOS]>;
3281 // On non-IOS platforms R9 is callee-saved.
3282 Defs = [LR], Uses = [SP] in {
3283 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
3284 // return stack predictor.
3285 def t2BMOVPCB_CALL : tPseudoInst<(outs),
3286 (ins t_bltarget:$func, variable_ops),
3287 6, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
3288 Requires<[IsThumb, IsNotIOS]>;
3292 // On IOS R9 is call-clobbered.
3293 // R7 is marked as a use to prevent frame-pointer assignments from being
3294 // moved above / below calls.
3295 Defs = [LR], Uses = [R7, SP] in {
3296 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
3297 // return stack predictor.
3298 def t2BMOVPCBr9_CALL : tPseudoInst<(outs),
3299 (ins t_bltarget:$func, variable_ops),
3300 6, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
3301 Requires<[IsThumb, IsIOS]>;
3305 def : T2Pat<(ARMcall_nolink texternalsym:$func),
3306 (t2BMOVPCB_CALL texternalsym:$func)>,
3307 Requires<[IsThumb, IsNotIOS]>;
3308 def : T2Pat<(ARMcall_nolink texternalsym:$func),
3309 (t2BMOVPCBr9_CALL texternalsym:$func)>,
3310 Requires<[IsThumb, IsIOS]>;
3313 let Defs = [ITSTATE] in
3314 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3315 AddrModeNone, 2, IIC_iALUx,
3316 "it$mask\t$cc", "", []> {
3317 // 16-bit instruction.
3318 let Inst{31-16} = 0x0000;
3319 let Inst{15-8} = 0b10111111;
3324 let Inst{3-0} = mask;
3326 let DecoderMethod = "DecodeIT";
3329 // Branch and Exchange Jazelle -- for disassembly only
3331 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3333 let Inst{31-27} = 0b11110;
3335 let Inst{25-20} = 0b111100;
3336 let Inst{19-16} = func;
3337 let Inst{15-0} = 0b1000111100000000;
3340 // Compare and branch on zero / non-zero
3341 let isBranch = 1, isTerminator = 1 in {
3342 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3343 "cbz\t$Rn, $target", []>,
3344 T1Misc<{0,0,?,1,?,?,?}>,
3345 Requires<[IsThumb2]> {
3349 let Inst{9} = target{5};
3350 let Inst{7-3} = target{4-0};
3354 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3355 "cbnz\t$Rn, $target", []>,
3356 T1Misc<{1,0,?,1,?,?,?}>,
3357 Requires<[IsThumb2]> {
3361 let Inst{9} = target{5};
3362 let Inst{7-3} = target{4-0};
3368 // Change Processor State is a system instruction.
3369 // FIXME: Since the asm parser has currently no clean way to handle optional
3370 // operands, create 3 versions of the same instruction. Once there's a clean
3371 // framework to represent optional operands, change this behavior.
3372 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3373 !strconcat("cps", asm_op), []> {
3379 let Inst{31-27} = 0b11110;
3381 let Inst{25-20} = 0b111010;
3382 let Inst{19-16} = 0b1111;
3383 let Inst{15-14} = 0b10;
3385 let Inst{10-9} = imod;
3387 let Inst{7-5} = iflags;
3388 let Inst{4-0} = mode;
3389 let DecoderMethod = "DecodeT2CPSInstruction";
3393 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3394 "$imod.w\t$iflags, $mode">;
3395 let mode = 0, M = 0 in
3396 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3397 "$imod.w\t$iflags">;
3398 let imod = 0, iflags = 0, M = 1 in
3399 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3401 // A6.3.4 Branches and miscellaneous control
3402 // Table A6-14 Change Processor State, and hint instructions
3403 class T2I_hint<bits<8> op7_0, string opc, string asm>
3404 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3405 let Inst{31-20} = 0xf3a;
3406 let Inst{19-16} = 0b1111;
3407 let Inst{15-14} = 0b10;
3409 let Inst{10-8} = 0b000;
3410 let Inst{7-0} = op7_0;
3413 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3414 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3415 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3416 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3417 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3419 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3421 let Inst{31-20} = 0b111100111010;
3422 let Inst{19-16} = 0b1111;
3423 let Inst{15-8} = 0b10000000;
3424 let Inst{7-4} = 0b1111;
3425 let Inst{3-0} = opt;
3428 // Secure Monitor Call is a system instruction.
3429 // Option = Inst{19-16}
3430 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3431 let Inst{31-27} = 0b11110;
3432 let Inst{26-20} = 0b1111111;
3433 let Inst{15-12} = 0b1000;
3436 let Inst{19-16} = opt;
3439 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3440 string opc, string asm, list<dag> pattern>
3441 : T2I<oops, iops, itin, opc, asm, pattern> {
3443 let Inst{31-25} = 0b1110100;
3444 let Inst{24-23} = Op;
3447 let Inst{20-16} = 0b01101;
3448 let Inst{15-5} = 0b11000000000;
3449 let Inst{4-0} = mode{4-0};
3452 // Store Return State is a system instruction.
3453 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3454 "srsdb", "\tsp!, $mode", []>;
3455 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3456 "srsdb","\tsp, $mode", []>;
3457 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3458 "srsia","\tsp!, $mode", []>;
3459 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3460 "srsia","\tsp, $mode", []>;
3462 // Return From Exception is a system instruction.
3463 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3464 string opc, string asm, list<dag> pattern>
3465 : T2I<oops, iops, itin, opc, asm, pattern> {
3466 let Inst{31-20} = op31_20{11-0};
3469 let Inst{19-16} = Rn;
3470 let Inst{15-0} = 0xc000;
3473 def t2RFEDBW : T2RFE<0b111010000011,
3474 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3475 [/* For disassembly only; pattern left blank */]>;
3476 def t2RFEDB : T2RFE<0b111010000001,
3477 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3478 [/* For disassembly only; pattern left blank */]>;
3479 def t2RFEIAW : T2RFE<0b111010011011,
3480 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3481 [/* For disassembly only; pattern left blank */]>;
3482 def t2RFEIA : T2RFE<0b111010011001,
3483 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3484 [/* For disassembly only; pattern left blank */]>;
3486 //===----------------------------------------------------------------------===//
3487 // Non-Instruction Patterns
3490 // 32-bit immediate using movw + movt.
3491 // This is a single pseudo instruction to make it re-materializable.
3492 // FIXME: Remove this when we can do generalized remat.
3493 let isReMaterializable = 1, isMoveImm = 1 in
3494 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3495 [(set rGPR:$dst, (i32 imm:$src))]>,
3496 Requires<[IsThumb, HasV6T2]>;
3498 // Pseudo instruction that combines movw + movt + add pc (if pic).
3499 // It also makes it possible to rematerialize the instructions.
3500 // FIXME: Remove this when we can do generalized remat and when machine licm
3501 // can properly the instructions.
3502 let isReMaterializable = 1 in {
3503 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3505 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3506 Requires<[IsThumb2, UseMovt]>;
3508 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3510 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3511 Requires<[IsThumb2, UseMovt]>;
3514 // ConstantPool, GlobalAddress, and JumpTable
3515 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3516 Requires<[IsThumb2, DontUseMovt]>;
3517 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3518 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3519 Requires<[IsThumb2, UseMovt]>;
3521 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3522 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3524 // Pseudo instruction that combines ldr from constpool and add pc. This should
3525 // be expanded into two instructions late to allow if-conversion and
3527 let canFoldAsLoad = 1, isReMaterializable = 1 in
3528 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3530 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3532 Requires<[IsThumb2]>;
3534 // Pseudo isntruction that combines movs + predicated rsbmi
3535 // to implement integer ABS
3536 let usesCustomInserter = 1, Defs = [CPSR] in {
3537 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3538 NoItinerary, []>, Requires<[IsThumb2]>;
3541 //===----------------------------------------------------------------------===//
3542 // Coprocessor load/store -- for disassembly only
3544 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3545 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3546 let Inst{31-28} = op31_28;
3547 let Inst{27-25} = 0b110;
3550 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3551 def _OFFSET : T2CI<op31_28,
3552 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3553 asm, "\t$cop, $CRd, $addr"> {
3557 let Inst{24} = 1; // P = 1
3558 let Inst{23} = addr{8};
3559 let Inst{22} = Dbit;
3560 let Inst{21} = 0; // W = 0
3561 let Inst{20} = load;
3562 let Inst{19-16} = addr{12-9};
3563 let Inst{15-12} = CRd;
3564 let Inst{11-8} = cop;
3565 let Inst{7-0} = addr{7-0};
3566 let DecoderMethod = "DecodeCopMemInstruction";
3568 def _PRE : T2CI<op31_28,
3569 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3570 asm, "\t$cop, $CRd, $addr!"> {
3574 let Inst{24} = 1; // P = 1
3575 let Inst{23} = addr{8};
3576 let Inst{22} = Dbit;
3577 let Inst{21} = 1; // W = 1
3578 let Inst{20} = load;
3579 let Inst{19-16} = addr{12-9};
3580 let Inst{15-12} = CRd;
3581 let Inst{11-8} = cop;
3582 let Inst{7-0} = addr{7-0};
3583 let DecoderMethod = "DecodeCopMemInstruction";
3585 def _POST: T2CI<op31_28,
3586 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3587 postidx_imm8s4:$offset),
3588 asm, "\t$cop, $CRd, $addr, $offset"> {
3593 let Inst{24} = 0; // P = 0
3594 let Inst{23} = offset{8};
3595 let Inst{22} = Dbit;
3596 let Inst{21} = 1; // W = 1
3597 let Inst{20} = load;
3598 let Inst{19-16} = addr;
3599 let Inst{15-12} = CRd;
3600 let Inst{11-8} = cop;
3601 let Inst{7-0} = offset{7-0};
3602 let DecoderMethod = "DecodeCopMemInstruction";
3604 def _OPTION : T2CI<op31_28, (outs),
3605 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3606 coproc_option_imm:$option),
3607 asm, "\t$cop, $CRd, $addr, $option"> {
3612 let Inst{24} = 0; // P = 0
3613 let Inst{23} = 1; // U = 1
3614 let Inst{22} = Dbit;
3615 let Inst{21} = 0; // W = 0
3616 let Inst{20} = load;
3617 let Inst{19-16} = addr;
3618 let Inst{15-12} = CRd;
3619 let Inst{11-8} = cop;
3620 let Inst{7-0} = option;
3621 let DecoderMethod = "DecodeCopMemInstruction";
3625 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3626 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3627 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3628 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3629 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3630 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3631 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3632 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3635 //===----------------------------------------------------------------------===//
3636 // Move between special register and ARM core register -- for disassembly only
3638 // Move to ARM core register from Special Register
3642 // A/R class can only move from CPSR or SPSR.
3643 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>,
3644 Requires<[IsThumb2,IsARClass]> {
3646 let Inst{31-12} = 0b11110011111011111000;
3647 let Inst{11-8} = Rd;
3648 let Inst{7-0} = 0b0000;
3651 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3653 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>,
3654 Requires<[IsThumb2,IsARClass]> {
3656 let Inst{31-12} = 0b11110011111111111000;
3657 let Inst{11-8} = Rd;
3658 let Inst{7-0} = 0b0000;
3663 // This MRS has a mask field in bits 7-0 and can take more values than
3664 // the A/R class (a full msr_mask).
3665 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3666 "mrs", "\t$Rd, $mask", []>,
3667 Requires<[IsThumb2,IsMClass]> {
3670 let Inst{31-12} = 0b11110011111011111000;
3671 let Inst{11-8} = Rd;
3672 let Inst{19-16} = 0b1111;
3673 let Inst{7-0} = mask;
3677 // Move from ARM core register to Special Register
3681 // No need to have both system and application versions, the encodings are the
3682 // same and the assembly parser has no way to distinguish between them. The mask
3683 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3684 // the mask with the fields to be accessed in the special register.
3685 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3686 NoItinerary, "msr", "\t$mask, $Rn", []>,
3687 Requires<[IsThumb2,IsARClass]> {
3690 let Inst{31-21} = 0b11110011100;
3691 let Inst{20} = mask{4}; // R Bit
3692 let Inst{19-16} = Rn;
3693 let Inst{15-12} = 0b1000;
3694 let Inst{11-8} = mask{3-0};
3700 // Move from ARM core register to Special Register
3701 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3702 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3703 Requires<[IsThumb2,IsMClass]> {
3706 let Inst{31-21} = 0b11110011100;
3708 let Inst{19-16} = Rn;
3709 let Inst{15-12} = 0b1000;
3710 let Inst{7-0} = SYSm;
3714 //===----------------------------------------------------------------------===//
3715 // Move between coprocessor and ARM core register
3718 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3720 : T2Cop<Op, oops, iops,
3721 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3723 let Inst{27-24} = 0b1110;
3724 let Inst{20} = direction;
3734 let Inst{15-12} = Rt;
3735 let Inst{11-8} = cop;
3736 let Inst{23-21} = opc1;
3737 let Inst{7-5} = opc2;
3738 let Inst{3-0} = CRm;
3739 let Inst{19-16} = CRn;
3742 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3743 list<dag> pattern = []>
3745 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3746 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3747 let Inst{27-24} = 0b1100;
3748 let Inst{23-21} = 0b010;
3749 let Inst{20} = direction;
3757 let Inst{15-12} = Rt;
3758 let Inst{19-16} = Rt2;
3759 let Inst{11-8} = cop;
3760 let Inst{7-4} = opc1;
3761 let Inst{3-0} = CRm;
3764 /* from ARM core register to coprocessor */
3765 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3767 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3768 c_imm:$CRm, imm0_7:$opc2),
3769 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3770 imm:$CRm, imm:$opc2)]>;
3771 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3772 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3773 c_imm:$CRm, imm0_7:$opc2),
3774 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3775 imm:$CRm, imm:$opc2)]>;
3777 /* from coprocessor to ARM core register */
3778 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3779 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3780 c_imm:$CRm, imm0_7:$opc2), []>;
3782 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3783 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3784 c_imm:$CRm, imm0_7:$opc2), []>;
3786 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3787 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3789 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3790 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3793 /* from ARM core register to coprocessor */
3794 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3795 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3797 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3798 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3799 GPR:$Rt2, imm:$CRm)]>;
3800 /* from coprocessor to ARM core register */
3801 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3803 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3805 //===----------------------------------------------------------------------===//
3806 // Other Coprocessor Instructions.
3809 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3810 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3811 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3812 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3813 imm:$CRm, imm:$opc2)]> {
3814 let Inst{27-24} = 0b1110;
3823 let Inst{3-0} = CRm;
3825 let Inst{7-5} = opc2;
3826 let Inst{11-8} = cop;
3827 let Inst{15-12} = CRd;
3828 let Inst{19-16} = CRn;
3829 let Inst{23-20} = opc1;
3832 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3833 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3834 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3835 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3836 imm:$CRm, imm:$opc2)]> {
3837 let Inst{27-24} = 0b1110;
3846 let Inst{3-0} = CRm;
3848 let Inst{7-5} = opc2;
3849 let Inst{11-8} = cop;
3850 let Inst{15-12} = CRd;
3851 let Inst{19-16} = CRn;
3852 let Inst{23-20} = opc1;
3857 //===----------------------------------------------------------------------===//
3858 // Non-Instruction Patterns
3861 // SXT/UXT with no rotate
3862 let AddedComplexity = 16 in {
3863 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3864 Requires<[IsThumb2]>;
3865 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3866 Requires<[IsThumb2]>;
3867 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3868 Requires<[HasT2ExtractPack, IsThumb2]>;
3869 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3870 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3871 Requires<[HasT2ExtractPack, IsThumb2]>;
3872 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3873 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3874 Requires<[HasT2ExtractPack, IsThumb2]>;
3877 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3878 Requires<[IsThumb2]>;
3879 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3880 Requires<[IsThumb2]>;
3881 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3882 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3883 Requires<[HasT2ExtractPack, IsThumb2]>;
3884 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3885 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3886 Requires<[HasT2ExtractPack, IsThumb2]>;
3888 // Atomic load/store patterns
3889 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3890 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3891 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3892 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3893 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3894 (t2LDRBs t2addrmode_so_reg:$addr)>;
3895 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3896 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3897 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3898 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3899 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3900 (t2LDRHs t2addrmode_so_reg:$addr)>;
3901 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3902 (t2LDRi12 t2addrmode_imm12:$addr)>;
3903 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3904 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3905 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3906 (t2LDRs t2addrmode_so_reg:$addr)>;
3907 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3908 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3909 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3910 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3911 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3912 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3913 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3914 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3915 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3916 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3917 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3918 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3919 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3920 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3921 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3922 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3923 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3924 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3927 //===----------------------------------------------------------------------===//
3928 // Assembler aliases
3931 // Aliases for ADC without the ".w" optional width specifier.
3932 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3933 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3934 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3935 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3936 pred:$p, cc_out:$s)>;
3938 // Aliases for SBC without the ".w" optional width specifier.
3939 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3940 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3941 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3942 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3943 pred:$p, cc_out:$s)>;
3945 // Aliases for ADD without the ".w" optional width specifier.
3946 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3947 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3948 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3949 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3950 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3951 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3952 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3953 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3954 pred:$p, cc_out:$s)>;
3955 // ... and with the destination and source register combined.
3956 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
3957 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3958 def : t2InstAlias<"add${p} $Rdn, $imm",
3959 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3960 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
3961 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3962 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
3963 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
3964 pred:$p, cc_out:$s)>;
3966 // Aliases for SUB without the ".w" optional width specifier.
3967 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3968 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3969 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3970 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3971 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3972 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3973 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3974 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3975 pred:$p, cc_out:$s)>;
3976 // ... and with the destination and source register combined.
3977 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
3978 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3979 def : t2InstAlias<"sub${p} $Rdn, $imm",
3980 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3981 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
3982 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3983 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
3984 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
3985 pred:$p, cc_out:$s)>;
3988 // Alias for compares without the ".w" optional width specifier.
3989 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3990 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3991 def : t2InstAlias<"teq${p} $Rn, $Rm",
3992 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3993 def : t2InstAlias<"tst${p} $Rn, $Rm",
3994 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3997 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3998 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3999 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
4001 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4003 def : t2InstAlias<"ldr${p} $Rt, $addr",
4004 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4005 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4006 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4007 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4008 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4009 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4010 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4011 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4012 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4014 def : t2InstAlias<"ldr${p} $Rt, $addr",
4015 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4016 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4017 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4018 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4019 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4020 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4021 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4022 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4023 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4025 def : t2InstAlias<"ldr${p} $Rt, $addr",
4026 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4027 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4028 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4029 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4030 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4031 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4032 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4033 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4034 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4036 // Alias for MVN with(out) the ".w" optional width specifier.
4037 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4038 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4039 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4040 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4041 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4042 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4044 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4045 // shift amount is zero (i.e., unspecified).
4046 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4047 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4048 Requires<[HasT2ExtractPack, IsThumb2]>;
4049 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4050 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4051 Requires<[HasT2ExtractPack, IsThumb2]>;
4053 // PUSH/POP aliases for STM/LDM
4054 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4055 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4056 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4057 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4059 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4060 def : t2InstAlias<"stm${p} $Rn, $regs",
4061 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4062 def : t2InstAlias<"stm${p} $Rn!, $regs",
4063 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4065 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4066 def : t2InstAlias<"ldm${p} $Rn, $regs",
4067 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4068 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4069 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4071 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4072 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4073 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4074 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4075 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4077 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4078 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4079 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4080 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4081 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4083 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4084 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4085 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4086 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4089 // Alias for RSB without the ".w" optional width specifier, and with optional
4090 // implied destination register.
4091 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4092 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4093 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4094 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4095 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4096 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4097 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4098 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4101 // SSAT/USAT optional shift operand.
4102 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4103 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4104 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4105 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4107 // STM w/o the .w suffix.
4108 def : t2InstAlias<"stm${p} $Rn, $regs",
4109 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4111 // Alias for STR, STRB, and STRH without the ".w" optional
4113 def : t2InstAlias<"str${p} $Rt, $addr",
4114 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4115 def : t2InstAlias<"strb${p} $Rt, $addr",
4116 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4117 def : t2InstAlias<"strh${p} $Rt, $addr",
4118 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4120 def : t2InstAlias<"str${p} $Rt, $addr",
4121 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4122 def : t2InstAlias<"strb${p} $Rt, $addr",
4123 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4124 def : t2InstAlias<"strh${p} $Rt, $addr",
4125 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4127 // Extend instruction optional rotate operand.
4128 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4129 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4130 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4131 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4132 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4133 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4135 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4136 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4137 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4138 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4139 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4140 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4141 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4142 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4143 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4144 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4146 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4147 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4148 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4149 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4150 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4151 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4152 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4153 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4154 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4155 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4156 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4157 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4159 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4160 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4161 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4162 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4164 // Extend instruction w/o the ".w" optional width specifier.
4165 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4166 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4167 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4168 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4169 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4170 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4172 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4173 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4174 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4175 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4176 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4177 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4180 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4182 def : t2InstAlias<"mov${p} $Rd, $imm",
4183 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4184 def : t2InstAlias<"mvn${p} $Rd, $imm",
4185 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4186 // Same for AND <--> BIC
4187 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4188 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4189 pred:$p, cc_out:$s)>;
4190 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4191 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4192 pred:$p, cc_out:$s)>;
4193 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4194 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4195 pred:$p, cc_out:$s)>;
4196 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4197 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4198 pred:$p, cc_out:$s)>;
4199 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4200 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4201 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4202 pred:$p, cc_out:$s)>;
4203 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4204 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4205 pred:$p, cc_out:$s)>;
4206 // Same for CMP <--> CMN via t2_so_imm_neg
4207 def : t2InstAlias<"cmp${p} $Rd, $imm",
4208 (t2CMNzri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4209 def : t2InstAlias<"cmn${p} $Rd, $imm",
4210 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4213 // Wide 'mul' encoding can be specified with only two operands.
4214 def : t2InstAlias<"mul${p} $Rn, $Rm",
4215 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4217 // "neg" is and alias for "rsb rd, rn, #0"
4218 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4219 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4221 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4222 // these, unfortunately.
4223 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4224 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4225 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4226 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4228 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4229 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4230 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4231 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4233 // ADR w/o the .w suffix
4234 def : t2InstAlias<"adr${p} $Rd, $addr",
4235 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4237 // LDR(literal) w/ alternate [pc, #imm] syntax.
4238 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4239 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4240 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4241 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4242 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4243 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4244 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4245 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4246 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4247 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4248 // Version w/ the .w suffix.
4249 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4250 (t2LDRpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4251 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4252 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4253 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4254 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4255 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4256 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4257 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4258 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4260 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4261 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;