1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let EncoderMethod = "getT2SORegOpValue";
30 let PrintMethod = "printT2SOOperand";
31 let MIOperandInfo = (ops rGPR, i32imm);
34 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
44 // t2_so_imm - Match a 32-bit immediate operand, which is an
45 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46 // immediate splatted into multiple bytes of the word. t2_so_imm values are
47 // represented in the imm field in the same 12-bit form that they are encoded
48 // into t2_so_imm instructions: the 8-bit immediate is the least significant
49 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
50 def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> {
51 let EncoderMethod = "getT2SOImmOpValue";
54 // t2_so_imm_not - Match an immediate that is a complement
56 def t2_so_imm_not : Operand<i32>,
58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
59 }], t2_so_imm_not_XFORM>;
61 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
62 def t2_so_imm_neg : Operand<i32>,
64 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
65 }], t2_so_imm_neg_XFORM>;
67 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
68 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
69 // to get the first/second pieces.
70 def t2_so_imm2part : Operand<i32>,
72 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
76 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
77 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
78 return CurDAG->getTargetConstant(V, MVT::i32);
81 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
87 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
91 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
92 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
93 return CurDAG->getTargetConstant(V, MVT::i32);
96 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
102 def imm1_31 : PatLeaf<(i32 imm), [{
103 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
106 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
107 def imm0_4095 : Operand<i32>,
108 PatLeaf<(i32 imm), [{
109 return (uint32_t)N->getZExtValue() < 4096;
112 def imm0_4095_neg : PatLeaf<(i32 imm), [{
113 return (uint32_t)(-N->getZExtValue()) < 4096;
116 def imm0_255_neg : PatLeaf<(i32 imm), [{
117 return (uint32_t)(-N->getZExtValue()) < 255;
120 def imm0_255_not : PatLeaf<(i32 imm), [{
121 return (uint32_t)(~N->getZExtValue()) < 255;
124 // Define Thumb2 specific addressing modes.
126 // t2addrmode_imm12 := reg + imm12
127 def t2addrmode_imm12 : Operand<i32>,
128 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
129 let PrintMethod = "printAddrModeImm12Operand";
130 string EncoderMethod = "getAddrModeImm12OpValue";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
134 // t2addrmode_imm8 := reg +/- imm8
135 def t2addrmode_imm8 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137 let PrintMethod = "printT2AddrModeImm8Operand";
138 string EncoderMethod = "getT2AddrModeImm8OpValue";
139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
142 def t2am_imm8_offset : Operand<i32>,
143 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
144 [], [SDNPWantRoot]> {
145 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146 string EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
149 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
150 def t2addrmode_imm8s4 : Operand<i32> {
151 let PrintMethod = "printT2AddrModeImm8s4Operand";
152 string EncoderMethod = "getT2AddrModeImm8s4OpValue";
153 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
156 def t2am_imm8s4_offset : Operand<i32> {
157 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
160 // t2addrmode_so_reg := reg + (reg << imm2)
161 def t2addrmode_so_reg : Operand<i32>,
162 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
163 let PrintMethod = "printT2AddrModeSoRegOperand";
164 string EncoderMethod = "getT2AddrModeSORegOpValue";
165 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
169 //===----------------------------------------------------------------------===//
170 // Multiclass helpers...
174 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
175 string opc, string asm, list<dag> pattern>
176 : T2I<oops, iops, itin, opc, asm, pattern> {
181 let Inst{26} = imm{11};
182 let Inst{14-12} = imm{10-8};
183 let Inst{7-0} = imm{7-0};
187 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
188 string opc, string asm, list<dag> pattern>
189 : T2sI<oops, iops, itin, opc, asm, pattern> {
195 let Inst{26} = imm{11};
196 let Inst{14-12} = imm{10-8};
197 let Inst{7-0} = imm{7-0};
200 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
201 string opc, string asm, list<dag> pattern>
202 : T2I<oops, iops, itin, opc, asm, pattern> {
206 let Inst{19-16} = Rn;
207 let Inst{26} = imm{11};
208 let Inst{14-12} = imm{10-8};
209 let Inst{7-0} = imm{7-0};
213 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
214 string opc, string asm, list<dag> pattern>
215 : T2I<oops, iops, itin, opc, asm, pattern> {
220 let Inst{3-0} = ShiftedRm{3-0};
221 let Inst{5-4} = ShiftedRm{6-5};
222 let Inst{14-12} = ShiftedRm{11-9};
223 let Inst{7-6} = ShiftedRm{8-7};
226 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
227 string opc, string asm, list<dag> pattern>
228 : T2sI<oops, iops, itin, opc, asm, pattern> {
233 let Inst{3-0} = ShiftedRm{3-0};
234 let Inst{5-4} = ShiftedRm{6-5};
235 let Inst{14-12} = ShiftedRm{11-9};
236 let Inst{7-6} = ShiftedRm{8-7};
239 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
240 string opc, string asm, list<dag> pattern>
241 : T2I<oops, iops, itin, opc, asm, pattern> {
245 let Inst{19-16} = Rn;
246 let Inst{3-0} = ShiftedRm{3-0};
247 let Inst{5-4} = ShiftedRm{6-5};
248 let Inst{14-12} = ShiftedRm{11-9};
249 let Inst{7-6} = ShiftedRm{8-7};
252 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
253 string opc, string asm, list<dag> pattern>
254 : T2I<oops, iops, itin, opc, asm, pattern> {
262 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
263 string opc, string asm, list<dag> pattern>
264 : T2sI<oops, iops, itin, opc, asm, pattern> {
272 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
273 string opc, string asm, list<dag> pattern>
274 : T2I<oops, iops, itin, opc, asm, pattern> {
278 let Inst{19-16} = Rn;
283 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
284 string opc, string asm, list<dag> pattern>
285 : T2I<oops, iops, itin, opc, asm, pattern> {
291 let Inst{19-16} = Rn;
292 let Inst{26} = imm{11};
293 let Inst{14-12} = imm{10-8};
294 let Inst{7-0} = imm{7-0};
297 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
298 string opc, string asm, list<dag> pattern>
299 : T2sI<oops, iops, itin, opc, asm, pattern> {
305 let Inst{19-16} = Rn;
306 let Inst{26} = imm{11};
307 let Inst{14-12} = imm{10-8};
308 let Inst{7-0} = imm{7-0};
311 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
312 string opc, string asm, list<dag> pattern>
313 : T2I<oops, iops, itin, opc, asm, pattern> {
320 let Inst{14-12} = imm{4-2};
321 let Inst{7-6} = imm{1-0};
324 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
325 string opc, string asm, list<dag> pattern>
326 : T2sI<oops, iops, itin, opc, asm, pattern> {
333 let Inst{14-12} = imm{4-2};
334 let Inst{7-6} = imm{1-0};
337 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
338 string opc, string asm, list<dag> pattern>
339 : T2I<oops, iops, itin, opc, asm, pattern> {
345 let Inst{19-16} = Rn;
349 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
350 string opc, string asm, list<dag> pattern>
351 : T2sI<oops, iops, itin, opc, asm, pattern> {
357 let Inst{19-16} = Rn;
361 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
362 string opc, string asm, list<dag> pattern>
363 : T2I<oops, iops, itin, opc, asm, pattern> {
369 let Inst{19-16} = Rn;
370 let Inst{3-0} = ShiftedRm{3-0};
371 let Inst{5-4} = ShiftedRm{6-5};
372 let Inst{14-12} = ShiftedRm{11-9};
373 let Inst{7-6} = ShiftedRm{8-7};
376 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
377 string opc, string asm, list<dag> pattern>
378 : T2sI<oops, iops, itin, opc, asm, pattern> {
384 let Inst{19-16} = Rn;
385 let Inst{3-0} = ShiftedRm{3-0};
386 let Inst{5-4} = ShiftedRm{6-5};
387 let Inst{14-12} = ShiftedRm{11-9};
388 let Inst{7-6} = ShiftedRm{8-7};
391 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
392 string opc, string asm, list<dag> pattern>
393 : T2I<oops, iops, itin, opc, asm, pattern> {
399 let Inst{19-16} = Rn;
400 let Inst{15-12} = Ra;
405 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
406 dag oops, dag iops, InstrItinClass itin,
407 string opc, string asm, list<dag> pattern>
408 : T2I<oops, iops, itin, opc, asm, pattern> {
414 let Inst{31-23} = 0b111110111;
415 let Inst{22-20} = opc22_20;
416 let Inst{19-16} = Rn;
417 let Inst{15-12} = RdLo;
418 let Inst{11-8} = RdHi;
419 let Inst{7-4} = opc7_4;
424 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
425 /// unary operation that produces a value. These are predicable and can be
426 /// changed to modify CPSR.
427 multiclass T2I_un_irs<bits<4> opcod, string opc,
428 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
429 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
431 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
433 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
434 let isAsCheapAsAMove = Cheap;
435 let isReMaterializable = ReMat;
436 let Inst{31-27} = 0b11110;
438 let Inst{24-21} = opcod;
439 let Inst{19-16} = 0b1111; // Rn
443 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
445 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
446 let Inst{31-27} = 0b11101;
447 let Inst{26-25} = 0b01;
448 let Inst{24-21} = opcod;
449 let Inst{19-16} = 0b1111; // Rn
450 let Inst{14-12} = 0b000; // imm3
451 let Inst{7-6} = 0b00; // imm2
452 let Inst{5-4} = 0b00; // type
455 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
456 opc, ".w\t$Rd, $ShiftedRm",
457 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
458 let Inst{31-27} = 0b11101;
459 let Inst{26-25} = 0b01;
460 let Inst{24-21} = opcod;
461 let Inst{19-16} = 0b1111; // Rn
465 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
466 /// binary operation that produces a value. These are predicable and can be
467 /// changed to modify CPSR.
468 multiclass T2I_bin_irs<bits<4> opcod, string opc,
469 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
470 PatFrag opnode, bit Commutable = 0, string wide = ""> {
472 def ri : T2sTwoRegImm<
473 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
474 opc, "\t$Rd, $Rn, $imm",
475 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
476 let Inst{31-27} = 0b11110;
478 let Inst{24-21} = opcod;
482 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
483 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
484 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
485 let isCommutable = Commutable;
486 let Inst{31-27} = 0b11101;
487 let Inst{26-25} = 0b01;
488 let Inst{24-21} = opcod;
489 let Inst{14-12} = 0b000; // imm3
490 let Inst{7-6} = 0b00; // imm2
491 let Inst{5-4} = 0b00; // type
494 def rs : T2sTwoRegShiftedReg<
495 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
496 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
497 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
498 let Inst{31-27} = 0b11101;
499 let Inst{26-25} = 0b01;
500 let Inst{24-21} = opcod;
504 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
505 // the ".w" prefix to indicate that they are wide.
506 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
507 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
508 PatFrag opnode, bit Commutable = 0> :
509 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">;
511 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
512 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
513 /// it is equivalent to the T2I_bin_irs counterpart.
514 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
516 def ri : T2sTwoRegImm<
517 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
518 opc, ".w\t$Rd, $Rn, $imm",
519 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
520 let Inst{31-27} = 0b11110;
522 let Inst{24-21} = opcod;
526 def rr : T2sThreeReg<
527 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
528 opc, "\t$Rd, $Rn, $Rm",
529 [/* For disassembly only; pattern left blank */]> {
530 let Inst{31-27} = 0b11101;
531 let Inst{26-25} = 0b01;
532 let Inst{24-21} = opcod;
533 let Inst{14-12} = 0b000; // imm3
534 let Inst{7-6} = 0b00; // imm2
535 let Inst{5-4} = 0b00; // type
538 def rs : T2sTwoRegShiftedReg<
539 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
540 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
541 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
542 let Inst{31-27} = 0b11101;
543 let Inst{26-25} = 0b01;
544 let Inst{24-21} = opcod;
548 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
549 /// instruction modifies the CPSR register.
550 let Defs = [CPSR] in {
551 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
552 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
553 PatFrag opnode, bit Commutable = 0> {
555 def ri : T2TwoRegImm<
556 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
557 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
558 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
559 let Inst{31-27} = 0b11110;
561 let Inst{24-21} = opcod;
562 let Inst{20} = 1; // The S bit.
567 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
568 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
569 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
570 let isCommutable = Commutable;
571 let Inst{31-27} = 0b11101;
572 let Inst{26-25} = 0b01;
573 let Inst{24-21} = opcod;
574 let Inst{20} = 1; // The S bit.
575 let Inst{14-12} = 0b000; // imm3
576 let Inst{7-6} = 0b00; // imm2
577 let Inst{5-4} = 0b00; // type
580 def rs : T2TwoRegShiftedReg<
581 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
582 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
583 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
584 let Inst{31-27} = 0b11101;
585 let Inst{26-25} = 0b01;
586 let Inst{24-21} = opcod;
587 let Inst{20} = 1; // The S bit.
592 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
593 /// patterns for a binary operation that produces a value.
594 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
595 bit Commutable = 0> {
597 // The register-immediate version is re-materializable. This is useful
598 // in particular for taking the address of a local.
599 let isReMaterializable = 1 in {
600 def ri : T2sTwoRegImm<
601 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
602 opc, ".w\t$Rd, $Rn, $imm",
603 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
604 let Inst{31-27} = 0b11110;
607 let Inst{23-21} = op23_21;
613 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
614 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
615 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
619 let Inst{31-27} = 0b11110;
620 let Inst{26} = imm{11};
621 let Inst{25-24} = 0b10;
622 let Inst{23-21} = op23_21;
623 let Inst{20} = 0; // The S bit.
624 let Inst{19-16} = Rn;
626 let Inst{14-12} = imm{10-8};
628 let Inst{7-0} = imm{7-0};
631 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
632 opc, ".w\t$Rd, $Rn, $Rm",
633 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
634 let isCommutable = Commutable;
635 let Inst{31-27} = 0b11101;
636 let Inst{26-25} = 0b01;
638 let Inst{23-21} = op23_21;
639 let Inst{14-12} = 0b000; // imm3
640 let Inst{7-6} = 0b00; // imm2
641 let Inst{5-4} = 0b00; // type
644 def rs : T2sTwoRegShiftedReg<
645 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
646 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
647 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
648 let Inst{31-27} = 0b11101;
649 let Inst{26-25} = 0b01;
651 let Inst{23-21} = op23_21;
655 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
656 /// for a binary operation that produces a value and use the carry
657 /// bit. It's not predicable.
658 let Uses = [CPSR] in {
659 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
660 bit Commutable = 0> {
662 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
663 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
664 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
665 Requires<[IsThumb2]> {
666 let Inst{31-27} = 0b11110;
668 let Inst{24-21} = opcod;
672 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
673 opc, ".w\t$Rd, $Rn, $Rm",
674 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
675 Requires<[IsThumb2]> {
676 let isCommutable = Commutable;
677 let Inst{31-27} = 0b11101;
678 let Inst{26-25} = 0b01;
679 let Inst{24-21} = opcod;
680 let Inst{14-12} = 0b000; // imm3
681 let Inst{7-6} = 0b00; // imm2
682 let Inst{5-4} = 0b00; // type
685 def rs : T2sTwoRegShiftedReg<
686 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
687 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
688 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
689 Requires<[IsThumb2]> {
690 let Inst{31-27} = 0b11101;
691 let Inst{26-25} = 0b01;
692 let Inst{24-21} = opcod;
696 // Carry setting variants
697 let Defs = [CPSR] in {
698 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
699 bit Commutable = 0> {
701 def ri : T2sTwoRegImm<
702 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
703 opc, "\t$Rd, $Rn, $imm",
704 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
705 Requires<[IsThumb2]> {
706 let Inst{31-27} = 0b11110;
708 let Inst{24-21} = opcod;
709 let Inst{20} = 1; // The S bit.
713 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
714 opc, ".w\t$Rd, $Rn, $Rm",
715 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
716 Requires<[IsThumb2]> {
717 let isCommutable = Commutable;
718 let Inst{31-27} = 0b11101;
719 let Inst{26-25} = 0b01;
720 let Inst{24-21} = opcod;
721 let Inst{20} = 1; // The S bit.
722 let Inst{14-12} = 0b000; // imm3
723 let Inst{7-6} = 0b00; // imm2
724 let Inst{5-4} = 0b00; // type
727 def rs : T2sTwoRegShiftedReg<
728 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
729 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
730 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
731 Requires<[IsThumb2]> {
732 let Inst{31-27} = 0b11101;
733 let Inst{26-25} = 0b01;
734 let Inst{24-21} = opcod;
735 let Inst{20} = 1; // The S bit.
741 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
742 /// version is not needed since this is only for codegen.
743 let Defs = [CPSR] in {
744 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
746 def ri : T2TwoRegImm<
747 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
748 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
749 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
750 let Inst{31-27} = 0b11110;
752 let Inst{24-21} = opcod;
753 let Inst{20} = 1; // The S bit.
757 def rs : T2TwoRegShiftedReg<
758 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
759 IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
760 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
761 let Inst{31-27} = 0b11101;
762 let Inst{26-25} = 0b01;
763 let Inst{24-21} = opcod;
764 let Inst{20} = 1; // The S bit.
769 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
770 // rotate operation that produces a value.
771 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
773 def ri : T2sTwoRegShiftImm<
774 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
775 opc, ".w\t$Rd, $Rm, $imm",
776 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
777 let Inst{31-27} = 0b11101;
778 let Inst{26-21} = 0b010010;
779 let Inst{19-16} = 0b1111; // Rn
780 let Inst{5-4} = opcod;
783 def rr : T2sThreeReg<
784 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
785 opc, ".w\t$Rd, $Rn, $Rm",
786 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
787 let Inst{31-27} = 0b11111;
788 let Inst{26-23} = 0b0100;
789 let Inst{22-21} = opcod;
790 let Inst{15-12} = 0b1111;
791 let Inst{7-4} = 0b0000;
795 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
796 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
797 /// a explicit result, only implicitly set CPSR.
798 let isCompare = 1, Defs = [CPSR] in {
799 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
800 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
803 def ri : T2OneRegCmpImm<
804 (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
805 opc, ".w\t$Rn, $imm",
806 [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
807 let Inst{31-27} = 0b11110;
809 let Inst{24-21} = opcod;
810 let Inst{20} = 1; // The S bit.
812 let Inst{11-8} = 0b1111; // Rd
815 def rr : T2TwoRegCmp<
816 (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
817 opc, ".w\t$lhs, $rhs",
818 [(opnode GPR:$lhs, rGPR:$rhs)]> {
819 let Inst{31-27} = 0b11101;
820 let Inst{26-25} = 0b01;
821 let Inst{24-21} = opcod;
822 let Inst{20} = 1; // The S bit.
823 let Inst{14-12} = 0b000; // imm3
824 let Inst{11-8} = 0b1111; // Rd
825 let Inst{7-6} = 0b00; // imm2
826 let Inst{5-4} = 0b00; // type
829 def rs : T2OneRegCmpShiftedReg<
830 (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
831 opc, ".w\t$Rn, $ShiftedRm",
832 [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
833 let Inst{31-27} = 0b11101;
834 let Inst{26-25} = 0b01;
835 let Inst{24-21} = opcod;
836 let Inst{20} = 1; // The S bit.
837 let Inst{11-8} = 0b1111; // Rd
842 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
843 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
844 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
845 def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
846 opc, ".w\t$Rt, $addr",
847 [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
848 let Inst{31-27} = 0b11111;
849 let Inst{26-25} = 0b00;
850 let Inst{24} = signed;
852 let Inst{22-21} = opcod;
853 let Inst{20} = 1; // load
856 let Inst{15-12} = Rt;
859 let Inst{19-16} = addr{16-13}; // Rn
860 let Inst{23} = addr{12}; // U
861 let Inst{11-0} = addr{11-0}; // imm
863 def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
865 [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
866 let Inst{31-27} = 0b11111;
867 let Inst{26-25} = 0b00;
868 let Inst{24} = signed;
870 let Inst{22-21} = opcod;
871 let Inst{20} = 1; // load
873 // Offset: index==TRUE, wback==FALSE
874 let Inst{10} = 1; // The P bit.
875 let Inst{8} = 0; // The W bit.
878 let Inst{15-12} = Rt;
881 let Inst{19-16} = addr{12-9}; // Rn
882 let Inst{9} = addr{8}; // U
883 let Inst{7-0} = addr{7-0}; // imm
885 def s : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
886 opc, ".w\t$Rt, $addr",
887 [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
888 let Inst{31-27} = 0b11111;
889 let Inst{26-25} = 0b00;
890 let Inst{24} = signed;
892 let Inst{22-21} = opcod;
893 let Inst{20} = 1; // load
894 let Inst{11-6} = 0b000000;
897 let Inst{15-12} = Rt;
900 let Inst{19-16} = addr{9-6}; // Rn
901 let Inst{3-0} = addr{5-2}; // Rm
902 let Inst{5-4} = addr{1-0}; // imm
905 def pci : tPseudoInst<(outs GPR:$Rt), (ins i32imm:$addr), Size4Bytes, iis,
906 [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>;
909 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
910 multiclass T2I_st<bits<2> opcod, string opc,
911 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
912 def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
913 opc, ".w\t$Rt, $addr",
914 [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
915 let Inst{31-27} = 0b11111;
916 let Inst{26-23} = 0b0001;
917 let Inst{22-21} = opcod;
918 let Inst{20} = 0; // !load
921 let Inst{15-12} = Rt;
924 let Inst{19-16} = addr{16-13}; // Rn
925 let Inst{23} = addr{12}; // U
926 let Inst{11-0} = addr{11-0}; // imm
928 def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
930 [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
931 let Inst{31-27} = 0b11111;
932 let Inst{26-23} = 0b0000;
933 let Inst{22-21} = opcod;
934 let Inst{20} = 0; // !load
936 // Offset: index==TRUE, wback==FALSE
937 let Inst{10} = 1; // The P bit.
938 let Inst{8} = 0; // The W bit.
941 let Inst{15-12} = Rt;
944 let Inst{19-16} = addr{12-9}; // Rn
945 let Inst{9} = addr{8}; // U
946 let Inst{7-0} = addr{7-0}; // imm
948 def s : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
949 opc, ".w\t$Rt, $addr",
950 [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
951 let Inst{31-27} = 0b11111;
952 let Inst{26-23} = 0b0000;
953 let Inst{22-21} = opcod;
954 let Inst{20} = 0; // !load
955 let Inst{11-6} = 0b000000;
958 let Inst{15-12} = Rt;
961 let Inst{19-16} = addr{9-6}; // Rn
962 let Inst{3-0} = addr{5-2}; // Rm
963 let Inst{5-4} = addr{1-0}; // imm
967 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
968 /// register and one whose operand is a register rotated by 8/16/24.
969 multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
970 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
972 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
973 let Inst{31-27} = 0b11111;
974 let Inst{26-23} = 0b0100;
975 let Inst{22-20} = opcod;
976 let Inst{19-16} = 0b1111; // Rn
977 let Inst{15-12} = 0b1111;
979 let Inst{5-4} = 0b00; // rotate
981 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
982 opc, ".w\t$Rd, $Rm, ror $rot",
983 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
984 let Inst{31-27} = 0b11111;
985 let Inst{26-23} = 0b0100;
986 let Inst{22-20} = opcod;
987 let Inst{19-16} = 0b1111; // Rn
988 let Inst{15-12} = 0b1111;
992 let Inst{5-4} = rot{1-0}; // rotate
996 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
997 multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
998 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1000 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
1001 Requires<[HasT2ExtractPack, IsThumb2]> {
1002 let Inst{31-27} = 0b11111;
1003 let Inst{26-23} = 0b0100;
1004 let Inst{22-20} = opcod;
1005 let Inst{19-16} = 0b1111; // Rn
1006 let Inst{15-12} = 0b1111;
1008 let Inst{5-4} = 0b00; // rotate
1010 def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1011 opc, "\t$dst, $Rm, ror $rot",
1012 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1013 Requires<[HasT2ExtractPack, IsThumb2]> {
1014 let Inst{31-27} = 0b11111;
1015 let Inst{26-23} = 0b0100;
1016 let Inst{22-20} = opcod;
1017 let Inst{19-16} = 0b1111; // Rn
1018 let Inst{15-12} = 0b1111;
1022 let Inst{5-4} = rot{1-0}; // rotate
1026 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1028 multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1029 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1030 opc, "\t$Rd, $Rm", []> {
1031 let Inst{31-27} = 0b11111;
1032 let Inst{26-23} = 0b0100;
1033 let Inst{22-20} = opcod;
1034 let Inst{19-16} = 0b1111; // Rn
1035 let Inst{15-12} = 0b1111;
1037 let Inst{5-4} = 0b00; // rotate
1039 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1040 opc, "\t$Rd, $Rm, ror $rot", []> {
1041 let Inst{31-27} = 0b11111;
1042 let Inst{26-23} = 0b0100;
1043 let Inst{22-20} = opcod;
1044 let Inst{19-16} = 0b1111; // Rn
1045 let Inst{15-12} = 0b1111;
1049 let Inst{5-4} = rot{1-0}; // rotate
1053 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1054 /// register and one whose operand is a register rotated by 8/16/24.
1055 multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1056 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1057 opc, "\t$Rd, $Rn, $Rm",
1058 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1059 Requires<[HasT2ExtractPack, IsThumb2]> {
1060 let Inst{31-27} = 0b11111;
1061 let Inst{26-23} = 0b0100;
1062 let Inst{22-20} = opcod;
1063 let Inst{15-12} = 0b1111;
1065 let Inst{5-4} = 0b00; // rotate
1067 def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1068 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1069 [(set rGPR:$Rd, (opnode rGPR:$Rn,
1070 (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1071 Requires<[HasT2ExtractPack, IsThumb2]> {
1072 let Inst{31-27} = 0b11111;
1073 let Inst{26-23} = 0b0100;
1074 let Inst{22-20} = opcod;
1075 let Inst{15-12} = 0b1111;
1079 let Inst{5-4} = rot{1-0}; // rotate
1083 // DO variant - disassembly only, no pattern
1085 multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
1086 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1087 opc, "\t$Rd, $Rn, $Rm", []> {
1088 let Inst{31-27} = 0b11111;
1089 let Inst{26-23} = 0b0100;
1090 let Inst{22-20} = opcod;
1091 let Inst{15-12} = 0b1111;
1093 let Inst{5-4} = 0b00; // rotate
1095 def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1096 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
1097 let Inst{31-27} = 0b11111;
1098 let Inst{26-23} = 0b0100;
1099 let Inst{22-20} = opcod;
1100 let Inst{15-12} = 0b1111;
1104 let Inst{5-4} = rot{1-0}; // rotate
1108 //===----------------------------------------------------------------------===//
1110 //===----------------------------------------------------------------------===//
1112 //===----------------------------------------------------------------------===//
1113 // Miscellaneous Instructions.
1116 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1117 string asm, list<dag> pattern>
1118 : T2XI<oops, iops, itin, asm, pattern> {
1122 let Inst{11-8} = Rd;
1123 let Inst{26} = label{11};
1124 let Inst{14-12} = label{10-8};
1125 let Inst{7-0} = label{7-0};
1128 // LEApcrel - Load a pc-relative address into a register without offending the
1130 let neverHasSideEffects = 1 in {
1131 let isReMaterializable = 1 in
1132 def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
1133 "adr${p}.w\t$Rd, #$label", []> {
1134 let Inst{31-27} = 0b11110;
1135 let Inst{25-24} = 0b10;
1136 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1139 let Inst{19-16} = 0b1111; // Rn
1144 } // neverHasSideEffects
1145 def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
1146 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
1147 "adr${p}.w\t$Rd, #${label}_${id}", []> {
1148 let Inst{31-27} = 0b11110;
1149 let Inst{25-24} = 0b10;
1150 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1153 let Inst{19-16} = 0b1111; // Rn
1158 // FIXME: None of these add/sub SP special instructions should be necessary
1159 // at all for thumb2 since they use the same encodings as the generic
1160 // add/sub instructions. In thumb1 we need them since they have dedicated
1161 // encodings. At the least, they should be pseudo instructions.
1162 // ADD r, sp, {so_imm|i12}
1163 def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1164 IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> {
1165 let Inst{31-27} = 0b11110;
1167 let Inst{24-21} = 0b1000;
1170 def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1171 IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> {
1172 let Inst{31-27} = 0b11110;
1173 let Inst{25-20} = 0b100000;
1177 // ADD r, sp, so_reg
1178 def t2ADDrSPs : T2sTwoRegShiftedReg<
1179 (outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
1180 IIC_iALUsi, "add", ".w\t$Rd, $Rn, $ShiftedRm", []> {
1181 let Inst{31-27} = 0b11101;
1182 let Inst{26-25} = 0b01;
1183 let Inst{24-21} = 0b1000;
1187 // SUB r, sp, {so_imm|i12}
1188 def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1189 IIC_iALUi, "sub", ".w\t$Rd, $Rn, $imm", []> {
1190 let Inst{31-27} = 0b11110;
1192 let Inst{24-21} = 0b1101;
1195 def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1196 IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> {
1197 let Inst{31-27} = 0b11110;
1198 let Inst{25-20} = 0b101010;
1202 // SUB r, sp, so_reg
1203 def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm),
1205 "sub", "\t$Rd, $Rn, $imm", []> {
1206 let Inst{31-27} = 0b11101;
1207 let Inst{26-25} = 0b01;
1208 let Inst{24-21} = 0b1101;
1209 let Inst{19-16} = 0b1101; // Rn = sp
1213 // Signed and unsigned division on v7-M
1214 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1215 "sdiv", "\t$Rd, $Rn, $Rm",
1216 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
1217 Requires<[HasDivide, IsThumb2]> {
1218 let Inst{31-27} = 0b11111;
1219 let Inst{26-21} = 0b011100;
1221 let Inst{15-12} = 0b1111;
1222 let Inst{7-4} = 0b1111;
1225 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1226 "udiv", "\t$Rd, $Rn, $Rm",
1227 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
1228 Requires<[HasDivide, IsThumb2]> {
1229 let Inst{31-27} = 0b11111;
1230 let Inst{26-21} = 0b011101;
1232 let Inst{15-12} = 0b1111;
1233 let Inst{7-4} = 0b1111;
1236 //===----------------------------------------------------------------------===//
1237 // Load / store Instructions.
1241 let canFoldAsLoad = 1, isReMaterializable = 1 in
1242 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1243 UnOpFrag<(load node:$Src)>>;
1245 // Loads with zero extension
1246 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1247 UnOpFrag<(zextloadi16 node:$Src)>>;
1248 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1249 UnOpFrag<(zextloadi8 node:$Src)>>;
1251 // Loads with sign extension
1252 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1253 UnOpFrag<(sextloadi16 node:$Src)>>;
1254 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1255 UnOpFrag<(sextloadi8 node:$Src)>>;
1257 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1259 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1260 (ins t2addrmode_imm8s4:$addr),
1261 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1262 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1264 // zextload i1 -> zextload i8
1265 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1266 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1267 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1268 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1269 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1270 (t2LDRBs t2addrmode_so_reg:$addr)>;
1271 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1272 (t2LDRBpci tconstpool:$addr)>;
1274 // extload -> zextload
1275 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1277 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1278 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1279 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1280 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1281 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1282 (t2LDRBs t2addrmode_so_reg:$addr)>;
1283 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1284 (t2LDRBpci tconstpool:$addr)>;
1286 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1287 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1288 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1289 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1290 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1291 (t2LDRBs t2addrmode_so_reg:$addr)>;
1292 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1293 (t2LDRBpci tconstpool:$addr)>;
1295 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1296 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1297 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1298 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1299 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1300 (t2LDRHs t2addrmode_so_reg:$addr)>;
1301 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1302 (t2LDRHpci tconstpool:$addr)>;
1304 // FIXME: The destination register of the loads and stores can't be PC, but
1305 // can be SP. We need another regclass (similar to rGPR) to represent
1306 // that. Not a pressing issue since these are selected manually,
1311 class T2Iidxld<bit signed, bits<2> opcod, bit pre,
1313 AddrMode am, IndexMode im, InstrItinClass itin,
1314 string opc, string asm, string cstr, list<dag> pattern>
1315 : T2Iidxldst<signed, opcod, 1, pre, oops,
1316 iops, am,im,itin, opc, asm, cstr, pattern>;
1317 class T2Iidxst<bit signed, bits<2> opcod, bit pre,
1319 AddrMode am, IndexMode im, InstrItinClass itin,
1320 string opc, string asm, string cstr, list<dag> pattern>
1321 : T2Iidxldst<signed, opcod, 0, pre, oops,
1322 iops, am,im,itin, opc, asm, cstr, pattern>;
1324 let mayLoad = 1, neverHasSideEffects = 1 in {
1325 def t2LDR_PRE : T2Iidxld<0, 0b10, 1, (outs GPR:$Rt, GPR:$Rn),
1326 (ins t2addrmode_imm8:$addr),
1327 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1328 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1331 def t2LDR_POST : T2Iidxld<0, 0b10, 0, (outs GPR:$Rt, GPR:$Rn),
1332 (ins GPR:$base, t2am_imm8_offset:$offset),
1333 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1334 "ldr", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1337 def t2LDRB_PRE : T2Iidxld<0, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
1338 (ins t2addrmode_imm8:$addr),
1339 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1340 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1342 def t2LDRB_POST : T2Iidxld<0, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
1343 (ins GPR:$base, t2am_imm8_offset:$offset),
1344 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1345 "ldrb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1348 def t2LDRH_PRE : T2Iidxld<0, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
1349 (ins t2addrmode_imm8:$addr),
1350 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1351 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1353 def t2LDRH_POST : T2Iidxld<0, 0b01, 0, (outs GPR:$Rt, GPR:$Rn),
1354 (ins GPR:$base, t2am_imm8_offset:$offset),
1355 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1356 "ldrh", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1359 def t2LDRSB_PRE : T2Iidxld<1, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
1360 (ins t2addrmode_imm8:$addr),
1361 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1362 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1364 def t2LDRSB_POST : T2Iidxld<1, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
1365 (ins GPR:$base, t2am_imm8_offset:$offset),
1366 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1367 "ldrsb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1370 def t2LDRSH_PRE : T2Iidxld<1, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
1371 (ins t2addrmode_imm8:$addr),
1372 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1373 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1375 def t2LDRSH_POST : T2Iidxld<1, 0b01, 0, (outs GPR:$dst, GPR:$Rn),
1376 (ins GPR:$base, t2am_imm8_offset:$offset),
1377 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1378 "ldrsh", "\t$dst, [$Rn], $offset", "$base = $Rn",
1380 } // mayLoad = 1, neverHasSideEffects = 1
1382 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1383 // for disassembly only.
1384 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1385 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1386 : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1387 "\t$Rt, $addr", []> {
1388 let Inst{31-27} = 0b11111;
1389 let Inst{26-25} = 0b00;
1390 let Inst{24} = signed;
1392 let Inst{22-21} = type;
1393 let Inst{20} = 1; // load
1395 let Inst{10-8} = 0b110; // PUW.
1399 let Inst{15-12} = Rt;
1400 let Inst{19-16} = addr{12-9};
1401 let Inst{7-0} = addr{7-0};
1404 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1405 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1406 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1407 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1408 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1411 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1412 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1413 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1414 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1415 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1416 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1419 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1420 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1421 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1422 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1425 def t2STR_PRE : T2Iidxst<0, 0b10, 1, (outs GPR:$base_wb),
1426 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1427 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1428 "str", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1430 (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1432 def t2STR_POST : T2Iidxst<0, 0b10, 0, (outs GPR:$base_wb),
1433 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1434 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1435 "str", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1437 (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1439 def t2STRH_PRE : T2Iidxst<0, 0b01, 1, (outs GPR:$base_wb),
1440 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1441 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1442 "strh", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1444 (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1446 def t2STRH_POST : T2Iidxst<0, 0b01, 0, (outs GPR:$base_wb),
1447 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1448 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1449 "strh", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1451 (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1453 def t2STRB_PRE : T2Iidxst<0, 0b00, 1, (outs GPR:$base_wb),
1454 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1455 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1456 "strb", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1458 (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1460 def t2STRB_POST : T2Iidxst<0, 0b00, 0, (outs GPR:$base_wb),
1461 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1462 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1463 "strb", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1465 (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1467 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1469 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1470 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1471 : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1472 "\t$Rt, $addr", []> {
1473 let Inst{31-27} = 0b11111;
1474 let Inst{26-25} = 0b00;
1475 let Inst{24} = 0; // not signed
1477 let Inst{22-21} = type;
1478 let Inst{20} = 0; // store
1480 let Inst{10-8} = 0b110; // PUW
1484 let Inst{15-12} = Rt;
1485 let Inst{19-16} = addr{12-9};
1486 let Inst{7-0} = addr{7-0};
1489 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1490 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1491 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1493 // ldrd / strd pre / post variants
1494 // For disassembly only.
1496 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1497 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1498 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1500 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1501 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1502 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1504 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1505 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1506 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1508 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1509 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1510 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1512 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1513 // data/instruction access. These are for disassembly only.
1514 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1515 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1516 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1518 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1520 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1521 let Inst{31-25} = 0b1111100;
1522 let Inst{24} = instr;
1524 let Inst{21} = write;
1526 let Inst{15-12} = 0b1111;
1529 let Inst{19-16} = addr{16-13}; // Rn
1530 let Inst{23} = addr{12}; // U
1531 let Inst{11-0} = addr{11-0}; // imm12
1534 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1536 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1537 let Inst{31-25} = 0b1111100;
1538 let Inst{24} = instr;
1539 let Inst{23} = 0; // U = 0
1541 let Inst{21} = write;
1543 let Inst{15-12} = 0b1111;
1544 let Inst{11-8} = 0b1100;
1547 let Inst{19-16} = addr{12-9}; // Rn
1548 let Inst{7-0} = addr{7-0}; // imm8
1551 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1553 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1554 let Inst{31-25} = 0b1111100;
1555 let Inst{24} = instr;
1556 let Inst{23} = 0; // add = TRUE for T1
1558 let Inst{21} = write;
1560 let Inst{15-12} = 0b1111;
1561 let Inst{11-6} = 0000000;
1564 let Inst{19-16} = addr{9-6}; // Rn
1565 let Inst{3-0} = addr{5-2}; // Rm
1566 let Inst{5-4} = addr{1-0}; // imm2
1570 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1571 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1572 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1574 //===----------------------------------------------------------------------===//
1575 // Load / store multiple Instructions.
1578 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1579 InstrItinClass itin_upd, bit L_bit> {
1581 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1582 itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1586 let Inst{31-27} = 0b11101;
1587 let Inst{26-25} = 0b00;
1588 let Inst{24-23} = 0b01; // Increment After
1590 let Inst{21} = 0; // No writeback
1591 let Inst{20} = L_bit;
1592 let Inst{19-16} = Rn;
1593 let Inst{15-0} = regs;
1596 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1597 itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1601 let Inst{31-27} = 0b11101;
1602 let Inst{26-25} = 0b00;
1603 let Inst{24-23} = 0b01; // Increment After
1605 let Inst{21} = 1; // Writeback
1606 let Inst{20} = L_bit;
1607 let Inst{19-16} = Rn;
1608 let Inst{15-0} = regs;
1611 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1612 itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1616 let Inst{31-27} = 0b11101;
1617 let Inst{26-25} = 0b00;
1618 let Inst{24-23} = 0b10; // Decrement Before
1620 let Inst{21} = 0; // No writeback
1621 let Inst{20} = L_bit;
1622 let Inst{19-16} = Rn;
1623 let Inst{15-0} = regs;
1626 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1627 itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1631 let Inst{31-27} = 0b11101;
1632 let Inst{26-25} = 0b00;
1633 let Inst{24-23} = 0b10; // Decrement Before
1635 let Inst{21} = 1; // Writeback
1636 let Inst{20} = L_bit;
1637 let Inst{19-16} = Rn;
1638 let Inst{15-0} = regs;
1642 let neverHasSideEffects = 1 in {
1644 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1645 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1647 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1648 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1650 } // neverHasSideEffects
1653 //===----------------------------------------------------------------------===//
1654 // Move Instructions.
1657 let neverHasSideEffects = 1 in
1658 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1659 "mov", ".w\t$Rd, $Rm", []> {
1660 let Inst{31-27} = 0b11101;
1661 let Inst{26-25} = 0b01;
1662 let Inst{24-21} = 0b0010;
1663 let Inst{19-16} = 0b1111; // Rn
1664 let Inst{14-12} = 0b000;
1665 let Inst{7-4} = 0b0000;
1668 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1669 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1670 AddedComplexity = 1 in
1671 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1672 "mov", ".w\t$Rd, $imm",
1673 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1674 let Inst{31-27} = 0b11110;
1676 let Inst{24-21} = 0b0010;
1677 let Inst{19-16} = 0b1111; // Rn
1681 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1682 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm:$imm), IIC_iMOVi,
1683 "movw", "\t$Rd, $imm",
1684 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1685 let Inst{31-27} = 0b11110;
1687 let Inst{24-21} = 0b0010;
1688 let Inst{20} = 0; // The S bit.
1694 let Inst{11-8} = Rd;
1695 let Inst{19-16} = imm{15-12};
1696 let Inst{26} = imm{11};
1697 let Inst{14-12} = imm{10-8};
1698 let Inst{7-0} = imm{7-0};
1701 let Constraints = "$src = $Rd" in
1702 def t2MOVTi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1703 "movt", "\t$Rd, $imm",
1705 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1706 let Inst{31-27} = 0b11110;
1708 let Inst{24-21} = 0b0110;
1709 let Inst{20} = 0; // The S bit.
1715 let Inst{11-8} = Rd;
1716 let Inst{19-16} = imm{15-12};
1717 let Inst{26} = imm{11};
1718 let Inst{14-12} = imm{10-8};
1719 let Inst{7-0} = imm{7-0};
1722 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1724 //===----------------------------------------------------------------------===//
1725 // Extend Instructions.
1730 defm t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1731 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1732 defm t2SXTH : T2I_ext_rrot<0b000, "sxth",
1733 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1734 defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1736 defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1737 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1738 defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1739 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1740 defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1742 // TODO: SXT(A){B|H}16 - done for disassembly only
1746 let AddedComplexity = 16 in {
1747 defm t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1748 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1749 defm t2UXTH : T2I_ext_rrot<0b001, "uxth",
1750 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1751 defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1752 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1754 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1755 // The transformation should probably be done as a combiner action
1756 // instead so we can include a check for masking back in the upper
1757 // eight bits of the source into the lower eight bits of the result.
1758 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1759 // (t2UXTB16r_rot rGPR:$Src, 24)>,
1760 // Requires<[HasT2ExtractPack, IsThumb2]>;
1761 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1762 (t2UXTB16r_rot rGPR:$Src, 8)>,
1763 Requires<[HasT2ExtractPack, IsThumb2]>;
1765 defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1766 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1767 defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1768 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1769 defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1772 //===----------------------------------------------------------------------===//
1773 // Arithmetic Instructions.
1776 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1777 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1778 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1779 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1781 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1782 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1783 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1784 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1785 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1786 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1787 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1789 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1790 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1791 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1792 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1793 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1794 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1795 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1796 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1799 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1800 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1801 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1802 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1804 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1805 // The assume-no-carry-in form uses the negation of the input since add/sub
1806 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1807 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1809 // The AddedComplexity preferences the first variant over the others since
1810 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1811 let AddedComplexity = 1 in
1812 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1813 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1814 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1815 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1816 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1817 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1818 let AddedComplexity = 1 in
1819 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1820 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1821 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1822 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1823 // The with-carry-in form matches bitwise not instead of the negation.
1824 // Effectively, the inverse interpretation of the carry flag already accounts
1825 // for part of the negation.
1826 let AddedComplexity = 1 in
1827 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1828 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1829 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1830 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1832 // Select Bytes -- for disassembly only
1834 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1835 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
1836 let Inst{31-27} = 0b11111;
1837 let Inst{26-24} = 0b010;
1839 let Inst{22-20} = 0b010;
1840 let Inst{15-12} = 0b1111;
1842 let Inst{6-4} = 0b000;
1845 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1846 // And Miscellaneous operations -- for disassembly only
1847 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1848 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1849 : T2I<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, opc,
1850 "\t$Rd, $Rn, $Rm", pat> {
1851 let Inst{31-27} = 0b11111;
1852 let Inst{26-23} = 0b0101;
1853 let Inst{22-20} = op22_20;
1854 let Inst{15-12} = 0b1111;
1855 let Inst{7-4} = op7_4;
1861 let Inst{11-8} = Rd;
1862 let Inst{19-16} = Rn;
1866 // Saturating add/subtract -- for disassembly only
1868 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1869 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))]>;
1870 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1871 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1872 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1873 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1874 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1875 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1876 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1877 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))]>;
1878 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1879 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1880 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1881 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1882 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1883 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1884 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1885 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1887 // Signed/Unsigned add/subtract -- for disassembly only
1889 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1890 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1891 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1892 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1893 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1894 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1895 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1896 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1897 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1898 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1899 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1900 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1902 // Signed/Unsigned halving add/subtract -- for disassembly only
1904 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1905 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1906 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1907 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1908 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1909 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1910 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1911 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1912 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1913 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1914 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1915 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1917 // Helper class for disassembly only
1918 // A6.3.16 & A6.3.17
1919 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1920 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1921 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1922 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1923 let Inst{31-27} = 0b11111;
1924 let Inst{26-24} = 0b011;
1925 let Inst{23} = long;
1926 let Inst{22-20} = op22_20;
1927 let Inst{7-4} = op7_4;
1930 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1931 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1932 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1933 let Inst{31-27} = 0b11111;
1934 let Inst{26-24} = 0b011;
1935 let Inst{23} = long;
1936 let Inst{22-20} = op22_20;
1937 let Inst{7-4} = op7_4;
1940 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1942 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1943 (ins rGPR:$Rn, rGPR:$Rm),
1944 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
1945 let Inst{15-12} = 0b1111;
1947 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1948 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1949 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
1951 // Signed/Unsigned saturate -- for disassembly only
1953 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1954 string opc, string asm, list<dag> pattern>
1955 : T2I<oops, iops, itin, opc, asm, pattern> {
1961 let Inst{11-8} = Rd;
1962 let Inst{19-16} = Rn;
1963 let Inst{4-0} = sat_imm{4-0};
1964 let Inst{21} = sh{6};
1965 let Inst{14-12} = sh{4-2};
1966 let Inst{7-6} = sh{1-0};
1970 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1971 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1972 [/* For disassembly only; pattern left blank */]> {
1973 let Inst{31-27} = 0b11110;
1974 let Inst{25-22} = 0b1100;
1979 def t2SSAT16: T2SatI<
1980 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
1981 "ssat16", "\t$Rd, $sat_imm, $Rn",
1982 [/* For disassembly only; pattern left blank */]> {
1983 let Inst{31-27} = 0b11110;
1984 let Inst{25-22} = 0b1100;
1987 let Inst{21} = 1; // sh = '1'
1988 let Inst{14-12} = 0b000; // imm3 = '000'
1989 let Inst{7-6} = 0b00; // imm2 = '00'
1993 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1994 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1995 [/* For disassembly only; pattern left blank */]> {
1996 let Inst{31-27} = 0b11110;
1997 let Inst{25-22} = 0b1110;
2002 def t2USAT16: T2SatI<
2003 (outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
2004 "usat16", "\t$dst, $sat_imm, $Rn",
2005 [/* For disassembly only; pattern left blank */]> {
2006 let Inst{31-27} = 0b11110;
2007 let Inst{25-22} = 0b1110;
2010 let Inst{21} = 1; // sh = '1'
2011 let Inst{14-12} = 0b000; // imm3 = '000'
2012 let Inst{7-6} = 0b00; // imm2 = '00'
2015 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2016 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2018 //===----------------------------------------------------------------------===//
2019 // Shift and rotate Instructions.
2022 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2023 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2024 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2025 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2027 let Uses = [CPSR] in {
2028 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2029 "rrx", "\t$Rd, $Rm",
2030 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2031 let Inst{31-27} = 0b11101;
2032 let Inst{26-25} = 0b01;
2033 let Inst{24-21} = 0b0010;
2034 let Inst{19-16} = 0b1111; // Rn
2035 let Inst{14-12} = 0b000;
2036 let Inst{7-4} = 0b0011;
2040 let Defs = [CPSR] in {
2041 def t2MOVsrl_flag : T2TwoRegShiftImm<
2042 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2043 "lsrs", ".w\t$Rd, $Rm, #1",
2044 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2045 let Inst{31-27} = 0b11101;
2046 let Inst{26-25} = 0b01;
2047 let Inst{24-21} = 0b0010;
2048 let Inst{20} = 1; // The S bit.
2049 let Inst{19-16} = 0b1111; // Rn
2050 let Inst{5-4} = 0b01; // Shift type.
2051 // Shift amount = Inst{14-12:7-6} = 1.
2052 let Inst{14-12} = 0b000;
2053 let Inst{7-6} = 0b01;
2055 def t2MOVsra_flag : T2TwoRegShiftImm<
2056 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2057 "asrs", ".w\t$Rd, $Rm, #1",
2058 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2059 let Inst{31-27} = 0b11101;
2060 let Inst{26-25} = 0b01;
2061 let Inst{24-21} = 0b0010;
2062 let Inst{20} = 1; // The S bit.
2063 let Inst{19-16} = 0b1111; // Rn
2064 let Inst{5-4} = 0b10; // Shift type.
2065 // Shift amount = Inst{14-12:7-6} = 1.
2066 let Inst{14-12} = 0b000;
2067 let Inst{7-6} = 0b01;
2071 //===----------------------------------------------------------------------===//
2072 // Bitwise Instructions.
2075 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2076 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2077 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2078 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2079 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2080 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2081 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2082 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2083 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2085 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2086 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2087 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2089 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2090 string opc, string asm, list<dag> pattern>
2091 : T2I<oops, iops, itin, opc, asm, pattern> {
2096 let Inst{11-8} = Rd;
2097 let Inst{4-0} = msb{4-0};
2098 let Inst{14-12} = lsb{4-2};
2099 let Inst{7-6} = lsb{1-0};
2102 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2103 string opc, string asm, list<dag> pattern>
2104 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2107 let Inst{19-16} = Rn;
2110 let Constraints = "$src = $Rd" in
2111 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2112 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2113 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2114 let Inst{31-27} = 0b11110;
2116 let Inst{24-20} = 0b10110;
2117 let Inst{19-16} = 0b1111; // Rn
2121 let msb{4-0} = imm{9-5};
2122 let lsb{4-0} = imm{4-0};
2125 def t2SBFX: T2TwoRegBitFI<
2126 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2127 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2128 let Inst{31-27} = 0b11110;
2130 let Inst{24-20} = 0b10100;
2134 def t2UBFX: T2TwoRegBitFI<
2135 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2136 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2137 let Inst{31-27} = 0b11110;
2139 let Inst{24-20} = 0b11100;
2143 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2144 let Constraints = "$src = $Rd" in
2145 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2146 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2147 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2148 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2149 bf_inv_mask_imm:$imm))]> {
2150 let Inst{31-27} = 0b11110;
2152 let Inst{24-20} = 0b10110;
2156 let msb{4-0} = imm{9-5};
2157 let lsb{4-0} = imm{4-0};
2160 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2161 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2162 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2164 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2165 let AddedComplexity = 1 in
2166 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2167 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2168 UnOpFrag<(not node:$Src)>, 1, 1>;
2171 let AddedComplexity = 1 in
2172 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2173 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2175 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2176 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2177 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2178 Requires<[IsThumb2]>;
2180 def : T2Pat<(t2_so_imm_not:$src),
2181 (t2MVNi t2_so_imm_not:$src)>;
2183 //===----------------------------------------------------------------------===//
2184 // Multiply Instructions.
2186 let isCommutable = 1 in
2187 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2188 "mul", "\t$Rd, $Rn, $Rm",
2189 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2190 let Inst{31-27} = 0b11111;
2191 let Inst{26-23} = 0b0110;
2192 let Inst{22-20} = 0b000;
2193 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2194 let Inst{7-4} = 0b0000; // Multiply
2197 def t2MLA: T2FourReg<
2198 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2199 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2200 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2201 let Inst{31-27} = 0b11111;
2202 let Inst{26-23} = 0b0110;
2203 let Inst{22-20} = 0b000;
2204 let Inst{7-4} = 0b0000; // Multiply
2207 def t2MLS: T2FourReg<
2208 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2209 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2210 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2211 let Inst{31-27} = 0b11111;
2212 let Inst{26-23} = 0b0110;
2213 let Inst{22-20} = 0b000;
2214 let Inst{7-4} = 0b0001; // Multiply and Subtract
2217 // Extra precision multiplies with low / high results
2218 let neverHasSideEffects = 1 in {
2219 let isCommutable = 1 in {
2220 def t2SMULL : T2MulLong<0b000, 0b0000,
2221 (outs rGPR:$Rd, rGPR:$Ra),
2222 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2223 "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
2225 def t2UMULL : T2MulLong<0b010, 0b0000,
2226 (outs rGPR:$RdLo, rGPR:$RdHi),
2227 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2228 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2231 // Multiply + accumulate
2232 def t2SMLAL : T2MulLong<0b100, 0b0000,
2233 (outs rGPR:$RdLo, rGPR:$RdHi),
2234 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2235 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2237 def t2UMLAL : T2MulLong<0b110, 0b0000,
2238 (outs rGPR:$RdLo, rGPR:$RdHi),
2239 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2240 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2242 def t2UMAAL : T2MulLong<0b110, 0b0110,
2243 (outs rGPR:$RdLo, rGPR:$RdHi),
2244 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2245 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2246 } // neverHasSideEffects
2248 // Rounding variants of the below included for disassembly only
2250 // Most significant word multiply
2251 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2252 "smmul", "\t$Rd, $Rn, $Rm",
2253 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
2254 let Inst{31-27} = 0b11111;
2255 let Inst{26-23} = 0b0110;
2256 let Inst{22-20} = 0b101;
2257 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2258 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2261 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2262 "smmulr", "\t$Rd, $Rn, $Rm", []> {
2263 let Inst{31-27} = 0b11111;
2264 let Inst{26-23} = 0b0110;
2265 let Inst{22-20} = 0b101;
2266 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2267 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2270 def t2SMMLA : T2FourReg<
2271 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2272 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2273 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
2274 let Inst{31-27} = 0b11111;
2275 let Inst{26-23} = 0b0110;
2276 let Inst{22-20} = 0b101;
2277 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2280 def t2SMMLAR: T2FourReg<
2281 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2282 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
2283 let Inst{31-27} = 0b11111;
2284 let Inst{26-23} = 0b0110;
2285 let Inst{22-20} = 0b101;
2286 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2289 def t2SMMLS: T2FourReg<
2290 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2291 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2292 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
2293 let Inst{31-27} = 0b11111;
2294 let Inst{26-23} = 0b0110;
2295 let Inst{22-20} = 0b110;
2296 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2299 def t2SMMLSR:T2FourReg<
2300 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2301 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
2302 let Inst{31-27} = 0b11111;
2303 let Inst{26-23} = 0b0110;
2304 let Inst{22-20} = 0b110;
2305 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2308 multiclass T2I_smul<string opc, PatFrag opnode> {
2309 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2310 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2311 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2312 (sext_inreg rGPR:$Rm, i16)))]> {
2313 let Inst{31-27} = 0b11111;
2314 let Inst{26-23} = 0b0110;
2315 let Inst{22-20} = 0b001;
2316 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2317 let Inst{7-6} = 0b00;
2318 let Inst{5-4} = 0b00;
2321 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2322 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2323 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2324 (sra rGPR:$Rm, (i32 16))))]> {
2325 let Inst{31-27} = 0b11111;
2326 let Inst{26-23} = 0b0110;
2327 let Inst{22-20} = 0b001;
2328 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2329 let Inst{7-6} = 0b00;
2330 let Inst{5-4} = 0b01;
2333 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2334 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2335 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2336 (sext_inreg rGPR:$Rm, i16)))]> {
2337 let Inst{31-27} = 0b11111;
2338 let Inst{26-23} = 0b0110;
2339 let Inst{22-20} = 0b001;
2340 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2341 let Inst{7-6} = 0b00;
2342 let Inst{5-4} = 0b10;
2345 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2346 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2347 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2348 (sra rGPR:$Rm, (i32 16))))]> {
2349 let Inst{31-27} = 0b11111;
2350 let Inst{26-23} = 0b0110;
2351 let Inst{22-20} = 0b001;
2352 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2353 let Inst{7-6} = 0b00;
2354 let Inst{5-4} = 0b11;
2357 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2358 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2359 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2360 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
2361 let Inst{31-27} = 0b11111;
2362 let Inst{26-23} = 0b0110;
2363 let Inst{22-20} = 0b011;
2364 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2365 let Inst{7-6} = 0b00;
2366 let Inst{5-4} = 0b00;
2369 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2370 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2371 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2372 (sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
2373 let Inst{31-27} = 0b11111;
2374 let Inst{26-23} = 0b0110;
2375 let Inst{22-20} = 0b011;
2376 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2377 let Inst{7-6} = 0b00;
2378 let Inst{5-4} = 0b01;
2383 multiclass T2I_smla<string opc, PatFrag opnode> {
2385 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2386 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2387 [(set rGPR:$Rd, (add rGPR:$Ra,
2388 (opnode (sext_inreg rGPR:$Rn, i16),
2389 (sext_inreg rGPR:$Rm, i16))))]> {
2390 let Inst{31-27} = 0b11111;
2391 let Inst{26-23} = 0b0110;
2392 let Inst{22-20} = 0b001;
2393 let Inst{7-6} = 0b00;
2394 let Inst{5-4} = 0b00;
2398 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2399 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2400 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2401 (sra rGPR:$Rm, (i32 16)))))]> {
2402 let Inst{31-27} = 0b11111;
2403 let Inst{26-23} = 0b0110;
2404 let Inst{22-20} = 0b001;
2405 let Inst{7-6} = 0b00;
2406 let Inst{5-4} = 0b01;
2410 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2411 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2412 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2413 (sext_inreg rGPR:$Rm, i16))))]> {
2414 let Inst{31-27} = 0b11111;
2415 let Inst{26-23} = 0b0110;
2416 let Inst{22-20} = 0b001;
2417 let Inst{7-6} = 0b00;
2418 let Inst{5-4} = 0b10;
2422 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2423 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2424 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2425 (sra rGPR:$Rm, (i32 16)))))]> {
2426 let Inst{31-27} = 0b11111;
2427 let Inst{26-23} = 0b0110;
2428 let Inst{22-20} = 0b001;
2429 let Inst{7-6} = 0b00;
2430 let Inst{5-4} = 0b11;
2434 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2435 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2436 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2437 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
2438 let Inst{31-27} = 0b11111;
2439 let Inst{26-23} = 0b0110;
2440 let Inst{22-20} = 0b011;
2441 let Inst{7-6} = 0b00;
2442 let Inst{5-4} = 0b00;
2446 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2447 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2448 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2449 (sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
2450 let Inst{31-27} = 0b11111;
2451 let Inst{26-23} = 0b0110;
2452 let Inst{22-20} = 0b011;
2453 let Inst{7-6} = 0b00;
2454 let Inst{5-4} = 0b01;
2458 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2459 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2461 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2462 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2463 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2464 [/* For disassembly only; pattern left blank */]>;
2465 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2466 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2467 [/* For disassembly only; pattern left blank */]>;
2468 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2469 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2470 [/* For disassembly only; pattern left blank */]>;
2471 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2472 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2473 [/* For disassembly only; pattern left blank */]>;
2475 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2476 // These are for disassembly only.
2478 def t2SMUAD: T2ThreeReg_mac<
2479 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2480 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
2481 let Inst{15-12} = 0b1111;
2483 def t2SMUADX:T2ThreeReg_mac<
2484 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2485 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
2486 let Inst{15-12} = 0b1111;
2488 def t2SMUSD: T2ThreeReg_mac<
2489 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2490 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
2491 let Inst{15-12} = 0b1111;
2493 def t2SMUSDX:T2ThreeReg_mac<
2494 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2495 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
2496 let Inst{15-12} = 0b1111;
2498 def t2SMLAD : T2ThreeReg_mac<
2499 0, 0b010, 0b0000, (outs rGPR:$Rd),
2500 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2501 "\t$Rd, $Rn, $Rm, $Ra", []>;
2502 def t2SMLADX : T2FourReg_mac<
2503 0, 0b010, 0b0001, (outs rGPR:$Rd),
2504 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2505 "\t$Rd, $Rn, $Rm, $Ra", []>;
2506 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2507 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2508 "\t$Rd, $Rn, $Rm, $Ra", []>;
2509 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2510 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2511 "\t$Rd, $Rn, $Rm, $Ra", []>;
2512 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2513 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2514 "\t$Ra, $Rd, $Rm, $Rn", []>;
2515 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2516 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2517 "\t$Ra, $Rd, $Rm, $Rn", []>;
2518 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2519 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2520 "\t$Ra, $Rd, $Rm, $Rn", []>;
2521 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2522 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2523 "\t$Ra, $Rd, $Rm, $Rn", []>;
2525 //===----------------------------------------------------------------------===//
2526 // Misc. Arithmetic Instructions.
2529 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2530 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2531 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2532 let Inst{31-27} = 0b11111;
2533 let Inst{26-22} = 0b01010;
2534 let Inst{21-20} = op1;
2535 let Inst{15-12} = 0b1111;
2536 let Inst{7-6} = 0b10;
2537 let Inst{5-4} = op2;
2541 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2542 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2544 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2545 "rbit", "\t$Rd, $Rm",
2546 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2548 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2549 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2551 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2552 "rev16", ".w\t$Rd, $Rm",
2554 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF),
2555 (or (and (shl rGPR:$Rm, (i32 8)), 0xFF00),
2556 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
2557 (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
2559 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2560 "revsh", ".w\t$Rd, $Rm",
2563 (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
2564 (shl rGPR:$Rm, (i32 8))), i16))]>;
2566 def t2PKHBT : T2ThreeReg<
2567 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2568 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2569 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2570 (and (shl rGPR:$Rm, lsl_amt:$sh),
2572 Requires<[HasT2ExtractPack, IsThumb2]> {
2573 let Inst{31-27} = 0b11101;
2574 let Inst{26-25} = 0b01;
2575 let Inst{24-20} = 0b01100;
2576 let Inst{5} = 0; // BT form
2580 let Inst{14-12} = sh{7-5};
2581 let Inst{7-6} = sh{4-3};
2584 // Alternate cases for PKHBT where identities eliminate some nodes.
2585 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2586 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2587 Requires<[HasT2ExtractPack, IsThumb2]>;
2588 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2589 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2590 Requires<[HasT2ExtractPack, IsThumb2]>;
2592 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2593 // will match the pattern below.
2594 def t2PKHTB : T2ThreeReg<
2595 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2596 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2597 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2598 (and (sra rGPR:$Rm, asr_amt:$sh),
2600 Requires<[HasT2ExtractPack, IsThumb2]> {
2601 let Inst{31-27} = 0b11101;
2602 let Inst{26-25} = 0b01;
2603 let Inst{24-20} = 0b01100;
2604 let Inst{5} = 1; // TB form
2608 let Inst{14-12} = sh{7-5};
2609 let Inst{7-6} = sh{4-3};
2612 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2613 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2614 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2615 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2616 Requires<[HasT2ExtractPack, IsThumb2]>;
2617 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2618 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2619 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2620 Requires<[HasT2ExtractPack, IsThumb2]>;
2622 //===----------------------------------------------------------------------===//
2623 // Comparison Instructions...
2625 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2626 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2627 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2629 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
2630 (t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
2631 def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
2632 (t2CMPrr GPR:$lhs, rGPR:$rhs)>;
2633 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
2634 (t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
2636 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2637 // Compare-to-zero still works out, just not the relationals
2638 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2639 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2640 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2641 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2642 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2644 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2645 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2647 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2648 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2650 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2651 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2652 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2653 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2654 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2655 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2657 // Conditional moves
2658 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2659 // a two-value operand where a dag node expects two operands. :(
2660 let neverHasSideEffects = 1 in {
2661 def t2MOVCCr : T2TwoReg<
2662 (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
2663 "mov", ".w\t$Rd, $Rm",
2664 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2665 RegConstraint<"$false = $Rd"> {
2666 let Inst{31-27} = 0b11101;
2667 let Inst{26-25} = 0b01;
2668 let Inst{24-21} = 0b0010;
2669 let Inst{20} = 0; // The S bit.
2670 let Inst{19-16} = 0b1111; // Rn
2671 let Inst{14-12} = 0b000;
2672 let Inst{7-4} = 0b0000;
2675 let isMoveImm = 1 in
2676 def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2677 IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
2678 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2679 RegConstraint<"$false = $Rd"> {
2680 let Inst{31-27} = 0b11110;
2682 let Inst{24-21} = 0b0010;
2683 let Inst{20} = 0; // The S bit.
2684 let Inst{19-16} = 0b1111; // Rn
2688 let isMoveImm = 1 in
2689 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm:$imm),
2691 "movw", "\t$Rd, $imm", []>,
2692 RegConstraint<"$false = $Rd"> {
2693 let Inst{31-27} = 0b11110;
2695 let Inst{24-21} = 0b0010;
2696 let Inst{20} = 0; // The S bit.
2702 let Inst{11-8} = Rd;
2703 let Inst{19-16} = imm{15-12};
2704 let Inst{26} = imm{11};
2705 let Inst{14-12} = imm{10-8};
2706 let Inst{7-0} = imm{7-0};
2709 let isMoveImm = 1 in
2710 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2711 (ins rGPR:$false, i32imm:$src, pred:$p),
2712 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2714 let isMoveImm = 1 in
2715 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2716 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2717 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2718 imm:$cc, CCR:$ccr))*/]>,
2719 RegConstraint<"$false = $Rd"> {
2720 let Inst{31-27} = 0b11110;
2722 let Inst{24-21} = 0b0011;
2723 let Inst{20} = 0; // The S bit.
2724 let Inst{19-16} = 0b1111; // Rn
2728 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2729 string opc, string asm, list<dag> pattern>
2730 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2731 let Inst{31-27} = 0b11101;
2732 let Inst{26-25} = 0b01;
2733 let Inst{24-21} = 0b0010;
2734 let Inst{20} = 0; // The S bit.
2735 let Inst{19-16} = 0b1111; // Rn
2736 let Inst{5-4} = opcod; // Shift type.
2738 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2739 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2740 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2741 RegConstraint<"$false = $Rd">;
2742 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2743 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2744 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2745 RegConstraint<"$false = $Rd">;
2746 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2747 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2748 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2749 RegConstraint<"$false = $Rd">;
2750 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2751 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2752 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2753 RegConstraint<"$false = $Rd">;
2754 } // neverHasSideEffects
2756 //===----------------------------------------------------------------------===//
2757 // Atomic operations intrinsics
2760 // memory barriers protect the atomic sequences
2761 let hasSideEffects = 1 in {
2762 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2763 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2764 Requires<[IsThumb, HasDB]> {
2766 let Inst{31-4} = 0xf3bf8f5;
2767 let Inst{3-0} = opt;
2771 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2773 [/* For disassembly only; pattern left blank */]>,
2774 Requires<[IsThumb, HasDB]> {
2776 let Inst{31-4} = 0xf3bf8f4;
2777 let Inst{3-0} = opt;
2780 // ISB has only full system option -- for disassembly only
2781 def t2ISB : T2I<(outs), (ins), NoItinerary, "isb", "",
2782 [/* For disassembly only; pattern left blank */]>,
2783 Requires<[IsThumb2, HasV7]> {
2784 let Inst{31-4} = 0xf3bf8f6;
2785 let Inst{3-0} = 0b1111;
2788 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2789 InstrItinClass itin, string opc, string asm, string cstr,
2790 list<dag> pattern, bits<4> rt2 = 0b1111>
2791 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2792 let Inst{31-27} = 0b11101;
2793 let Inst{26-20} = 0b0001101;
2794 let Inst{11-8} = rt2;
2795 let Inst{7-6} = 0b01;
2796 let Inst{5-4} = opcod;
2797 let Inst{3-0} = 0b1111;
2801 let Inst{19-16} = Rn;
2802 let Inst{15-12} = Rt;
2804 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2805 InstrItinClass itin, string opc, string asm, string cstr,
2806 list<dag> pattern, bits<4> rt2 = 0b1111>
2807 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2808 let Inst{31-27} = 0b11101;
2809 let Inst{26-20} = 0b0001100;
2810 let Inst{11-8} = rt2;
2811 let Inst{7-6} = 0b01;
2812 let Inst{5-4} = opcod;
2817 let Inst{11-8} = Rd;
2818 let Inst{19-16} = Rn;
2819 let Inst{15-12} = Rt;
2822 let mayLoad = 1 in {
2823 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2824 Size4Bytes, NoItinerary, "ldrexb", "\t$Rt, [$Rn]",
2826 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2827 Size4Bytes, NoItinerary, "ldrexh", "\t$Rt, [$Rn]",
2829 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2830 Size4Bytes, NoItinerary,
2831 "ldrex", "\t$Rt, [$Rn]", "",
2833 let Inst{31-27} = 0b11101;
2834 let Inst{26-20} = 0b0000101;
2835 let Inst{11-8} = 0b1111;
2836 let Inst{7-0} = 0b00000000; // imm8 = 0
2838 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), (ins rGPR:$Rn),
2839 AddrModeNone, Size4Bytes, NoItinerary,
2840 "ldrexd", "\t$Rt, $Rt2, [$Rn]", "",
2843 let Inst{11-8} = Rt2;
2847 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2848 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2849 AddrModeNone, Size4Bytes, NoItinerary,
2850 "strexb", "\t$Rd, $Rt, [$Rn]", "", []>;
2851 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2852 AddrModeNone, Size4Bytes, NoItinerary,
2853 "strexh", "\t$Rd, $Rt, [$Rn]", "", []>;
2854 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2855 AddrModeNone, Size4Bytes, NoItinerary,
2856 "strex", "\t$Rd, $Rt, [$Rn]", "",
2858 let Inst{31-27} = 0b11101;
2859 let Inst{26-20} = 0b0000100;
2860 let Inst{7-0} = 0b00000000; // imm8 = 0
2862 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2863 (ins rGPR:$Rt, rGPR:$Rt2, rGPR:$Rn),
2864 AddrModeNone, Size4Bytes, NoItinerary,
2865 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]", "", [],
2868 let Inst{11-8} = Rt2;
2872 // Clear-Exclusive is for disassembly only.
2873 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2874 [/* For disassembly only; pattern left blank */]>,
2875 Requires<[IsARM, HasV7]> {
2876 let Inst{31-20} = 0xf3b;
2877 let Inst{15-14} = 0b10;
2879 let Inst{7-4} = 0b0010;
2882 //===----------------------------------------------------------------------===//
2886 // __aeabi_read_tp preserves the registers r1-r3.
2888 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
2889 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2890 "bl\t__aeabi_read_tp",
2891 [(set R0, ARMthread_pointer)]> {
2892 let Inst{31-27} = 0b11110;
2893 let Inst{15-14} = 0b11;
2898 //===----------------------------------------------------------------------===//
2899 // SJLJ Exception handling intrinsics
2900 // eh_sjlj_setjmp() is an instruction sequence to store the return
2901 // address and save #0 in R0 for the non-longjmp case.
2902 // Since by its nature we may be coming from some other function to get
2903 // here, and we're using the stack frame for the containing function to
2904 // save/restore registers, we can't keep anything live in regs across
2905 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2906 // when we get here from a longjmp(). We force everthing out of registers
2907 // except for our own input by listing the relevant registers in Defs. By
2908 // doing so, we also cause the prologue/epilogue code to actively preserve
2909 // all of the callee-saved resgisters, which is exactly what we want.
2910 // $val is a scratch register for our use.
2912 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2913 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2914 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2915 D31 ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2916 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2917 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2918 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2919 Requires<[IsThumb2, HasVFP2]>;
2923 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2924 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2925 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2926 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2927 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2928 Requires<[IsThumb2, NoVFP]>;
2932 //===----------------------------------------------------------------------===//
2933 // Control-Flow Instructions
2936 // FIXME: remove when we have a way to marking a MI with these properties.
2937 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2939 // FIXME: Should pc be an implicit operand like PICADD, etc?
2940 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2941 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2942 def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2943 reglist:$regs, variable_ops),
2945 "ldmia${p}.w\t$Rn!, $regs",
2950 let Inst{31-27} = 0b11101;
2951 let Inst{26-25} = 0b00;
2952 let Inst{24-23} = 0b01; // Increment After
2954 let Inst{21} = 1; // Writeback
2956 let Inst{19-16} = Rn;
2957 let Inst{15-0} = regs;
2960 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2961 let isPredicable = 1 in
2962 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2964 [(br bb:$target)]> {
2965 let Inst{31-27} = 0b11110;
2966 let Inst{15-14} = 0b10;
2970 let Inst{26} = target{19};
2971 let Inst{11} = target{18};
2972 let Inst{13} = target{17};
2973 let Inst{21-16} = target{16-11};
2974 let Inst{10-0} = target{10-0};
2977 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2978 def t2BR_JT : tPseudoInst<(outs),
2979 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
2980 SizeSpecial, IIC_Br,
2981 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
2983 // FIXME: Add a non-pc based case that can be predicated.
2984 def t2TBB_JT : tPseudoInst<(outs),
2985 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2986 SizeSpecial, IIC_Br, []>;
2988 def t2TBH_JT : tPseudoInst<(outs),
2989 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2990 SizeSpecial, IIC_Br, []>;
2992 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2993 "tbb", "\t[$Rn, $Rm]", []> {
2996 let Inst{27-20} = 0b10001101;
2997 let Inst{19-16} = Rn;
2998 let Inst{15-5} = 0b11110000000;
2999 let Inst{4} = 0; // B form
3003 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3004 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3007 let Inst{27-20} = 0b10001101;
3008 let Inst{19-16} = Rn;
3009 let Inst{15-5} = 0b11110000000;
3010 let Inst{4} = 1; // H form
3013 } // isNotDuplicable, isIndirectBranch
3015 } // isBranch, isTerminator, isBarrier
3017 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3018 // a two-value operand where a dag node expects two operands. :(
3019 let isBranch = 1, isTerminator = 1 in
3020 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3022 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3023 let Inst{31-27} = 0b11110;
3024 let Inst{15-14} = 0b10;
3028 let Inst{26} = target{19};
3029 let Inst{11} = target{18};
3030 let Inst{13} = target{17};
3031 let Inst{21-16} = target{16-11};
3032 let Inst{10-0} = target{10-0};
3037 let Defs = [ITSTATE] in
3038 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3039 AddrModeNone, Size2Bytes, IIC_iALUx,
3040 "it$mask\t$cc", "", []> {
3041 // 16-bit instruction.
3042 let Inst{31-16} = 0x0000;
3043 let Inst{15-8} = 0b10111111;
3048 let Inst{3-0} = mask;
3051 // Branch and Exchange Jazelle -- for disassembly only
3053 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3054 [/* For disassembly only; pattern left blank */]> {
3055 let Inst{31-27} = 0b11110;
3057 let Inst{25-20} = 0b111100;
3058 let Inst{15-14} = 0b10;
3062 let Inst{19-16} = func;
3065 // Change Processor State is a system instruction -- for disassembly only.
3066 // The singleton $opt operand contains the following information:
3067 // opt{4-0} = mode from Inst{4-0}
3068 // opt{5} = changemode from Inst{17}
3069 // opt{8-6} = AIF from Inst{8-6}
3070 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3071 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
3072 [/* For disassembly only; pattern left blank */]> {
3073 let Inst{31-27} = 0b11110;
3075 let Inst{25-20} = 0b111010;
3076 let Inst{15-14} = 0b10;
3082 let Inst{4-0} = opt{4-0};
3085 let Inst{8} = opt{5};
3088 let Inst{5} = opt{6};
3091 let Inst{6} = opt{7};
3094 let Inst{7} = opt{8};
3097 let Inst{10-9} = opt{10-9};
3100 // A6.3.4 Branches and miscellaneous control
3101 // Table A6-14 Change Processor State, and hint instructions
3102 // Helper class for disassembly only.
3103 class T2I_hint<bits<8> op7_0, string opc, string asm>
3104 : T2I<(outs), (ins), NoItinerary, opc, asm,
3105 [/* For disassembly only; pattern left blank */]> {
3106 let Inst{31-20} = 0xf3a;
3107 let Inst{15-14} = 0b10;
3109 let Inst{10-8} = 0b000;
3110 let Inst{7-0} = op7_0;
3113 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3114 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3115 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3116 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3117 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3119 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
3120 [/* For disassembly only; pattern left blank */]> {
3121 let Inst{31-20} = 0xf3a;
3122 let Inst{15-14} = 0b10;
3124 let Inst{10-8} = 0b000;
3125 let Inst{7-4} = 0b1111;
3128 let Inst{3-0} = opt;
3131 // Secure Monitor Call is a system instruction -- for disassembly only
3132 // Option = Inst{19-16}
3133 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
3134 [/* For disassembly only; pattern left blank */]> {
3135 let Inst{31-27} = 0b11110;
3136 let Inst{26-20} = 0b1111111;
3137 let Inst{15-12} = 0b1000;
3140 let Inst{19-16} = opt;
3143 class T2SRS<bits<12> op31_20,
3144 dag oops, dag iops, InstrItinClass itin,
3145 string opc, string asm, list<dag> pattern>
3146 : T2I<oops, iops, itin, opc, asm, pattern> {
3147 let Inst{31-20} = op31_20{11-0};
3150 let Inst{4-0} = mode{4-0};
3153 // Store Return State is a system instruction -- for disassembly only
3154 def t2SRSDBW : T2SRS<0b111010000010,
3155 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3156 [/* For disassembly only; pattern left blank */]>;
3157 def t2SRSDB : T2SRS<0b111010000000,
3158 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3159 [/* For disassembly only; pattern left blank */]>;
3160 def t2SRSIAW : T2SRS<0b111010011010,
3161 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3162 [/* For disassembly only; pattern left blank */]>;
3163 def t2SRSIA : T2SRS<0b111010011000,
3164 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3165 [/* For disassembly only; pattern left blank */]>;
3167 // Return From Exception is a system instruction -- for disassembly only
3169 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3170 string opc, string asm, list<dag> pattern>
3171 : T2I<oops, iops, itin, opc, asm, pattern> {
3172 let Inst{31-20} = op31_20{11-0};
3175 let Inst{19-16} = Rn;
3178 def t2RFEDBW : T2RFE<0b111010000011,
3179 (outs), (ins rGPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3180 [/* For disassembly only; pattern left blank */]>;
3181 def t2RFEDB : T2RFE<0b111010000001,
3182 (outs), (ins rGPR:$Rn), NoItinerary, "rfeab", "\t$Rn",
3183 [/* For disassembly only; pattern left blank */]>;
3184 def t2RFEIAW : T2RFE<0b111010011011,
3185 (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3186 [/* For disassembly only; pattern left blank */]>;
3187 def t2RFEIA : T2RFE<0b111010011001,
3188 (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3189 [/* For disassembly only; pattern left blank */]>;
3191 //===----------------------------------------------------------------------===//
3192 // Non-Instruction Patterns
3195 // 32-bit immediate using movw + movt.
3196 // This is a single pseudo instruction to make it re-materializable.
3197 // FIXME: Remove this when we can do generalized remat.
3198 let isReMaterializable = 1, isMoveImm = 1 in
3199 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3200 [(set rGPR:$dst, (i32 imm:$src))]>,
3201 Requires<[IsThumb, HasV6T2]>;
3203 // ConstantPool, GlobalAddress, and JumpTable
3204 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3205 Requires<[IsThumb2, DontUseMovt]>;
3206 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3207 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3208 Requires<[IsThumb2, UseMovt]>;
3210 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3211 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3213 // Pseudo instruction that combines ldr from constpool and add pc. This should
3214 // be expanded into two instructions late to allow if-conversion and
3216 let canFoldAsLoad = 1, isReMaterializable = 1 in
3217 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3219 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3221 Requires<[IsThumb2]>;
3223 //===----------------------------------------------------------------------===//
3224 // Move between special register and ARM core register -- for disassembly only
3227 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3228 dag oops, dag iops, InstrItinClass itin,
3229 string opc, string asm, list<dag> pattern>
3230 : T2I<oops, iops, itin, opc, asm, pattern> {
3231 let Inst{31-20} = op31_20{11-0};
3232 let Inst{15-14} = op15_14{1-0};
3233 let Inst{12} = op12{0};
3236 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3237 dag oops, dag iops, InstrItinClass itin,
3238 string opc, string asm, list<dag> pattern>
3239 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3241 let Inst{11-8} = Rd;
3244 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3245 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3246 [/* For disassembly only; pattern left blank */]>;
3247 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3248 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3249 [/* For disassembly only; pattern left blank */]>;
3251 class T2MSR<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3252 dag oops, dag iops, InstrItinClass itin,
3253 string opc, string asm, list<dag> pattern>
3254 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3257 let Inst{19-16} = Rn;
3258 let Inst{11-8} = mask;
3261 def t2MSR : T2MSR<0b111100111000, 0b10, 0,
3262 (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3264 [/* For disassembly only; pattern left blank */]>;
3265 def t2MSRsys : T2MSR<0b111100111001, 0b10, 0,
3266 (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3268 [/* For disassembly only; pattern left blank */]>;