1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let EncoderMethod = "getT2SORegOpValue";
30 let PrintMethod = "printT2SOOperand";
31 let MIOperandInfo = (ops rGPR, i32imm);
34 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
44 // t2_so_imm - Match a 32-bit immediate operand, which is an
45 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46 // immediate splatted into multiple bytes of the word. t2_so_imm values are
47 // represented in the imm field in the same 12-bit form that they are encoded
48 // into t2_so_imm instructions: the 8-bit immediate is the least significant
49 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
50 def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> {
51 let EncoderMethod = "getT2SOImmOpValue";
54 // t2_so_imm_not - Match an immediate that is a complement
56 def t2_so_imm_not : Operand<i32>,
58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
59 }], t2_so_imm_not_XFORM>;
61 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
62 def t2_so_imm_neg : Operand<i32>,
64 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
65 }], t2_so_imm_neg_XFORM>;
67 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
68 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
69 // to get the first/second pieces.
70 def t2_so_imm2part : Operand<i32>,
72 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
76 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
77 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
78 return CurDAG->getTargetConstant(V, MVT::i32);
81 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
87 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
91 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
92 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
93 return CurDAG->getTargetConstant(V, MVT::i32);
96 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
102 def imm1_31 : PatLeaf<(i32 imm), [{
103 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
106 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
107 def imm0_4095 : Operand<i32>,
108 PatLeaf<(i32 imm), [{
109 return (uint32_t)N->getZExtValue() < 4096;
112 def imm0_4095_neg : PatLeaf<(i32 imm), [{
113 return (uint32_t)(-N->getZExtValue()) < 4096;
116 def imm0_255_neg : PatLeaf<(i32 imm), [{
117 return (uint32_t)(-N->getZExtValue()) < 255;
120 def imm0_255_not : PatLeaf<(i32 imm), [{
121 return (uint32_t)(~N->getZExtValue()) < 255;
124 // Define Thumb2 specific addressing modes.
126 // t2addrmode_imm12 := reg + imm12
127 def t2addrmode_imm12 : Operand<i32>,
128 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
129 let PrintMethod = "printAddrModeImm12Operand";
130 let EncoderMethod = "getAddrModeImm12OpValue";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
132 let ParserMatchClass = MemMode5AsmOperand;
135 // ADR instruction labels.
136 def t2adrlabel : Operand<i32> {
137 let EncoderMethod = "getT2AdrLabelOpValue";
141 // t2addrmode_imm8 := reg +/- imm8
142 def t2addrmode_imm8 : Operand<i32>,
143 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
144 let PrintMethod = "printT2AddrModeImm8Operand";
145 let EncoderMethod = "getT2AddrModeImm8OpValue";
146 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
147 let ParserMatchClass = MemMode5AsmOperand;
150 def t2am_imm8_offset : Operand<i32>,
151 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
152 [], [SDNPWantRoot]> {
153 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
154 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
155 let ParserMatchClass = MemMode5AsmOperand;
158 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
159 def t2addrmode_imm8s4 : Operand<i32> {
160 let PrintMethod = "printT2AddrModeImm8s4Operand";
161 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
162 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
163 let ParserMatchClass = MemMode5AsmOperand;
166 def t2am_imm8s4_offset : Operand<i32> {
167 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
170 // t2addrmode_so_reg := reg + (reg << imm2)
171 def t2addrmode_so_reg : Operand<i32>,
172 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
173 let PrintMethod = "printT2AddrModeSoRegOperand";
174 let EncoderMethod = "getT2AddrModeSORegOpValue";
175 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
176 let ParserMatchClass = MemMode5AsmOperand;
180 //===----------------------------------------------------------------------===//
181 // Multiclass helpers...
185 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
186 string opc, string asm, list<dag> pattern>
187 : T2I<oops, iops, itin, opc, asm, pattern> {
192 let Inst{26} = imm{11};
193 let Inst{14-12} = imm{10-8};
194 let Inst{7-0} = imm{7-0};
198 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
199 string opc, string asm, list<dag> pattern>
200 : T2sI<oops, iops, itin, opc, asm, pattern> {
206 let Inst{26} = imm{11};
207 let Inst{14-12} = imm{10-8};
208 let Inst{7-0} = imm{7-0};
211 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
212 string opc, string asm, list<dag> pattern>
213 : T2I<oops, iops, itin, opc, asm, pattern> {
217 let Inst{19-16} = Rn;
218 let Inst{26} = imm{11};
219 let Inst{14-12} = imm{10-8};
220 let Inst{7-0} = imm{7-0};
224 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
225 string opc, string asm, list<dag> pattern>
226 : T2I<oops, iops, itin, opc, asm, pattern> {
231 let Inst{3-0} = ShiftedRm{3-0};
232 let Inst{5-4} = ShiftedRm{6-5};
233 let Inst{14-12} = ShiftedRm{11-9};
234 let Inst{7-6} = ShiftedRm{8-7};
237 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
238 string opc, string asm, list<dag> pattern>
239 : T2sI<oops, iops, itin, opc, asm, pattern> {
244 let Inst{3-0} = ShiftedRm{3-0};
245 let Inst{5-4} = ShiftedRm{6-5};
246 let Inst{14-12} = ShiftedRm{11-9};
247 let Inst{7-6} = ShiftedRm{8-7};
250 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
251 string opc, string asm, list<dag> pattern>
252 : T2I<oops, iops, itin, opc, asm, pattern> {
256 let Inst{19-16} = Rn;
257 let Inst{3-0} = ShiftedRm{3-0};
258 let Inst{5-4} = ShiftedRm{6-5};
259 let Inst{14-12} = ShiftedRm{11-9};
260 let Inst{7-6} = ShiftedRm{8-7};
263 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
264 string opc, string asm, list<dag> pattern>
265 : T2I<oops, iops, itin, opc, asm, pattern> {
273 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
274 string opc, string asm, list<dag> pattern>
275 : T2sI<oops, iops, itin, opc, asm, pattern> {
283 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
284 string opc, string asm, list<dag> pattern>
285 : T2I<oops, iops, itin, opc, asm, pattern> {
289 let Inst{19-16} = Rn;
294 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
295 string opc, string asm, list<dag> pattern>
296 : T2I<oops, iops, itin, opc, asm, pattern> {
302 let Inst{19-16} = Rn;
303 let Inst{26} = imm{11};
304 let Inst{14-12} = imm{10-8};
305 let Inst{7-0} = imm{7-0};
308 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
309 string opc, string asm, list<dag> pattern>
310 : T2sI<oops, iops, itin, opc, asm, pattern> {
316 let Inst{19-16} = Rn;
317 let Inst{26} = imm{11};
318 let Inst{14-12} = imm{10-8};
319 let Inst{7-0} = imm{7-0};
322 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
323 string opc, string asm, list<dag> pattern>
324 : T2I<oops, iops, itin, opc, asm, pattern> {
331 let Inst{14-12} = imm{4-2};
332 let Inst{7-6} = imm{1-0};
335 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
336 string opc, string asm, list<dag> pattern>
337 : T2sI<oops, iops, itin, opc, asm, pattern> {
344 let Inst{14-12} = imm{4-2};
345 let Inst{7-6} = imm{1-0};
348 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
349 string opc, string asm, list<dag> pattern>
350 : T2I<oops, iops, itin, opc, asm, pattern> {
356 let Inst{19-16} = Rn;
360 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : T2sI<oops, iops, itin, opc, asm, pattern> {
368 let Inst{19-16} = Rn;
372 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
373 string opc, string asm, list<dag> pattern>
374 : T2I<oops, iops, itin, opc, asm, pattern> {
380 let Inst{19-16} = Rn;
381 let Inst{3-0} = ShiftedRm{3-0};
382 let Inst{5-4} = ShiftedRm{6-5};
383 let Inst{14-12} = ShiftedRm{11-9};
384 let Inst{7-6} = ShiftedRm{8-7};
387 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
388 string opc, string asm, list<dag> pattern>
389 : T2sI<oops, iops, itin, opc, asm, pattern> {
395 let Inst{19-16} = Rn;
396 let Inst{3-0} = ShiftedRm{3-0};
397 let Inst{5-4} = ShiftedRm{6-5};
398 let Inst{14-12} = ShiftedRm{11-9};
399 let Inst{7-6} = ShiftedRm{8-7};
402 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : T2I<oops, iops, itin, opc, asm, pattern> {
410 let Inst{19-16} = Rn;
411 let Inst{15-12} = Ra;
416 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
417 dag oops, dag iops, InstrItinClass itin,
418 string opc, string asm, list<dag> pattern>
419 : T2I<oops, iops, itin, opc, asm, pattern> {
425 let Inst{31-23} = 0b111110111;
426 let Inst{22-20} = opc22_20;
427 let Inst{19-16} = Rn;
428 let Inst{15-12} = RdLo;
429 let Inst{11-8} = RdHi;
430 let Inst{7-4} = opc7_4;
435 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
436 /// unary operation that produces a value. These are predicable and can be
437 /// changed to modify CPSR.
438 multiclass T2I_un_irs<bits<4> opcod, string opc,
439 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
440 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
442 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
444 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
445 let isAsCheapAsAMove = Cheap;
446 let isReMaterializable = ReMat;
447 let Inst{31-27} = 0b11110;
449 let Inst{24-21} = opcod;
450 let Inst{19-16} = 0b1111; // Rn
454 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
456 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
457 let Inst{31-27} = 0b11101;
458 let Inst{26-25} = 0b01;
459 let Inst{24-21} = opcod;
460 let Inst{19-16} = 0b1111; // Rn
461 let Inst{14-12} = 0b000; // imm3
462 let Inst{7-6} = 0b00; // imm2
463 let Inst{5-4} = 0b00; // type
466 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
467 opc, ".w\t$Rd, $ShiftedRm",
468 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
469 let Inst{31-27} = 0b11101;
470 let Inst{26-25} = 0b01;
471 let Inst{24-21} = opcod;
472 let Inst{19-16} = 0b1111; // Rn
476 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
477 /// binary operation that produces a value. These are predicable and can be
478 /// changed to modify CPSR.
479 multiclass T2I_bin_irs<bits<4> opcod, string opc,
480 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
481 PatFrag opnode, bit Commutable = 0, string wide = ""> {
483 def ri : T2sTwoRegImm<
484 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
485 opc, "\t$Rd, $Rn, $imm",
486 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
487 let Inst{31-27} = 0b11110;
489 let Inst{24-21} = opcod;
493 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
494 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
495 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
496 let isCommutable = Commutable;
497 let Inst{31-27} = 0b11101;
498 let Inst{26-25} = 0b01;
499 let Inst{24-21} = opcod;
500 let Inst{14-12} = 0b000; // imm3
501 let Inst{7-6} = 0b00; // imm2
502 let Inst{5-4} = 0b00; // type
505 def rs : T2sTwoRegShiftedReg<
506 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
507 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
508 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
509 let Inst{31-27} = 0b11101;
510 let Inst{26-25} = 0b01;
511 let Inst{24-21} = opcod;
515 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
516 // the ".w" prefix to indicate that they are wide.
517 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
518 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
519 PatFrag opnode, bit Commutable = 0> :
520 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">;
522 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
523 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
524 /// it is equivalent to the T2I_bin_irs counterpart.
525 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
527 def ri : T2sTwoRegImm<
528 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
529 opc, ".w\t$Rd, $Rn, $imm",
530 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
531 let Inst{31-27} = 0b11110;
533 let Inst{24-21} = opcod;
537 def rr : T2sThreeReg<
538 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
539 opc, "\t$Rd, $Rn, $Rm",
540 [/* For disassembly only; pattern left blank */]> {
541 let Inst{31-27} = 0b11101;
542 let Inst{26-25} = 0b01;
543 let Inst{24-21} = opcod;
544 let Inst{14-12} = 0b000; // imm3
545 let Inst{7-6} = 0b00; // imm2
546 let Inst{5-4} = 0b00; // type
549 def rs : T2sTwoRegShiftedReg<
550 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
551 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
552 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
553 let Inst{31-27} = 0b11101;
554 let Inst{26-25} = 0b01;
555 let Inst{24-21} = opcod;
559 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
560 /// instruction modifies the CPSR register.
561 let isCodeGenOnly = 1, Defs = [CPSR] in {
562 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
563 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
564 PatFrag opnode, bit Commutable = 0> {
566 def ri : T2TwoRegImm<
567 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
568 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
569 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
570 let Inst{31-27} = 0b11110;
572 let Inst{24-21} = opcod;
573 let Inst{20} = 1; // The S bit.
578 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
579 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
580 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
581 let isCommutable = Commutable;
582 let Inst{31-27} = 0b11101;
583 let Inst{26-25} = 0b01;
584 let Inst{24-21} = opcod;
585 let Inst{20} = 1; // The S bit.
586 let Inst{14-12} = 0b000; // imm3
587 let Inst{7-6} = 0b00; // imm2
588 let Inst{5-4} = 0b00; // type
591 def rs : T2TwoRegShiftedReg<
592 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
593 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
594 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
595 let Inst{31-27} = 0b11101;
596 let Inst{26-25} = 0b01;
597 let Inst{24-21} = opcod;
598 let Inst{20} = 1; // The S bit.
603 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
604 /// patterns for a binary operation that produces a value.
605 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
606 bit Commutable = 0> {
608 // The register-immediate version is re-materializable. This is useful
609 // in particular for taking the address of a local.
610 let isReMaterializable = 1 in {
611 def ri : T2sTwoRegImm<
612 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
613 opc, ".w\t$Rd, $Rn, $imm",
614 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
615 let Inst{31-27} = 0b11110;
618 let Inst{23-21} = op23_21;
624 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
625 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
626 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
630 let Inst{31-27} = 0b11110;
631 let Inst{26} = imm{11};
632 let Inst{25-24} = 0b10;
633 let Inst{23-21} = op23_21;
634 let Inst{20} = 0; // The S bit.
635 let Inst{19-16} = Rn;
637 let Inst{14-12} = imm{10-8};
639 let Inst{7-0} = imm{7-0};
642 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
643 opc, ".w\t$Rd, $Rn, $Rm",
644 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
645 let isCommutable = Commutable;
646 let Inst{31-27} = 0b11101;
647 let Inst{26-25} = 0b01;
649 let Inst{23-21} = op23_21;
650 let Inst{14-12} = 0b000; // imm3
651 let Inst{7-6} = 0b00; // imm2
652 let Inst{5-4} = 0b00; // type
655 def rs : T2sTwoRegShiftedReg<
656 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
657 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
658 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
659 let Inst{31-27} = 0b11101;
660 let Inst{26-25} = 0b01;
662 let Inst{23-21} = op23_21;
666 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
667 /// for a binary operation that produces a value and use the carry
668 /// bit. It's not predicable.
669 let Uses = [CPSR] in {
670 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
671 bit Commutable = 0> {
673 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
674 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
675 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
676 Requires<[IsThumb2]> {
677 let Inst{31-27} = 0b11110;
679 let Inst{24-21} = opcod;
683 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
684 opc, ".w\t$Rd, $Rn, $Rm",
685 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
686 Requires<[IsThumb2]> {
687 let isCommutable = Commutable;
688 let Inst{31-27} = 0b11101;
689 let Inst{26-25} = 0b01;
690 let Inst{24-21} = opcod;
691 let Inst{14-12} = 0b000; // imm3
692 let Inst{7-6} = 0b00; // imm2
693 let Inst{5-4} = 0b00; // type
696 def rs : T2sTwoRegShiftedReg<
697 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
698 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
699 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
700 Requires<[IsThumb2]> {
701 let Inst{31-27} = 0b11101;
702 let Inst{26-25} = 0b01;
703 let Inst{24-21} = opcod;
707 // Carry setting variants
708 let isCodeGenOnly = 1, Defs = [CPSR] in {
709 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
710 bit Commutable = 0> {
712 def ri : T2sTwoRegImm<
713 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
714 opc, "\t$Rd, $Rn, $imm",
715 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
716 Requires<[IsThumb2]> {
717 let Inst{31-27} = 0b11110;
719 let Inst{24-21} = opcod;
720 let Inst{20} = 1; // The S bit.
724 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
725 opc, ".w\t$Rd, $Rn, $Rm",
726 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
727 Requires<[IsThumb2]> {
728 let isCommutable = Commutable;
729 let Inst{31-27} = 0b11101;
730 let Inst{26-25} = 0b01;
731 let Inst{24-21} = opcod;
732 let Inst{20} = 1; // The S bit.
733 let Inst{14-12} = 0b000; // imm3
734 let Inst{7-6} = 0b00; // imm2
735 let Inst{5-4} = 0b00; // type
738 def rs : T2sTwoRegShiftedReg<
739 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
740 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
741 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
742 Requires<[IsThumb2]> {
743 let Inst{31-27} = 0b11101;
744 let Inst{26-25} = 0b01;
745 let Inst{24-21} = opcod;
746 let Inst{20} = 1; // The S bit.
752 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
753 /// version is not needed since this is only for codegen.
754 let isCodeGenOnly = 1, Defs = [CPSR] in {
755 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
757 def ri : T2TwoRegImm<
758 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
759 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
760 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
761 let Inst{31-27} = 0b11110;
763 let Inst{24-21} = opcod;
764 let Inst{20} = 1; // The S bit.
768 def rs : T2TwoRegShiftedReg<
769 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
770 IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
771 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
772 let Inst{31-27} = 0b11101;
773 let Inst{26-25} = 0b01;
774 let Inst{24-21} = opcod;
775 let Inst{20} = 1; // The S bit.
780 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
781 // rotate operation that produces a value.
782 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
784 def ri : T2sTwoRegShiftImm<
785 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
786 opc, ".w\t$Rd, $Rm, $imm",
787 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
788 let Inst{31-27} = 0b11101;
789 let Inst{26-21} = 0b010010;
790 let Inst{19-16} = 0b1111; // Rn
791 let Inst{5-4} = opcod;
794 def rr : T2sThreeReg<
795 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
796 opc, ".w\t$Rd, $Rn, $Rm",
797 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
798 let Inst{31-27} = 0b11111;
799 let Inst{26-23} = 0b0100;
800 let Inst{22-21} = opcod;
801 let Inst{15-12} = 0b1111;
802 let Inst{7-4} = 0b0000;
806 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
807 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
808 /// a explicit result, only implicitly set CPSR.
809 let isCompare = 1, Defs = [CPSR] in {
810 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
811 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
814 def ri : T2OneRegCmpImm<
815 (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
816 opc, ".w\t$Rn, $imm",
817 [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
818 let Inst{31-27} = 0b11110;
820 let Inst{24-21} = opcod;
821 let Inst{20} = 1; // The S bit.
823 let Inst{11-8} = 0b1111; // Rd
826 def rr : T2TwoRegCmp<
827 (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
828 opc, ".w\t$lhs, $rhs",
829 [(opnode GPR:$lhs, rGPR:$rhs)]> {
830 let Inst{31-27} = 0b11101;
831 let Inst{26-25} = 0b01;
832 let Inst{24-21} = opcod;
833 let Inst{20} = 1; // The S bit.
834 let Inst{14-12} = 0b000; // imm3
835 let Inst{11-8} = 0b1111; // Rd
836 let Inst{7-6} = 0b00; // imm2
837 let Inst{5-4} = 0b00; // type
840 def rs : T2OneRegCmpShiftedReg<
841 (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
842 opc, ".w\t$Rn, $ShiftedRm",
843 [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
844 let Inst{31-27} = 0b11101;
845 let Inst{26-25} = 0b01;
846 let Inst{24-21} = opcod;
847 let Inst{20} = 1; // The S bit.
848 let Inst{11-8} = 0b1111; // Rd
853 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
854 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
855 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
856 def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
857 opc, ".w\t$Rt, $addr",
858 [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
859 let Inst{31-27} = 0b11111;
860 let Inst{26-25} = 0b00;
861 let Inst{24} = signed;
863 let Inst{22-21} = opcod;
864 let Inst{20} = 1; // load
867 let Inst{15-12} = Rt;
870 let Inst{19-16} = addr{16-13}; // Rn
871 let Inst{23} = addr{12}; // U
872 let Inst{11-0} = addr{11-0}; // imm
874 def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
876 [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
877 let Inst{31-27} = 0b11111;
878 let Inst{26-25} = 0b00;
879 let Inst{24} = signed;
881 let Inst{22-21} = opcod;
882 let Inst{20} = 1; // load
884 // Offset: index==TRUE, wback==FALSE
885 let Inst{10} = 1; // The P bit.
886 let Inst{8} = 0; // The W bit.
889 let Inst{15-12} = Rt;
892 let Inst{19-16} = addr{12-9}; // Rn
893 let Inst{9} = addr{8}; // U
894 let Inst{7-0} = addr{7-0}; // imm
896 def s : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
897 opc, ".w\t$Rt, $addr",
898 [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
899 let Inst{31-27} = 0b11111;
900 let Inst{26-25} = 0b00;
901 let Inst{24} = signed;
903 let Inst{22-21} = opcod;
904 let Inst{20} = 1; // load
905 let Inst{11-6} = 0b000000;
908 let Inst{15-12} = Rt;
911 let Inst{19-16} = addr{9-6}; // Rn
912 let Inst{3-0} = addr{5-2}; // Rm
913 let Inst{5-4} = addr{1-0}; // imm
916 def pci : t2PseudoInst<(outs GPR:$Rt), (ins i32imm:$addr), Size4Bytes, iis,
917 [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>;
920 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
921 multiclass T2I_st<bits<2> opcod, string opc,
922 InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
923 def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
924 opc, ".w\t$Rt, $addr",
925 [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
926 let Inst{31-27} = 0b11111;
927 let Inst{26-23} = 0b0001;
928 let Inst{22-21} = opcod;
929 let Inst{20} = 0; // !load
932 let Inst{15-12} = Rt;
935 let Inst{19-16} = addr{16-13}; // Rn
936 let Inst{23} = addr{12}; // U
937 let Inst{11-0} = addr{11-0}; // imm
939 def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
941 [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
942 let Inst{31-27} = 0b11111;
943 let Inst{26-23} = 0b0000;
944 let Inst{22-21} = opcod;
945 let Inst{20} = 0; // !load
947 // Offset: index==TRUE, wback==FALSE
948 let Inst{10} = 1; // The P bit.
949 let Inst{8} = 0; // The W bit.
952 let Inst{15-12} = Rt;
955 let Inst{19-16} = addr{12-9}; // Rn
956 let Inst{9} = addr{8}; // U
957 let Inst{7-0} = addr{7-0}; // imm
959 def s : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
960 opc, ".w\t$Rt, $addr",
961 [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
962 let Inst{31-27} = 0b11111;
963 let Inst{26-23} = 0b0000;
964 let Inst{22-21} = opcod;
965 let Inst{20} = 0; // !load
966 let Inst{11-6} = 0b000000;
969 let Inst{15-12} = Rt;
972 let Inst{19-16} = addr{9-6}; // Rn
973 let Inst{3-0} = addr{5-2}; // Rm
974 let Inst{5-4} = addr{1-0}; // imm
978 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
979 /// register and one whose operand is a register rotated by 8/16/24.
980 multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
981 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
983 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
984 let Inst{31-27} = 0b11111;
985 let Inst{26-23} = 0b0100;
986 let Inst{22-20} = opcod;
987 let Inst{19-16} = 0b1111; // Rn
988 let Inst{15-12} = 0b1111;
990 let Inst{5-4} = 0b00; // rotate
992 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
993 opc, ".w\t$Rd, $Rm, ror $rot",
994 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
995 let Inst{31-27} = 0b11111;
996 let Inst{26-23} = 0b0100;
997 let Inst{22-20} = opcod;
998 let Inst{19-16} = 0b1111; // Rn
999 let Inst{15-12} = 0b1111;
1003 let Inst{5-4} = rot{1-0}; // rotate
1007 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1008 multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
1009 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1011 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
1012 Requires<[HasT2ExtractPack, IsThumb2]> {
1013 let Inst{31-27} = 0b11111;
1014 let Inst{26-23} = 0b0100;
1015 let Inst{22-20} = opcod;
1016 let Inst{19-16} = 0b1111; // Rn
1017 let Inst{15-12} = 0b1111;
1019 let Inst{5-4} = 0b00; // rotate
1021 def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
1022 IIC_iEXTr, opc, "\t$dst, $Rm, ror $rot",
1023 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1024 Requires<[HasT2ExtractPack, IsThumb2]> {
1025 let Inst{31-27} = 0b11111;
1026 let Inst{26-23} = 0b0100;
1027 let Inst{22-20} = opcod;
1028 let Inst{19-16} = 0b1111; // Rn
1029 let Inst{15-12} = 0b1111;
1033 let Inst{5-4} = rot{1-0}; // rotate
1037 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1039 multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1040 def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1041 opc, "\t$Rd, $Rm", []> {
1042 let Inst{31-27} = 0b11111;
1043 let Inst{26-23} = 0b0100;
1044 let Inst{22-20} = opcod;
1045 let Inst{19-16} = 0b1111; // Rn
1046 let Inst{15-12} = 0b1111;
1048 let Inst{5-4} = 0b00; // rotate
1050 def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1051 opc, "\t$Rd, $Rm, ror $rot", []> {
1052 let Inst{31-27} = 0b11111;
1053 let Inst{26-23} = 0b0100;
1054 let Inst{22-20} = opcod;
1055 let Inst{19-16} = 0b1111; // Rn
1056 let Inst{15-12} = 0b1111;
1060 let Inst{5-4} = rot{1-0}; // rotate
1064 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1065 /// register and one whose operand is a register rotated by 8/16/24.
1066 multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1067 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1068 opc, "\t$Rd, $Rn, $Rm",
1069 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1070 Requires<[HasT2ExtractPack, IsThumb2]> {
1071 let Inst{31-27} = 0b11111;
1072 let Inst{26-23} = 0b0100;
1073 let Inst{22-20} = opcod;
1074 let Inst{15-12} = 0b1111;
1076 let Inst{5-4} = 0b00; // rotate
1078 def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
1079 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1080 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1081 [(set rGPR:$Rd, (opnode rGPR:$Rn,
1082 (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1083 Requires<[HasT2ExtractPack, IsThumb2]> {
1084 let Inst{31-27} = 0b11111;
1085 let Inst{26-23} = 0b0100;
1086 let Inst{22-20} = opcod;
1087 let Inst{15-12} = 0b1111;
1091 let Inst{5-4} = rot{1-0}; // rotate
1095 // DO variant - disassembly only, no pattern
1097 multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
1098 def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1099 opc, "\t$Rd, $Rn, $Rm", []> {
1100 let Inst{31-27} = 0b11111;
1101 let Inst{26-23} = 0b0100;
1102 let Inst{22-20} = opcod;
1103 let Inst{15-12} = 0b1111;
1105 let Inst{5-4} = 0b00; // rotate
1107 def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1108 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
1109 let Inst{31-27} = 0b11111;
1110 let Inst{26-23} = 0b0100;
1111 let Inst{22-20} = opcod;
1112 let Inst{15-12} = 0b1111;
1116 let Inst{5-4} = rot{1-0}; // rotate
1120 //===----------------------------------------------------------------------===//
1122 //===----------------------------------------------------------------------===//
1124 //===----------------------------------------------------------------------===//
1125 // Miscellaneous Instructions.
1128 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1129 string asm, list<dag> pattern>
1130 : T2XI<oops, iops, itin, asm, pattern> {
1134 let Inst{11-8} = Rd;
1135 let Inst{26} = label{11};
1136 let Inst{14-12} = label{10-8};
1137 let Inst{7-0} = label{7-0};
1140 // LEApcrel - Load a pc-relative address into a register without offending the
1142 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1143 (ins t2adrlabel:$addr, pred:$p),
1144 IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1145 let Inst{31-27} = 0b11110;
1146 let Inst{25-24} = 0b10;
1147 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1150 let Inst{19-16} = 0b1111; // Rn
1155 let Inst{11-8} = Rd;
1156 let Inst{23} = addr{12};
1157 let Inst{21} = addr{12};
1158 let Inst{26} = addr{11};
1159 let Inst{14-12} = addr{10-8};
1160 let Inst{7-0} = addr{7-0};
1163 let neverHasSideEffects = 1, isReMaterializable = 1 in
1164 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1165 Size4Bytes, IIC_iALUi, []>;
1166 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1167 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1168 Size4Bytes, IIC_iALUi,
1172 // FIXME: None of these add/sub SP special instructions should be necessary
1173 // at all for thumb2 since they use the same encodings as the generic
1174 // add/sub instructions. In thumb1 we need them since they have dedicated
1175 // encodings. At the least, they should be pseudo instructions.
1176 // ADD r, sp, {so_imm|i12}
1177 let isCodeGenOnly = 1 in {
1178 def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1179 IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> {
1180 let Inst{31-27} = 0b11110;
1182 let Inst{24-21} = 0b1000;
1185 def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1186 IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> {
1187 let Inst{31-27} = 0b11110;
1188 let Inst{25-20} = 0b100000;
1192 // ADD r, sp, so_reg
1193 def t2ADDrSPs : T2sTwoRegShiftedReg<
1194 (outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
1195 IIC_iALUsi, "add", ".w\t$Rd, $Rn, $ShiftedRm", []> {
1196 let Inst{31-27} = 0b11101;
1197 let Inst{26-25} = 0b01;
1198 let Inst{24-21} = 0b1000;
1202 // SUB r, sp, {so_imm|i12}
1203 def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
1204 IIC_iALUi, "sub", ".w\t$Rd, $Rn, $imm", []> {
1205 let Inst{31-27} = 0b11110;
1207 let Inst{24-21} = 0b1101;
1210 def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
1211 IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> {
1212 let Inst{31-27} = 0b11110;
1213 let Inst{25-20} = 0b101010;
1217 // SUB r, sp, so_reg
1218 def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm),
1220 "sub", "\t$Rd, $Rn, $imm", []> {
1221 let Inst{31-27} = 0b11101;
1222 let Inst{26-25} = 0b01;
1223 let Inst{24-21} = 0b1101;
1224 let Inst{19-16} = 0b1101; // Rn = sp
1227 } // end isCodeGenOnly = 1
1229 // Signed and unsigned division on v7-M
1230 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1231 "sdiv", "\t$Rd, $Rn, $Rm",
1232 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
1233 Requires<[HasDivide, IsThumb2]> {
1234 let Inst{31-27} = 0b11111;
1235 let Inst{26-21} = 0b011100;
1237 let Inst{15-12} = 0b1111;
1238 let Inst{7-4} = 0b1111;
1241 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1242 "udiv", "\t$Rd, $Rn, $Rm",
1243 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
1244 Requires<[HasDivide, IsThumb2]> {
1245 let Inst{31-27} = 0b11111;
1246 let Inst{26-21} = 0b011101;
1248 let Inst{15-12} = 0b1111;
1249 let Inst{7-4} = 0b1111;
1252 //===----------------------------------------------------------------------===//
1253 // Load / store Instructions.
1257 let canFoldAsLoad = 1, isReMaterializable = 1 in
1258 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1259 UnOpFrag<(load node:$Src)>>;
1261 // Loads with zero extension
1262 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1263 UnOpFrag<(zextloadi16 node:$Src)>>;
1264 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1265 UnOpFrag<(zextloadi8 node:$Src)>>;
1267 // Loads with sign extension
1268 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1269 UnOpFrag<(sextloadi16 node:$Src)>>;
1270 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1271 UnOpFrag<(sextloadi8 node:$Src)>>;
1273 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1275 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1276 (ins t2addrmode_imm8s4:$addr),
1277 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1278 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1280 // zextload i1 -> zextload i8
1281 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1282 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1283 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1284 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1285 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1286 (t2LDRBs t2addrmode_so_reg:$addr)>;
1287 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1288 (t2LDRBpci tconstpool:$addr)>;
1290 // extload -> zextload
1291 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1293 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1294 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1295 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1296 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1297 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1298 (t2LDRBs t2addrmode_so_reg:$addr)>;
1299 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1300 (t2LDRBpci tconstpool:$addr)>;
1302 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1303 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1304 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1305 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1306 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1307 (t2LDRBs t2addrmode_so_reg:$addr)>;
1308 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1309 (t2LDRBpci tconstpool:$addr)>;
1311 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1312 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1313 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1314 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1315 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1316 (t2LDRHs t2addrmode_so_reg:$addr)>;
1317 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1318 (t2LDRHpci tconstpool:$addr)>;
1320 // FIXME: The destination register of the loads and stores can't be PC, but
1321 // can be SP. We need another regclass (similar to rGPR) to represent
1322 // that. Not a pressing issue since these are selected manually,
1327 let mayLoad = 1, neverHasSideEffects = 1 in {
1328 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1329 (ins t2addrmode_imm8:$addr),
1330 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1331 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1334 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1335 (ins GPR:$base, t2am_imm8_offset:$addr),
1336 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1337 "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1340 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1341 (ins t2addrmode_imm8:$addr),
1342 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1343 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1345 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1346 (ins GPR:$base, t2am_imm8_offset:$addr),
1347 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1348 "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1351 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1352 (ins t2addrmode_imm8:$addr),
1353 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1354 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1356 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1357 (ins GPR:$base, t2am_imm8_offset:$addr),
1358 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1359 "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1362 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1363 (ins t2addrmode_imm8:$addr),
1364 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1365 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1367 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1368 (ins GPR:$base, t2am_imm8_offset:$addr),
1369 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1370 "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1373 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1374 (ins t2addrmode_imm8:$addr),
1375 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1376 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1378 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
1379 (ins GPR:$base, t2am_imm8_offset:$addr),
1380 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1381 "ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
1383 } // mayLoad = 1, neverHasSideEffects = 1
1385 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1386 // for disassembly only.
1387 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1388 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1389 : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1390 "\t$Rt, $addr", []> {
1391 let Inst{31-27} = 0b11111;
1392 let Inst{26-25} = 0b00;
1393 let Inst{24} = signed;
1395 let Inst{22-21} = type;
1396 let Inst{20} = 1; // load
1398 let Inst{10-8} = 0b110; // PUW.
1402 let Inst{15-12} = Rt;
1403 let Inst{19-16} = addr{12-9};
1404 let Inst{7-0} = addr{7-0};
1407 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1408 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1409 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1410 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1411 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1414 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1415 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1416 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1417 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1418 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1419 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1422 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1423 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1424 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1425 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1428 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1429 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1430 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1431 "str", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1433 (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1435 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1436 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1437 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1438 "str", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1440 (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1442 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1443 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1444 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1445 "strh", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1447 (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1449 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1450 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1451 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1452 "strh", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1454 (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1456 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1457 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1458 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1459 "strb", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1461 (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1463 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1464 (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1465 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1466 "strb", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1468 (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1470 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1472 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1473 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1474 : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1475 "\t$Rt, $addr", []> {
1476 let Inst{31-27} = 0b11111;
1477 let Inst{26-25} = 0b00;
1478 let Inst{24} = 0; // not signed
1480 let Inst{22-21} = type;
1481 let Inst{20} = 0; // store
1483 let Inst{10-8} = 0b110; // PUW
1487 let Inst{15-12} = Rt;
1488 let Inst{19-16} = addr{12-9};
1489 let Inst{7-0} = addr{7-0};
1492 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1493 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1494 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1496 // ldrd / strd pre / post variants
1497 // For disassembly only.
1499 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1500 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1501 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1503 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1504 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1505 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1507 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1508 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1509 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1511 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1512 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1513 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1515 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1516 // data/instruction access. These are for disassembly only.
1517 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1518 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1519 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1521 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1523 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1524 let Inst{31-25} = 0b1111100;
1525 let Inst{24} = instr;
1527 let Inst{21} = write;
1529 let Inst{15-12} = 0b1111;
1532 let Inst{19-16} = addr{16-13}; // Rn
1533 let Inst{23} = addr{12}; // U
1534 let Inst{11-0} = addr{11-0}; // imm12
1537 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1539 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1540 let Inst{31-25} = 0b1111100;
1541 let Inst{24} = instr;
1542 let Inst{23} = 0; // U = 0
1544 let Inst{21} = write;
1546 let Inst{15-12} = 0b1111;
1547 let Inst{11-8} = 0b1100;
1550 let Inst{19-16} = addr{12-9}; // Rn
1551 let Inst{7-0} = addr{7-0}; // imm8
1554 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1556 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1557 let Inst{31-25} = 0b1111100;
1558 let Inst{24} = instr;
1559 let Inst{23} = 0; // add = TRUE for T1
1561 let Inst{21} = write;
1563 let Inst{15-12} = 0b1111;
1564 let Inst{11-6} = 0000000;
1567 let Inst{19-16} = addr{9-6}; // Rn
1568 let Inst{3-0} = addr{5-2}; // Rm
1569 let Inst{5-4} = addr{1-0}; // imm2
1573 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1574 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1575 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1577 //===----------------------------------------------------------------------===//
1578 // Load / store multiple Instructions.
1581 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1582 InstrItinClass itin_upd, bit L_bit> {
1584 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1585 itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1589 let Inst{31-27} = 0b11101;
1590 let Inst{26-25} = 0b00;
1591 let Inst{24-23} = 0b01; // Increment After
1593 let Inst{21} = 0; // No writeback
1594 let Inst{20} = L_bit;
1595 let Inst{19-16} = Rn;
1596 let Inst{15-0} = regs;
1599 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1600 itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1604 let Inst{31-27} = 0b11101;
1605 let Inst{26-25} = 0b00;
1606 let Inst{24-23} = 0b01; // Increment After
1608 let Inst{21} = 1; // Writeback
1609 let Inst{20} = L_bit;
1610 let Inst{19-16} = Rn;
1611 let Inst{15-0} = regs;
1614 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1615 itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1619 let Inst{31-27} = 0b11101;
1620 let Inst{26-25} = 0b00;
1621 let Inst{24-23} = 0b10; // Decrement Before
1623 let Inst{21} = 0; // No writeback
1624 let Inst{20} = L_bit;
1625 let Inst{19-16} = Rn;
1626 let Inst{15-0} = regs;
1629 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1630 itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1634 let Inst{31-27} = 0b11101;
1635 let Inst{26-25} = 0b00;
1636 let Inst{24-23} = 0b10; // Decrement Before
1638 let Inst{21} = 1; // Writeback
1639 let Inst{20} = L_bit;
1640 let Inst{19-16} = Rn;
1641 let Inst{15-0} = regs;
1645 let neverHasSideEffects = 1 in {
1647 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1648 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1650 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1651 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1653 } // neverHasSideEffects
1656 //===----------------------------------------------------------------------===//
1657 // Move Instructions.
1660 let neverHasSideEffects = 1 in
1661 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1662 "mov", ".w\t$Rd, $Rm", []> {
1663 let Inst{31-27} = 0b11101;
1664 let Inst{26-25} = 0b01;
1665 let Inst{24-21} = 0b0010;
1666 let Inst{19-16} = 0b1111; // Rn
1667 let Inst{14-12} = 0b000;
1668 let Inst{7-4} = 0b0000;
1671 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1672 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1673 AddedComplexity = 1 in
1674 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1675 "mov", ".w\t$Rd, $imm",
1676 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1677 let Inst{31-27} = 0b11110;
1679 let Inst{24-21} = 0b0010;
1680 let Inst{19-16} = 0b1111; // Rn
1684 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1685 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi,
1686 "movw", "\t$Rd, $imm",
1687 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1688 let Inst{31-27} = 0b11110;
1690 let Inst{24-21} = 0b0010;
1691 let Inst{20} = 0; // The S bit.
1697 let Inst{11-8} = Rd;
1698 let Inst{19-16} = imm{15-12};
1699 let Inst{26} = imm{11};
1700 let Inst{14-12} = imm{10-8};
1701 let Inst{7-0} = imm{7-0};
1704 def t2MOVi16_pic_ga : PseudoInst<(outs rGPR:$Rd),
1705 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1707 let Constraints = "$src = $Rd" in {
1708 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1709 (ins rGPR:$src, i32imm_hilo16:$imm), IIC_iMOVi,
1710 "movt", "\t$Rd, $imm",
1712 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1713 let Inst{31-27} = 0b11110;
1715 let Inst{24-21} = 0b0110;
1716 let Inst{20} = 0; // The S bit.
1722 let Inst{11-8} = Rd;
1723 let Inst{19-16} = imm{15-12};
1724 let Inst{26} = imm{11};
1725 let Inst{14-12} = imm{10-8};
1726 let Inst{7-0} = imm{7-0};
1729 def t2MOVTi16_pic_ga : PseudoInst<(outs rGPR:$Rd),
1730 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1733 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1735 //===----------------------------------------------------------------------===//
1736 // Extend Instructions.
1741 defm t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1742 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1743 defm t2SXTH : T2I_ext_rrot<0b000, "sxth",
1744 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1745 defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1747 defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1748 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1749 defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1750 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1751 defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1753 // TODO: SXT(A){B|H}16 - done for disassembly only
1757 let AddedComplexity = 16 in {
1758 defm t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1759 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1760 defm t2UXTH : T2I_ext_rrot<0b001, "uxth",
1761 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1762 defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1763 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1765 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1766 // The transformation should probably be done as a combiner action
1767 // instead so we can include a check for masking back in the upper
1768 // eight bits of the source into the lower eight bits of the result.
1769 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1770 // (t2UXTB16r_rot rGPR:$Src, 24)>,
1771 // Requires<[HasT2ExtractPack, IsThumb2]>;
1772 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1773 (t2UXTB16r_rot rGPR:$Src, 8)>,
1774 Requires<[HasT2ExtractPack, IsThumb2]>;
1776 defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1777 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1778 defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1779 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1780 defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1783 //===----------------------------------------------------------------------===//
1784 // Arithmetic Instructions.
1787 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1788 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1789 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1790 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1792 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1793 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1794 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1795 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1796 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1797 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1798 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1800 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1801 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1802 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1803 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1804 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1805 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1806 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1807 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1810 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1811 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1812 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1813 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1815 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1816 // The assume-no-carry-in form uses the negation of the input since add/sub
1817 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1818 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1820 // The AddedComplexity preferences the first variant over the others since
1821 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1822 let AddedComplexity = 1 in
1823 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1824 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1825 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1826 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1827 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1828 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1829 let AddedComplexity = 1 in
1830 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1831 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1832 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1833 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1834 // The with-carry-in form matches bitwise not instead of the negation.
1835 // Effectively, the inverse interpretation of the carry flag already accounts
1836 // for part of the negation.
1837 let AddedComplexity = 1 in
1838 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1839 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1840 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1841 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1843 // Select Bytes -- for disassembly only
1845 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1846 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
1847 let Inst{31-27} = 0b11111;
1848 let Inst{26-24} = 0b010;
1850 let Inst{22-20} = 0b010;
1851 let Inst{15-12} = 0b1111;
1853 let Inst{6-4} = 0b000;
1856 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1857 // And Miscellaneous operations -- for disassembly only
1858 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1859 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1860 : T2I<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, opc,
1861 "\t$Rd, $Rn, $Rm", pat> {
1862 let Inst{31-27} = 0b11111;
1863 let Inst{26-23} = 0b0101;
1864 let Inst{22-20} = op22_20;
1865 let Inst{15-12} = 0b1111;
1866 let Inst{7-4} = op7_4;
1872 let Inst{11-8} = Rd;
1873 let Inst{19-16} = Rn;
1877 // Saturating add/subtract -- for disassembly only
1879 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1880 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))]>;
1881 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1882 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1883 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1884 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1885 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1886 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1887 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1888 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))]>;
1889 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1890 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1891 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1892 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1893 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1894 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1895 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1896 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1898 // Signed/Unsigned add/subtract -- for disassembly only
1900 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1901 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1902 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1903 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1904 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1905 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1906 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1907 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1908 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1909 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1910 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1911 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1913 // Signed/Unsigned halving add/subtract -- for disassembly only
1915 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1916 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1917 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1918 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1919 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1920 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1921 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1922 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1923 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1924 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1925 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1926 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1928 // Helper class for disassembly only
1929 // A6.3.16 & A6.3.17
1930 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1931 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1932 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1933 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1934 let Inst{31-27} = 0b11111;
1935 let Inst{26-24} = 0b011;
1936 let Inst{23} = long;
1937 let Inst{22-20} = op22_20;
1938 let Inst{7-4} = op7_4;
1941 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1942 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1943 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1944 let Inst{31-27} = 0b11111;
1945 let Inst{26-24} = 0b011;
1946 let Inst{23} = long;
1947 let Inst{22-20} = op22_20;
1948 let Inst{7-4} = op7_4;
1951 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1953 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1954 (ins rGPR:$Rn, rGPR:$Rm),
1955 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
1956 let Inst{15-12} = 0b1111;
1958 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1959 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1960 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
1962 // Signed/Unsigned saturate -- for disassembly only
1964 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1965 string opc, string asm, list<dag> pattern>
1966 : T2I<oops, iops, itin, opc, asm, pattern> {
1972 let Inst{11-8} = Rd;
1973 let Inst{19-16} = Rn;
1974 let Inst{4-0} = sat_imm{4-0};
1975 let Inst{21} = sh{6};
1976 let Inst{14-12} = sh{4-2};
1977 let Inst{7-6} = sh{1-0};
1981 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1982 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1983 [/* For disassembly only; pattern left blank */]> {
1984 let Inst{31-27} = 0b11110;
1985 let Inst{25-22} = 0b1100;
1990 def t2SSAT16: T2SatI<
1991 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
1992 "ssat16", "\t$Rd, $sat_imm, $Rn",
1993 [/* For disassembly only; pattern left blank */]> {
1994 let Inst{31-27} = 0b11110;
1995 let Inst{25-22} = 0b1100;
1998 let Inst{21} = 1; // sh = '1'
1999 let Inst{14-12} = 0b000; // imm3 = '000'
2000 let Inst{7-6} = 0b00; // imm2 = '00'
2004 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2005 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
2006 [/* For disassembly only; pattern left blank */]> {
2007 let Inst{31-27} = 0b11110;
2008 let Inst{25-22} = 0b1110;
2013 def t2USAT16: T2SatI<
2014 (outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
2015 "usat16", "\t$dst, $sat_imm, $Rn",
2016 [/* For disassembly only; pattern left blank */]> {
2017 let Inst{31-27} = 0b11110;
2018 let Inst{25-22} = 0b1110;
2021 let Inst{21} = 1; // sh = '1'
2022 let Inst{14-12} = 0b000; // imm3 = '000'
2023 let Inst{7-6} = 0b00; // imm2 = '00'
2026 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2027 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2029 //===----------------------------------------------------------------------===//
2030 // Shift and rotate Instructions.
2033 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2034 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2035 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2036 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2038 let Uses = [CPSR] in {
2039 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2040 "rrx", "\t$Rd, $Rm",
2041 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2042 let Inst{31-27} = 0b11101;
2043 let Inst{26-25} = 0b01;
2044 let Inst{24-21} = 0b0010;
2045 let Inst{19-16} = 0b1111; // Rn
2046 let Inst{14-12} = 0b000;
2047 let Inst{7-4} = 0b0011;
2051 let isCodeGenOnly = 1, Defs = [CPSR] in {
2052 def t2MOVsrl_flag : T2TwoRegShiftImm<
2053 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2054 "lsrs", ".w\t$Rd, $Rm, #1",
2055 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2056 let Inst{31-27} = 0b11101;
2057 let Inst{26-25} = 0b01;
2058 let Inst{24-21} = 0b0010;
2059 let Inst{20} = 1; // The S bit.
2060 let Inst{19-16} = 0b1111; // Rn
2061 let Inst{5-4} = 0b01; // Shift type.
2062 // Shift amount = Inst{14-12:7-6} = 1.
2063 let Inst{14-12} = 0b000;
2064 let Inst{7-6} = 0b01;
2066 def t2MOVsra_flag : T2TwoRegShiftImm<
2067 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2068 "asrs", ".w\t$Rd, $Rm, #1",
2069 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2070 let Inst{31-27} = 0b11101;
2071 let Inst{26-25} = 0b01;
2072 let Inst{24-21} = 0b0010;
2073 let Inst{20} = 1; // The S bit.
2074 let Inst{19-16} = 0b1111; // Rn
2075 let Inst{5-4} = 0b10; // Shift type.
2076 // Shift amount = Inst{14-12:7-6} = 1.
2077 let Inst{14-12} = 0b000;
2078 let Inst{7-6} = 0b01;
2082 //===----------------------------------------------------------------------===//
2083 // Bitwise Instructions.
2086 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2087 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2088 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2089 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2090 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2091 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2092 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2093 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2094 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2096 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2097 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2098 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2100 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2101 string opc, string asm, list<dag> pattern>
2102 : T2I<oops, iops, itin, opc, asm, pattern> {
2107 let Inst{11-8} = Rd;
2108 let Inst{4-0} = msb{4-0};
2109 let Inst{14-12} = lsb{4-2};
2110 let Inst{7-6} = lsb{1-0};
2113 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2114 string opc, string asm, list<dag> pattern>
2115 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2118 let Inst{19-16} = Rn;
2121 let Constraints = "$src = $Rd" in
2122 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2123 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2124 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2125 let Inst{31-27} = 0b11110;
2127 let Inst{24-20} = 0b10110;
2128 let Inst{19-16} = 0b1111; // Rn
2132 let msb{4-0} = imm{9-5};
2133 let lsb{4-0} = imm{4-0};
2136 def t2SBFX: T2TwoRegBitFI<
2137 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2138 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2139 let Inst{31-27} = 0b11110;
2141 let Inst{24-20} = 0b10100;
2145 def t2UBFX: T2TwoRegBitFI<
2146 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2147 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2148 let Inst{31-27} = 0b11110;
2150 let Inst{24-20} = 0b11100;
2154 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2155 let Constraints = "$src = $Rd" in {
2156 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2157 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2158 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2159 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2160 bf_inv_mask_imm:$imm))]> {
2161 let Inst{31-27} = 0b11110;
2163 let Inst{24-20} = 0b10110;
2167 let msb{4-0} = imm{9-5};
2168 let lsb{4-0} = imm{4-0};
2171 // GNU as only supports this form of bfi (w/ 4 arguments)
2172 let isAsmParserOnly = 1 in
2173 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2174 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2176 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2178 let Inst{31-27} = 0b11110;
2180 let Inst{24-20} = 0b10110;
2185 let msb{4-0} = width; // Custom encoder => lsb+width-1
2186 let lsb{4-0} = lsbit;
2190 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2191 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2192 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2194 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2195 let AddedComplexity = 1 in
2196 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2197 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2198 UnOpFrag<(not node:$Src)>, 1, 1>;
2201 let AddedComplexity = 1 in
2202 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2203 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2205 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2206 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2207 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2208 Requires<[IsThumb2]>;
2210 def : T2Pat<(t2_so_imm_not:$src),
2211 (t2MVNi t2_so_imm_not:$src)>;
2213 //===----------------------------------------------------------------------===//
2214 // Multiply Instructions.
2216 let isCommutable = 1 in
2217 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2218 "mul", "\t$Rd, $Rn, $Rm",
2219 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2220 let Inst{31-27} = 0b11111;
2221 let Inst{26-23} = 0b0110;
2222 let Inst{22-20} = 0b000;
2223 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2224 let Inst{7-4} = 0b0000; // Multiply
2227 def t2MLA: T2FourReg<
2228 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2229 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2230 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2231 let Inst{31-27} = 0b11111;
2232 let Inst{26-23} = 0b0110;
2233 let Inst{22-20} = 0b000;
2234 let Inst{7-4} = 0b0000; // Multiply
2237 def t2MLS: T2FourReg<
2238 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2239 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2240 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2241 let Inst{31-27} = 0b11111;
2242 let Inst{26-23} = 0b0110;
2243 let Inst{22-20} = 0b000;
2244 let Inst{7-4} = 0b0001; // Multiply and Subtract
2247 // Extra precision multiplies with low / high results
2248 let neverHasSideEffects = 1 in {
2249 let isCommutable = 1 in {
2250 def t2SMULL : T2MulLong<0b000, 0b0000,
2251 (outs rGPR:$Rd, rGPR:$Ra),
2252 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2253 "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
2255 def t2UMULL : T2MulLong<0b010, 0b0000,
2256 (outs rGPR:$RdLo, rGPR:$RdHi),
2257 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2258 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2261 // Multiply + accumulate
2262 def t2SMLAL : T2MulLong<0b100, 0b0000,
2263 (outs rGPR:$RdLo, rGPR:$RdHi),
2264 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2265 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2267 def t2UMLAL : T2MulLong<0b110, 0b0000,
2268 (outs rGPR:$RdLo, rGPR:$RdHi),
2269 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2270 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2272 def t2UMAAL : T2MulLong<0b110, 0b0110,
2273 (outs rGPR:$RdLo, rGPR:$RdHi),
2274 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2275 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2276 } // neverHasSideEffects
2278 // Rounding variants of the below included for disassembly only
2280 // Most significant word multiply
2281 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2282 "smmul", "\t$Rd, $Rn, $Rm",
2283 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
2284 let Inst{31-27} = 0b11111;
2285 let Inst{26-23} = 0b0110;
2286 let Inst{22-20} = 0b101;
2287 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2288 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2291 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2292 "smmulr", "\t$Rd, $Rn, $Rm", []> {
2293 let Inst{31-27} = 0b11111;
2294 let Inst{26-23} = 0b0110;
2295 let Inst{22-20} = 0b101;
2296 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2297 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2300 def t2SMMLA : T2FourReg<
2301 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2302 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2303 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
2304 let Inst{31-27} = 0b11111;
2305 let Inst{26-23} = 0b0110;
2306 let Inst{22-20} = 0b101;
2307 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2310 def t2SMMLAR: T2FourReg<
2311 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2312 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
2313 let Inst{31-27} = 0b11111;
2314 let Inst{26-23} = 0b0110;
2315 let Inst{22-20} = 0b101;
2316 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2319 def t2SMMLS: T2FourReg<
2320 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2321 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2322 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
2323 let Inst{31-27} = 0b11111;
2324 let Inst{26-23} = 0b0110;
2325 let Inst{22-20} = 0b110;
2326 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2329 def t2SMMLSR:T2FourReg<
2330 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2331 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
2332 let Inst{31-27} = 0b11111;
2333 let Inst{26-23} = 0b0110;
2334 let Inst{22-20} = 0b110;
2335 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2338 multiclass T2I_smul<string opc, PatFrag opnode> {
2339 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2340 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2341 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2342 (sext_inreg rGPR:$Rm, i16)))]> {
2343 let Inst{31-27} = 0b11111;
2344 let Inst{26-23} = 0b0110;
2345 let Inst{22-20} = 0b001;
2346 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2347 let Inst{7-6} = 0b00;
2348 let Inst{5-4} = 0b00;
2351 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2352 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2353 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2354 (sra rGPR:$Rm, (i32 16))))]> {
2355 let Inst{31-27} = 0b11111;
2356 let Inst{26-23} = 0b0110;
2357 let Inst{22-20} = 0b001;
2358 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2359 let Inst{7-6} = 0b00;
2360 let Inst{5-4} = 0b01;
2363 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2364 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2365 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2366 (sext_inreg rGPR:$Rm, i16)))]> {
2367 let Inst{31-27} = 0b11111;
2368 let Inst{26-23} = 0b0110;
2369 let Inst{22-20} = 0b001;
2370 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2371 let Inst{7-6} = 0b00;
2372 let Inst{5-4} = 0b10;
2375 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2376 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2377 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2378 (sra rGPR:$Rm, (i32 16))))]> {
2379 let Inst{31-27} = 0b11111;
2380 let Inst{26-23} = 0b0110;
2381 let Inst{22-20} = 0b001;
2382 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2383 let Inst{7-6} = 0b00;
2384 let Inst{5-4} = 0b11;
2387 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2388 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2389 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2390 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
2391 let Inst{31-27} = 0b11111;
2392 let Inst{26-23} = 0b0110;
2393 let Inst{22-20} = 0b011;
2394 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2395 let Inst{7-6} = 0b00;
2396 let Inst{5-4} = 0b00;
2399 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2400 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2401 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2402 (sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
2403 let Inst{31-27} = 0b11111;
2404 let Inst{26-23} = 0b0110;
2405 let Inst{22-20} = 0b011;
2406 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2407 let Inst{7-6} = 0b00;
2408 let Inst{5-4} = 0b01;
2413 multiclass T2I_smla<string opc, PatFrag opnode> {
2415 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2416 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2417 [(set rGPR:$Rd, (add rGPR:$Ra,
2418 (opnode (sext_inreg rGPR:$Rn, i16),
2419 (sext_inreg rGPR:$Rm, i16))))]> {
2420 let Inst{31-27} = 0b11111;
2421 let Inst{26-23} = 0b0110;
2422 let Inst{22-20} = 0b001;
2423 let Inst{7-6} = 0b00;
2424 let Inst{5-4} = 0b00;
2428 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2429 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2430 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2431 (sra rGPR:$Rm, (i32 16)))))]> {
2432 let Inst{31-27} = 0b11111;
2433 let Inst{26-23} = 0b0110;
2434 let Inst{22-20} = 0b001;
2435 let Inst{7-6} = 0b00;
2436 let Inst{5-4} = 0b01;
2440 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2441 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2442 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2443 (sext_inreg rGPR:$Rm, i16))))]> {
2444 let Inst{31-27} = 0b11111;
2445 let Inst{26-23} = 0b0110;
2446 let Inst{22-20} = 0b001;
2447 let Inst{7-6} = 0b00;
2448 let Inst{5-4} = 0b10;
2452 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2453 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2454 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2455 (sra rGPR:$Rm, (i32 16)))))]> {
2456 let Inst{31-27} = 0b11111;
2457 let Inst{26-23} = 0b0110;
2458 let Inst{22-20} = 0b001;
2459 let Inst{7-6} = 0b00;
2460 let Inst{5-4} = 0b11;
2464 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2465 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2466 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2467 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
2468 let Inst{31-27} = 0b11111;
2469 let Inst{26-23} = 0b0110;
2470 let Inst{22-20} = 0b011;
2471 let Inst{7-6} = 0b00;
2472 let Inst{5-4} = 0b00;
2476 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2477 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2478 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2479 (sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
2480 let Inst{31-27} = 0b11111;
2481 let Inst{26-23} = 0b0110;
2482 let Inst{22-20} = 0b011;
2483 let Inst{7-6} = 0b00;
2484 let Inst{5-4} = 0b01;
2488 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2489 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2491 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2492 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2493 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2494 [/* For disassembly only; pattern left blank */]>;
2495 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2496 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2497 [/* For disassembly only; pattern left blank */]>;
2498 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2499 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2500 [/* For disassembly only; pattern left blank */]>;
2501 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2502 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2503 [/* For disassembly only; pattern left blank */]>;
2505 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2506 // These are for disassembly only.
2508 def t2SMUAD: T2ThreeReg_mac<
2509 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2510 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
2511 let Inst{15-12} = 0b1111;
2513 def t2SMUADX:T2ThreeReg_mac<
2514 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2515 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
2516 let Inst{15-12} = 0b1111;
2518 def t2SMUSD: T2ThreeReg_mac<
2519 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2520 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
2521 let Inst{15-12} = 0b1111;
2523 def t2SMUSDX:T2ThreeReg_mac<
2524 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2525 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
2526 let Inst{15-12} = 0b1111;
2528 def t2SMLAD : T2ThreeReg_mac<
2529 0, 0b010, 0b0000, (outs rGPR:$Rd),
2530 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2531 "\t$Rd, $Rn, $Rm, $Ra", []>;
2532 def t2SMLADX : T2FourReg_mac<
2533 0, 0b010, 0b0001, (outs rGPR:$Rd),
2534 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2535 "\t$Rd, $Rn, $Rm, $Ra", []>;
2536 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2537 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2538 "\t$Rd, $Rn, $Rm, $Ra", []>;
2539 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2540 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2541 "\t$Rd, $Rn, $Rm, $Ra", []>;
2542 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2543 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2544 "\t$Ra, $Rd, $Rm, $Rn", []>;
2545 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2546 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2547 "\t$Ra, $Rd, $Rm, $Rn", []>;
2548 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2549 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2550 "\t$Ra, $Rd, $Rm, $Rn", []>;
2551 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2552 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2553 "\t$Ra, $Rd, $Rm, $Rn", []>;
2555 //===----------------------------------------------------------------------===//
2556 // Misc. Arithmetic Instructions.
2559 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2560 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2561 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2562 let Inst{31-27} = 0b11111;
2563 let Inst{26-22} = 0b01010;
2564 let Inst{21-20} = op1;
2565 let Inst{15-12} = 0b1111;
2566 let Inst{7-6} = 0b10;
2567 let Inst{5-4} = op2;
2571 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2572 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2574 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2575 "rbit", "\t$Rd, $Rm",
2576 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2578 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2579 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2581 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2582 "rev16", ".w\t$Rd, $Rm",
2584 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF),
2585 (or (and (shl rGPR:$Rm, (i32 8)), 0xFF00),
2586 (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
2587 (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
2589 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2590 "revsh", ".w\t$Rd, $Rm",
2593 (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
2594 (shl rGPR:$Rm, (i32 8))), i16))]>;
2596 def t2PKHBT : T2ThreeReg<
2597 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2598 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2599 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2600 (and (shl rGPR:$Rm, lsl_amt:$sh),
2602 Requires<[HasT2ExtractPack, IsThumb2]> {
2603 let Inst{31-27} = 0b11101;
2604 let Inst{26-25} = 0b01;
2605 let Inst{24-20} = 0b01100;
2606 let Inst{5} = 0; // BT form
2610 let Inst{14-12} = sh{7-5};
2611 let Inst{7-6} = sh{4-3};
2614 // Alternate cases for PKHBT where identities eliminate some nodes.
2615 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2616 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2617 Requires<[HasT2ExtractPack, IsThumb2]>;
2618 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2619 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2620 Requires<[HasT2ExtractPack, IsThumb2]>;
2622 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2623 // will match the pattern below.
2624 def t2PKHTB : T2ThreeReg<
2625 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2626 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2627 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2628 (and (sra rGPR:$Rm, asr_amt:$sh),
2630 Requires<[HasT2ExtractPack, IsThumb2]> {
2631 let Inst{31-27} = 0b11101;
2632 let Inst{26-25} = 0b01;
2633 let Inst{24-20} = 0b01100;
2634 let Inst{5} = 1; // TB form
2638 let Inst{14-12} = sh{7-5};
2639 let Inst{7-6} = sh{4-3};
2642 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2643 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2644 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2645 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2646 Requires<[HasT2ExtractPack, IsThumb2]>;
2647 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2648 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2649 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2650 Requires<[HasT2ExtractPack, IsThumb2]>;
2652 //===----------------------------------------------------------------------===//
2653 // Comparison Instructions...
2655 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2656 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2657 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2659 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
2660 (t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
2661 def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
2662 (t2CMPrr GPR:$lhs, rGPR:$rhs)>;
2663 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
2664 (t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
2666 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2667 // Compare-to-zero still works out, just not the relationals
2668 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2669 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2670 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2671 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2672 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2674 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2675 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2677 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2678 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2680 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2681 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2682 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2683 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2684 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2685 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2687 // Conditional moves
2688 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2689 // a two-value operand where a dag node expects two operands. :(
2690 let neverHasSideEffects = 1 in {
2691 def t2MOVCCr : T2TwoReg<
2692 (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
2693 "mov", ".w\t$Rd, $Rm",
2694 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2695 RegConstraint<"$false = $Rd"> {
2696 let Inst{31-27} = 0b11101;
2697 let Inst{26-25} = 0b01;
2698 let Inst{24-21} = 0b0010;
2699 let Inst{20} = 0; // The S bit.
2700 let Inst{19-16} = 0b1111; // Rn
2701 let Inst{14-12} = 0b000;
2702 let Inst{7-4} = 0b0000;
2705 let isMoveImm = 1 in
2706 def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2707 IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
2708 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2709 RegConstraint<"$false = $Rd"> {
2710 let Inst{31-27} = 0b11110;
2712 let Inst{24-21} = 0b0010;
2713 let Inst{20} = 0; // The S bit.
2714 let Inst{19-16} = 0b1111; // Rn
2718 let isMoveImm = 1 in
2719 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm_hilo16:$imm),
2721 "movw", "\t$Rd, $imm", []>,
2722 RegConstraint<"$false = $Rd"> {
2723 let Inst{31-27} = 0b11110;
2725 let Inst{24-21} = 0b0010;
2726 let Inst{20} = 0; // The S bit.
2732 let Inst{11-8} = Rd;
2733 let Inst{19-16} = imm{15-12};
2734 let Inst{26} = imm{11};
2735 let Inst{14-12} = imm{10-8};
2736 let Inst{7-0} = imm{7-0};
2739 let isMoveImm = 1 in
2740 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2741 (ins rGPR:$false, i32imm:$src, pred:$p),
2742 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2744 let isMoveImm = 1 in
2745 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2746 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2747 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2748 imm:$cc, CCR:$ccr))*/]>,
2749 RegConstraint<"$false = $Rd"> {
2750 let Inst{31-27} = 0b11110;
2752 let Inst{24-21} = 0b0011;
2753 let Inst{20} = 0; // The S bit.
2754 let Inst{19-16} = 0b1111; // Rn
2758 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2759 string opc, string asm, list<dag> pattern>
2760 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2761 let Inst{31-27} = 0b11101;
2762 let Inst{26-25} = 0b01;
2763 let Inst{24-21} = 0b0010;
2764 let Inst{20} = 0; // The S bit.
2765 let Inst{19-16} = 0b1111; // Rn
2766 let Inst{5-4} = opcod; // Shift type.
2768 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2769 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2770 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2771 RegConstraint<"$false = $Rd">;
2772 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2773 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2774 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2775 RegConstraint<"$false = $Rd">;
2776 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2777 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2778 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2779 RegConstraint<"$false = $Rd">;
2780 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2781 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2782 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2783 RegConstraint<"$false = $Rd">;
2784 } // neverHasSideEffects
2786 //===----------------------------------------------------------------------===//
2787 // Atomic operations intrinsics
2790 // memory barriers protect the atomic sequences
2791 let hasSideEffects = 1 in {
2792 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2793 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2794 Requires<[IsThumb, HasDB]> {
2796 let Inst{31-4} = 0xf3bf8f5;
2797 let Inst{3-0} = opt;
2801 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2803 [/* For disassembly only; pattern left blank */]>,
2804 Requires<[IsThumb, HasDB]> {
2806 let Inst{31-4} = 0xf3bf8f4;
2807 let Inst{3-0} = opt;
2810 // ISB has only full system option -- for disassembly only
2811 def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2812 [/* For disassembly only; pattern left blank */]>,
2813 Requires<[IsThumb2, HasV7]> {
2814 let Inst{31-4} = 0xf3bf8f6;
2815 let Inst{3-0} = 0b1111;
2818 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2819 InstrItinClass itin, string opc, string asm, string cstr,
2820 list<dag> pattern, bits<4> rt2 = 0b1111>
2821 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2822 let Inst{31-27} = 0b11101;
2823 let Inst{26-20} = 0b0001101;
2824 let Inst{11-8} = rt2;
2825 let Inst{7-6} = 0b01;
2826 let Inst{5-4} = opcod;
2827 let Inst{3-0} = 0b1111;
2831 let Inst{19-16} = Rn;
2832 let Inst{15-12} = Rt;
2834 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2835 InstrItinClass itin, string opc, string asm, string cstr,
2836 list<dag> pattern, bits<4> rt2 = 0b1111>
2837 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2838 let Inst{31-27} = 0b11101;
2839 let Inst{26-20} = 0b0001100;
2840 let Inst{11-8} = rt2;
2841 let Inst{7-6} = 0b01;
2842 let Inst{5-4} = opcod;
2847 let Inst{11-8} = Rd;
2848 let Inst{19-16} = Rn;
2849 let Inst{15-12} = Rt;
2852 let mayLoad = 1 in {
2853 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2854 Size4Bytes, NoItinerary, "ldrexb", "\t$Rt, [$Rn]",
2856 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2857 Size4Bytes, NoItinerary, "ldrexh", "\t$Rt, [$Rn]",
2859 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2860 Size4Bytes, NoItinerary,
2861 "ldrex", "\t$Rt, [$Rn]", "",
2863 let Inst{31-27} = 0b11101;
2864 let Inst{26-20} = 0b0000101;
2865 let Inst{11-8} = 0b1111;
2866 let Inst{7-0} = 0b00000000; // imm8 = 0
2870 let Inst{19-16} = Rn;
2871 let Inst{15-12} = Rt;
2873 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), (ins rGPR:$Rn),
2874 AddrModeNone, Size4Bytes, NoItinerary,
2875 "ldrexd", "\t$Rt, $Rt2, [$Rn]", "",
2878 let Inst{11-8} = Rt2;
2882 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2883 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2884 AddrModeNone, Size4Bytes, NoItinerary,
2885 "strexb", "\t$Rd, $Rt, [$Rn]", "", []>;
2886 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2887 AddrModeNone, Size4Bytes, NoItinerary,
2888 "strexh", "\t$Rd, $Rt, [$Rn]", "", []>;
2889 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2890 AddrModeNone, Size4Bytes, NoItinerary,
2891 "strex", "\t$Rd, $Rt, [$Rn]", "",
2893 let Inst{31-27} = 0b11101;
2894 let Inst{26-20} = 0b0000100;
2895 let Inst{7-0} = 0b00000000; // imm8 = 0
2900 let Inst{11-8} = Rd;
2901 let Inst{19-16} = Rn;
2902 let Inst{15-12} = Rt;
2904 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2905 (ins rGPR:$Rt, rGPR:$Rt2, rGPR:$Rn),
2906 AddrModeNone, Size4Bytes, NoItinerary,
2907 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]", "", [],
2910 let Inst{11-8} = Rt2;
2914 // Clear-Exclusive is for disassembly only.
2915 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2916 [/* For disassembly only; pattern left blank */]>,
2917 Requires<[IsARM, HasV7]> {
2918 let Inst{31-20} = 0xf3b;
2919 let Inst{15-14} = 0b10;
2921 let Inst{7-4} = 0b0010;
2924 //===----------------------------------------------------------------------===//
2928 // __aeabi_read_tp preserves the registers r1-r3.
2930 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
2931 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2932 "bl\t__aeabi_read_tp",
2933 [(set R0, ARMthread_pointer)]> {
2934 let Inst{31-27} = 0b11110;
2935 let Inst{15-14} = 0b11;
2940 //===----------------------------------------------------------------------===//
2941 // SJLJ Exception handling intrinsics
2942 // eh_sjlj_setjmp() is an instruction sequence to store the return
2943 // address and save #0 in R0 for the non-longjmp case.
2944 // Since by its nature we may be coming from some other function to get
2945 // here, and we're using the stack frame for the containing function to
2946 // save/restore registers, we can't keep anything live in regs across
2947 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2948 // when we get here from a longjmp(). We force everthing out of registers
2949 // except for our own input by listing the relevant registers in Defs. By
2950 // doing so, we also cause the prologue/epilogue code to actively preserve
2951 // all of the callee-saved resgisters, which is exactly what we want.
2952 // $val is a scratch register for our use.
2954 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2955 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2956 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2957 D31 ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2958 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2959 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2960 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2961 Requires<[IsThumb2, HasVFP2]>;
2965 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2966 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2967 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2968 AddrModeNone, SizeSpecial, NoItinerary, "", "",
2969 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2970 Requires<[IsThumb2, NoVFP]>;
2974 //===----------------------------------------------------------------------===//
2975 // Control-Flow Instructions
2978 // FIXME: remove when we have a way to marking a MI with these properties.
2979 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2981 // FIXME: Should pc be an implicit operand like PICADD, etc?
2982 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2983 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2984 def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2985 reglist:$regs, variable_ops),
2987 "ldmia${p}.w\t$Rn!, $regs",
2992 let Inst{31-27} = 0b11101;
2993 let Inst{26-25} = 0b00;
2994 let Inst{24-23} = 0b01; // Increment After
2996 let Inst{21} = 1; // Writeback
2998 let Inst{19-16} = Rn;
2999 let Inst{15-0} = regs;
3002 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3003 let isPredicable = 1 in
3004 def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
3006 [(br bb:$target)]> {
3007 let Inst{31-27} = 0b11110;
3008 let Inst{15-14} = 0b10;
3012 let Inst{26} = target{19};
3013 let Inst{11} = target{18};
3014 let Inst{13} = target{17};
3015 let Inst{21-16} = target{16-11};
3016 let Inst{10-0} = target{10-0};
3019 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3020 def t2BR_JT : t2PseudoInst<(outs),
3021 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3022 SizeSpecial, IIC_Br,
3023 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3025 // FIXME: Add a non-pc based case that can be predicated.
3026 def t2TBB_JT : t2PseudoInst<(outs),
3027 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3028 SizeSpecial, IIC_Br, []>;
3030 def t2TBH_JT : t2PseudoInst<(outs),
3031 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3032 SizeSpecial, IIC_Br, []>;
3034 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3035 "tbb", "\t[$Rn, $Rm]", []> {
3038 let Inst{31-20} = 0b111010001101;
3039 let Inst{19-16} = Rn;
3040 let Inst{15-5} = 0b11110000000;
3041 let Inst{4} = 0; // B form
3045 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3046 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3049 let Inst{31-20} = 0b111010001101;
3050 let Inst{19-16} = Rn;
3051 let Inst{15-5} = 0b11110000000;
3052 let Inst{4} = 1; // H form
3055 } // isNotDuplicable, isIndirectBranch
3057 } // isBranch, isTerminator, isBarrier
3059 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3060 // a two-value operand where a dag node expects two operands. :(
3061 let isBranch = 1, isTerminator = 1 in
3062 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3064 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3065 let Inst{31-27} = 0b11110;
3066 let Inst{15-14} = 0b10;
3070 let Inst{25-22} = p;
3073 let Inst{26} = target{20};
3074 let Inst{11} = target{19};
3075 let Inst{13} = target{18};
3076 let Inst{21-16} = target{17-12};
3077 let Inst{10-0} = target{11-1};
3082 let Defs = [ITSTATE] in
3083 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3084 AddrModeNone, Size2Bytes, IIC_iALUx,
3085 "it$mask\t$cc", "", []> {
3086 // 16-bit instruction.
3087 let Inst{31-16} = 0x0000;
3088 let Inst{15-8} = 0b10111111;
3093 let Inst{3-0} = mask;
3096 // Branch and Exchange Jazelle -- for disassembly only
3098 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3099 [/* For disassembly only; pattern left blank */]> {
3100 let Inst{31-27} = 0b11110;
3102 let Inst{25-20} = 0b111100;
3103 let Inst{15-14} = 0b10;
3107 let Inst{19-16} = func;
3110 // Change Processor State is a system instruction -- for disassembly only.
3111 // The singleton $opt operand contains the following information:
3112 // opt{4-0} = mode from Inst{4-0}
3113 // opt{5} = changemode from Inst{17}
3114 // opt{8-6} = AIF from Inst{8-6}
3115 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3116 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
3117 [/* For disassembly only; pattern left blank */]> {
3118 let Inst{31-27} = 0b11110;
3120 let Inst{25-20} = 0b111010;
3121 let Inst{15-14} = 0b10;
3127 let Inst{4-0} = opt{4-0};
3130 let Inst{8} = opt{5};
3133 let Inst{5} = opt{6};
3136 let Inst{6} = opt{7};
3139 let Inst{7} = opt{8};
3142 let Inst{10-9} = opt{10-9};
3145 // A6.3.4 Branches and miscellaneous control
3146 // Table A6-14 Change Processor State, and hint instructions
3147 // Helper class for disassembly only.
3148 class T2I_hint<bits<8> op7_0, string opc, string asm>
3149 : T2I<(outs), (ins), NoItinerary, opc, asm,
3150 [/* For disassembly only; pattern left blank */]> {
3151 let Inst{31-20} = 0xf3a;
3152 let Inst{15-14} = 0b10;
3154 let Inst{10-8} = 0b000;
3155 let Inst{7-0} = op7_0;
3158 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3159 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3160 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3161 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3162 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3164 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
3165 [/* For disassembly only; pattern left blank */]> {
3166 let Inst{31-20} = 0xf3a;
3167 let Inst{15-14} = 0b10;
3169 let Inst{10-8} = 0b000;
3170 let Inst{7-4} = 0b1111;
3173 let Inst{3-0} = opt;
3176 // Secure Monitor Call is a system instruction -- for disassembly only
3177 // Option = Inst{19-16}
3178 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
3179 [/* For disassembly only; pattern left blank */]> {
3180 let Inst{31-27} = 0b11110;
3181 let Inst{26-20} = 0b1111111;
3182 let Inst{15-12} = 0b1000;
3185 let Inst{19-16} = opt;
3188 class T2SRS<bits<12> op31_20,
3189 dag oops, dag iops, InstrItinClass itin,
3190 string opc, string asm, list<dag> pattern>
3191 : T2I<oops, iops, itin, opc, asm, pattern> {
3192 let Inst{31-20} = op31_20{11-0};
3195 let Inst{4-0} = mode{4-0};
3198 // Store Return State is a system instruction -- for disassembly only
3199 def t2SRSDBW : T2SRS<0b111010000010,
3200 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3201 [/* For disassembly only; pattern left blank */]>;
3202 def t2SRSDB : T2SRS<0b111010000000,
3203 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3204 [/* For disassembly only; pattern left blank */]>;
3205 def t2SRSIAW : T2SRS<0b111010011010,
3206 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3207 [/* For disassembly only; pattern left blank */]>;
3208 def t2SRSIA : T2SRS<0b111010011000,
3209 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3210 [/* For disassembly only; pattern left blank */]>;
3212 // Return From Exception is a system instruction -- for disassembly only
3214 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3215 string opc, string asm, list<dag> pattern>
3216 : T2I<oops, iops, itin, opc, asm, pattern> {
3217 let Inst{31-20} = op31_20{11-0};
3220 let Inst{19-16} = Rn;
3223 def t2RFEDBW : T2RFE<0b111010000011,
3224 (outs), (ins rGPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3225 [/* For disassembly only; pattern left blank */]>;
3226 def t2RFEDB : T2RFE<0b111010000001,
3227 (outs), (ins rGPR:$Rn), NoItinerary, "rfeab", "\t$Rn",
3228 [/* For disassembly only; pattern left blank */]>;
3229 def t2RFEIAW : T2RFE<0b111010011011,
3230 (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3231 [/* For disassembly only; pattern left blank */]>;
3232 def t2RFEIA : T2RFE<0b111010011001,
3233 (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3234 [/* For disassembly only; pattern left blank */]>;
3236 //===----------------------------------------------------------------------===//
3237 // Non-Instruction Patterns
3240 // 32-bit immediate using movw + movt.
3241 // This is a single pseudo instruction to make it re-materializable.
3242 // FIXME: Remove this when we can do generalized remat.
3243 let isReMaterializable = 1, isMoveImm = 1 in
3244 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3245 [(set rGPR:$dst, (i32 imm:$src))]>,
3246 Requires<[IsThumb, HasV6T2]>;
3248 // Pseudo instruction that combines movw + movt + add pc.
3249 // It also makes it possible to rematerialize the instructions.
3250 // FIXME: Remove this when we can do generalized remat and when machine licm
3251 // can properly the instructions.
3252 let isReMaterializable = 1 in
3253 def t2MOV_pic_ga_add_pc : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3255 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3256 Requires<[IsThumb2, UseMovt]>;
3258 // ConstantPool, GlobalAddress, and JumpTable
3259 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3260 Requires<[IsThumb2, DontUseMovt]>;
3261 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3262 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3263 Requires<[IsThumb2, UseMovt]>;
3265 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3266 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3268 // Pseudo instruction that combines ldr from constpool and add pc. This should
3269 // be expanded into two instructions late to allow if-conversion and
3271 let canFoldAsLoad = 1, isReMaterializable = 1 in
3272 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3274 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3276 Requires<[IsThumb2]>;
3278 //===----------------------------------------------------------------------===//
3279 // Move between special register and ARM core register -- for disassembly only
3282 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3283 dag oops, dag iops, InstrItinClass itin,
3284 string opc, string asm, list<dag> pattern>
3285 : T2I<oops, iops, itin, opc, asm, pattern> {
3286 let Inst{31-20} = op31_20{11-0};
3287 let Inst{15-14} = op15_14{1-0};
3288 let Inst{12} = op12{0};
3291 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3292 dag oops, dag iops, InstrItinClass itin,
3293 string opc, string asm, list<dag> pattern>
3294 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3296 let Inst{11-8} = Rd;
3297 let Inst{19-16} = 0b1111;
3300 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3301 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3302 [/* For disassembly only; pattern left blank */]>;
3303 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3304 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3305 [/* For disassembly only; pattern left blank */]>;
3307 class T2MSR<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3308 dag oops, dag iops, InstrItinClass itin,
3309 string opc, string asm, list<dag> pattern>
3310 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3313 let Inst{19-16} = Rn;
3314 let Inst{11-8} = mask;
3317 def t2MSR : T2MSR<0b111100111000, 0b10, 0,
3318 (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3320 [/* For disassembly only; pattern left blank */]>;
3321 def t2MSRsys : T2MSR<0b111100111001, 0b10, 0,
3322 (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3324 [/* For disassembly only; pattern left blank */]>;
3326 //===----------------------------------------------------------------------===//
3327 // Move between coprocessor and ARM core register -- for disassembly only
3330 class t2MovRCopro<string opc, bit direction>
3331 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
3332 GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3333 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3334 [/* For disassembly only; pattern left blank */]> {
3335 let Inst{27-24} = 0b1110;
3336 let Inst{20} = direction;
3346 let Inst{15-12} = Rt;
3347 let Inst{11-8} = cop;
3348 let Inst{23-21} = opc1;
3349 let Inst{7-5} = opc2;
3350 let Inst{3-0} = CRm;
3351 let Inst{19-16} = CRn;
3354 def t2MCR2 : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */>;
3355 def t2MRC2 : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */>;
3357 class t2MovRRCopro<string opc, bit direction>
3358 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3359 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3360 [/* For disassembly only; pattern left blank */]> {
3361 let Inst{27-24} = 0b1100;
3362 let Inst{23-21} = 0b010;
3363 let Inst{20} = direction;
3371 let Inst{15-12} = Rt;
3372 let Inst{19-16} = Rt2;
3373 let Inst{11-8} = cop;
3374 let Inst{7-4} = opc1;
3375 let Inst{3-0} = CRm;
3378 def t2MCRR2 : t2MovRRCopro<"mcrr2",
3379 0 /* from ARM core register to coprocessor */>;
3380 def t2MRRC2 : t2MovRRCopro<"mrrc2",
3381 1 /* from coprocessor to ARM core register */>;
3383 //===----------------------------------------------------------------------===//
3384 // Other Coprocessor Instructions. For disassembly only.
3387 def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
3388 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3389 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3390 [/* For disassembly only; pattern left blank */]> {
3391 let Inst{27-24} = 0b1110;
3400 let Inst{3-0} = CRm;
3402 let Inst{7-5} = opc2;
3403 let Inst{11-8} = cop;
3404 let Inst{15-12} = CRd;
3405 let Inst{19-16} = CRn;
3406 let Inst{23-20} = opc1;