1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let PrintMethod = "printT2SOOperand";
30 let MIOperandInfo = (ops GPR, i32imm);
33 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
34 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
35 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
38 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
39 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
43 // t2_so_imm - Match a 32-bit immediate operand, which is an
44 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
45 // immediate splatted into multiple bytes of the word. t2_so_imm values are
46 // represented in the imm field in the same 12-bit form that they are encoded
47 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
48 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
49 def t2_so_imm : Operand<i32>,
51 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
54 // t2_so_imm_not - Match an immediate that is a complement
56 def t2_so_imm_not : Operand<i32>,
58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
59 }], t2_so_imm_not_XFORM>;
61 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
62 def t2_so_imm_neg : Operand<i32>,
64 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
65 }], t2_so_imm_neg_XFORM>;
67 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
68 def imm1_31 : PatLeaf<(i32 imm), [{
69 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
72 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
73 def imm0_4095 : PatLeaf<(i32 imm), [{
74 return (uint32_t)N->getZExtValue() < 4096;
77 def imm0_4095_neg : PatLeaf<(i32 imm), [{
78 return (uint32_t)(-N->getZExtValue()) < 4096;
81 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
83 def imm0_65535 : PatLeaf<(i32 imm), [{
84 return (uint32_t)N->getZExtValue() < 65536;
87 /// Split a 32-bit immediate into two 16 bit parts.
88 def t2_lo16 : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
93 def t2_hi16 : SDNodeXForm<imm, [{
94 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
97 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
98 // Returns true if all low 16-bits are 0.
99 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
103 // Define Thumb2 specific addressing modes.
105 // t2addrmode_imm12 := reg + imm12
106 def t2addrmode_imm12 : Operand<i32>,
107 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
108 let PrintMethod = "printT2AddrModeImm12Operand";
109 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
112 // t2addrmode_imm8 := reg - imm8
113 def t2addrmode_imm8 : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
115 let PrintMethod = "printT2AddrModeImm8Operand";
116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
119 def t2am_imm8_offset : Operand<i32>,
120 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
121 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
124 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
125 def t2addrmode_imm8s4 : Operand<i32>,
126 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
127 let PrintMethod = "printT2AddrModeImm8s4Operand";
128 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
131 // t2addrmode_so_reg := reg + (reg << imm2)
132 def t2addrmode_so_reg : Operand<i32>,
133 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
134 let PrintMethod = "printT2AddrModeSoRegOperand";
135 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
139 //===----------------------------------------------------------------------===//
140 // Multiclass helpers...
143 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
144 /// unary operation that produces a value. These are predicable and can be
145 /// changed to modify CPSR.
146 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
148 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
150 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
151 let isAsCheapAsAMove = Cheap;
152 let isReMaterializable = ReMat;
155 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
156 opc, ".w $dst, $src",
157 [(set GPR:$dst, (opnode GPR:$src))]>;
159 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
160 opc, ".w $dst, $src",
161 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
164 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
165 // binary operation that produces a value. These are predicable and can be
166 /// changed to modify CPSR.
167 multiclass T2I_bin_irs<string opc, PatFrag opnode,
168 bit Commutable = 0, string wide =""> {
170 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
171 opc, " $dst, $lhs, $rhs",
172 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
174 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
175 opc, !strconcat(wide, " $dst, $lhs, $rhs"),
176 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
177 let isCommutable = Commutable;
180 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
181 opc, !strconcat(wide, " $dst, $lhs, $rhs"),
182 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
185 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
186 // the ".w" prefix to indicate that they are wide.
187 multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> :
188 T2I_bin_irs<opc, opnode, Commutable, ".w">;
190 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
191 /// reversed. It doesn't define the 'rr' form since it's handled by its
192 /// T2I_bin_irs counterpart.
193 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
195 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
196 opc, ".w $dst, $rhs, $lhs",
197 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
199 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
200 opc, " $dst, $rhs, $lhs",
201 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
204 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
205 /// instruction modifies the CPSR register.
206 let Defs = [CPSR] in {
207 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
209 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
210 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
211 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
213 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
214 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
215 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
216 let isCommutable = Commutable;
219 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
220 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
221 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
225 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
226 /// patterns for a binary operation that produces a value.
227 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
229 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
230 opc, ".w $dst, $lhs, $rhs",
231 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
233 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
234 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
235 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
237 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
238 opc, ".w $dst, $lhs, $rhs",
239 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
240 let isCommutable = Commutable;
243 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
244 opc, ".w $dst, $lhs, $rhs",
245 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
248 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
249 /// binary operation that produces a value and use and define the carry bit.
250 /// It's not predicable.
251 let Uses = [CPSR] in {
252 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
254 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
255 opc, " $dst, $lhs, $rhs",
256 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
257 Requires<[IsThumb2, CarryDefIsUnused]>;
259 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
260 opc, ".w $dst, $lhs, $rhs",
261 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
262 Requires<[IsThumb2, CarryDefIsUnused]> {
263 let isCommutable = Commutable;
266 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
267 opc, ".w $dst, $lhs, $rhs",
268 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
269 Requires<[IsThumb2, CarryDefIsUnused]>;
270 // Carry setting variants
272 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
273 !strconcat(opc, "s $dst, $lhs, $rhs"),
274 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
275 Requires<[IsThumb2, CarryDefIsUsed]> {
279 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
280 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
281 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
282 Requires<[IsThumb2, CarryDefIsUsed]> {
284 let isCommutable = Commutable;
287 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
288 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
289 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
290 Requires<[IsThumb2, CarryDefIsUsed]> {
296 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
297 let Defs = [CPSR] in {
298 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
300 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
301 !strconcat(opc, "${s}.w $dst, $rhs, $lhs"),
302 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
304 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
305 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
306 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
310 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
311 // rotate operation that produces a value.
312 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
314 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
315 opc, ".w $dst, $lhs, $rhs",
316 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
318 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
319 opc, ".w $dst, $lhs, $rhs",
320 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
323 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
324 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
325 /// a explicit result, only implicitly set CPSR.
326 let Defs = [CPSR] in {
327 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
329 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
330 opc, ".w $lhs, $rhs",
331 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
333 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
334 opc, ".w $lhs, $rhs",
335 [(opnode GPR:$lhs, GPR:$rhs)]>;
337 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
338 opc, ".w $lhs, $rhs",
339 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
343 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
344 multiclass T2I_ld<string opc, PatFrag opnode> {
345 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
346 opc, ".w $dst, $addr",
347 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
348 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
350 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
351 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
352 opc, ".w $dst, $addr",
353 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
354 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
355 opc, ".w $dst, $addr",
356 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
359 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
360 multiclass T2I_st<string opc, PatFrag opnode> {
361 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
362 opc, ".w $src, $addr",
363 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
364 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
366 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
367 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
368 opc, ".w $src, $addr",
369 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
372 /// T2I_picld - Defines the PIC load pattern.
373 class T2I_picld<string opc, PatFrag opnode> :
374 T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
375 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
376 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
378 /// T2I_picst - Defines the PIC store pattern.
379 class T2I_picst<string opc, PatFrag opnode> :
380 T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
381 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
382 [(opnode GPR:$src, addrmodepc:$addr)]>;
385 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
386 /// register and one whose operand is a register rotated by 8/16/24.
387 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
388 def r : T2I<(outs GPR:$dst), (ins GPR:$Src),
389 opc, ".w $dst, $Src",
390 [(set GPR:$dst, (opnode GPR:$Src))]>;
391 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
392 opc, ".w $dst, $Src, ror $rot",
393 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
396 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
397 /// register and one whose operand is a register rotated by 8/16/24.
398 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
399 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
400 opc, " $dst, $LHS, $RHS",
401 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
402 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
403 opc, " $dst, $LHS, $RHS, ror $rot",
404 [(set GPR:$dst, (opnode GPR:$LHS,
405 (rotr GPR:$RHS, rot_imm:$rot)))]>;
408 //===----------------------------------------------------------------------===//
410 //===----------------------------------------------------------------------===//
412 //===----------------------------------------------------------------------===//
413 // Miscellaneous Instructions.
416 let isNotDuplicable = 1 in
417 def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
418 "$cp:\n\tadd.w $dst, $lhs, pc",
419 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
422 // LEApcrel - Load a pc-relative address into a register without offending the
424 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
425 "adr$p.w $dst, #$label", []>;
427 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
428 (ins i32imm:$label, i32imm:$id, pred:$p),
429 "adr$p.w $dst, #${label}_${id:no_hash}", []>;
431 //===----------------------------------------------------------------------===//
432 // Load / store Instructions.
436 let canFoldAsLoad = 1 in
437 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
439 // Loads with zero extension
440 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
441 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
443 // Loads with sign extension
444 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
445 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
449 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
450 "ldrd", " $dst, $addr", []>;
451 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
452 "ldrd", " $dst, $addr", []>;
455 // zextload i1 -> zextload i8
456 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
457 (t2LDRBi12 t2addrmode_imm12:$addr)>;
458 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
459 (t2LDRBi8 t2addrmode_imm8:$addr)>;
460 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
461 (t2LDRBs t2addrmode_so_reg:$addr)>;
462 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
463 (t2LDRBpci tconstpool:$addr)>;
465 // extload -> zextload
466 // FIXME: Reduce the number of patterns by legalizing extload to zextload
468 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
469 (t2LDRBi12 t2addrmode_imm12:$addr)>;
470 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
471 (t2LDRBi8 t2addrmode_imm8:$addr)>;
472 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
473 (t2LDRBs t2addrmode_so_reg:$addr)>;
474 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
475 (t2LDRBpci tconstpool:$addr)>;
477 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
478 (t2LDRBi12 t2addrmode_imm12:$addr)>;
479 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
480 (t2LDRBi8 t2addrmode_imm8:$addr)>;
481 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
482 (t2LDRBs t2addrmode_so_reg:$addr)>;
483 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
484 (t2LDRBpci tconstpool:$addr)>;
486 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
487 (t2LDRHi12 t2addrmode_imm12:$addr)>;
488 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
489 (t2LDRHi8 t2addrmode_imm8:$addr)>;
490 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
491 (t2LDRHs t2addrmode_so_reg:$addr)>;
492 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
493 (t2LDRHpci tconstpool:$addr)>;
497 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
498 (ins t2addrmode_imm8:$addr),
499 AddrModeT2_i8, IndexModePre,
500 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
503 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
504 (ins GPR:$base, t2am_imm8_offset:$offset),
505 AddrModeT2_i8, IndexModePost,
506 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
509 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
510 (ins t2addrmode_imm8:$addr),
511 AddrModeT2_i8, IndexModePre,
512 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
514 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
515 (ins GPR:$base, t2am_imm8_offset:$offset),
516 AddrModeT2_i8, IndexModePost,
517 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
520 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
521 (ins t2addrmode_imm8:$addr),
522 AddrModeT2_i8, IndexModePre,
523 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
525 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
526 (ins GPR:$base, t2am_imm8_offset:$offset),
527 AddrModeT2_i8, IndexModePost,
528 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
531 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
532 (ins t2addrmode_imm8:$addr),
533 AddrModeT2_i8, IndexModePre,
534 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
536 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
537 (ins GPR:$base, t2am_imm8_offset:$offset),
538 AddrModeT2_i8, IndexModePost,
539 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
542 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
543 (ins t2addrmode_imm8:$addr),
544 AddrModeT2_i8, IndexModePre,
545 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
547 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
548 (ins GPR:$base, t2am_imm8_offset:$offset),
549 AddrModeT2_i8, IndexModePost,
550 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
555 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
556 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
557 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
561 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
562 "strd", " $src, $addr", []>;
565 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
566 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
567 AddrModeT2_i8, IndexModePre,
568 "str", " $src, [$base, $offset]!", "$base = $base_wb",
570 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
572 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
573 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
574 AddrModeT2_i8, IndexModePost,
575 "str", " $src, [$base], $offset", "$base = $base_wb",
577 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
579 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
580 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
581 AddrModeT2_i8, IndexModePre,
582 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
584 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
586 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
587 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
588 AddrModeT2_i8, IndexModePost,
589 "strh", " $src, [$base], $offset", "$base = $base_wb",
591 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
593 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
594 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
595 AddrModeT2_i8, IndexModePre,
596 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
598 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
600 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
601 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
602 AddrModeT2_i8, IndexModePost,
603 "strb", " $src, [$base], $offset", "$base = $base_wb",
605 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
608 // FIXME: ldrd / strd pre / post variants
610 //===----------------------------------------------------------------------===//
611 // Load / store multiple Instructions.
615 def t2LDM : T2XI<(outs),
616 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
617 "ldm${addr:submode}${p}.w $addr, $dst1", []>;
620 def t2STM : T2XI<(outs),
621 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
622 "stm${addr:submode}${p}.w $addr, $src1", []>;
624 //===----------------------------------------------------------------------===//
625 // Move Instructions.
628 let neverHasSideEffects = 1 in
629 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
630 "mov", ".w $dst, $src", []>;
632 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
633 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
634 "mov", ".w $dst, $src",
635 [(set GPR:$dst, t2_so_imm:$src)]>;
637 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
638 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
639 "movw", " $dst, $src",
640 [(set GPR:$dst, imm0_65535:$src)]>;
642 // FIXME: Also available in ARM mode.
643 let Constraints = "$src = $dst" in
644 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
645 "movt", " $dst, $imm",
647 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
649 //===----------------------------------------------------------------------===//
650 // Extend Instructions.
655 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
656 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
658 defm t2SXTAB : T2I_bin_rrot<"sxtab",
659 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
660 defm t2SXTAH : T2I_bin_rrot<"sxtah",
661 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
663 // TODO: SXT(A){B|H}16
667 let AddedComplexity = 16 in {
668 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
669 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
670 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
672 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
673 (t2UXTB16r_rot GPR:$Src, 24)>;
674 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
675 (t2UXTB16r_rot GPR:$Src, 8)>;
677 defm t2UXTAB : T2I_bin_rrot<"uxtab",
678 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
679 defm t2UXTAH : T2I_bin_rrot<"uxtah",
680 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
683 //===----------------------------------------------------------------------===//
684 // Arithmetic Instructions.
687 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
688 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
690 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
691 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
692 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
694 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
695 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
698 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
699 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
701 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
702 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
703 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
704 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
705 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
708 //===----------------------------------------------------------------------===//
709 // Shift and rotate Instructions.
712 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
713 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
714 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
715 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
717 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
718 "mov", " $dst, $src, rrx",
719 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
721 //===----------------------------------------------------------------------===//
722 // Bitwise Instructions.
725 defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
726 defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
727 defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
729 defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
731 let Constraints = "$src = $dst" in
732 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
733 "bfc", " $dst, $imm",
734 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
736 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
738 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
740 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
741 let AddedComplexity = 1 in
742 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
745 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
746 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
748 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
749 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
751 def : T2Pat<(t2_so_imm_not:$src),
752 (t2MVNi t2_so_imm_not:$src)>;
754 //===----------------------------------------------------------------------===//
755 // Multiply Instructions.
757 let isCommutable = 1 in
758 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
759 "mul", " $dst, $a, $b",
760 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
762 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
763 "mla", " $dst, $a, $b, $c",
764 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
766 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
767 "mls", " $dst, $a, $b, $c",
768 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
770 // Extra precision multiplies with low / high results
771 let neverHasSideEffects = 1 in {
772 let isCommutable = 1 in {
773 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
774 "smull", " $ldst, $hdst, $a, $b", []>;
776 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
777 "umull", " $ldst, $hdst, $a, $b", []>;
780 // Multiply + accumulate
781 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
782 "smlal", " $ldst, $hdst, $a, $b", []>;
784 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
785 "umlal", " $ldst, $hdst, $a, $b", []>;
787 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
788 "umaal", " $ldst, $hdst, $a, $b", []>;
789 } // neverHasSideEffects
791 // Most significant word multiply
792 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
793 "smmul", " $dst, $a, $b",
794 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
796 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
797 "smmla", " $dst, $a, $b, $c",
798 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
801 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
802 "smmls", " $dst, $a, $b, $c",
803 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
805 multiclass T2I_smul<string opc, PatFrag opnode> {
806 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
807 !strconcat(opc, "bb"), " $dst, $a, $b",
808 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
809 (sext_inreg GPR:$b, i16)))]>;
811 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
812 !strconcat(opc, "bt"), " $dst, $a, $b",
813 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
814 (sra GPR:$b, (i32 16))))]>;
816 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
817 !strconcat(opc, "tb"), " $dst, $a, $b",
818 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
819 (sext_inreg GPR:$b, i16)))]>;
821 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
822 !strconcat(opc, "tt"), " $dst, $a, $b",
823 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
824 (sra GPR:$b, (i32 16))))]>;
826 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
827 !strconcat(opc, "wb"), " $dst, $a, $b",
828 [(set GPR:$dst, (sra (opnode GPR:$a,
829 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
831 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
832 !strconcat(opc, "wt"), " $dst, $a, $b",
833 [(set GPR:$dst, (sra (opnode GPR:$a,
834 (sra GPR:$b, (i32 16))), (i32 16)))]>;
838 multiclass T2I_smla<string opc, PatFrag opnode> {
839 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
840 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
841 [(set GPR:$dst, (add GPR:$acc,
842 (opnode (sext_inreg GPR:$a, i16),
843 (sext_inreg GPR:$b, i16))))]>;
845 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
846 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
847 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
848 (sra GPR:$b, (i32 16)))))]>;
850 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
851 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
852 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
853 (sext_inreg GPR:$b, i16))))]>;
855 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
856 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
857 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
858 (sra GPR:$b, (i32 16)))))]>;
860 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
861 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
862 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
863 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
865 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
866 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
867 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
868 (sra GPR:$b, (i32 16))), (i32 16))))]>;
871 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
872 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
874 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
875 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
878 //===----------------------------------------------------------------------===//
879 // Misc. Arithmetic Instructions.
882 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
883 "clz", " $dst, $src",
884 [(set GPR:$dst, (ctlz GPR:$src))]>;
886 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
887 "rev", ".w $dst, $src",
888 [(set GPR:$dst, (bswap GPR:$src))]>;
890 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
891 "rev16", ".w $dst, $src",
893 (or (and (srl GPR:$src, (i32 8)), 0xFF),
894 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
895 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
896 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
898 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
899 "revsh", ".w $dst, $src",
902 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
903 (shl GPR:$src, (i32 8))), i16))]>;
905 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
906 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
907 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
908 (and (shl GPR:$src2, (i32 imm:$shamt)),
911 // Alternate cases for PKHBT where identities eliminate some nodes.
912 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
913 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
914 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
915 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
917 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
918 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
919 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
920 (and (sra GPR:$src2, imm16_31:$shamt),
923 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
924 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
925 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
926 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
927 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
928 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
929 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
931 //===----------------------------------------------------------------------===//
932 // Comparison Instructions...
935 defm t2CMP : T2I_cmp_is<"cmp",
936 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
937 defm t2CMPz : T2I_cmp_is<"cmp",
938 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
940 defm t2CMN : T2I_cmp_is<"cmn",
941 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
942 defm t2CMNz : T2I_cmp_is<"cmn",
943 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
945 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
946 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
948 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
949 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
951 defm t2TST : T2I_cmp_is<"tst",
952 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
953 defm t2TEQ : T2I_cmp_is<"teq",
954 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
956 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
957 // Short range conditional branch. Looks awesome for loops. Need to figure
958 // out how to use this one.
962 // FIXME: should be able to write a pattern for ARMcmov, but can't use
963 // a two-value operand where a dag node expects two operands. :(
964 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
965 "mov", " $dst, $true",
966 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
967 RegConstraint<"$false = $dst">;
969 def t2MOVCCs : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_reg:$true),
970 "mov", " $dst, $true",
971 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
972 RegConstraint<"$false = $dst">;
974 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
975 "mov", " $dst, $true",
976 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
977 RegConstraint<"$false = $dst">;
979 //===----------------------------------------------------------------------===//
983 // __aeabi_read_tp preserves the registers r1-r3.
985 Defs = [R0, R12, LR, CPSR] in {
986 def t2TPsoft : T2XI<(outs), (ins),
987 "bl __aeabi_read_tp",
988 [(set R0, ARMthread_pointer)]>;
991 //===----------------------------------------------------------------------===//
992 // Control-Flow Instructions
995 // FIXME: remove when we have a way to marking a MI with these properties.
996 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
998 // FIXME: Should pc be an implicit operand like PICADD, etc?
999 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
1000 def t2LDM_RET : T2XI<(outs),
1001 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
1002 "ldm${addr:submode}${p} $addr, $dst1",
1005 // On non-Darwin platforms R9 is callee-saved.
1007 Defs = [R0, R1, R2, R3, R12, LR,
1008 D0, D1, D2, D3, D4, D5, D6, D7,
1009 D16, D17, D18, D19, D20, D21, D22, D23,
1010 D24, D25, D26, D27, D28, D29, D31, D31, CPSR] in {
1011 def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
1013 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
1015 def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
1017 [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
1020 // On Darwin R9 is call-clobbered.
1022 Defs = [R0, R1, R2, R3, R9, R12, LR,
1023 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1024 def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
1026 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
1028 def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
1030 [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
1033 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1034 let isPredicable = 1 in
1035 def t2B : T2XI<(outs), (ins brtarget:$target),
1039 let isNotDuplicable = 1, isIndirectBranch = 1 in
1042 (ins GPR:$base, GPR:$idx, jt2block_operand:$jt, i32imm:$id),
1043 "add.w pc, $base, $idx, lsl #2\n$jt",
1044 [(ARMbr2jt GPR:$base, GPR:$idx, tjumptable:$jt, imm:$id)]>;
1045 } // isBranch, isTerminator, isBarrier
1047 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1048 // a two-value operand where a dag node expects two operands. :(
1049 let isBranch = 1, isTerminator = 1 in
1050 def t2Bcc : T2I<(outs), (ins brtarget:$target),
1052 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1056 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1057 AddrModeNone, Size2Bytes,
1058 "it$mask $cc", "", []>;
1060 //===----------------------------------------------------------------------===//
1061 // Non-Instruction Patterns
1064 // ConstantPool, GlobalAddress, and JumpTable
1065 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1066 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1067 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1068 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1070 // Large immediate handling.
1072 def : T2Pat<(i32 imm:$src),
1073 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;