1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
53 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
92 def imm1_31 : PatLeaf<(i32 imm), [{
93 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
96 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
97 def imm0_4095 : Operand<i32>,
99 return (uint32_t)N->getZExtValue() < 4096;
102 def imm0_4095_neg : PatLeaf<(i32 imm), [{
103 return (uint32_t)(-N->getZExtValue()) < 4096;
106 def imm0_255_neg : PatLeaf<(i32 imm), [{
107 return (uint32_t)(-N->getZExtValue()) < 255;
110 // Define Thumb2 specific addressing modes.
112 // t2addrmode_imm12 := reg + imm12
113 def t2addrmode_imm12 : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
115 let PrintMethod = "printT2AddrModeImm12Operand";
116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
119 // t2addrmode_imm8 := reg - imm8
120 def t2addrmode_imm8 : Operand<i32>,
121 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
122 let PrintMethod = "printT2AddrModeImm8Operand";
123 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
126 def t2am_imm8_offset : Operand<i32>,
127 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
128 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
131 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
132 def t2addrmode_imm8s4 : Operand<i32>,
133 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
134 let PrintMethod = "printT2AddrModeImm8s4Operand";
135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
138 // t2addrmode_so_reg := reg + (reg << imm2)
139 def t2addrmode_so_reg : Operand<i32>,
140 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
141 let PrintMethod = "printT2AddrModeSoRegOperand";
142 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
146 //===----------------------------------------------------------------------===//
147 // Multiclass helpers...
150 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
151 /// unary operation that produces a value. These are predicable and can be
152 /// changed to modify CPSR.
153 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
155 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
157 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
158 let isAsCheapAsAMove = Cheap;
159 let isReMaterializable = ReMat;
162 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
163 opc, ".w\t$dst, $src",
164 [(set GPR:$dst, (opnode GPR:$src))]>;
166 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
167 opc, ".w\t$dst, $src",
168 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
171 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
172 // binary operation that produces a value. These are predicable and can be
173 /// changed to modify CPSR.
174 multiclass T2I_bin_irs<string opc, PatFrag opnode,
175 bit Commutable = 0, string wide =""> {
177 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
178 opc, "\t$dst, $lhs, $rhs",
179 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
181 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
182 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
183 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
184 let isCommutable = Commutable;
187 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
188 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
189 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
192 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
193 // the ".w" prefix to indicate that they are wide.
194 multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> :
195 T2I_bin_irs<opc, opnode, Commutable, ".w">;
197 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
198 /// reversed. It doesn't define the 'rr' form since it's handled by its
199 /// T2I_bin_irs counterpart.
200 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
202 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
203 opc, ".w\t$dst, $rhs, $lhs",
204 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
206 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
207 opc, "\t$dst, $rhs, $lhs",
208 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
211 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
212 /// instruction modifies the CPSR register.
213 let Defs = [CPSR] in {
214 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
216 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
217 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
218 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
220 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
221 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
222 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
223 let isCommutable = Commutable;
226 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
227 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
228 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
232 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
233 /// patterns for a binary operation that produces a value.
234 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
236 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
237 opc, ".w\t$dst, $lhs, $rhs",
238 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
240 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
241 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
242 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
244 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
245 opc, ".w\t$dst, $lhs, $rhs",
246 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
247 let isCommutable = Commutable;
250 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
251 opc, ".w\t$dst, $lhs, $rhs",
252 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
255 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
256 /// binary operation that produces a value and use and define the carry bit.
257 /// It's not predicable.
258 let Uses = [CPSR] in {
259 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
261 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
262 opc, "\t$dst, $lhs, $rhs",
263 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
264 Requires<[IsThumb2, CarryDefIsUnused]>;
266 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
267 opc, ".w\t$dst, $lhs, $rhs",
268 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
269 Requires<[IsThumb2, CarryDefIsUnused]> {
270 let isCommutable = Commutable;
273 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
274 opc, ".w\t$dst, $lhs, $rhs",
275 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
276 Requires<[IsThumb2, CarryDefIsUnused]>;
277 // Carry setting variants
279 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
280 !strconcat(opc, "s\t$dst, $lhs, $rhs"),
281 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
282 Requires<[IsThumb2, CarryDefIsUsed]> {
286 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
287 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
288 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
289 Requires<[IsThumb2, CarryDefIsUsed]> {
291 let isCommutable = Commutable;
294 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
295 !strconcat(opc, "s.w\t$dst, $lhs, $rhs"),
296 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
297 Requires<[IsThumb2, CarryDefIsUsed]> {
303 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
304 let Defs = [CPSR] in {
305 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
307 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
309 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"),
310 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
312 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
314 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"),
315 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
319 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
320 // rotate operation that produces a value.
321 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
324 opc, ".w\t$dst, $lhs, $rhs",
325 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
327 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
328 opc, ".w\t$dst, $lhs, $rhs",
329 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
332 /// T2I_cmp_is - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
333 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
334 /// a explicit result, only implicitly set CPSR.
335 let Defs = [CPSR] in {
336 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
338 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
339 opc, ".w\t$lhs, $rhs",
340 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
342 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
343 opc, ".w\t$lhs, $rhs",
344 [(opnode GPR:$lhs, GPR:$rhs)]>;
346 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
347 opc, ".w\t$lhs, $rhs",
348 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
352 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
353 multiclass T2I_ld<string opc, PatFrag opnode> {
354 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
355 opc, ".w\t$dst, $addr",
356 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
357 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
358 opc, "\t$dst, $addr",
359 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
360 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
361 opc, ".w\t$dst, $addr",
362 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
363 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
364 opc, ".w\t$dst, $addr",
365 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
368 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
369 multiclass T2I_st<string opc, PatFrag opnode> {
370 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
371 opc, ".w\t$src, $addr",
372 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
373 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
374 opc, "\t$src, $addr",
375 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
376 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
377 opc, ".w\t$src, $addr",
378 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
381 /// T2I_picld - Defines the PIC load pattern.
382 class T2I_picld<string opc, PatFrag opnode> :
383 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi,
384 !strconcat("\n${addr:label}:\n\t", opc), "\t$dst, $addr",
385 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
387 /// T2I_picst - Defines the PIC store pattern.
388 class T2I_picst<string opc, PatFrag opnode> :
389 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer,
390 !strconcat("\n${addr:label}:\n\t", opc), "\t$src, $addr",
391 [(opnode GPR:$src, addrmodepc:$addr)]>;
394 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
395 /// register and one whose operand is a register rotated by 8/16/24.
396 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
397 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
398 opc, ".w\t$dst, $src",
399 [(set GPR:$dst, (opnode GPR:$src))]>;
400 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
401 opc, ".w\t$dst, $src, ror $rot",
402 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>;
405 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
406 /// register and one whose operand is a register rotated by 8/16/24.
407 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
408 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
409 opc, "\t$dst, $LHS, $RHS",
410 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
411 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
412 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
413 [(set GPR:$dst, (opnode GPR:$LHS,
414 (rotr GPR:$RHS, rot_imm:$rot)))]>;
417 //===----------------------------------------------------------------------===//
419 //===----------------------------------------------------------------------===//
421 //===----------------------------------------------------------------------===//
422 // Miscellaneous Instructions.
425 // LEApcrel - Load a pc-relative address into a register without offending the
427 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
428 "adr$p.w\t$dst, #$label", []>;
430 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
431 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
432 "adr$p.w\t$dst, #${label}_${id}", []>;
434 // ADD r, sp, {so_imm|i12}
435 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
436 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []>;
437 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
438 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []>;
441 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
442 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []>;
444 // SUB r, sp, {so_imm|i12}
445 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
446 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []>;
447 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
448 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []>;
451 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
453 "sub", "\t$dst, $sp, $rhs", []>;
456 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
457 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
458 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
459 NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
460 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
461 NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
462 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
463 NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
464 } // usesCustomDAGSchedInserter
467 //===----------------------------------------------------------------------===//
468 // Load / store Instructions.
472 let canFoldAsLoad = 1 in
473 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
475 // Loads with zero extension
476 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
477 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
479 // Loads with sign extension
480 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
481 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
483 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
485 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
486 (ins t2addrmode_imm8s4:$addr),
487 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
488 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
489 (ins i32imm:$addr), IIC_iLoadi,
490 "ldrd", "\t$dst1, $addr", []>;
493 // zextload i1 -> zextload i8
494 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
495 (t2LDRBi12 t2addrmode_imm12:$addr)>;
496 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
497 (t2LDRBi8 t2addrmode_imm8:$addr)>;
498 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
499 (t2LDRBs t2addrmode_so_reg:$addr)>;
500 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
501 (t2LDRBpci tconstpool:$addr)>;
503 // extload -> zextload
504 // FIXME: Reduce the number of patterns by legalizing extload to zextload
506 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
507 (t2LDRBi12 t2addrmode_imm12:$addr)>;
508 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
509 (t2LDRBi8 t2addrmode_imm8:$addr)>;
510 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
511 (t2LDRBs t2addrmode_so_reg:$addr)>;
512 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
513 (t2LDRBpci tconstpool:$addr)>;
515 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
516 (t2LDRBi12 t2addrmode_imm12:$addr)>;
517 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
518 (t2LDRBi8 t2addrmode_imm8:$addr)>;
519 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
520 (t2LDRBs t2addrmode_so_reg:$addr)>;
521 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
522 (t2LDRBpci tconstpool:$addr)>;
524 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
525 (t2LDRHi12 t2addrmode_imm12:$addr)>;
526 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
527 (t2LDRHi8 t2addrmode_imm8:$addr)>;
528 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
529 (t2LDRHs t2addrmode_so_reg:$addr)>;
530 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
531 (t2LDRHpci tconstpool:$addr)>;
535 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
536 (ins t2addrmode_imm8:$addr),
537 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
538 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
541 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
542 (ins GPR:$base, t2am_imm8_offset:$offset),
543 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
544 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
547 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
548 (ins t2addrmode_imm8:$addr),
549 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
550 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
552 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
553 (ins GPR:$base, t2am_imm8_offset:$offset),
554 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
555 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
558 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
559 (ins t2addrmode_imm8:$addr),
560 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
561 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
563 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
564 (ins GPR:$base, t2am_imm8_offset:$offset),
565 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
566 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
569 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
570 (ins t2addrmode_imm8:$addr),
571 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
572 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
574 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
575 (ins GPR:$base, t2am_imm8_offset:$offset),
576 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
577 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
580 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
581 (ins t2addrmode_imm8:$addr),
582 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
583 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
585 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
586 (ins GPR:$base, t2am_imm8_offset:$offset),
587 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
588 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
593 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
594 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
595 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
598 let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
599 def t2STRDi8 : T2Ii8s4<(outs),
600 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
601 IIC_iStorer, "strd", "\t$src1, $addr", []>;
604 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
605 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
606 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
607 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
609 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
611 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
612 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
613 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
614 "str", "\t$src, [$base], $offset", "$base = $base_wb",
616 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
618 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
619 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
620 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
621 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
623 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
625 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
626 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
627 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
628 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
630 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
632 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
633 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
634 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
635 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
637 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
639 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
640 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
641 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
642 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
644 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
647 // FIXME: ldrd / strd pre / post variants
649 //===----------------------------------------------------------------------===//
650 // Load / store multiple Instructions.
653 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
654 def t2LDM : T2XI<(outs),
655 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
656 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []>;
658 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
659 def t2STM : T2XI<(outs),
660 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
661 IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []>;
663 //===----------------------------------------------------------------------===//
664 // Move Instructions.
667 let neverHasSideEffects = 1 in
668 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
669 "mov", ".w\t$dst, $src", []>;
671 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
672 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
673 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
674 "mov", ".w\t$dst, $src",
675 [(set GPR:$dst, t2_so_imm:$src)]>;
677 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
678 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
679 "movw", "\t$dst, $src",
680 [(set GPR:$dst, imm0_65535:$src)]>;
682 let Constraints = "$src = $dst" in
683 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
684 "movt", "\t$dst, $imm",
686 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]>;
688 def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
690 //===----------------------------------------------------------------------===//
691 // Extend Instructions.
696 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
697 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
699 defm t2SXTAB : T2I_bin_rrot<"sxtab",
700 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
701 defm t2SXTAH : T2I_bin_rrot<"sxtah",
702 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
704 // TODO: SXT(A){B|H}16
708 let AddedComplexity = 16 in {
709 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
710 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
711 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
713 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
714 (t2UXTB16r_rot GPR:$Src, 24)>;
715 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
716 (t2UXTB16r_rot GPR:$Src, 8)>;
718 defm t2UXTAB : T2I_bin_rrot<"uxtab",
719 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
720 defm t2UXTAH : T2I_bin_rrot<"uxtah",
721 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
724 //===----------------------------------------------------------------------===//
725 // Arithmetic Instructions.
728 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
729 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
731 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
732 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
733 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
735 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
736 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
739 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
740 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
742 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
743 let AddedComplexity = 1 in
744 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
745 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
746 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
747 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
748 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
749 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
752 //===----------------------------------------------------------------------===//
753 // Shift and rotate Instructions.
756 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
757 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
758 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
759 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
761 let Uses = [CPSR] in {
762 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
763 "rrx", "\t$dst, $src",
764 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
767 let Defs = [CPSR] in {
768 def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
769 "lsrs.w\t$dst, $src, #1",
770 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
771 def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
772 "asrs.w\t$dst, $src, #1",
773 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
776 //===----------------------------------------------------------------------===//
777 // Bitwise Instructions.
780 defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
781 defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
782 defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
784 defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
786 let Constraints = "$src = $dst" in
787 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
788 IIC_iALUi, "bfc", "\t$dst, $imm",
789 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
791 def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
792 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []>;
794 def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
795 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []>;
797 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
799 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
801 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
802 let AddedComplexity = 1 in
803 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
806 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
807 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
809 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
810 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
811 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
812 Requires<[IsThumb2]>;
814 def : T2Pat<(t2_so_imm_not:$src),
815 (t2MVNi t2_so_imm_not:$src)>;
817 //===----------------------------------------------------------------------===//
818 // Multiply Instructions.
820 let isCommutable = 1 in
821 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
822 "mul", "\t$dst, $a, $b",
823 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
825 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
826 "mla", "\t$dst, $a, $b, $c",
827 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
829 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
830 "mls", "\t$dst, $a, $b, $c",
831 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
833 // Extra precision multiplies with low / high results
834 let neverHasSideEffects = 1 in {
835 let isCommutable = 1 in {
836 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
837 "smull", "\t$ldst, $hdst, $a, $b", []>;
839 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
840 "umull", "\t$ldst, $hdst, $a, $b", []>;
843 // Multiply + accumulate
844 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
845 "smlal", "\t$ldst, $hdst, $a, $b", []>;
847 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
848 "umlal", "\t$ldst, $hdst, $a, $b", []>;
850 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
851 "umaal", "\t$ldst, $hdst, $a, $b", []>;
852 } // neverHasSideEffects
854 // Most significant word multiply
855 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
856 "smmul", "\t$dst, $a, $b",
857 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
859 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
860 "smmla", "\t$dst, $a, $b, $c",
861 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
864 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
865 "smmls", "\t$dst, $a, $b, $c",
866 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
868 multiclass T2I_smul<string opc, PatFrag opnode> {
869 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
870 !strconcat(opc, "bb"), "\t$dst, $a, $b",
871 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
872 (sext_inreg GPR:$b, i16)))]>;
874 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
875 !strconcat(opc, "bt"), "\t$dst, $a, $b",
876 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
877 (sra GPR:$b, (i32 16))))]>;
879 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
880 !strconcat(opc, "tb"), "\t$dst, $a, $b",
881 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
882 (sext_inreg GPR:$b, i16)))]>;
884 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
885 !strconcat(opc, "tt"), "\t$dst, $a, $b",
886 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
887 (sra GPR:$b, (i32 16))))]>;
889 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
890 !strconcat(opc, "wb"), "\t$dst, $a, $b",
891 [(set GPR:$dst, (sra (opnode GPR:$a,
892 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
894 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
895 !strconcat(opc, "wt"), "\t$dst, $a, $b",
896 [(set GPR:$dst, (sra (opnode GPR:$a,
897 (sra GPR:$b, (i32 16))), (i32 16)))]>;
901 multiclass T2I_smla<string opc, PatFrag opnode> {
902 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
903 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
904 [(set GPR:$dst, (add GPR:$acc,
905 (opnode (sext_inreg GPR:$a, i16),
906 (sext_inreg GPR:$b, i16))))]>;
908 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
909 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
910 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
911 (sra GPR:$b, (i32 16)))))]>;
913 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
914 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
915 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
916 (sext_inreg GPR:$b, i16))))]>;
918 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
919 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
920 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
921 (sra GPR:$b, (i32 16)))))]>;
923 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
924 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
925 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
926 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
928 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
929 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
930 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
931 (sra GPR:$b, (i32 16))), (i32 16))))]>;
934 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
935 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
937 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
938 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
941 //===----------------------------------------------------------------------===//
942 // Misc. Arithmetic Instructions.
945 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
946 "clz", "\t$dst, $src",
947 [(set GPR:$dst, (ctlz GPR:$src))]>;
949 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
950 "rev", ".w\t$dst, $src",
951 [(set GPR:$dst, (bswap GPR:$src))]>;
953 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
954 "rev16", ".w\t$dst, $src",
956 (or (and (srl GPR:$src, (i32 8)), 0xFF),
957 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
958 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
959 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
961 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
962 "revsh", ".w\t$dst, $src",
965 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
966 (shl GPR:$src, (i32 8))), i16))]>;
968 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
969 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
970 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
971 (and (shl GPR:$src2, (i32 imm:$shamt)),
974 // Alternate cases for PKHBT where identities eliminate some nodes.
975 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
976 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
977 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
978 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
980 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
981 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
982 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
983 (and (sra GPR:$src2, imm16_31:$shamt),
986 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
987 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
988 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
989 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
990 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
991 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
992 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
994 //===----------------------------------------------------------------------===//
995 // Comparison Instructions...
998 defm t2CMP : T2I_cmp_is<"cmp",
999 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1000 defm t2CMPz : T2I_cmp_is<"cmp",
1001 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1003 defm t2CMN : T2I_cmp_is<"cmn",
1004 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1005 defm t2CMNz : T2I_cmp_is<"cmn",
1006 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1008 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1009 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1011 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1012 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1014 defm t2TST : T2I_cmp_is<"tst",
1015 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1016 defm t2TEQ : T2I_cmp_is<"teq",
1017 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1019 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1020 // Short range conditional branch. Looks awesome for loops. Need to figure
1021 // out how to use this one.
1024 // Conditional moves
1025 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1026 // a two-value operand where a dag node expects two operands. :(
1027 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
1028 "mov", ".w\t$dst, $true",
1029 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1030 RegConstraint<"$false = $dst">;
1032 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1033 IIC_iCMOVi, "mov", ".w\t$dst, $true",
1034 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1035 RegConstraint<"$false = $dst">;
1037 def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1038 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
1039 RegConstraint<"$false = $dst">;
1040 def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1041 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
1042 RegConstraint<"$false = $dst">;
1043 def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1044 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
1045 RegConstraint<"$false = $dst">;
1046 def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1047 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
1048 RegConstraint<"$false = $dst">;
1050 //===----------------------------------------------------------------------===//
1054 // __aeabi_read_tp preserves the registers r1-r3.
1056 Defs = [R0, R12, LR, CPSR] in {
1057 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
1058 "bl\t__aeabi_read_tp",
1059 [(set R0, ARMthread_pointer)]>;
1062 //===----------------------------------------------------------------------===//
1063 // SJLJ Exception handling intrinsics
1064 // eh_sjlj_setjmp() is an instruction sequence to store the return
1065 // address and save #0 in R0 for the non-longjmp case.
1066 // Since by its nature we may be coming from some other function to get
1067 // here, and we're using the stack frame for the containing function to
1068 // save/restore registers, we can't keep anything live in regs across
1069 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1070 // when we get here from a longjmp(). We force everthing out of registers
1071 // except for our own input by listing the relevant registers in Defs. By
1072 // doing so, we also cause the prologue/epilogue code to actively preserve
1073 // all of the callee-saved resgisters, which is exactly what we want.
1075 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1076 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1077 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1079 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src),
1080 AddrModeNone, SizeSpecial, NoItinerary,
1081 "str.w\tsp, [$src, #+8] @ eh_setjmp begin\n"
1084 "\tstr.w\tr12, [$src, #+4]\n"
1087 "0:\tmovs\tr0, #1 @ eh_setjmp end\n"
1089 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1094 //===----------------------------------------------------------------------===//
1095 // Control-Flow Instructions
1098 // FIXME: remove when we have a way to marking a MI with these properties.
1099 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1101 // FIXME: Should pc be an implicit operand like PICADD, etc?
1102 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1103 hasExtraDefRegAllocReq = 1 in
1104 def t2LDM_RET : T2XI<(outs),
1105 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1106 IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb",
1109 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1110 let isPredicable = 1 in
1111 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
1115 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1118 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
1119 IIC_Br, "mov\tpc, $target\n$jt",
1120 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
1122 // FIXME: Add a non-pc based case that can be predicated.
1125 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1126 IIC_Br, "tbb\t$index\n$jt", []>;
1130 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1131 IIC_Br, "tbh\t$index\n$jt", []>;
1132 } // isNotDuplicable, isIndirectBranch
1134 } // isBranch, isTerminator, isBarrier
1136 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1137 // a two-value operand where a dag node expects two operands. :(
1138 let isBranch = 1, isTerminator = 1 in
1139 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
1141 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1145 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1146 AddrModeNone, Size2Bytes, IIC_iALUx,
1147 "it$mask\t$cc", "", []>;
1149 //===----------------------------------------------------------------------===//
1150 // Non-Instruction Patterns
1153 // Two piece so_imms.
1154 def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
1155 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
1156 (t2_so_imm2part_2 imm:$RHS))>;
1157 def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
1158 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
1159 (t2_so_imm2part_2 imm:$RHS))>;
1160 def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
1161 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
1162 (t2_so_imm2part_2 imm:$RHS))>;
1163 def : T2Pat<(sub GPR:$LHS, t2_so_imm2part:$RHS),
1164 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
1165 (t2_so_imm2part_2 imm:$RHS))>;
1167 // ConstantPool, GlobalAddress, and JumpTable
1168 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1169 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1170 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1171 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1173 // 32-bit immediate using movw + movt.
1174 // This is a single pseudo instruction to make it re-materializable. Remove
1175 // when we can do generalized remat.
1176 let isReMaterializable = 1 in
1177 def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1178 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
1179 [(set GPR:$dst, (i32 imm:$src))]>;