1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
19 let PrintMethod = "printT2SOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
24 // described for t2_so_imm def below.
25 def t2_so_imm_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(
27 ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
30 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
31 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
32 return CurDAG->getTargetConstant(
33 ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
36 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
37 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(
39 ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
42 // t2_so_imm - Match a 32-bit immediate operand, which is an
43 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
44 // immediate splatted into multiple bytes of the word. t2_so_imm values are
45 // represented in the imm field in the same 12-bit form that they are encoded
46 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
47 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
48 def t2_so_imm : Operand<i32>,
50 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
51 }], t2_so_imm_XFORM> {
52 let PrintMethod = "printT2SOImmOperand";
55 // t2_so_imm_not - Match an immediate that is a complement
57 def t2_so_imm_not : Operand<i32>,
59 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60 }], t2_so_imm_not_XFORM> {
61 let PrintMethod = "printT2SOImmOperand";
64 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65 def t2_so_imm_neg : Operand<i32>,
67 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
68 }], t2_so_imm_neg_XFORM> {
69 let PrintMethod = "printT2SOImmOperand";
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
88 def imm0_65535 : PatLeaf<(i32 imm), [{
89 return (uint32_t)N->getZExtValue() < 65536;
93 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
95 def bf_inv_mask_imm : Operand<i32>,
97 uint32_t v = (uint32_t)N->getZExtValue();
100 // naive checker. should do better, but simple is best for now since it's
101 // more likely to be correct.
102 while (v & 1) v >>= 1; // shift off the leading 1's
105 while (!(v & 1)) v >>=1; // shift off the mask
106 while (v & 1) v >>= 1; // shift off the trailing 1's
108 // if this is a mask for clearing a bitfield, what's left should be zero.
111 let PrintMethod = "printBitfieldInvMaskImmOperand";
114 /// Split a 32-bit immediate into two 16 bit parts.
115 def t2_lo16 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
120 def t2_hi16 : SDNodeXForm<imm, [{
121 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
124 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
125 // Returns true if all low 16-bits are 0.
126 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
130 // Define Thumb2 specific addressing modes.
132 // t2addrmode_imm12 := reg + imm12
133 def t2addrmode_imm12 : Operand<i32>,
134 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
135 let PrintMethod = "printT2AddrModeImm12Operand";
136 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
139 // t2addrmode_imm8 := reg - imm8 (also reg + imm8 for some instructions)
140 def t2addrmode_imm8 : Operand<i32>,
141 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
142 let PrintMethod = "printT2AddrModeImm8Operand";
143 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
146 // t2addrmode_so_reg := reg + reg << imm2
147 def t2addrmode_so_reg : Operand<i32>,
148 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
149 let PrintMethod = "printT2AddrModeSoRegOperand";
150 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
154 //===----------------------------------------------------------------------===//
155 // Multiclass helpers...
158 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
159 /// unary operation that produces a value. These are predicable and can be
160 /// changed to modify CPSR.
161 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
163 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
165 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
166 let isAsCheapAsAMove = Cheap;
167 let isReMaterializable = ReMat;
170 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
172 [(set GPR:$dst, (opnode GPR:$src))]>;
174 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
176 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
179 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
180 // binary operation that produces a value. These are predicable and can be
181 /// changed to modify CPSR.
182 multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
184 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
185 opc, " $dst, $lhs, $rhs",
186 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
188 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
189 opc, " $dst, $lhs, $rhs",
190 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
191 let isCommutable = Commutable;
194 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
195 opc, " $dst, $lhs, $rhs",
196 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
199 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
200 /// reversed. It doesn't define the 'rr' form since it's handled by its
201 /// T2I_bin_irs counterpart.
202 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
204 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
205 opc, " $dst, $rhs, $lhs",
206 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
208 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
209 opc, " $dst, $rhs, $lhs",
210 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
213 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
214 /// instruction modifies the CPSR register.
215 let Defs = [CPSR] in {
216 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
218 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
219 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
220 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
222 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
223 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
224 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
225 let isCommutable = Commutable;
228 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
229 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
230 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
234 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
235 /// patterns for a binary operation that produces a value.
236 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
238 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
239 opc, " $dst, $lhs, $rhs",
240 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
242 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
243 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
244 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
246 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
247 opc, " $dst, $lhs, $rhs",
248 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
249 let isCommutable = Commutable;
252 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
253 opc, " $dst, $lhs, $rhs",
254 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
257 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
258 /// binary operation that produces a value and use and define the carry bit.
259 /// It's not predicable.
260 let Uses = [CPSR] in {
261 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
263 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
264 opc, " $dst, $lhs, $rhs",
265 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
266 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
268 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
269 opc, " $dst, $lhs, $rhs",
270 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
271 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]> {
272 let isCommutable = Commutable;
275 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
276 opc, " $dst, $lhs, $rhs",
277 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
278 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
279 // Carry setting variants
281 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
282 !strconcat(opc, "s $dst, $lhs, $rhs"),
283 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
284 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
288 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
289 !strconcat(opc, "s $dst, $lhs, $rhs"),
290 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
291 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
293 let isCommutable = Commutable;
296 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
297 !strconcat(opc, "s $dst, $lhs, $rhs"),
298 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
299 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
305 /// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
306 /// reversed. It doesn't define the 'rr' form since it's handled by its
307 /// T2I_adde_sube_irs counterpart.
308 let Defs = [CPSR], Uses = [CPSR] in {
309 multiclass T2I_rsc_is<string opc, PatFrag opnode> {
311 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
312 opc, " $dst, $rhs, $lhs",
313 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
314 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
316 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
317 opc, " $dst, $rhs, $lhs",
318 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
319 Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
321 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
322 !strconcat(opc, "s $dst, $rhs, $lhs"),
323 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
324 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
328 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
329 !strconcat(opc, "s $dst, $rhs, $lhs"),
330 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
331 Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
337 /// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
338 /// reversed. It doesn't define the 'rr' form since it's handled by its
339 /// T2I_bin_s_irs counterpart.
340 let Defs = [CPSR] in {
341 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
343 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
344 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
345 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
347 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
348 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
349 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
353 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
354 // rotate operation that produces a value.
355 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
357 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
358 opc, " $dst, $lhs, $rhs",
359 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
361 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
362 opc, " $dst, $lhs, $rhs",
363 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
366 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
367 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
368 /// a explicit result, only implicitly set CPSR.
369 let Uses = [CPSR] in {
370 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
372 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
374 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
376 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
378 [(opnode GPR:$lhs, GPR:$rhs)]>;
380 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
382 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
386 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
387 multiclass T2I_ld<string opc, PatFrag opnode> {
388 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
390 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
391 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
393 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
394 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
396 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
397 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
399 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
402 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
403 multiclass T2I_st<string opc, PatFrag opnode> {
404 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
406 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
407 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
409 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
410 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
412 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
415 //===----------------------------------------------------------------------===//
417 //===----------------------------------------------------------------------===//
419 //===----------------------------------------------------------------------===//
420 // Miscellaneous Instructions.
423 let isNotDuplicable = 1 in
424 def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
425 "$cp:\n\tadd $dst, pc",
426 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
429 // LEApcrel - Load a pc-relative address into a register without offending the
431 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
432 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
433 "${:private}PCRELL${:uid}+8))\n"),
434 !strconcat("${:private}PCRELL${:uid}:\n\t",
435 "add$p $dst, pc, #PCRELV${:uid}")),
438 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
439 (ins i32imm:$label, i32imm:$id, pred:$p),
440 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
441 "${:private}PCRELL${:uid}+8))\n"),
442 !strconcat("${:private}PCRELL${:uid}:\n\t",
443 "add$p $dst, pc, #PCRELV${:uid}")),
446 // ADD rd, sp, #so_imm
447 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
448 "add $dst, $sp, $imm",
451 // ADD rd, sp, #imm12
452 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
453 "addw $dst, $sp, $imm",
456 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
457 "addw $dst, $sp, $rhs",
461 //===----------------------------------------------------------------------===//
462 // Load / store Instructions.
466 let canFoldAsLoad = 1 in
467 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
469 // Loads with zero extension
470 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
471 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
473 // Loads with sign extension
474 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
475 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
479 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
480 "ldrd", " $dst, $addr", []>;
481 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
482 "ldrd", " $dst, $addr", []>;
485 // zextload i1 -> zextload i8
486 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
487 (t2LDRBi12 t2addrmode_imm12:$addr)>;
488 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
489 (t2LDRBi8 t2addrmode_imm8:$addr)>;
490 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
491 (t2LDRBs t2addrmode_so_reg:$addr)>;
492 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
493 (t2LDRBpci tconstpool:$addr)>;
495 // extload -> zextload
496 // FIXME: Reduce the number of patterns by legalizing extload to zextload
498 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
499 (t2LDRBi12 t2addrmode_imm12:$addr)>;
500 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
501 (t2LDRBi8 t2addrmode_imm8:$addr)>;
502 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
503 (t2LDRBs t2addrmode_so_reg:$addr)>;
504 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
505 (t2LDRBpci tconstpool:$addr)>;
507 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
508 (t2LDRBi12 t2addrmode_imm12:$addr)>;
509 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
510 (t2LDRBi8 t2addrmode_imm8:$addr)>;
511 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
512 (t2LDRBs t2addrmode_so_reg:$addr)>;
513 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
514 (t2LDRBpci tconstpool:$addr)>;
516 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
517 (t2LDRHi12 t2addrmode_imm12:$addr)>;
518 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
519 (t2LDRHi8 t2addrmode_imm8:$addr)>;
520 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
521 (t2LDRHs t2addrmode_so_reg:$addr)>;
522 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
523 (t2LDRHpci tconstpool:$addr)>;
526 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
527 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
528 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
530 //===----------------------------------------------------------------------===//
531 // Move Instructions.
534 let neverHasSideEffects = 1 in
535 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
536 "mov", " $dst, $src", []>;
538 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
539 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
540 "mov", " $dst, $src",
541 [(set GPR:$dst, t2_so_imm:$src)]>;
543 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
544 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
545 "movw", " $dst, $src",
546 [(set GPR:$dst, imm0_65535:$src)]>;
548 // FIXME: Also available in ARM mode.
549 let Constraints = "$src = $dst" in
550 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
551 "movt", " $dst, $imm",
553 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
555 //===----------------------------------------------------------------------===//
556 // Arithmetic Instructions.
559 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
560 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
562 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
563 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
564 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
566 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
567 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
570 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
571 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
572 defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
574 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
575 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
576 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
577 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
578 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
581 //===----------------------------------------------------------------------===//
582 // Shift and rotate Instructions.
585 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
586 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
587 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
588 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
590 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
591 "mov", " $dst, $src, rrx",
592 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
594 //===----------------------------------------------------------------------===//
595 // Bitwise Instructions.
598 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
599 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
600 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
602 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
604 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
605 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
607 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
609 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
610 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
612 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
613 let AddedComplexity = 1 in
614 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
616 def : T2Pat<(t2_so_imm_not:$src),
617 (t2MVNi t2_so_imm_not:$src)>;
619 // A8.6.17 BFC - Bitfield clear
620 // FIXME: Also available in ARM mode.
621 let Constraints = "$src = $dst" in
622 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
623 "bfc", " $dst, $imm",
624 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
626 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
628 //===----------------------------------------------------------------------===//
629 // Multiply Instructions.
631 let isCommutable = 1 in
632 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
633 "mul", " $dst, $a, $b",
634 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
636 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
637 "mla", " $dst, $a, $b, $c",
638 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
640 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
641 "mls", " $dst, $a, $b, $c",
642 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
644 // FIXME: SMULL, etc.
646 //===----------------------------------------------------------------------===//
647 // Misc. Arithmetic Instructions.
650 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
651 "clz", " $dst, $src",
652 [(set GPR:$dst, (ctlz GPR:$src))]>;
654 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
655 "rev", " $dst, $src",
656 [(set GPR:$dst, (bswap GPR:$src))]>;
658 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
659 "rev16", " $dst, $src",
661 (or (and (srl GPR:$src, (i32 8)), 0xFF),
662 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
663 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
664 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
669 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
670 "revsh", " $dst, $src",
673 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
674 (shl GPR:$src, (i32 8))), i16))]>;
678 //===----------------------------------------------------------------------===//
679 // Comparison Instructions...
682 defm t2CMP : T2I_cmp_is<"cmp",
683 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
684 defm t2CMPz : T2I_cmp_is<"cmp",
685 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
687 defm t2CMN : T2I_cmp_is<"cmn",
688 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
689 defm t2CMNz : T2I_cmp_is<"cmn",
690 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
692 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
693 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
695 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
696 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
698 defm t2TST : T2I_cmp_is<"tst",
699 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
700 defm t2TEQ : T2I_cmp_is<"teq",
701 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
703 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
704 // Short range conditional branch. Looks awesome for loops. Need to figure
705 // out how to use this one.
707 // FIXME: Conditional moves
709 //===----------------------------------------------------------------------===//
710 // Control-Flow Instructions
713 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
714 let isPredicable = 1 in
715 def t2B : T2XI<(outs), (ins brtarget:$target),
719 let isNotDuplicable = 1, isIndirectBranch = 1 in {
720 def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
721 "mov pc, $target \n$jt",
722 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
726 (ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id),
727 "ldr pc, $target \n$jt",
728 [(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt,
733 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
734 "add pc, $target, $idx \n$jt",
735 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>;
736 } // isNotDuplicate, isIndirectBranch
737 } // isBranch, isTerminator, isBarrier
739 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
740 // a two-value operand where a dag node expects two operands. :(
741 let isBranch = 1, isTerminator = 1 in
742 def t2Bcc : T2I<(outs), (ins brtarget:$target),
744 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
746 //===----------------------------------------------------------------------===//
747 // Non-Instruction Patterns
750 // ConstantPool, GlobalAddress, and JumpTable
751 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
752 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
753 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
754 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
756 // Large immediate handling.
758 def : T2Pat<(i32 imm:$src),
759 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;