1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let PrintMethod = "printT2SOOperand";
30 let MIOperandInfo = (ops GPR, i32imm);
33 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
34 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
35 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
38 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
39 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
43 // t2_so_imm - Match a 32-bit immediate operand, which is an
44 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
45 // immediate splatted into multiple bytes of the word. t2_so_imm values are
46 // represented in the imm field in the same 12-bit form that they are encoded
47 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
48 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
49 def t2_so_imm : Operand<i32>,
51 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
54 // t2_so_imm_not - Match an immediate that is a complement
56 def t2_so_imm_not : Operand<i32>,
58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
59 }], t2_so_imm_not_XFORM>;
61 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
62 def t2_so_imm_neg : Operand<i32>,
64 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
65 }], t2_so_imm_neg_XFORM>;
67 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
68 def imm1_31 : PatLeaf<(i32 imm), [{
69 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
72 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
73 def imm0_4095 : PatLeaf<(i32 imm), [{
74 return (uint32_t)N->getZExtValue() < 4096;
77 def imm0_4095_neg : PatLeaf<(i32 imm), [{
78 return (uint32_t)(-N->getZExtValue()) < 4096;
81 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
83 def imm0_65535 : PatLeaf<(i32 imm), [{
84 return (uint32_t)N->getZExtValue() < 65536;
87 /// Split a 32-bit immediate into two 16 bit parts.
88 def t2_lo16 : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
93 def t2_hi16 : SDNodeXForm<imm, [{
94 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
97 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
98 // Returns true if all low 16-bits are 0.
99 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
103 // Define Thumb2 specific addressing modes.
105 // t2addrmode_imm12 := reg + imm12
106 def t2addrmode_imm12 : Operand<i32>,
107 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
108 let PrintMethod = "printT2AddrModeImm12Operand";
109 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
112 // t2addrmode_imm8 := reg - imm8
113 def t2addrmode_imm8 : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
115 let PrintMethod = "printT2AddrModeImm8Operand";
116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
119 def t2am_imm8_offset : Operand<i32>,
120 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
121 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
124 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
125 def t2addrmode_imm8s4 : Operand<i32>,
126 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
127 let PrintMethod = "printT2AddrModeImm8s4Operand";
128 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
131 // t2addrmode_so_reg := reg + (reg << imm2)
132 def t2addrmode_so_reg : Operand<i32>,
133 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
134 let PrintMethod = "printT2AddrModeSoRegOperand";
135 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
139 //===----------------------------------------------------------------------===//
140 // Multiclass helpers...
143 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
144 /// unary operation that produces a value. These are predicable and can be
145 /// changed to modify CPSR.
146 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
148 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
150 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
151 let isAsCheapAsAMove = Cheap;
152 let isReMaterializable = ReMat;
155 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
156 opc, ".w $dst, $src",
157 [(set GPR:$dst, (opnode GPR:$src))]>;
159 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
160 opc, ".w $dst, $src",
161 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
164 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
165 // binary operation that produces a value. These are predicable and can be
166 /// changed to modify CPSR.
167 multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
169 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
170 opc, " $dst, $lhs, $rhs",
171 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
173 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
174 opc, ".w $dst, $lhs, $rhs",
175 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
176 let isCommutable = Commutable;
179 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
180 opc, ".w $dst, $lhs, $rhs",
181 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
184 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
185 /// reversed. It doesn't define the 'rr' form since it's handled by its
186 /// T2I_bin_irs counterpart.
187 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
189 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
190 opc, ".w $dst, $rhs, $lhs",
191 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
193 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
194 opc, " $dst, $rhs, $lhs",
195 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
198 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
199 /// instruction modifies the CPSR register.
200 let Defs = [CPSR] in {
201 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
203 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
204 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
205 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
207 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
208 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
209 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
210 let isCommutable = Commutable;
213 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
214 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
215 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
219 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
220 /// patterns for a binary operation that produces a value.
221 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
223 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
224 opc, ".w $dst, $lhs, $rhs",
225 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
227 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
228 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
229 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
231 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
232 opc, ".w $dst, $lhs, $rhs",
233 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
234 let isCommutable = Commutable;
237 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
238 opc, ".w $dst, $lhs, $rhs",
239 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
242 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
243 /// binary operation that produces a value and use and define the carry bit.
244 /// It's not predicable.
245 let Uses = [CPSR] in {
246 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
248 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
249 opc, " $dst, $lhs, $rhs",
250 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
251 Requires<[IsThumb2, CarryDefIsUnused]>;
253 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
254 opc, ".w $dst, $lhs, $rhs",
255 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
256 Requires<[IsThumb2, CarryDefIsUnused]> {
257 let isCommutable = Commutable;
260 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
261 opc, ".w $dst, $lhs, $rhs",
262 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
263 Requires<[IsThumb2, CarryDefIsUnused]>;
264 // Carry setting variants
266 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
267 !strconcat(opc, "s $dst, $lhs, $rhs"),
268 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
269 Requires<[IsThumb2, CarryDefIsUsed]> {
273 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
274 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
275 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
276 Requires<[IsThumb2, CarryDefIsUsed]> {
278 let isCommutable = Commutable;
281 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
282 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
283 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
284 Requires<[IsThumb2, CarryDefIsUsed]> {
290 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
291 let Defs = [CPSR] in {
292 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
294 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
295 !strconcat(opc, "${s}.w $dst, $rhs, $lhs"),
296 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
298 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
299 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
300 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
304 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
305 // rotate operation that produces a value.
306 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
308 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
309 opc, ".w $dst, $lhs, $rhs",
310 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
312 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
313 opc, ".w $dst, $lhs, $rhs",
314 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
317 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
318 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
319 /// a explicit result, only implicitly set CPSR.
320 let Defs = [CPSR] in {
321 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
323 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
324 opc, ".w $lhs, $rhs",
325 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
327 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
328 opc, ".w $lhs, $rhs",
329 [(opnode GPR:$lhs, GPR:$rhs)]>;
331 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
332 opc, ".w $lhs, $rhs",
333 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
337 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
338 multiclass T2I_ld<string opc, PatFrag opnode> {
339 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
340 opc, ".w $dst, $addr",
341 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
342 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
344 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
345 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
346 opc, ".w $dst, $addr",
347 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
348 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
349 opc, ".w $dst, $addr",
350 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
353 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
354 multiclass T2I_st<string opc, PatFrag opnode> {
355 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
356 opc, ".w $src, $addr",
357 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
358 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
360 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
361 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
362 opc, ".w $src, $addr",
363 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
366 /// T2I_picld - Defines the PIC load pattern.
367 class T2I_picld<string opc, PatFrag opnode> :
368 T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
369 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
370 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
372 /// T2I_picst - Defines the PIC store pattern.
373 class T2I_picst<string opc, PatFrag opnode> :
374 T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
375 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
376 [(opnode GPR:$src, addrmodepc:$addr)]>;
379 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
380 /// register and one whose operand is a register rotated by 8/16/24.
381 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
382 def r : T2I<(outs GPR:$dst), (ins GPR:$Src),
383 opc, ".w $dst, $Src",
384 [(set GPR:$dst, (opnode GPR:$Src))]>;
385 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
386 opc, ".w $dst, $Src, ror $rot",
387 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
390 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
391 /// register and one whose operand is a register rotated by 8/16/24.
392 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
393 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
394 opc, " $dst, $LHS, $RHS",
395 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
396 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
397 opc, " $dst, $LHS, $RHS, ror $rot",
398 [(set GPR:$dst, (opnode GPR:$LHS,
399 (rotr GPR:$RHS, rot_imm:$rot)))]>;
402 //===----------------------------------------------------------------------===//
404 //===----------------------------------------------------------------------===//
406 //===----------------------------------------------------------------------===//
407 // Miscellaneous Instructions.
410 let isNotDuplicable = 1 in
411 def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
412 "$cp:\n\tadd.w $dst, $lhs, pc",
413 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
416 // LEApcrel - Load a pc-relative address into a register without offending the
418 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
419 "adr$p.w $dst, #$label", []>;
421 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
422 (ins i32imm:$label, i32imm:$id, pred:$p),
423 "adr$p.w $dst, #${label}_${id:no_hash}", []>;
425 // ADD rd, sp, #so_imm
426 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
427 "add.w $dst, $sp, $imm",
430 // ADD rd, sp, #imm12
431 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
432 "addw $dst, $sp, $imm",
435 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
436 "addw $dst, $sp, $rhs",
440 //===----------------------------------------------------------------------===//
441 // Load / store Instructions.
445 let canFoldAsLoad = 1 in
446 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
448 // Loads with zero extension
449 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
450 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
452 // Loads with sign extension
453 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
454 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
458 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
459 "ldrd", " $dst, $addr", []>;
460 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
461 "ldrd", " $dst, $addr", []>;
464 // zextload i1 -> zextload i8
465 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
466 (t2LDRBi12 t2addrmode_imm12:$addr)>;
467 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
468 (t2LDRBi8 t2addrmode_imm8:$addr)>;
469 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
470 (t2LDRBs t2addrmode_so_reg:$addr)>;
471 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
472 (t2LDRBpci tconstpool:$addr)>;
474 // extload -> zextload
475 // FIXME: Reduce the number of patterns by legalizing extload to zextload
477 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
478 (t2LDRBi12 t2addrmode_imm12:$addr)>;
479 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
480 (t2LDRBi8 t2addrmode_imm8:$addr)>;
481 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
482 (t2LDRBs t2addrmode_so_reg:$addr)>;
483 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
484 (t2LDRBpci tconstpool:$addr)>;
486 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
487 (t2LDRBi12 t2addrmode_imm12:$addr)>;
488 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
489 (t2LDRBi8 t2addrmode_imm8:$addr)>;
490 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
491 (t2LDRBs t2addrmode_so_reg:$addr)>;
492 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
493 (t2LDRBpci tconstpool:$addr)>;
495 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
496 (t2LDRHi12 t2addrmode_imm12:$addr)>;
497 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
498 (t2LDRHi8 t2addrmode_imm8:$addr)>;
499 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
500 (t2LDRHs t2addrmode_so_reg:$addr)>;
501 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
502 (t2LDRHpci tconstpool:$addr)>;
506 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
507 (ins t2addrmode_imm8:$addr),
508 AddrModeT2_i8, IndexModePre,
509 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
512 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
513 (ins GPR:$base, t2am_imm8_offset:$offset),
514 AddrModeT2_i8, IndexModePost,
515 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
518 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
519 (ins t2addrmode_imm8:$addr),
520 AddrModeT2_i8, IndexModePre,
521 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
523 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
524 (ins GPR:$base, t2am_imm8_offset:$offset),
525 AddrModeT2_i8, IndexModePost,
526 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
529 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
530 (ins t2addrmode_imm8:$addr),
531 AddrModeT2_i8, IndexModePre,
532 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
534 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
535 (ins GPR:$base, t2am_imm8_offset:$offset),
536 AddrModeT2_i8, IndexModePost,
537 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
540 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
541 (ins t2addrmode_imm8:$addr),
542 AddrModeT2_i8, IndexModePre,
543 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
545 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
546 (ins GPR:$base, t2am_imm8_offset:$offset),
547 AddrModeT2_i8, IndexModePost,
548 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
551 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
552 (ins t2addrmode_imm8:$addr),
553 AddrModeT2_i8, IndexModePre,
554 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
556 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
557 (ins GPR:$base, t2am_imm8_offset:$offset),
558 AddrModeT2_i8, IndexModePost,
559 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
564 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
565 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
566 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
570 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
571 "strd", " $src, $addr", []>;
574 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
575 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
576 AddrModeT2_i8, IndexModePre,
577 "str", " $src, [$base, $offset]!", "$base = $base_wb",
579 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
581 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
582 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
583 AddrModeT2_i8, IndexModePost,
584 "str", " $src, [$base], $offset", "$base = $base_wb",
586 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
588 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
589 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
590 AddrModeT2_i8, IndexModePre,
591 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
593 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
595 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
596 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
597 AddrModeT2_i8, IndexModePost,
598 "strh", " $src, [$base], $offset", "$base = $base_wb",
600 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
602 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
603 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
604 AddrModeT2_i8, IndexModePre,
605 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
607 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
609 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
610 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
611 AddrModeT2_i8, IndexModePost,
612 "strb", " $src, [$base], $offset", "$base = $base_wb",
614 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
617 // FIXME: ldrd / strd pre / post variants
619 //===----------------------------------------------------------------------===//
620 // Load / store multiple Instructions.
624 def t2LDM : T2XI<(outs),
625 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
626 "ldm${addr:submode}${p}.w $addr, $dst1", []>;
629 def t2STM : T2XI<(outs),
630 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
631 "stm${addr:submode}${p}.w $addr, $src1", []>;
633 //===----------------------------------------------------------------------===//
634 // Move Instructions.
637 let neverHasSideEffects = 1 in
638 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
639 "mov", ".w $dst, $src", []>;
641 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
642 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
643 "mov", ".w $dst, $src",
644 [(set GPR:$dst, t2_so_imm:$src)]>;
646 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
647 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
648 "movw", " $dst, $src",
649 [(set GPR:$dst, imm0_65535:$src)]>;
651 // FIXME: Also available in ARM mode.
652 let Constraints = "$src = $dst" in
653 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
654 "movt", " $dst, $imm",
656 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
658 //===----------------------------------------------------------------------===//
659 // Extend Instructions.
664 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
665 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
667 defm t2SXTAB : T2I_bin_rrot<"sxtab",
668 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
669 defm t2SXTAH : T2I_bin_rrot<"sxtah",
670 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
672 // TODO: SXT(A){B|H}16
676 let AddedComplexity = 16 in {
677 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
678 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
679 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
681 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
682 (t2UXTB16r_rot GPR:$Src, 24)>;
683 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
684 (t2UXTB16r_rot GPR:$Src, 8)>;
686 defm t2UXTAB : T2I_bin_rrot<"uxtab",
687 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
688 defm t2UXTAH : T2I_bin_rrot<"uxtah",
689 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
692 //===----------------------------------------------------------------------===//
693 // Arithmetic Instructions.
696 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
697 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
699 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
700 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
701 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
703 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
704 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
707 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
708 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
710 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
711 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
712 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
713 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
714 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
717 //===----------------------------------------------------------------------===//
718 // Shift and rotate Instructions.
721 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
722 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
723 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
724 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
726 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
727 "mov", " $dst, $src, rrx",
728 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
730 //===----------------------------------------------------------------------===//
731 // Bitwise Instructions.
734 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
735 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
736 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
738 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
740 let Constraints = "$src = $dst" in
741 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
742 "bfc", " $dst, $imm",
743 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
745 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
747 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
749 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
750 let AddedComplexity = 1 in
751 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
754 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
755 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
757 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
758 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
760 def : T2Pat<(t2_so_imm_not:$src),
761 (t2MVNi t2_so_imm_not:$src)>;
763 //===----------------------------------------------------------------------===//
764 // Multiply Instructions.
766 let isCommutable = 1 in
767 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
768 "mul", " $dst, $a, $b",
769 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
771 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
772 "mla", " $dst, $a, $b, $c",
773 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
775 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
776 "mls", " $dst, $a, $b, $c",
777 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
779 // Extra precision multiplies with low / high results
780 let neverHasSideEffects = 1 in {
781 let isCommutable = 1 in {
782 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
783 "smull", " $ldst, $hdst, $a, $b", []>;
785 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
786 "umull", " $ldst, $hdst, $a, $b", []>;
789 // Multiply + accumulate
790 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
791 "smlal", " $ldst, $hdst, $a, $b", []>;
793 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
794 "umlal", " $ldst, $hdst, $a, $b", []>;
796 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
797 "umaal", " $ldst, $hdst, $a, $b", []>;
798 } // neverHasSideEffects
800 // Most significant word multiply
801 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
802 "smmul", " $dst, $a, $b",
803 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
805 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
806 "smmla", " $dst, $a, $b, $c",
807 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
810 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
811 "smmls", " $dst, $a, $b, $c",
812 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
814 multiclass T2I_smul<string opc, PatFrag opnode> {
815 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
816 !strconcat(opc, "bb"), " $dst, $a, $b",
817 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
818 (sext_inreg GPR:$b, i16)))]>;
820 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
821 !strconcat(opc, "bt"), " $dst, $a, $b",
822 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
823 (sra GPR:$b, (i32 16))))]>;
825 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
826 !strconcat(opc, "tb"), " $dst, $a, $b",
827 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
828 (sext_inreg GPR:$b, i16)))]>;
830 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
831 !strconcat(opc, "tt"), " $dst, $a, $b",
832 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
833 (sra GPR:$b, (i32 16))))]>;
835 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
836 !strconcat(opc, "wb"), " $dst, $a, $b",
837 [(set GPR:$dst, (sra (opnode GPR:$a,
838 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
840 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
841 !strconcat(opc, "wt"), " $dst, $a, $b",
842 [(set GPR:$dst, (sra (opnode GPR:$a,
843 (sra GPR:$b, (i32 16))), (i32 16)))]>;
847 multiclass T2I_smla<string opc, PatFrag opnode> {
848 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
849 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
850 [(set GPR:$dst, (add GPR:$acc,
851 (opnode (sext_inreg GPR:$a, i16),
852 (sext_inreg GPR:$b, i16))))]>;
854 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
855 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
856 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
857 (sra GPR:$b, (i32 16)))))]>;
859 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
860 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
861 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
862 (sext_inreg GPR:$b, i16))))]>;
864 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
865 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
866 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
867 (sra GPR:$b, (i32 16)))))]>;
869 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
870 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
871 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
872 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
874 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
875 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
876 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
877 (sra GPR:$b, (i32 16))), (i32 16))))]>;
880 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
881 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
883 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
884 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
887 //===----------------------------------------------------------------------===//
888 // Misc. Arithmetic Instructions.
891 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
892 "clz", " $dst, $src",
893 [(set GPR:$dst, (ctlz GPR:$src))]>;
895 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
896 "rev", ".w $dst, $src",
897 [(set GPR:$dst, (bswap GPR:$src))]>;
899 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
900 "rev16", ".w $dst, $src",
902 (or (and (srl GPR:$src, (i32 8)), 0xFF),
903 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
904 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
905 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
907 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
908 "revsh", ".w $dst, $src",
911 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
912 (shl GPR:$src, (i32 8))), i16))]>;
914 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
915 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
916 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
917 (and (shl GPR:$src2, (i32 imm:$shamt)),
920 // Alternate cases for PKHBT where identities eliminate some nodes.
921 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
922 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
923 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
924 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
926 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
927 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
928 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
929 (and (sra GPR:$src2, imm16_31:$shamt),
932 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
933 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
934 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
935 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
936 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
937 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
938 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
940 //===----------------------------------------------------------------------===//
941 // Comparison Instructions...
944 defm t2CMP : T2I_cmp_is<"cmp",
945 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
946 defm t2CMPz : T2I_cmp_is<"cmp",
947 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
949 defm t2CMN : T2I_cmp_is<"cmn",
950 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
951 defm t2CMNz : T2I_cmp_is<"cmn",
952 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
954 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
955 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
957 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
958 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
960 defm t2TST : T2I_cmp_is<"tst",
961 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
962 defm t2TEQ : T2I_cmp_is<"teq",
963 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
965 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
966 // Short range conditional branch. Looks awesome for loops. Need to figure
967 // out how to use this one.
971 // FIXME: should be able to write a pattern for ARMcmov, but can't use
972 // a two-value operand where a dag node expects two operands. :(
973 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
974 "mov", " $dst, $true",
975 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
976 RegConstraint<"$false = $dst">;
978 def t2MOVCCs : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_reg:$true),
979 "mov", " $dst, $true",
980 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
981 RegConstraint<"$false = $dst">;
983 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
984 "mov", " $dst, $true",
985 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
986 RegConstraint<"$false = $dst">;
988 //===----------------------------------------------------------------------===//
992 // __aeabi_read_tp preserves the registers r1-r3.
994 Defs = [R0, R12, LR, CPSR] in {
995 def t2TPsoft : T2XI<(outs), (ins),
996 "bl __aeabi_read_tp",
997 [(set R0, ARMthread_pointer)]>;
1000 //===----------------------------------------------------------------------===//
1001 // Control-Flow Instructions
1004 // FIXME: remove when we have a way to marking a MI with these properties.
1005 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1007 // FIXME: Should pc be an implicit operand like PICADD, etc?
1008 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
1009 def t2LDM_RET : T2XI<(outs),
1010 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
1011 "ldm${addr:submode}${p} $addr, $dst1",
1014 // On non-Darwin platforms R9 is callee-saved.
1016 Defs = [R0, R1, R2, R3, R12, LR,
1017 D0, D1, D2, D3, D4, D5, D6, D7,
1018 D16, D17, D18, D19, D20, D21, D22, D23,
1019 D24, D25, D26, D27, D28, D29, D31, D31, CPSR] in {
1020 def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
1022 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
1024 def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
1026 [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
1029 // On Darwin R9 is call-clobbered.
1031 Defs = [R0, R1, R2, R3, R9, R12, LR,
1032 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1033 def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
1035 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
1037 def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
1039 [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
1042 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1043 let isPredicable = 1 in
1044 def t2B : T2XI<(outs), (ins brtarget:$target),
1048 let isNotDuplicable = 1, isIndirectBranch = 1 in
1051 (ins GPR:$base, GPR:$idx, jt2block_operand:$jt, i32imm:$id),
1052 "add.w pc, $base, $idx, lsl #2\n$jt",
1053 [(ARMbr2jt GPR:$base, GPR:$idx, tjumptable:$jt, imm:$id)]>;
1054 } // isBranch, isTerminator, isBarrier
1056 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1057 // a two-value operand where a dag node expects two operands. :(
1058 let isBranch = 1, isTerminator = 1 in
1059 def t2Bcc : T2I<(outs), (ins brtarget:$target),
1061 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1065 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1066 AddrModeNone, Size2Bytes,
1067 "it$mask $cc", "", []>;
1069 //===----------------------------------------------------------------------===//
1070 // Non-Instruction Patterns
1073 // ConstantPool, GlobalAddress, and JumpTable
1074 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1075 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1076 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1077 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1079 // Large immediate handling.
1081 def : T2Pat<(i32 imm:$src),
1082 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;