1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectShifterOperand",
19 let PrintMethod = "printSOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
24 // described for t2_so_imm def below.
25 def t2_so_imm_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(
27 ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
30 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
31 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
32 return CurDAG->getTargetConstant(
33 ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
36 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
37 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(
39 ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
42 // t2_so_imm - Match a 32-bit immediate operand, which is an
43 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
44 // immediate splatted into multiple bytes of the word. t2_so_imm values are
45 // represented in the imm field in the same 12-bit form that they are encoded
46 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
47 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
48 def t2_so_imm : Operand<i32>,
50 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
51 }], t2_so_imm_XFORM> {
52 let PrintMethod = "printT2SOImmOperand";
55 // t2_so_imm_not - Match an immediate that is a complement
57 def t2_so_imm_not : Operand<i32>,
59 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60 }], t2_so_imm_not_XFORM> {
61 let PrintMethod = "printT2SOImmOperand";
64 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65 def t2_so_imm_neg : Operand<i32>,
67 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
68 }], t2_so_imm_neg_XFORM> {
69 let PrintMethod = "printT2SOImmOperand";
72 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
73 def imm0_4095 : PatLeaf<(i32 imm), [{
74 return (uint32_t)N->getZExtValue() < 4096;
77 def imm0_4095_neg : PatLeaf<(i32 imm), [{
78 return (uint32_t)(-N->getZExtValue()) < 4096;
81 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
83 def imm0_65535 : PatLeaf<(i32 imm), [{
84 return (uint32_t)N->getZExtValue() < 65536;
88 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
90 def bf_inv_mask_imm : Operand<i32>,
92 uint32_t v = (uint32_t)N->getZExtValue();
95 // naive checker. should do better, but simple is best for now since it's
96 // more likely to be correct.
97 while (v & 1) v >>= 1; // shift off the leading 1's
100 while (!(v & 1)) v >>=1; // shift off the mask
101 while (v & 1) v >>= 1; // shift off the trailing 1's
103 // if this is a mask for clearing a bitfield, what's left should be zero.
106 let PrintMethod = "printBitfieldInvMaskImmOperand";
109 /// Split a 32-bit immediate into two 16 bit parts.
110 def t2_lo16 : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
115 def t2_hi16 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
119 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
120 // Returns true if all low 16-bits are 0.
121 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
124 //===----------------------------------------------------------------------===//
125 // Thumb2 to cover the functionality of the ARM instruction set.
128 /// T2I_bin_is - Defines a set of (op reg, {so_imm|so_reg}) patterns for a
129 // binary operation that produces a value.
130 multiclass T2I_bin_is<string opc, PatFrag opnode> {
132 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
133 !strconcat(opc, " $dst, $lhs, $rhs"),
134 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
136 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
137 !strconcat(opc, " $dst, $lhs, $rhs"),
138 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
141 /// T2I_2bin_is - Same as T2I_bin_is except the order of operands are reversed.
142 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
144 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
145 !strconcat(opc, " $dst, $lhs, $rhs"),
146 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
148 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
149 !strconcat(opc, " $dst, $lhs, $rhs"),
150 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
153 /// T2I_bin_s_is - Similar to T2I_bin_is except it sets the 's' bit so the
154 /// instruction modifies the CPSR register.
155 let Defs = [CPSR] in {
156 multiclass T2I_bin_s_is<string opc, PatFrag opnode> {
158 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
159 !strconcat(opc, "s $dst, $lhs, $rhs"),
160 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
163 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
164 !strconcat(opc, "s $dst, $lhs, $rhs"),
165 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
169 /// T2I_rbin_s_is - Same as T2I_bin_s_is except the order of operands are
171 let Defs = [CPSR] in {
172 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
174 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
175 !strconcat(opc, "s $dst, $lhs, $rhs"),
176 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
179 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
180 !strconcat(opc, "s $dst, $lhs, $rhs"),
181 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
185 /// T2I_bin_ii12s - Defines a set of (op reg, {so_imm|imm0_4095|so_reg}) patterns
186 /// for a binary operation that produces a value.
187 multiclass T2I_bin_ii12s<string opc, PatFrag opnode> {
189 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
190 !strconcat(opc, " $dst, $lhs, $rhs"),
191 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
193 def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
194 !strconcat(opc, "w $dst, $lhs, $rhs"),
195 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
197 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
198 !strconcat(opc, " $dst, $lhs, $rhs"),
199 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
202 /// T2I_bin_c_is - Defines a set of (op reg, {so_imm|reg}) patterns for a
203 // binary operation that produces a value and set the carry bit. It can also
204 /// optionally set CPSR.
205 let Uses = [CPSR] in {
206 multiclass T2I_bin_c_is<string opc, PatFrag opnode> {
208 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s),
209 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
210 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
213 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
214 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
215 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
219 /// T2I_rbin_c_is - Same as T2I_bin_c_is except the order of operands are
221 let Uses = [CPSR] in {
222 multiclass T2I_rbin_c_is<string opc, PatFrag opnode> {
224 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
225 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
226 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
229 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
230 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
231 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
236 /// T21_cmp_irs - Defines a set of (op r, {so_imm|so_reg}) cmp / test
237 /// patterns. Similar to T2I_bin_is except the instruction does not produce
238 /// a explicit result, only implicitly set CPSR.
239 let Uses = [CPSR] in {
240 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
242 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
243 !strconcat(opc, " $lhs, $rhs"),
244 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
247 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
248 !strconcat(opc, " $lhs, $rhs"),
249 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
253 //===----------------------------------------------------------------------===//
254 // Arithmetic Instructions.
257 //===----------------------------------------------------------------------===//
258 // Move Instructions.
261 let neverHasSideEffects = 1 in
262 def t2MOVr : T2I<(outs GPR:$dst), (ins GPR:$src),
263 "mov $dst, $src", []>;
265 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
267 [(set GPR:$dst, imm0_65535:$src)]>;
270 // FIXME: Move (shifted register) is a pseudo-instruction for ASR, LSL, LSR,
271 // ROR, and RRX. Consider splitting into multiple instructions.
272 def t2MOVs : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
274 [(set GPR:$dst, t2_so_reg:$src)]>;
275 def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src),
276 "mov $dst, $src, rrx",
277 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
280 // FIXME: Also available in ARM mode.
281 let Constraints = "$src = $dst" in
282 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
285 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
287 //===----------------------------------------------------------------------===//
288 // Arithmetic Instructions.
291 defm t2ADD : T2I_bin_ii12s<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
292 defm t2SUB : T2I_bin_ii12s<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
294 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
295 defm t2ADDS : T2I_bin_s_is<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
296 defm t2SUBS : T2I_bin_s_is<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
298 // FIXME: predication support
299 defm t2ADC : T2I_bin_c_is<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
300 defm t2SBC : T2I_bin_c_is<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
303 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
304 defm t2RSBS : T2I_rbin_c_is<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
305 defm t2RSC : T2I_rbin_s_is<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
307 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
308 def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
309 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
310 def : Thumb2Pat<(add GPR:$src, imm0_4095_neg:$imm),
311 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
314 //===----------------------------------------------------------------------===//
315 // Bitwise Instructions.
318 defm t2AND : T2I_bin_is <"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
319 defm t2ORR : T2I_bin_is <"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
320 defm t2EOR : T2I_bin_is <"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
322 defm t2BIC : T2I_bin_is <"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
324 def : Thumb2Pat<(and GPR:$src, t2_so_imm_not:$imm),
325 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
327 defm t2ORN : T2I_bin_is <"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
329 def : Thumb2Pat<(or GPR:$src, t2_so_imm_not:$imm),
330 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
333 def t2MVNr : T2I<(outs GPR:$dst), (ins t2_so_reg:$rhs),
335 [(set GPR:$dst, (not t2_so_reg:$rhs))]>;
336 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
337 def t2MVNi : T2I<(outs GPR:$dst), (ins t2_so_imm_not:$rhs),
339 [(set GPR:$dst, t2_so_imm_not:$rhs)]>;
341 // A8.6.17 BFC - Bitfield clear
342 // FIXME: Also available in ARM mode.
343 let Constraints = "$src = $dst" in
344 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
346 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
348 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
350 //===----------------------------------------------------------------------===//
351 // Multiply Instructions.
353 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
355 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
357 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
358 "mla $dst, $a, $b, $c",
359 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
361 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
362 "mls $dst, $a, $b, $c",
363 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
365 // FIXME: SMULL, etc.
367 //===----------------------------------------------------------------------===//
368 // Misc. Arithmetic Instructions.
374 // FIXME not firing? but ARM version does...
375 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
377 [(set GPR:$dst, (ctlz GPR:$src))]>;
379 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
381 [(set GPR:$dst, (bswap GPR:$src))]>;
383 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
386 (or (and (srl GPR:$src, (i32 8)), 0xFF),
387 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
388 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
389 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
394 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
398 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
399 (shl GPR:$src, (i32 8))), i16))]>;
403 //===----------------------------------------------------------------------===//
404 // Comparison Instructions...
407 defm t2CMP : T2I_cmp_is<"cmp",
408 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
409 defm t2CMPnz : T2I_cmp_is<"cmp",
410 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
412 defm t2CMN : T2I_cmp_is<"cmn",
413 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
414 defm t2CMNnz : T2I_cmp_is<"cmn",
415 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
417 def : Thumb2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
418 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
420 def : Thumb2Pat<(ARMcmpNZ GPR:$src, t2_so_imm_neg:$imm),
421 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
423 // FIXME: TST, TEQ, etc.
425 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
426 // Short range conditional branch. Looks awesome for loops. Need to figure
427 // out how to use this one.
429 // FIXME: Conditional moves
432 //===----------------------------------------------------------------------===//
433 // Non-Instruction Patterns
436 // Large immediate handling.
438 def : Thumb2Pat<(i32 imm:$src),
439 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)),
440 (t2_hi16 imm:$src))>;