1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 // Define Thumb2 specific addressing modes.
127 // t2addrmode_imm12 := reg + imm12
128 def t2addrmode_imm12 : Operand<i32>,
129 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
130 let PrintMethod = "printT2AddrModeImm12Operand";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
134 // t2addrmode_imm8 := reg +/- imm8
135 def t2addrmode_imm8 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137 let PrintMethod = "printT2AddrModeImm8Operand";
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141 def t2am_imm8_offset : Operand<i32>,
142 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
143 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
147 def t2addrmode_imm8s4 : Operand<i32>,
148 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
149 let PrintMethod = "printT2AddrModeImm8s4Operand";
150 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
153 def t2am_imm8s4_offset : Operand<i32> {
154 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
157 // t2addrmode_so_reg := reg + (reg << imm2)
158 def t2addrmode_so_reg : Operand<i32>,
159 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
160 let PrintMethod = "printT2AddrModeSoRegOperand";
161 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
165 //===----------------------------------------------------------------------===//
166 // Multiclass helpers...
169 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
170 /// unary operation that produces a value. These are predicable and can be
171 /// changed to modify CPSR.
172 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
173 bit Cheap = 0, bit ReMat = 0> {
175 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
177 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
178 let isAsCheapAsAMove = Cheap;
179 let isReMaterializable = ReMat;
180 let Inst{31-27} = 0b11110;
182 let Inst{24-21} = opcod;
183 let Inst{20} = ?; // The S bit.
184 let Inst{19-16} = 0b1111; // Rn
188 def r : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
189 opc, ".w\t$dst, $src",
190 [(set GPR:$dst, (opnode GPR:$src))]> {
191 let Inst{31-27} = 0b11101;
192 let Inst{26-25} = 0b01;
193 let Inst{24-21} = opcod;
194 let Inst{20} = ?; // The S bit.
195 let Inst{19-16} = 0b1111; // Rn
196 let Inst{14-12} = 0b000; // imm3
197 let Inst{7-6} = 0b00; // imm2
198 let Inst{5-4} = 0b00; // type
201 def s : T2sI<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
202 opc, ".w\t$dst, $src",
203 [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
204 let Inst{31-27} = 0b11101;
205 let Inst{26-25} = 0b01;
206 let Inst{24-21} = opcod;
207 let Inst{20} = ?; // The S bit.
208 let Inst{19-16} = 0b1111; // Rn
212 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
213 /// binary operation that produces a value. These are predicable and can be
214 /// changed to modify CPSR.
215 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
216 bit Commutable = 0, string wide =""> {
218 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
219 opc, "\t$dst, $lhs, $rhs",
220 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
221 let Inst{31-27} = 0b11110;
223 let Inst{24-21} = opcod;
224 let Inst{20} = ?; // The S bit.
228 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
229 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
230 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
231 let isCommutable = Commutable;
232 let Inst{31-27} = 0b11101;
233 let Inst{26-25} = 0b01;
234 let Inst{24-21} = opcod;
235 let Inst{20} = ?; // The S bit.
236 let Inst{14-12} = 0b000; // imm3
237 let Inst{7-6} = 0b00; // imm2
238 let Inst{5-4} = 0b00; // type
241 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
242 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
243 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
244 let Inst{31-27} = 0b11101;
245 let Inst{26-25} = 0b01;
246 let Inst{24-21} = opcod;
247 let Inst{20} = ?; // The S bit.
251 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
252 // the ".w" prefix to indicate that they are wide.
253 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
254 bit Commutable = 0> :
255 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
257 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
258 /// reversed. It doesn't define the 'rr' form since it's handled by its
259 /// T2I_bin_irs counterpart.
260 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
262 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
263 opc, ".w\t$dst, $rhs, $lhs",
264 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
265 let Inst{31-27} = 0b11110;
267 let Inst{24-21} = opcod;
268 let Inst{20} = ?; // The S bit.
272 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
273 opc, "\t$dst, $rhs, $lhs",
274 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
275 let Inst{31-27} = 0b11101;
276 let Inst{26-25} = 0b01;
277 let Inst{24-21} = opcod;
278 let Inst{20} = ?; // The S bit.
282 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
283 /// instruction modifies the CPSR register.
284 let Defs = [CPSR] in {
285 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
286 bit Commutable = 0> {
288 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
289 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
290 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
291 let Inst{31-27} = 0b11110;
293 let Inst{24-21} = opcod;
294 let Inst{20} = 1; // The S bit.
298 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
299 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
300 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
301 let isCommutable = Commutable;
302 let Inst{31-27} = 0b11101;
303 let Inst{26-25} = 0b01;
304 let Inst{24-21} = opcod;
305 let Inst{20} = 1; // The S bit.
306 let Inst{14-12} = 0b000; // imm3
307 let Inst{7-6} = 0b00; // imm2
308 let Inst{5-4} = 0b00; // type
311 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
312 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
313 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
314 let Inst{31-27} = 0b11101;
315 let Inst{26-25} = 0b01;
316 let Inst{24-21} = opcod;
317 let Inst{20} = 1; // The S bit.
322 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
323 /// patterns for a binary operation that produces a value.
324 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
325 bit Commutable = 0> {
327 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
328 opc, ".w\t$dst, $lhs, $rhs",
329 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
330 let Inst{31-27} = 0b11110;
333 let Inst{23-21} = op23_21;
334 let Inst{20} = 0; // The S bit.
338 def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
339 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
340 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
341 let Inst{31-27} = 0b11110;
344 let Inst{23-21} = op23_21;
345 let Inst{20} = 0; // The S bit.
349 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
350 opc, ".w\t$dst, $lhs, $rhs",
351 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
352 let isCommutable = Commutable;
353 let Inst{31-27} = 0b11101;
354 let Inst{26-25} = 0b01;
356 let Inst{23-21} = op23_21;
357 let Inst{20} = 0; // The S bit.
358 let Inst{14-12} = 0b000; // imm3
359 let Inst{7-6} = 0b00; // imm2
360 let Inst{5-4} = 0b00; // type
363 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
364 opc, ".w\t$dst, $lhs, $rhs",
365 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
366 let Inst{31-27} = 0b11101;
367 let Inst{26-25} = 0b01;
369 let Inst{23-21} = op23_21;
370 let Inst{20} = 0; // The S bit.
374 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
375 /// for a binary operation that produces a value and use the carry
376 /// bit. It's not predicable.
377 let Uses = [CPSR] in {
378 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
379 bit Commutable = 0> {
381 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
382 opc, "\t$dst, $lhs, $rhs",
383 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
384 Requires<[IsThumb2]> {
385 let Inst{31-27} = 0b11110;
387 let Inst{24-21} = opcod;
388 let Inst{20} = 0; // The S bit.
392 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
393 opc, ".w\t$dst, $lhs, $rhs",
394 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
395 Requires<[IsThumb2]> {
396 let isCommutable = Commutable;
397 let Inst{31-27} = 0b11101;
398 let Inst{26-25} = 0b01;
399 let Inst{24-21} = opcod;
400 let Inst{20} = 0; // The S bit.
401 let Inst{14-12} = 0b000; // imm3
402 let Inst{7-6} = 0b00; // imm2
403 let Inst{5-4} = 0b00; // type
406 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
407 opc, ".w\t$dst, $lhs, $rhs",
408 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
409 Requires<[IsThumb2]> {
410 let Inst{31-27} = 0b11101;
411 let Inst{26-25} = 0b01;
412 let Inst{24-21} = opcod;
413 let Inst{20} = 0; // The S bit.
417 // Carry setting variants
418 let Defs = [CPSR] in {
419 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
420 bit Commutable = 0> {
422 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
423 opc, "\t$dst, $lhs, $rhs",
424 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
425 Requires<[IsThumb2]> {
426 let Inst{31-27} = 0b11110;
428 let Inst{24-21} = opcod;
429 let Inst{20} = 1; // The S bit.
433 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
434 opc, ".w\t$dst, $lhs, $rhs",
435 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
436 Requires<[IsThumb2]> {
437 let isCommutable = Commutable;
438 let Inst{31-27} = 0b11101;
439 let Inst{26-25} = 0b01;
440 let Inst{24-21} = opcod;
441 let Inst{20} = 1; // The S bit.
442 let Inst{14-12} = 0b000; // imm3
443 let Inst{7-6} = 0b00; // imm2
444 let Inst{5-4} = 0b00; // type
447 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
448 opc, ".w\t$dst, $lhs, $rhs",
449 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
450 Requires<[IsThumb2]> {
451 let Inst{31-27} = 0b11101;
452 let Inst{26-25} = 0b01;
453 let Inst{24-21} = opcod;
454 let Inst{20} = 1; // The S bit.
460 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
461 let Defs = [CPSR] in {
462 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
464 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
465 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
466 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
467 let Inst{31-27} = 0b11110;
469 let Inst{24-21} = opcod;
470 let Inst{20} = 1; // The S bit.
474 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
475 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
476 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
477 let Inst{31-27} = 0b11101;
478 let Inst{26-25} = 0b01;
479 let Inst{24-21} = opcod;
480 let Inst{20} = 1; // The S bit.
485 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
486 // rotate operation that produces a value.
487 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
489 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
490 opc, ".w\t$dst, $lhs, $rhs",
491 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
492 let Inst{31-27} = 0b11101;
493 let Inst{26-21} = 0b010010;
494 let Inst{19-16} = 0b1111; // Rn
495 let Inst{5-4} = opcod;
498 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
499 opc, ".w\t$dst, $lhs, $rhs",
500 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
501 let Inst{31-27} = 0b11111;
502 let Inst{26-23} = 0b0100;
503 let Inst{22-21} = opcod;
504 let Inst{15-12} = 0b1111;
505 let Inst{7-4} = 0b0000;
509 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
510 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
511 /// a explicit result, only implicitly set CPSR.
512 let Defs = [CPSR] in {
513 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
515 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
516 opc, ".w\t$lhs, $rhs",
517 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
518 let Inst{31-27} = 0b11110;
520 let Inst{24-21} = opcod;
521 let Inst{20} = 1; // The S bit.
523 let Inst{11-8} = 0b1111; // Rd
526 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
527 opc, ".w\t$lhs, $rhs",
528 [(opnode GPR:$lhs, GPR:$rhs)]> {
529 let Inst{31-27} = 0b11101;
530 let Inst{26-25} = 0b01;
531 let Inst{24-21} = opcod;
532 let Inst{20} = 1; // The S bit.
533 let Inst{14-12} = 0b000; // imm3
534 let Inst{11-8} = 0b1111; // Rd
535 let Inst{7-6} = 0b00; // imm2
536 let Inst{5-4} = 0b00; // type
539 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
540 opc, ".w\t$lhs, $rhs",
541 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
542 let Inst{31-27} = 0b11101;
543 let Inst{26-25} = 0b01;
544 let Inst{24-21} = opcod;
545 let Inst{20} = 1; // The S bit.
546 let Inst{11-8} = 0b1111; // Rd
551 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
552 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
553 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
554 opc, ".w\t$dst, $addr",
555 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
556 let Inst{31-27} = 0b11111;
557 let Inst{26-25} = 0b00;
558 let Inst{24} = signed;
560 let Inst{22-21} = opcod;
561 let Inst{20} = 1; // load
563 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
564 opc, "\t$dst, $addr",
565 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
566 let Inst{31-27} = 0b11111;
567 let Inst{26-25} = 0b00;
568 let Inst{24} = signed;
570 let Inst{22-21} = opcod;
571 let Inst{20} = 1; // load
573 // Offset: index==TRUE, wback==FALSE
574 let Inst{10} = 1; // The P bit.
575 let Inst{8} = 0; // The W bit.
577 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
578 opc, ".w\t$dst, $addr",
579 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
580 let Inst{31-27} = 0b11111;
581 let Inst{26-25} = 0b00;
582 let Inst{24} = signed;
584 let Inst{22-21} = opcod;
585 let Inst{20} = 1; // load
586 let Inst{11-6} = 0b000000;
588 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
589 opc, ".w\t$dst, $addr",
590 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
591 let isReMaterializable = 1;
592 let Inst{31-27} = 0b11111;
593 let Inst{26-25} = 0b00;
594 let Inst{24} = signed;
595 let Inst{23} = ?; // add = (U == '1')
596 let Inst{22-21} = opcod;
597 let Inst{20} = 1; // load
598 let Inst{19-16} = 0b1111; // Rn
602 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
603 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
604 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
605 opc, ".w\t$src, $addr",
606 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
607 let Inst{31-27} = 0b11111;
608 let Inst{26-23} = 0b0001;
609 let Inst{22-21} = opcod;
610 let Inst{20} = 0; // !load
612 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
613 opc, "\t$src, $addr",
614 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
615 let Inst{31-27} = 0b11111;
616 let Inst{26-23} = 0b0000;
617 let Inst{22-21} = opcod;
618 let Inst{20} = 0; // !load
620 // Offset: index==TRUE, wback==FALSE
621 let Inst{10} = 1; // The P bit.
622 let Inst{8} = 0; // The W bit.
624 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
625 opc, ".w\t$src, $addr",
626 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
627 let Inst{31-27} = 0b11111;
628 let Inst{26-23} = 0b0000;
629 let Inst{22-21} = opcod;
630 let Inst{20} = 0; // !load
631 let Inst{11-6} = 0b000000;
635 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
636 /// register and one whose operand is a register rotated by 8/16/24.
637 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
638 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
639 opc, ".w\t$dst, $src",
640 [(set GPR:$dst, (opnode GPR:$src))]>,
641 Requires<[HasT2ExtractPack]> {
642 let Inst{31-27} = 0b11111;
643 let Inst{26-23} = 0b0100;
644 let Inst{22-20} = opcod;
645 let Inst{19-16} = 0b1111; // Rn
646 let Inst{15-12} = 0b1111;
648 let Inst{5-4} = 0b00; // rotate
650 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
651 opc, ".w\t$dst, $src, ror $rot",
652 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
653 Requires<[HasT2ExtractPack]> {
654 let Inst{31-27} = 0b11111;
655 let Inst{26-23} = 0b0100;
656 let Inst{22-20} = opcod;
657 let Inst{19-16} = 0b1111; // Rn
658 let Inst{15-12} = 0b1111;
660 let Inst{5-4} = {?,?}; // rotate
664 // SXTB16 and UXTB16 do not need the .w qualifier.
665 multiclass T2I_unary_rrot_nw<bits<3> opcod, string opc, PatFrag opnode> {
666 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
668 [(set GPR:$dst, (opnode GPR:$src))]>,
669 Requires<[HasT2ExtractPack]> {
670 let Inst{31-27} = 0b11111;
671 let Inst{26-23} = 0b0100;
672 let Inst{22-20} = opcod;
673 let Inst{19-16} = 0b1111; // Rn
674 let Inst{15-12} = 0b1111;
676 let Inst{5-4} = 0b00; // rotate
678 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
679 opc, "\t$dst, $src, ror $rot",
680 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
681 Requires<[HasT2ExtractPack]> {
682 let Inst{31-27} = 0b11111;
683 let Inst{26-23} = 0b0100;
684 let Inst{22-20} = opcod;
685 let Inst{19-16} = 0b1111; // Rn
686 let Inst{15-12} = 0b1111;
688 let Inst{5-4} = {?,?}; // rotate
692 // DO variant - disassembly only, no pattern
694 multiclass T2I_unary_rrot_DO<bits<3> opcod, string opc> {
695 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
696 opc, "\t$dst, $src", []> {
697 let Inst{31-27} = 0b11111;
698 let Inst{26-23} = 0b0100;
699 let Inst{22-20} = opcod;
700 let Inst{19-16} = 0b1111; // Rn
701 let Inst{15-12} = 0b1111;
703 let Inst{5-4} = 0b00; // rotate
705 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
706 opc, "\t$dst, $src, ror $rot", []> {
707 let Inst{31-27} = 0b11111;
708 let Inst{26-23} = 0b0100;
709 let Inst{22-20} = opcod;
710 let Inst{19-16} = 0b1111; // Rn
711 let Inst{15-12} = 0b1111;
713 let Inst{5-4} = {?,?}; // rotate
717 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
718 /// register and one whose operand is a register rotated by 8/16/24.
719 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
720 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
721 opc, "\t$dst, $LHS, $RHS",
722 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
723 Requires<[HasT2ExtractPack]> {
724 let Inst{31-27} = 0b11111;
725 let Inst{26-23} = 0b0100;
726 let Inst{22-20} = opcod;
727 let Inst{15-12} = 0b1111;
729 let Inst{5-4} = 0b00; // rotate
731 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
732 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
733 [(set GPR:$dst, (opnode GPR:$LHS,
734 (rotr GPR:$RHS, rot_imm:$rot)))]>,
735 Requires<[HasT2ExtractPack]> {
736 let Inst{31-27} = 0b11111;
737 let Inst{26-23} = 0b0100;
738 let Inst{22-20} = opcod;
739 let Inst{15-12} = 0b1111;
741 let Inst{5-4} = {?,?}; // rotate
745 // DO variant - disassembly only, no pattern
747 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
748 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
749 opc, "\t$dst, $LHS, $RHS", []> {
750 let Inst{31-27} = 0b11111;
751 let Inst{26-23} = 0b0100;
752 let Inst{22-20} = opcod;
753 let Inst{15-12} = 0b1111;
755 let Inst{5-4} = 0b00; // rotate
757 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
758 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
759 let Inst{31-27} = 0b11111;
760 let Inst{26-23} = 0b0100;
761 let Inst{22-20} = opcod;
762 let Inst{15-12} = 0b1111;
764 let Inst{5-4} = {?,?}; // rotate
768 //===----------------------------------------------------------------------===//
770 //===----------------------------------------------------------------------===//
772 //===----------------------------------------------------------------------===//
773 // Miscellaneous Instructions.
776 // LEApcrel - Load a pc-relative address into a register without offending the
778 let neverHasSideEffects = 1 in {
779 let isReMaterializable = 1 in
780 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
781 "adr$p.w\t$dst, #$label", []> {
782 let Inst{31-27} = 0b11110;
783 let Inst{25-24} = 0b10;
784 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
787 let Inst{19-16} = 0b1111; // Rn
790 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
791 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
792 "adr$p.w\t$dst, #${label}_${id}", []> {
793 let Inst{31-27} = 0b11110;
794 let Inst{25-24} = 0b10;
795 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
798 let Inst{19-16} = 0b1111; // Rn
801 } // neverHasSideEffects
803 // ADD r, sp, {so_imm|i12}
804 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
805 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
806 let Inst{31-27} = 0b11110;
808 let Inst{24-21} = 0b1000;
809 let Inst{20} = ?; // The S bit.
810 let Inst{19-16} = 0b1101; // Rn = sp
813 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
814 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
815 let Inst{31-27} = 0b11110;
817 let Inst{24-21} = 0b0000;
818 let Inst{20} = 0; // The S bit.
819 let Inst{19-16} = 0b1101; // Rn = sp
824 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
825 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
826 let Inst{31-27} = 0b11101;
827 let Inst{26-25} = 0b01;
828 let Inst{24-21} = 0b1000;
829 let Inst{20} = ?; // The S bit.
830 let Inst{19-16} = 0b1101; // Rn = sp
834 // SUB r, sp, {so_imm|i12}
835 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
836 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
837 let Inst{31-27} = 0b11110;
839 let Inst{24-21} = 0b1101;
840 let Inst{20} = ?; // The S bit.
841 let Inst{19-16} = 0b1101; // Rn = sp
844 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
845 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
846 let Inst{31-27} = 0b11110;
848 let Inst{24-21} = 0b0101;
849 let Inst{20} = 0; // The S bit.
850 let Inst{19-16} = 0b1101; // Rn = sp
855 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
857 "sub", "\t$dst, $sp, $rhs", []> {
858 let Inst{31-27} = 0b11101;
859 let Inst{26-25} = 0b01;
860 let Inst{24-21} = 0b1101;
861 let Inst{20} = ?; // The S bit.
862 let Inst{19-16} = 0b1101; // Rn = sp
866 // Signed and unsigned division on v7-M
867 def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
868 "sdiv", "\t$dst, $a, $b",
869 [(set GPR:$dst, (sdiv GPR:$a, GPR:$b))]>,
870 Requires<[HasDivide]> {
871 let Inst{31-27} = 0b11111;
872 let Inst{26-21} = 0b011100;
874 let Inst{15-12} = 0b1111;
875 let Inst{7-4} = 0b1111;
878 def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
879 "udiv", "\t$dst, $a, $b",
880 [(set GPR:$dst, (udiv GPR:$a, GPR:$b))]>,
881 Requires<[HasDivide]> {
882 let Inst{31-27} = 0b11111;
883 let Inst{26-21} = 0b011101;
885 let Inst{15-12} = 0b1111;
886 let Inst{7-4} = 0b1111;
889 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
890 let usesCustomInserter = 1 in { // Expanded after instruction selection.
891 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
892 NoItinerary, "${:comment} sub.w\t$dst, $sp, $imm", []>;
893 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
894 NoItinerary, "${:comment} subw\t$dst, $sp, $imm", []>;
895 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
896 NoItinerary, "${:comment} sub\t$dst, $sp, $rhs", []>;
897 } // usesCustomInserter
900 //===----------------------------------------------------------------------===//
901 // Load / store Instructions.
905 let canFoldAsLoad = 1, isReMaterializable = 1 in
906 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
908 // Loads with zero extension
909 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
910 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
912 // Loads with sign extension
913 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
914 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
916 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
918 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
919 (ins t2addrmode_imm8s4:$addr),
920 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
921 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
922 (ins i32imm:$addr), IIC_iLoadi,
923 "ldrd", "\t$dst1, $addr", []> {
924 let Inst{19-16} = 0b1111; // Rn
926 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
928 // zextload i1 -> zextload i8
929 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
930 (t2LDRBi12 t2addrmode_imm12:$addr)>;
931 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
932 (t2LDRBi8 t2addrmode_imm8:$addr)>;
933 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
934 (t2LDRBs t2addrmode_so_reg:$addr)>;
935 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
936 (t2LDRBpci tconstpool:$addr)>;
938 // extload -> zextload
939 // FIXME: Reduce the number of patterns by legalizing extload to zextload
941 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
942 (t2LDRBi12 t2addrmode_imm12:$addr)>;
943 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
944 (t2LDRBi8 t2addrmode_imm8:$addr)>;
945 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
946 (t2LDRBs t2addrmode_so_reg:$addr)>;
947 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
948 (t2LDRBpci tconstpool:$addr)>;
950 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
951 (t2LDRBi12 t2addrmode_imm12:$addr)>;
952 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
953 (t2LDRBi8 t2addrmode_imm8:$addr)>;
954 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
955 (t2LDRBs t2addrmode_so_reg:$addr)>;
956 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
957 (t2LDRBpci tconstpool:$addr)>;
959 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
960 (t2LDRHi12 t2addrmode_imm12:$addr)>;
961 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
962 (t2LDRHi8 t2addrmode_imm8:$addr)>;
963 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
964 (t2LDRHs t2addrmode_so_reg:$addr)>;
965 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
966 (t2LDRHpci tconstpool:$addr)>;
969 let mayLoad = 1, neverHasSideEffects = 1 in {
970 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
971 (ins t2addrmode_imm8:$addr),
972 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
973 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
976 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
977 (ins GPR:$base, t2am_imm8_offset:$offset),
978 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
979 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
982 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
983 (ins t2addrmode_imm8:$addr),
984 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
985 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
987 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
988 (ins GPR:$base, t2am_imm8_offset:$offset),
989 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
990 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
993 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
994 (ins t2addrmode_imm8:$addr),
995 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
996 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
998 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
999 (ins GPR:$base, t2am_imm8_offset:$offset),
1000 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1001 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
1004 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1005 (ins t2addrmode_imm8:$addr),
1006 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1007 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
1009 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1010 (ins GPR:$base, t2am_imm8_offset:$offset),
1011 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1012 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1015 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1016 (ins t2addrmode_imm8:$addr),
1017 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1018 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1020 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1021 (ins GPR:$base, t2am_imm8_offset:$offset),
1022 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1023 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1025 } // mayLoad = 1, neverHasSideEffects = 1
1027 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1028 // for disassembly only.
1029 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1030 class T2IldT<bit signed, bits<2> type, string opc>
1031 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
1032 "\t$dst, $addr", []> {
1033 let Inst{31-27} = 0b11111;
1034 let Inst{26-25} = 0b00;
1035 let Inst{24} = signed;
1037 let Inst{22-21} = type;
1038 let Inst{20} = 1; // load
1040 let Inst{10-8} = 0b110; // PUW.
1043 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1044 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1045 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1046 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1047 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1050 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1051 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1052 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1055 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1056 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1057 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1058 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1061 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1062 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1063 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1064 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1066 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1068 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1069 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1070 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1071 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1073 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1075 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1076 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1077 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1078 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1080 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1082 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1083 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1084 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1085 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1087 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1089 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1090 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1091 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1092 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1094 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1096 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1097 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1098 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1099 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1101 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1103 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1105 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1106 class T2IstT<bits<2> type, string opc>
1107 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1108 "\t$src, $addr", []> {
1109 let Inst{31-27} = 0b11111;
1110 let Inst{26-25} = 0b00;
1111 let Inst{24} = 0; // not signed
1113 let Inst{22-21} = type;
1114 let Inst{20} = 0; // store
1116 let Inst{10-8} = 0b110; // PUW
1119 def t2STRT : T2IstT<0b10, "strt">;
1120 def t2STRBT : T2IstT<0b00, "strbt">;
1121 def t2STRHT : T2IstT<0b01, "strht">;
1123 // ldrd / strd pre / post variants
1124 // For disassembly only.
1126 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1127 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1128 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1130 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1131 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1132 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1134 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1135 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1136 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1138 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1139 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1140 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>;
1142 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1143 // data/instruction access. These are for disassembly only.
1145 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1146 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1147 multiclass T2Ipl<bit instr, bit write, string opc> {
1149 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc,
1150 "\t[$base, $imm]", []> {
1151 let Inst{31-25} = 0b1111100;
1152 let Inst{24} = instr;
1153 let Inst{23} = 1; // U = 1
1155 let Inst{21} = write;
1157 let Inst{15-12} = 0b1111;
1160 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1161 "\t[$base, $imm]", []> {
1162 let Inst{31-25} = 0b1111100;
1163 let Inst{24} = instr;
1164 let Inst{23} = 0; // U = 0
1166 let Inst{21} = write;
1168 let Inst{15-12} = 0b1111;
1169 let Inst{11-8} = 0b1100;
1172 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1173 "\t[pc, $imm]", []> {
1174 let Inst{31-25} = 0b1111100;
1175 let Inst{24} = instr;
1176 let Inst{23} = ?; // add = (U == 1)
1178 let Inst{21} = write;
1180 let Inst{19-16} = 0b1111; // Rn = 0b1111
1181 let Inst{15-12} = 0b1111;
1184 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc,
1185 "\t[$base, $a]", []> {
1186 let Inst{31-25} = 0b1111100;
1187 let Inst{24} = instr;
1188 let Inst{23} = 0; // add = TRUE for T1
1190 let Inst{21} = write;
1192 let Inst{15-12} = 0b1111;
1193 let Inst{11-6} = 0000000;
1194 let Inst{5-4} = 0b00; // no shift is applied
1197 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc,
1198 "\t[$base, $a, lsl $shamt]", []> {
1199 let Inst{31-25} = 0b1111100;
1200 let Inst{24} = instr;
1201 let Inst{23} = 0; // add = TRUE for T1
1203 let Inst{21} = write;
1205 let Inst{15-12} = 0b1111;
1206 let Inst{11-6} = 0000000;
1210 defm t2PLD : T2Ipl<0, 0, "pld">;
1211 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1212 defm t2PLI : T2Ipl<1, 0, "pli">;
1214 //===----------------------------------------------------------------------===//
1215 // Load / store multiple Instructions.
1218 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1219 def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1220 reglist:$dsts, variable_ops), IIC_iLoadm,
1221 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
1222 let Inst{31-27} = 0b11101;
1223 let Inst{26-25} = 0b00;
1224 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1226 let Inst{21} = 0; // The W bit.
1227 let Inst{20} = 1; // Load
1230 def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1231 reglist:$dsts, variable_ops), IIC_iLoadm,
1232 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
1233 "$addr.addr = $wb", []> {
1234 let Inst{31-27} = 0b11101;
1235 let Inst{26-25} = 0b00;
1236 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1238 let Inst{21} = 1; // The W bit.
1239 let Inst{20} = 1; // Load
1241 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1243 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1244 def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1245 reglist:$srcs, variable_ops), IIC_iStorem,
1246 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
1247 let Inst{31-27} = 0b11101;
1248 let Inst{26-25} = 0b00;
1249 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1251 let Inst{21} = 0; // The W bit.
1252 let Inst{20} = 0; // Store
1255 def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1256 reglist:$srcs, variable_ops),
1258 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
1259 "$addr.addr = $wb", []> {
1260 let Inst{31-27} = 0b11101;
1261 let Inst{26-25} = 0b00;
1262 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1264 let Inst{21} = 1; // The W bit.
1265 let Inst{20} = 0; // Store
1267 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1269 //===----------------------------------------------------------------------===//
1270 // Move Instructions.
1273 let neverHasSideEffects = 1 in
1274 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1275 "mov", ".w\t$dst, $src", []> {
1276 let Inst{31-27} = 0b11101;
1277 let Inst{26-25} = 0b01;
1278 let Inst{24-21} = 0b0010;
1279 let Inst{20} = ?; // The S bit.
1280 let Inst{19-16} = 0b1111; // Rn
1281 let Inst{14-12} = 0b000;
1282 let Inst{7-4} = 0b0000;
1285 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1286 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1287 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1288 "mov", ".w\t$dst, $src",
1289 [(set GPR:$dst, t2_so_imm:$src)]> {
1290 let Inst{31-27} = 0b11110;
1292 let Inst{24-21} = 0b0010;
1293 let Inst{20} = ?; // The S bit.
1294 let Inst{19-16} = 0b1111; // Rn
1298 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1299 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1300 "movw", "\t$dst, $src",
1301 [(set GPR:$dst, imm0_65535:$src)]> {
1302 let Inst{31-27} = 0b11110;
1304 let Inst{24-21} = 0b0010;
1305 let Inst{20} = 0; // The S bit.
1309 let Constraints = "$src = $dst" in
1310 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
1311 "movt", "\t$dst, $imm",
1313 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
1314 let Inst{31-27} = 0b11110;
1316 let Inst{24-21} = 0b0110;
1317 let Inst{20} = 0; // The S bit.
1321 def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
1323 //===----------------------------------------------------------------------===//
1324 // Extend Instructions.
1329 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1330 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1331 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1332 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1333 defm t2SXTB16 : T2I_unary_rrot_DO<0b010, "sxtb16">;
1335 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1336 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1337 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1338 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1339 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1341 // TODO: SXT(A){B|H}16 - done for disassembly only
1345 let AddedComplexity = 16 in {
1346 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1347 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1348 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1349 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1350 defm t2UXTB16 : T2I_unary_rrot_nw<0b011, "uxtb16",
1351 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1353 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1354 (t2UXTB16r_rot GPR:$Src, 24)>;
1355 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1356 (t2UXTB16r_rot GPR:$Src, 8)>;
1358 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1359 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1360 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1361 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1362 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1365 //===----------------------------------------------------------------------===//
1366 // Arithmetic Instructions.
1369 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1370 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1371 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1372 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1374 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1375 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1376 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1377 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1378 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1380 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1381 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1382 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1383 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1384 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1385 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1386 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1387 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1390 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1391 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1392 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1393 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1395 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1396 let AddedComplexity = 1 in
1397 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1398 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1399 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1400 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1401 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1402 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1404 // Select Bytes -- for disassembly only
1406 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1407 "\t$dst, $a, $b", []> {
1408 let Inst{31-27} = 0b11111;
1409 let Inst{26-24} = 0b010;
1411 let Inst{22-20} = 0b010;
1412 let Inst{15-12} = 0b1111;
1414 let Inst{6-4} = 0b000;
1417 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1418 // And Miscellaneous operations -- for disassembly only
1419 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc>
1420 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
1421 "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> {
1422 let Inst{31-27} = 0b11111;
1423 let Inst{26-23} = 0b0101;
1424 let Inst{22-20} = op22_20;
1425 let Inst{15-12} = 0b1111;
1426 let Inst{7-4} = op7_4;
1429 // Saturating add/subtract -- for disassembly only
1431 def t2QADD : T2I_pam<0b000, 0b1000, "qadd">;
1432 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1433 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1434 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1435 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1436 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1437 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1438 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">;
1439 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1440 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1441 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1442 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1443 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1444 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1445 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1446 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1448 // Signed/Unsigned add/subtract -- for disassembly only
1450 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1451 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1452 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1453 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1454 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1455 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1456 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1457 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1458 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1459 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1460 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1461 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1463 // Signed/Unsigned halving add/subtract -- for disassembly only
1465 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1466 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1467 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1468 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1469 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1470 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1471 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1472 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1473 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1474 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1475 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1476 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1478 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1480 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1481 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1482 let Inst{15-12} = 0b1111;
1484 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst),
1485 (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8",
1486 "\t$dst, $a, $b, $acc", []>;
1488 // Signed/Unsigned saturate -- for disassembly only
1490 def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1491 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1492 [/* For disassembly only; pattern left blank */]> {
1493 let Inst{31-27} = 0b11110;
1494 let Inst{25-22} = 0b1100;
1497 let Inst{21} = 0; // sh = '0'
1500 def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1501 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1502 [/* For disassembly only; pattern left blank */]> {
1503 let Inst{31-27} = 0b11110;
1504 let Inst{25-22} = 0b1100;
1507 let Inst{21} = 1; // sh = '1'
1510 def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1511 "ssat16", "\t$dst, $bit_pos, $a",
1512 [/* For disassembly only; pattern left blank */]> {
1513 let Inst{31-27} = 0b11110;
1514 let Inst{25-22} = 0b1100;
1517 let Inst{21} = 1; // sh = '1'
1518 let Inst{14-12} = 0b000; // imm3 = '000'
1519 let Inst{7-6} = 0b00; // imm2 = '00'
1522 def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1523 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1524 [/* For disassembly only; pattern left blank */]> {
1525 let Inst{31-27} = 0b11110;
1526 let Inst{25-22} = 0b1110;
1529 let Inst{21} = 0; // sh = '0'
1532 def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1533 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1534 [/* For disassembly only; pattern left blank */]> {
1535 let Inst{31-27} = 0b11110;
1536 let Inst{25-22} = 0b1110;
1539 let Inst{21} = 1; // sh = '1'
1542 def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1543 "usat16", "\t$dst, $bit_pos, $a",
1544 [/* For disassembly only; pattern left blank */]> {
1545 let Inst{31-27} = 0b11110;
1546 let Inst{25-22} = 0b1110;
1549 let Inst{21} = 1; // sh = '1'
1550 let Inst{14-12} = 0b000; // imm3 = '000'
1551 let Inst{7-6} = 0b00; // imm2 = '00'
1554 //===----------------------------------------------------------------------===//
1555 // Shift and rotate Instructions.
1558 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1559 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1560 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1561 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1563 let Uses = [CPSR] in {
1564 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1565 "rrx", "\t$dst, $src",
1566 [(set GPR:$dst, (ARMrrx GPR:$src))]> {
1567 let Inst{31-27} = 0b11101;
1568 let Inst{26-25} = 0b01;
1569 let Inst{24-21} = 0b0010;
1570 let Inst{20} = ?; // The S bit.
1571 let Inst{19-16} = 0b1111; // Rn
1572 let Inst{14-12} = 0b000;
1573 let Inst{7-4} = 0b0011;
1577 let Defs = [CPSR] in {
1578 def t2MOVsrl_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1579 "lsrs", ".w\t$dst, $src, #1",
1580 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
1581 let Inst{31-27} = 0b11101;
1582 let Inst{26-25} = 0b01;
1583 let Inst{24-21} = 0b0010;
1584 let Inst{20} = 1; // The S bit.
1585 let Inst{19-16} = 0b1111; // Rn
1586 let Inst{5-4} = 0b01; // Shift type.
1587 // Shift amount = Inst{14-12:7-6} = 1.
1588 let Inst{14-12} = 0b000;
1589 let Inst{7-6} = 0b01;
1591 def t2MOVsra_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1592 "asrs", ".w\t$dst, $src, #1",
1593 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
1594 let Inst{31-27} = 0b11101;
1595 let Inst{26-25} = 0b01;
1596 let Inst{24-21} = 0b0010;
1597 let Inst{20} = 1; // The S bit.
1598 let Inst{19-16} = 0b1111; // Rn
1599 let Inst{5-4} = 0b10; // Shift type.
1600 // Shift amount = Inst{14-12:7-6} = 1.
1601 let Inst{14-12} = 0b000;
1602 let Inst{7-6} = 0b01;
1606 //===----------------------------------------------------------------------===//
1607 // Bitwise Instructions.
1610 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1611 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1612 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1613 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1614 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1615 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1617 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1618 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1620 let Constraints = "$src = $dst" in
1621 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1622 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1623 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
1624 let Inst{31-27} = 0b11110;
1626 let Inst{24-20} = 0b10110;
1627 let Inst{19-16} = 0b1111; // Rn
1631 def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1632 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1633 let Inst{31-27} = 0b11110;
1635 let Inst{24-20} = 0b10100;
1639 def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1640 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1641 let Inst{31-27} = 0b11110;
1643 let Inst{24-20} = 0b11100;
1647 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1648 // Added for disassembler with the pattern field purposely left blank.
1649 // FIXME: Utilize this instruction in codgen.
1650 def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1651 IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> {
1652 let Inst{31-27} = 0b11110;
1654 let Inst{24-20} = 0b10110;
1658 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1661 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1662 let AddedComplexity = 1 in
1663 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1666 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
1667 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
1669 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1670 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
1671 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
1672 Requires<[IsThumb2]>;
1674 def : T2Pat<(t2_so_imm_not:$src),
1675 (t2MVNi t2_so_imm_not:$src)>;
1677 //===----------------------------------------------------------------------===//
1678 // Multiply Instructions.
1680 let isCommutable = 1 in
1681 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1682 "mul", "\t$dst, $a, $b",
1683 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
1684 let Inst{31-27} = 0b11111;
1685 let Inst{26-23} = 0b0110;
1686 let Inst{22-20} = 0b000;
1687 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1688 let Inst{7-4} = 0b0000; // Multiply
1691 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1692 "mla", "\t$dst, $a, $b, $c",
1693 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
1694 let Inst{31-27} = 0b11111;
1695 let Inst{26-23} = 0b0110;
1696 let Inst{22-20} = 0b000;
1697 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1698 let Inst{7-4} = 0b0000; // Multiply
1701 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1702 "mls", "\t$dst, $a, $b, $c",
1703 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
1704 let Inst{31-27} = 0b11111;
1705 let Inst{26-23} = 0b0110;
1706 let Inst{22-20} = 0b000;
1707 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1708 let Inst{7-4} = 0b0001; // Multiply and Subtract
1711 // Extra precision multiplies with low / high results
1712 let neverHasSideEffects = 1 in {
1713 let isCommutable = 1 in {
1714 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1715 "smull", "\t$ldst, $hdst, $a, $b", []> {
1716 let Inst{31-27} = 0b11111;
1717 let Inst{26-23} = 0b0111;
1718 let Inst{22-20} = 0b000;
1719 let Inst{7-4} = 0b0000;
1722 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1723 "umull", "\t$ldst, $hdst, $a, $b", []> {
1724 let Inst{31-27} = 0b11111;
1725 let Inst{26-23} = 0b0111;
1726 let Inst{22-20} = 0b010;
1727 let Inst{7-4} = 0b0000;
1731 // Multiply + accumulate
1732 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1733 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1734 let Inst{31-27} = 0b11111;
1735 let Inst{26-23} = 0b0111;
1736 let Inst{22-20} = 0b100;
1737 let Inst{7-4} = 0b0000;
1740 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1741 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1742 let Inst{31-27} = 0b11111;
1743 let Inst{26-23} = 0b0111;
1744 let Inst{22-20} = 0b110;
1745 let Inst{7-4} = 0b0000;
1748 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1749 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1750 let Inst{31-27} = 0b11111;
1751 let Inst{26-23} = 0b0111;
1752 let Inst{22-20} = 0b110;
1753 let Inst{7-4} = 0b0110;
1755 } // neverHasSideEffects
1757 // Rounding variants of the below included for disassembly only
1759 // Most significant word multiply
1760 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1761 "smmul", "\t$dst, $a, $b",
1762 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
1763 let Inst{31-27} = 0b11111;
1764 let Inst{26-23} = 0b0110;
1765 let Inst{22-20} = 0b101;
1766 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1767 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1770 def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1771 "smmulr", "\t$dst, $a, $b", []> {
1772 let Inst{31-27} = 0b11111;
1773 let Inst{26-23} = 0b0110;
1774 let Inst{22-20} = 0b101;
1775 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1776 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1779 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1780 "smmla", "\t$dst, $a, $b, $c",
1781 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
1782 let Inst{31-27} = 0b11111;
1783 let Inst{26-23} = 0b0110;
1784 let Inst{22-20} = 0b101;
1785 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1786 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1789 def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1790 "smmlar", "\t$dst, $a, $b, $c", []> {
1791 let Inst{31-27} = 0b11111;
1792 let Inst{26-23} = 0b0110;
1793 let Inst{22-20} = 0b101;
1794 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1795 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1798 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1799 "smmls", "\t$dst, $a, $b, $c",
1800 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
1801 let Inst{31-27} = 0b11111;
1802 let Inst{26-23} = 0b0110;
1803 let Inst{22-20} = 0b110;
1804 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1805 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1808 def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1809 "smmlsr", "\t$dst, $a, $b, $c", []> {
1810 let Inst{31-27} = 0b11111;
1811 let Inst{26-23} = 0b0110;
1812 let Inst{22-20} = 0b110;
1813 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1814 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1817 multiclass T2I_smul<string opc, PatFrag opnode> {
1818 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1819 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1820 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1821 (sext_inreg GPR:$b, i16)))]> {
1822 let Inst{31-27} = 0b11111;
1823 let Inst{26-23} = 0b0110;
1824 let Inst{22-20} = 0b001;
1825 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1826 let Inst{7-6} = 0b00;
1827 let Inst{5-4} = 0b00;
1830 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1831 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1832 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1833 (sra GPR:$b, (i32 16))))]> {
1834 let Inst{31-27} = 0b11111;
1835 let Inst{26-23} = 0b0110;
1836 let Inst{22-20} = 0b001;
1837 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1838 let Inst{7-6} = 0b00;
1839 let Inst{5-4} = 0b01;
1842 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1843 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1844 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1845 (sext_inreg GPR:$b, i16)))]> {
1846 let Inst{31-27} = 0b11111;
1847 let Inst{26-23} = 0b0110;
1848 let Inst{22-20} = 0b001;
1849 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1850 let Inst{7-6} = 0b00;
1851 let Inst{5-4} = 0b10;
1854 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1855 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1856 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1857 (sra GPR:$b, (i32 16))))]> {
1858 let Inst{31-27} = 0b11111;
1859 let Inst{26-23} = 0b0110;
1860 let Inst{22-20} = 0b001;
1861 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1862 let Inst{7-6} = 0b00;
1863 let Inst{5-4} = 0b11;
1866 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1867 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1868 [(set GPR:$dst, (sra (opnode GPR:$a,
1869 (sext_inreg GPR:$b, i16)), (i32 16)))]> {
1870 let Inst{31-27} = 0b11111;
1871 let Inst{26-23} = 0b0110;
1872 let Inst{22-20} = 0b011;
1873 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1874 let Inst{7-6} = 0b00;
1875 let Inst{5-4} = 0b00;
1878 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1879 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1880 [(set GPR:$dst, (sra (opnode GPR:$a,
1881 (sra GPR:$b, (i32 16))), (i32 16)))]> {
1882 let Inst{31-27} = 0b11111;
1883 let Inst{26-23} = 0b0110;
1884 let Inst{22-20} = 0b011;
1885 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1886 let Inst{7-6} = 0b00;
1887 let Inst{5-4} = 0b01;
1892 multiclass T2I_smla<string opc, PatFrag opnode> {
1893 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1894 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1895 [(set GPR:$dst, (add GPR:$acc,
1896 (opnode (sext_inreg GPR:$a, i16),
1897 (sext_inreg GPR:$b, i16))))]> {
1898 let Inst{31-27} = 0b11111;
1899 let Inst{26-23} = 0b0110;
1900 let Inst{22-20} = 0b001;
1901 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1902 let Inst{7-6} = 0b00;
1903 let Inst{5-4} = 0b00;
1906 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1907 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1908 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1909 (sra GPR:$b, (i32 16)))))]> {
1910 let Inst{31-27} = 0b11111;
1911 let Inst{26-23} = 0b0110;
1912 let Inst{22-20} = 0b001;
1913 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1914 let Inst{7-6} = 0b00;
1915 let Inst{5-4} = 0b01;
1918 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1919 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1920 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1921 (sext_inreg GPR:$b, i16))))]> {
1922 let Inst{31-27} = 0b11111;
1923 let Inst{26-23} = 0b0110;
1924 let Inst{22-20} = 0b001;
1925 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1926 let Inst{7-6} = 0b00;
1927 let Inst{5-4} = 0b10;
1930 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1931 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1932 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1933 (sra GPR:$b, (i32 16)))))]> {
1934 let Inst{31-27} = 0b11111;
1935 let Inst{26-23} = 0b0110;
1936 let Inst{22-20} = 0b001;
1937 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1938 let Inst{7-6} = 0b00;
1939 let Inst{5-4} = 0b11;
1942 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1943 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1944 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1945 (sext_inreg GPR:$b, i16)), (i32 16))))]> {
1946 let Inst{31-27} = 0b11111;
1947 let Inst{26-23} = 0b0110;
1948 let Inst{22-20} = 0b011;
1949 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1950 let Inst{7-6} = 0b00;
1951 let Inst{5-4} = 0b00;
1954 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1955 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1956 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1957 (sra GPR:$b, (i32 16))), (i32 16))))]> {
1958 let Inst{31-27} = 0b11111;
1959 let Inst{26-23} = 0b0110;
1960 let Inst{22-20} = 0b011;
1961 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1962 let Inst{7-6} = 0b00;
1963 let Inst{5-4} = 0b01;
1967 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1968 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1970 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
1971 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst),
1972 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1973 [/* For disassembly only; pattern left blank */]>;
1974 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst),
1975 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1976 [/* For disassembly only; pattern left blank */]>;
1977 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst),
1978 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
1979 [/* For disassembly only; pattern left blank */]>;
1980 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst),
1981 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
1982 [/* For disassembly only; pattern left blank */]>;
1984 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1985 // These are for disassembly only.
1987 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1988 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
1989 let Inst{15-12} = 0b1111;
1991 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1992 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
1993 let Inst{15-12} = 0b1111;
1995 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1996 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
1997 let Inst{15-12} = 0b1111;
1999 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2000 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2001 let Inst{15-12} = 0b1111;
2003 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst),
2004 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad",
2005 "\t$dst, $a, $b, $acc", []>;
2006 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst),
2007 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx",
2008 "\t$dst, $a, $b, $acc", []>;
2009 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst),
2010 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd",
2011 "\t$dst, $a, $b, $acc", []>;
2012 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst),
2013 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx",
2014 "\t$dst, $a, $b, $acc", []>;
2015 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst),
2016 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald",
2017 "\t$ldst, $hdst, $a, $b", []>;
2018 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst),
2019 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx",
2020 "\t$ldst, $hdst, $a, $b", []>;
2021 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst),
2022 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld",
2023 "\t$ldst, $hdst, $a, $b", []>;
2024 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst),
2025 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx",
2026 "\t$ldst, $hdst, $a, $b", []>;
2028 //===----------------------------------------------------------------------===//
2029 // Misc. Arithmetic Instructions.
2032 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2033 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2034 : T2I<oops, iops, itin, opc, asm, pattern> {
2035 let Inst{31-27} = 0b11111;
2036 let Inst{26-22} = 0b01010;
2037 let Inst{21-20} = op1;
2038 let Inst{15-12} = 0b1111;
2039 let Inst{7-6} = 0b10;
2040 let Inst{5-4} = op2;
2043 def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2044 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
2046 def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2047 "rbit", "\t$dst, $src",
2048 [(set GPR:$dst, (ARMrbit GPR:$src))]>;
2050 def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2051 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
2053 def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2054 "rev16", ".w\t$dst, $src",
2056 (or (and (srl GPR:$src, (i32 8)), 0xFF),
2057 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
2058 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
2059 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
2061 def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2062 "revsh", ".w\t$dst, $src",
2065 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
2066 (shl GPR:$src, (i32 8))), i16))]>;
2068 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2069 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2070 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
2071 (and (shl GPR:$src2, (i32 imm:$shamt)),
2073 Requires<[HasT2ExtractPack]> {
2074 let Inst{31-27} = 0b11101;
2075 let Inst{26-25} = 0b01;
2076 let Inst{24-20} = 0b01100;
2077 let Inst{5} = 0; // BT form
2081 // Alternate cases for PKHBT where identities eliminate some nodes.
2082 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
2083 (t2PKHBT GPR:$src1, GPR:$src2, 0)>,
2084 Requires<[HasT2ExtractPack]>;
2085 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
2086 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>,
2087 Requires<[HasT2ExtractPack]>;
2089 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2090 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2091 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
2092 (and (sra GPR:$src2, imm16_31:$shamt),
2094 Requires<[HasT2ExtractPack]> {
2095 let Inst{31-27} = 0b11101;
2096 let Inst{26-25} = 0b01;
2097 let Inst{24-20} = 0b01100;
2098 let Inst{5} = 1; // TB form
2102 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2103 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2104 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
2105 (t2PKHTB GPR:$src1, GPR:$src2, 16)>,
2106 Requires<[HasT2ExtractPack]>;
2107 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
2108 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
2109 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>,
2110 Requires<[HasT2ExtractPack]>;
2112 //===----------------------------------------------------------------------===//
2113 // Comparison Instructions...
2116 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2117 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2118 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2119 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2121 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2122 // Compare-to-zero still works out, just not the relationals
2123 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2124 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2125 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2126 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2128 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2129 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2131 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2132 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2134 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2135 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2136 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2137 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2139 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
2140 // Short range conditional branch. Looks awesome for loops. Need to figure
2141 // out how to use this one.
2144 // Conditional moves
2145 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2146 // a two-value operand where a dag node expects two operands. :(
2147 let neverHasSideEffects = 1 in {
2148 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
2149 "mov", ".w\t$dst, $true",
2150 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
2151 RegConstraint<"$false = $dst"> {
2152 let Inst{31-27} = 0b11101;
2153 let Inst{26-25} = 0b01;
2154 let Inst{24-21} = 0b0010;
2155 let Inst{20} = 0; // The S bit.
2156 let Inst{19-16} = 0b1111; // Rn
2157 let Inst{14-12} = 0b000;
2158 let Inst{7-4} = 0b0000;
2161 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
2162 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2163 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2164 RegConstraint<"$false = $dst"> {
2165 let Inst{31-27} = 0b11110;
2167 let Inst{24-21} = 0b0010;
2168 let Inst{20} = 0; // The S bit.
2169 let Inst{19-16} = 0b1111; // Rn
2173 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2174 string opc, string asm, list<dag> pattern>
2175 : T2I<oops, iops, itin, opc, asm, pattern> {
2176 let Inst{31-27} = 0b11101;
2177 let Inst{26-25} = 0b01;
2178 let Inst{24-21} = 0b0010;
2179 let Inst{20} = 0; // The S bit.
2180 let Inst{19-16} = 0b1111; // Rn
2181 let Inst{5-4} = opcod; // Shift type.
2183 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
2184 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2185 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2186 RegConstraint<"$false = $dst">;
2187 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
2188 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2189 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2190 RegConstraint<"$false = $dst">;
2191 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
2192 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2193 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2194 RegConstraint<"$false = $dst">;
2195 def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
2196 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2197 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2198 RegConstraint<"$false = $dst">;
2199 } // neverHasSideEffects
2201 //===----------------------------------------------------------------------===//
2202 // Atomic operations intrinsics
2205 // memory barriers protect the atomic sequences
2206 let hasSideEffects = 1 in {
2207 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
2208 ThumbFrm, NoItinerary,
2210 [(ARMMemBarrierV7)]>,
2211 Requires<[IsThumb2]> {
2212 let Inst{31-4} = 0xF3BF8F5;
2213 // FIXME: add support for options other than a full system DMB
2214 let Inst{3-0} = 0b1111;
2217 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
2218 ThumbFrm, NoItinerary,
2220 [(ARMSyncBarrierV7)]>,
2221 Requires<[IsThumb2]> {
2222 let Inst{31-4} = 0xF3BF8F4;
2223 // FIXME: add support for options other than a full system DSB
2224 let Inst{3-0} = 0b1111;
2228 // Helper class for multiclass T2MemB -- for disassembly only
2229 class T2I_memb<string opc, string asm>
2230 : T2I<(outs), (ins), NoItinerary, opc, asm,
2231 [/* For disassembly only; pattern left blank */]>,
2232 Requires<[IsThumb2, HasV7]> {
2233 let Inst{31-20} = 0xf3b;
2234 let Inst{15-14} = 0b10;
2238 multiclass T2MemB<bits<4> op7_4, string opc> {
2240 def st : T2I_memb<opc, "\tst"> {
2241 let Inst{7-4} = op7_4;
2242 let Inst{3-0} = 0b1110;
2245 def ish : T2I_memb<opc, "\tish"> {
2246 let Inst{7-4} = op7_4;
2247 let Inst{3-0} = 0b1011;
2250 def ishst : T2I_memb<opc, "\tishst"> {
2251 let Inst{7-4} = op7_4;
2252 let Inst{3-0} = 0b1010;
2255 def nsh : T2I_memb<opc, "\tnsh"> {
2256 let Inst{7-4} = op7_4;
2257 let Inst{3-0} = 0b0111;
2260 def nshst : T2I_memb<opc, "\tnshst"> {
2261 let Inst{7-4} = op7_4;
2262 let Inst{3-0} = 0b0110;
2265 def osh : T2I_memb<opc, "\tosh"> {
2266 let Inst{7-4} = op7_4;
2267 let Inst{3-0} = 0b0011;
2270 def oshst : T2I_memb<opc, "\toshst"> {
2271 let Inst{7-4} = op7_4;
2272 let Inst{3-0} = 0b0010;
2276 // These DMB variants are for disassembly only.
2277 defm t2DMB : T2MemB<0b0101, "dmb">;
2279 // These DSB variants are for disassembly only.
2280 defm t2DSB : T2MemB<0b0100, "dsb">;
2282 // ISB has only full system option -- for disassembly only
2283 def t2ISBsy : T2I_memb<"isb", ""> {
2284 let Inst{7-4} = 0b0110;
2285 let Inst{3-0} = 0b1111;
2288 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2289 InstrItinClass itin, string opc, string asm, string cstr,
2290 list<dag> pattern, bits<4> rt2 = 0b1111>
2291 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2292 let Inst{31-27} = 0b11101;
2293 let Inst{26-20} = 0b0001101;
2294 let Inst{11-8} = rt2;
2295 let Inst{7-6} = 0b01;
2296 let Inst{5-4} = opcod;
2297 let Inst{3-0} = 0b1111;
2299 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2300 InstrItinClass itin, string opc, string asm, string cstr,
2301 list<dag> pattern, bits<4> rt2 = 0b1111>
2302 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2303 let Inst{31-27} = 0b11101;
2304 let Inst{26-20} = 0b0001100;
2305 let Inst{11-8} = rt2;
2306 let Inst{7-6} = 0b01;
2307 let Inst{5-4} = opcod;
2310 let mayLoad = 1 in {
2311 def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2312 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2314 def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2315 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2317 def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2318 Size4Bytes, NoItinerary,
2319 "ldrex", "\t$dest, [$ptr]", "",
2321 let Inst{31-27} = 0b11101;
2322 let Inst{26-20} = 0b0000101;
2323 let Inst{11-8} = 0b1111;
2324 let Inst{7-0} = 0b00000000; // imm8 = 0
2326 def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2327 AddrModeNone, Size4Bytes, NoItinerary,
2328 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2332 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2333 def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2334 AddrModeNone, Size4Bytes, NoItinerary,
2335 "strexb", "\t$success, $src, [$ptr]", "", []>;
2336 def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2337 AddrModeNone, Size4Bytes, NoItinerary,
2338 "strexh", "\t$success, $src, [$ptr]", "", []>;
2339 def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2340 AddrModeNone, Size4Bytes, NoItinerary,
2341 "strex", "\t$success, $src, [$ptr]", "",
2343 let Inst{31-27} = 0b11101;
2344 let Inst{26-20} = 0b0000100;
2345 let Inst{7-0} = 0b00000000; // imm8 = 0
2347 def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
2348 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2349 AddrModeNone, Size4Bytes, NoItinerary,
2350 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2354 // Clear-Exclusive is for disassembly only.
2355 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2356 [/* For disassembly only; pattern left blank */]>,
2357 Requires<[IsARM, HasV7]> {
2358 let Inst{31-20} = 0xf3b;
2359 let Inst{15-14} = 0b10;
2361 let Inst{7-4} = 0b0010;
2364 //===----------------------------------------------------------------------===//
2368 // __aeabi_read_tp preserves the registers r1-r3.
2370 Defs = [R0, R12, LR, CPSR] in {
2371 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2372 "bl\t__aeabi_read_tp",
2373 [(set R0, ARMthread_pointer)]> {
2374 let Inst{31-27} = 0b11110;
2375 let Inst{15-14} = 0b11;
2380 //===----------------------------------------------------------------------===//
2381 // SJLJ Exception handling intrinsics
2382 // eh_sjlj_setjmp() is an instruction sequence to store the return
2383 // address and save #0 in R0 for the non-longjmp case.
2384 // Since by its nature we may be coming from some other function to get
2385 // here, and we're using the stack frame for the containing function to
2386 // save/restore registers, we can't keep anything live in regs across
2387 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2388 // when we get here from a longjmp(). We force everthing out of registers
2389 // except for our own input by listing the relevant registers in Defs. By
2390 // doing so, we also cause the prologue/epilogue code to actively preserve
2391 // all of the callee-saved resgisters, which is exactly what we want.
2392 // $val is a scratch register for our use.
2394 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2395 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2396 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2397 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2398 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2399 AddrModeNone, SizeSpecial, NoItinerary,
2400 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2401 "adds\t$val, #7\n\t"
2402 "str\t$val, [$src, #4]\n\t"
2405 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2407 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2408 Requires<[IsThumb2, HasVFP2]>;
2412 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2413 hasSideEffects = 1, isBarrier = 1 in {
2414 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2415 AddrModeNone, SizeSpecial, NoItinerary,
2416 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2417 "adds\t$val, #7\n\t"
2418 "str\t$val, [$src, #4]\n\t"
2421 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2423 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>,
2424 Requires<[IsThumb2, NoVFP]>;
2428 //===----------------------------------------------------------------------===//
2429 // Control-Flow Instructions
2432 // FIXME: remove when we have a way to marking a MI with these properties.
2433 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2435 // FIXME: Should pc be an implicit operand like PICADD, etc?
2436 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2437 hasExtraDefRegAllocReq = 1 in
2438 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
2439 reglist:$dsts, variable_ops), IIC_Br,
2440 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts",
2441 "$addr.addr = $wb", []> {
2442 let Inst{31-27} = 0b11101;
2443 let Inst{26-25} = 0b00;
2444 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2446 let Inst{21} = 1; // The W bit.
2447 let Inst{20} = 1; // Load
2450 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2451 let isPredicable = 1 in
2452 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2454 [(br bb:$target)]> {
2455 let Inst{31-27} = 0b11110;
2456 let Inst{15-14} = 0b10;
2460 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2463 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2464 IIC_Br, "mov\tpc, $target\n$jt",
2465 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2466 let Inst{31-27} = 0b11101;
2467 let Inst{26-20} = 0b0100100;
2468 let Inst{19-16} = 0b1111;
2469 let Inst{14-12} = 0b000;
2470 let Inst{11-8} = 0b1111; // Rd = pc
2471 let Inst{7-4} = 0b0000;
2474 // FIXME: Add a non-pc based case that can be predicated.
2477 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2478 IIC_Br, "tbb\t$index\n$jt", []> {
2479 let Inst{31-27} = 0b11101;
2480 let Inst{26-20} = 0b0001101;
2481 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2482 let Inst{15-8} = 0b11110000;
2483 let Inst{7-4} = 0b0000; // B form
2488 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2489 IIC_Br, "tbh\t$index\n$jt", []> {
2490 let Inst{31-27} = 0b11101;
2491 let Inst{26-20} = 0b0001101;
2492 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2493 let Inst{15-8} = 0b11110000;
2494 let Inst{7-4} = 0b0001; // H form
2497 // Generic versions of the above two instructions, for disassembly only
2499 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2500 "tbb", "\t[$a, $b]", []>{
2501 let Inst{31-27} = 0b11101;
2502 let Inst{26-20} = 0b0001101;
2503 let Inst{15-8} = 0b11110000;
2504 let Inst{7-4} = 0b0000; // B form
2507 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2508 "tbh", "\t[$a, $b, lsl #1]", []> {
2509 let Inst{31-27} = 0b11101;
2510 let Inst{26-20} = 0b0001101;
2511 let Inst{15-8} = 0b11110000;
2512 let Inst{7-4} = 0b0001; // H form
2514 } // isNotDuplicable, isIndirectBranch
2516 } // isBranch, isTerminator, isBarrier
2518 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2519 // a two-value operand where a dag node expects two operands. :(
2520 let isBranch = 1, isTerminator = 1 in
2521 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2523 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2524 let Inst{31-27} = 0b11110;
2525 let Inst{15-14} = 0b10;
2531 let Defs = [ITSTATE] in
2532 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2533 AddrModeNone, Size2Bytes, IIC_iALUx,
2534 "it$mask\t$cc", "", []> {
2535 // 16-bit instruction.
2536 let Inst{31-16} = 0x0000;
2537 let Inst{15-8} = 0b10111111;
2540 // Branch and Exchange Jazelle -- for disassembly only
2542 def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2543 [/* For disassembly only; pattern left blank */]> {
2544 let Inst{31-27} = 0b11110;
2546 let Inst{25-20} = 0b111100;
2547 let Inst{15-14} = 0b10;
2551 // Change Processor State is a system instruction -- for disassembly only.
2552 // The singleton $opt operand contains the following information:
2553 // opt{4-0} = mode from Inst{4-0}
2554 // opt{5} = changemode from Inst{17}
2555 // opt{8-6} = AIF from Inst{8-6}
2556 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2557 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2558 [/* For disassembly only; pattern left blank */]> {
2559 let Inst{31-27} = 0b11110;
2561 let Inst{25-20} = 0b111010;
2562 let Inst{15-14} = 0b10;
2566 // A6.3.4 Branches and miscellaneous control
2567 // Table A6-14 Change Processor State, and hint instructions
2568 // Helper class for disassembly only.
2569 class T2I_hint<bits<8> op7_0, string opc, string asm>
2570 : T2I<(outs), (ins), NoItinerary, opc, asm,
2571 [/* For disassembly only; pattern left blank */]> {
2572 let Inst{31-20} = 0xf3a;
2573 let Inst{15-14} = 0b10;
2575 let Inst{10-8} = 0b000;
2576 let Inst{7-0} = op7_0;
2579 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2580 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2581 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2582 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2583 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2585 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2586 [/* For disassembly only; pattern left blank */]> {
2587 let Inst{31-20} = 0xf3a;
2588 let Inst{15-14} = 0b10;
2590 let Inst{10-8} = 0b000;
2591 let Inst{7-4} = 0b1111;
2594 // Secure Monitor Call is a system instruction -- for disassembly only
2595 // Option = Inst{19-16}
2596 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2597 [/* For disassembly only; pattern left blank */]> {
2598 let Inst{31-27} = 0b11110;
2599 let Inst{26-20} = 0b1111111;
2600 let Inst{15-12} = 0b1000;
2603 // Store Return State is a system instruction -- for disassembly only
2604 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2605 [/* For disassembly only; pattern left blank */]> {
2606 let Inst{31-27} = 0b11101;
2607 let Inst{26-20} = 0b0000010; // W = 1
2610 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2611 [/* For disassembly only; pattern left blank */]> {
2612 let Inst{31-27} = 0b11101;
2613 let Inst{26-20} = 0b0000000; // W = 0
2616 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2617 [/* For disassembly only; pattern left blank */]> {
2618 let Inst{31-27} = 0b11101;
2619 let Inst{26-20} = 0b0011010; // W = 1
2622 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2623 [/* For disassembly only; pattern left blank */]> {
2624 let Inst{31-27} = 0b11101;
2625 let Inst{26-20} = 0b0011000; // W = 0
2628 // Return From Exception is a system instruction -- for disassembly only
2629 def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!",
2630 [/* For disassembly only; pattern left blank */]> {
2631 let Inst{31-27} = 0b11101;
2632 let Inst{26-20} = 0b0000011; // W = 1
2635 def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base",
2636 [/* For disassembly only; pattern left blank */]> {
2637 let Inst{31-27} = 0b11101;
2638 let Inst{26-20} = 0b0000001; // W = 0
2641 def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!",
2642 [/* For disassembly only; pattern left blank */]> {
2643 let Inst{31-27} = 0b11101;
2644 let Inst{26-20} = 0b0011011; // W = 1
2647 def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base",
2648 [/* For disassembly only; pattern left blank */]> {
2649 let Inst{31-27} = 0b11101;
2650 let Inst{26-20} = 0b0011001; // W = 0
2653 //===----------------------------------------------------------------------===//
2654 // Non-Instruction Patterns
2657 // Two piece so_imms.
2658 def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
2659 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2660 (t2_so_imm2part_2 imm:$RHS))>;
2661 def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
2662 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2663 (t2_so_imm2part_2 imm:$RHS))>;
2664 def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
2665 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2666 (t2_so_imm2part_2 imm:$RHS))>;
2667 def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS),
2668 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2669 (t2_so_neg_imm2part_2 imm:$RHS))>;
2671 // 32-bit immediate using movw + movt.
2672 // This is a single pseudo instruction to make it re-materializable. Remove
2673 // when we can do generalized remat.
2674 let isReMaterializable = 1 in
2675 def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2676 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2677 [(set GPR:$dst, (i32 imm:$src))]>;
2679 // ConstantPool, GlobalAddress, and JumpTable
2680 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2681 Requires<[IsThumb2, DontUseMovt]>;
2682 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2683 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2684 Requires<[IsThumb2, UseMovt]>;
2686 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2687 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2689 // Pseudo instruction that combines ldr from constpool and add pc. This should
2690 // be expanded into two instructions late to allow if-conversion and
2692 let canFoldAsLoad = 1, isReMaterializable = 1 in
2693 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2695 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2696 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2698 Requires<[IsThumb2]>;
2700 //===----------------------------------------------------------------------===//
2701 // Move between special register and ARM core register -- for disassembly only
2705 def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2706 [/* For disassembly only; pattern left blank */]> {
2707 let Inst{31-27} = 0b11110;
2709 let Inst{25-21} = 0b11111;
2710 let Inst{20} = 0; // The R bit.
2711 let Inst{15-14} = 0b10;
2716 def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2717 [/* For disassembly only; pattern left blank */]> {
2718 let Inst{31-27} = 0b11110;
2720 let Inst{25-21} = 0b11111;
2721 let Inst{20} = 1; // The R bit.
2722 let Inst{15-14} = 0b10;
2727 def t2MSR : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
2728 "\tcpsr$mask, $src",
2729 [/* For disassembly only; pattern left blank */]> {
2730 let Inst{31-27} = 0b11110;
2732 let Inst{25-21} = 0b11100;
2733 let Inst{20} = 0; // The R bit.
2734 let Inst{15-14} = 0b10;
2739 def t2MSRsys : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
2740 "\tspsr$mask, $src",
2741 [/* For disassembly only; pattern left blank */]> {
2742 let Inst{31-27} = 0b11110;
2744 let Inst{25-21} = 0b11100;
2745 let Inst{20} = 1; // The R bit.
2746 let Inst{15-14} = 0b10;