1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
66 // described for so_imm_notSext def below, with sign extension from 16
68 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
69 APInt apIntN = N->getAPIntValue();
70 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
71 return CurDAG->getTargetConstant(~N16bitSignExt, MVT::i32);
74 // t2_so_imm - Match a 32-bit immediate operand, which is an
75 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
76 // immediate splatted into multiple bytes of the word.
77 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
78 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
79 return ARM_AM::getT2SOImmVal(Imm) != -1;
81 let ParserMatchClass = t2_so_imm_asmoperand;
82 let EncoderMethod = "getT2SOImmOpValue";
83 let DecoderMethod = "DecodeT2SOImm";
86 // t2_so_imm_not - Match an immediate that is a complement
88 // Note: this pattern doesn't require an encoder method and such, as it's
89 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
90 // is handled by the destination instructions, which use t2_so_imm.
91 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
92 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
93 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
94 }], t2_so_imm_not_XFORM> {
95 let ParserMatchClass = t2_so_imm_not_asmoperand;
98 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
99 // if the upper 16 bits are zero.
100 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
101 APInt apIntN = N->getAPIntValue();
102 if (!apIntN.isIntN(16)) return false;
103 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
104 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
105 }], t2_so_imm_notSext16_XFORM> {
106 let ParserMatchClass = t2_so_imm_not_asmoperand;
109 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
110 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
111 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
112 int64_t Value = -(int)N->getZExtValue();
113 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
114 }], t2_so_imm_neg_XFORM> {
115 let ParserMatchClass = t2_so_imm_neg_asmoperand;
118 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
119 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
120 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
121 return Imm >= 0 && Imm < 4096;
123 let ParserMatchClass = imm0_4095_asmoperand;
126 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
127 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
128 return (uint32_t)(-N->getZExtValue()) < 4096;
130 let ParserMatchClass = imm0_4095_neg_asmoperand;
133 def imm1_255_neg : PatLeaf<(i32 imm), [{
134 uint32_t Val = -N->getZExtValue();
135 return (Val > 0 && Val < 255);
138 def imm0_255_not : PatLeaf<(i32 imm), [{
139 return (uint32_t)(~N->getZExtValue()) < 255;
142 def lo5AllOne : PatLeaf<(i32 imm), [{
143 // Returns true if all low 5-bits are 1.
144 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
147 // Define Thumb2 specific addressing modes.
149 // t2addrmode_imm12 := reg + imm12
150 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
151 def t2addrmode_imm12 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
153 let PrintMethod = "printAddrModeImm12Operand<false>";
154 let EncoderMethod = "getAddrModeImm12OpValue";
155 let DecoderMethod = "DecodeT2AddrModeImm12";
156 let ParserMatchClass = t2addrmode_imm12_asmoperand;
157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
160 // t2ldrlabel := imm12
161 def t2ldrlabel : Operand<i32> {
162 let EncoderMethod = "getAddrModeImm12OpValue";
163 let PrintMethod = "printThumbLdrLabelOperand";
166 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
167 def t2ldr_pcrel_imm12 : Operand<i32> {
168 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
169 // used for assembler pseudo instruction and maps to t2ldrlabel, so
170 // doesn't need encoder or print methods of its own.
173 // ADR instruction labels.
174 def t2adrlabel : Operand<i32> {
175 let EncoderMethod = "getT2AdrLabelOpValue";
176 let PrintMethod = "printAdrLabelOperand<0>";
179 // t2addrmode_posimm8 := reg + imm8
180 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
181 def t2addrmode_posimm8 : Operand<i32> {
182 let PrintMethod = "printT2AddrModeImm8Operand<false>";
183 let EncoderMethod = "getT2AddrModeImm8OpValue";
184 let DecoderMethod = "DecodeT2AddrModeImm8";
185 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
189 // t2addrmode_negimm8 := reg - imm8
190 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
191 def t2addrmode_negimm8 : Operand<i32>,
192 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
193 let PrintMethod = "printT2AddrModeImm8Operand<false>";
194 let EncoderMethod = "getT2AddrModeImm8OpValue";
195 let DecoderMethod = "DecodeT2AddrModeImm8";
196 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
197 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
200 // t2addrmode_imm8 := reg +/- imm8
201 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
202 class T2AddrMode_Imm8 : Operand<i32>,
203 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
204 let EncoderMethod = "getT2AddrModeImm8OpValue";
205 let DecoderMethod = "DecodeT2AddrModeImm8";
206 let ParserMatchClass = MemImm8OffsetAsmOperand;
207 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
210 def t2addrmode_imm8 : T2AddrMode_Imm8 {
211 let PrintMethod = "printT2AddrModeImm8Operand<false>";
214 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
215 let PrintMethod = "printT2AddrModeImm8Operand<true>";
218 def t2am_imm8_offset : Operand<i32>,
219 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
220 [], [SDNPWantRoot]> {
221 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
222 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
223 let DecoderMethod = "DecodeT2Imm8";
226 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
227 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
228 class T2AddrMode_Imm8s4 : Operand<i32> {
229 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
230 let DecoderMethod = "DecodeT2AddrModeImm8s4";
231 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
232 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
235 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
236 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
239 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
240 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
243 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
244 def t2am_imm8s4_offset : Operand<i32> {
245 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
246 let EncoderMethod = "getT2Imm8s4OpValue";
247 let DecoderMethod = "DecodeT2Imm8S4";
250 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
251 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
252 let Name = "MemImm0_1020s4Offset";
254 def t2addrmode_imm0_1020s4 : Operand<i32>,
255 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
256 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
257 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
258 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
259 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
260 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
263 // t2addrmode_so_reg := reg + (reg << imm2)
264 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
265 def t2addrmode_so_reg : Operand<i32>,
266 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
267 let PrintMethod = "printT2AddrModeSoRegOperand";
268 let EncoderMethod = "getT2AddrModeSORegOpValue";
269 let DecoderMethod = "DecodeT2AddrModeSOReg";
270 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
271 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
274 // Addresses for the TBB/TBH instructions.
275 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
276 def addrmode_tbb : Operand<i32> {
277 let PrintMethod = "printAddrModeTBB";
278 let ParserMatchClass = addrmode_tbb_asmoperand;
279 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
281 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
282 def addrmode_tbh : Operand<i32> {
283 let PrintMethod = "printAddrModeTBH";
284 let ParserMatchClass = addrmode_tbh_asmoperand;
285 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
288 //===----------------------------------------------------------------------===//
289 // Multiclass helpers...
293 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
294 string opc, string asm, list<dag> pattern>
295 : T2I<oops, iops, itin, opc, asm, pattern> {
300 let Inst{26} = imm{11};
301 let Inst{14-12} = imm{10-8};
302 let Inst{7-0} = imm{7-0};
306 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
307 string opc, string asm, list<dag> pattern>
308 : T2sI<oops, iops, itin, opc, asm, pattern> {
314 let Inst{26} = imm{11};
315 let Inst{14-12} = imm{10-8};
316 let Inst{7-0} = imm{7-0};
319 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
320 string opc, string asm, list<dag> pattern>
321 : T2I<oops, iops, itin, opc, asm, pattern> {
325 let Inst{19-16} = Rn;
326 let Inst{26} = imm{11};
327 let Inst{14-12} = imm{10-8};
328 let Inst{7-0} = imm{7-0};
332 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
333 string opc, string asm, list<dag> pattern>
334 : T2I<oops, iops, itin, opc, asm, pattern> {
339 let Inst{3-0} = ShiftedRm{3-0};
340 let Inst{5-4} = ShiftedRm{6-5};
341 let Inst{14-12} = ShiftedRm{11-9};
342 let Inst{7-6} = ShiftedRm{8-7};
345 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
346 string opc, string asm, list<dag> pattern>
347 : T2sI<oops, iops, itin, opc, asm, pattern> {
352 let Inst{3-0} = ShiftedRm{3-0};
353 let Inst{5-4} = ShiftedRm{6-5};
354 let Inst{14-12} = ShiftedRm{11-9};
355 let Inst{7-6} = ShiftedRm{8-7};
358 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
359 string opc, string asm, list<dag> pattern>
360 : T2I<oops, iops, itin, opc, asm, pattern> {
364 let Inst{19-16} = Rn;
365 let Inst{3-0} = ShiftedRm{3-0};
366 let Inst{5-4} = ShiftedRm{6-5};
367 let Inst{14-12} = ShiftedRm{11-9};
368 let Inst{7-6} = ShiftedRm{8-7};
371 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
372 string opc, string asm, list<dag> pattern>
373 : T2I<oops, iops, itin, opc, asm, pattern> {
381 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
382 string opc, string asm, list<dag> pattern>
383 : T2sI<oops, iops, itin, opc, asm, pattern> {
391 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
392 string opc, string asm, list<dag> pattern>
393 : T2I<oops, iops, itin, opc, asm, pattern> {
397 let Inst{19-16} = Rn;
402 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : T2I<oops, iops, itin, opc, asm, pattern> {
410 let Inst{19-16} = Rn;
411 let Inst{26} = imm{11};
412 let Inst{14-12} = imm{10-8};
413 let Inst{7-0} = imm{7-0};
416 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
417 string opc, string asm, list<dag> pattern>
418 : T2sI<oops, iops, itin, opc, asm, pattern> {
424 let Inst{19-16} = Rn;
425 let Inst{26} = imm{11};
426 let Inst{14-12} = imm{10-8};
427 let Inst{7-0} = imm{7-0};
430 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
431 string opc, string asm, list<dag> pattern>
432 : T2I<oops, iops, itin, opc, asm, pattern> {
439 let Inst{14-12} = imm{4-2};
440 let Inst{7-6} = imm{1-0};
443 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
444 string opc, string asm, list<dag> pattern>
445 : T2sI<oops, iops, itin, opc, asm, pattern> {
452 let Inst{14-12} = imm{4-2};
453 let Inst{7-6} = imm{1-0};
456 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
457 string opc, string asm, list<dag> pattern>
458 : T2I<oops, iops, itin, opc, asm, pattern> {
464 let Inst{19-16} = Rn;
468 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : T2sI<oops, iops, itin, opc, asm, pattern> {
476 let Inst{19-16} = Rn;
480 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
481 string opc, string asm, list<dag> pattern>
482 : T2I<oops, iops, itin, opc, asm, pattern> {
488 let Inst{19-16} = Rn;
489 let Inst{3-0} = ShiftedRm{3-0};
490 let Inst{5-4} = ShiftedRm{6-5};
491 let Inst{14-12} = ShiftedRm{11-9};
492 let Inst{7-6} = ShiftedRm{8-7};
495 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
496 string opc, string asm, list<dag> pattern>
497 : T2sI<oops, iops, itin, opc, asm, pattern> {
503 let Inst{19-16} = Rn;
504 let Inst{3-0} = ShiftedRm{3-0};
505 let Inst{5-4} = ShiftedRm{6-5};
506 let Inst{14-12} = ShiftedRm{11-9};
507 let Inst{7-6} = ShiftedRm{8-7};
510 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
511 string opc, string asm, list<dag> pattern>
512 : T2I<oops, iops, itin, opc, asm, pattern> {
518 let Inst{19-16} = Rn;
519 let Inst{15-12} = Ra;
524 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
525 dag oops, dag iops, InstrItinClass itin,
526 string opc, string asm, list<dag> pattern>
527 : T2I<oops, iops, itin, opc, asm, pattern> {
533 let Inst{31-23} = 0b111110111;
534 let Inst{22-20} = opc22_20;
535 let Inst{19-16} = Rn;
536 let Inst{15-12} = RdLo;
537 let Inst{11-8} = RdHi;
538 let Inst{7-4} = opc7_4;
541 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
542 dag oops, dag iops, InstrItinClass itin,
543 string opc, string asm, list<dag> pattern>
544 : T2I<oops, iops, itin, opc, asm, pattern> {
550 let Inst{31-23} = 0b111110111;
551 let Inst{22-20} = opc22_20;
552 let Inst{19-16} = Rn;
553 let Inst{15-12} = RdLo;
554 let Inst{11-8} = RdHi;
555 let Inst{7-4} = opc7_4;
560 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
561 /// binary operation that produces a value. These are predicable and can be
562 /// changed to modify CPSR.
563 multiclass T2I_bin_irs<bits<4> opcod, string opc,
564 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
565 PatFrag opnode, bit Commutable = 0,
568 def ri : T2sTwoRegImm<
569 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
570 opc, "\t$Rd, $Rn, $imm",
571 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
572 Sched<[WriteALU, ReadALU]> {
573 let Inst{31-27} = 0b11110;
575 let Inst{24-21} = opcod;
579 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
580 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
581 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
582 Sched<[WriteALU, ReadALU, ReadALU]> {
583 let isCommutable = Commutable;
584 let Inst{31-27} = 0b11101;
585 let Inst{26-25} = 0b01;
586 let Inst{24-21} = opcod;
587 let Inst{14-12} = 0b000; // imm3
588 let Inst{7-6} = 0b00; // imm2
589 let Inst{5-4} = 0b00; // type
592 def rs : T2sTwoRegShiftedReg<
593 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
594 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
595 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
596 Sched<[WriteALUsi, ReadALU]> {
597 let Inst{31-27} = 0b11101;
598 let Inst{26-25} = 0b01;
599 let Inst{24-21} = opcod;
601 // Assembly aliases for optional destination operand when it's the same
602 // as the source operand.
603 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
604 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
605 t2_so_imm:$imm, pred:$p,
607 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
608 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
611 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
612 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
613 t2_so_reg:$shift, pred:$p,
617 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
618 // the ".w" suffix to indicate that they are wide.
619 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
620 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
621 PatFrag opnode, bit Commutable = 0> :
622 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
623 // Assembler aliases w/ the ".w" suffix.
624 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
625 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
627 // Assembler aliases w/o the ".w" suffix.
628 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
629 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
631 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
632 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
633 pred:$p, cc_out:$s)>;
635 // and with the optional destination operand, too.
636 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
637 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
638 pred:$p, cc_out:$s)>;
639 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
640 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
642 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
643 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
644 pred:$p, cc_out:$s)>;
647 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
648 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
649 /// it is equivalent to the T2I_bin_irs counterpart.
650 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
652 def ri : T2sTwoRegImm<
653 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
654 opc, ".w\t$Rd, $Rn, $imm",
655 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
656 Sched<[WriteALU, ReadALU]> {
657 let Inst{31-27} = 0b11110;
659 let Inst{24-21} = opcod;
663 def rr : T2sThreeReg<
664 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
665 opc, "\t$Rd, $Rn, $Rm",
666 [/* For disassembly only; pattern left blank */]>,
667 Sched<[WriteALU, ReadALU, ReadALU]> {
668 let Inst{31-27} = 0b11101;
669 let Inst{26-25} = 0b01;
670 let Inst{24-21} = opcod;
671 let Inst{14-12} = 0b000; // imm3
672 let Inst{7-6} = 0b00; // imm2
673 let Inst{5-4} = 0b00; // type
676 def rs : T2sTwoRegShiftedReg<
677 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
678 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
679 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
680 Sched<[WriteALUsi, ReadALU]> {
681 let Inst{31-27} = 0b11101;
682 let Inst{26-25} = 0b01;
683 let Inst{24-21} = opcod;
687 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
688 /// instruction modifies the CPSR register.
690 /// These opcodes will be converted to the real non-S opcodes by
691 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
692 let hasPostISelHook = 1, Defs = [CPSR] in {
693 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
694 InstrItinClass iis, PatFrag opnode,
695 bit Commutable = 0> {
697 def ri : t2PseudoInst<(outs rGPR:$Rd),
698 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
700 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
702 Sched<[WriteALU, ReadALU]>;
704 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
706 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
708 Sched<[WriteALU, ReadALU, ReadALU]> {
709 let isCommutable = Commutable;
712 def rs : t2PseudoInst<(outs rGPR:$Rd),
713 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
715 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
716 t2_so_reg:$ShiftedRm))]>,
717 Sched<[WriteALUsi, ReadALUsr]>;
721 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
722 /// operands are reversed.
723 let hasPostISelHook = 1, Defs = [CPSR] in {
724 multiclass T2I_rbin_s_is<PatFrag opnode> {
726 def ri : t2PseudoInst<(outs rGPR:$Rd),
727 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
729 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
731 Sched<[WriteALU, ReadALU]>;
733 def rs : t2PseudoInst<(outs rGPR:$Rd),
734 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
736 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
738 Sched<[WriteALUsi, ReadALU]>;
742 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
743 /// patterns for a binary operation that produces a value.
744 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
745 bit Commutable = 0> {
747 // The register-immediate version is re-materializable. This is useful
748 // in particular for taking the address of a local.
749 let isReMaterializable = 1 in {
750 def ri : T2sTwoRegImm<
751 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
752 opc, ".w\t$Rd, $Rn, $imm",
753 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
754 Sched<[WriteALU, ReadALU]> {
755 let Inst{31-27} = 0b11110;
758 let Inst{23-21} = op23_21;
764 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
765 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
766 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
767 Sched<[WriteALU, ReadALU]> {
771 let Inst{31-27} = 0b11110;
772 let Inst{26} = imm{11};
773 let Inst{25-24} = 0b10;
774 let Inst{23-21} = op23_21;
775 let Inst{20} = 0; // The S bit.
776 let Inst{19-16} = Rn;
778 let Inst{14-12} = imm{10-8};
780 let Inst{7-0} = imm{7-0};
783 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
784 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
785 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
786 Sched<[WriteALU, ReadALU, ReadALU]> {
787 let isCommutable = Commutable;
788 let Inst{31-27} = 0b11101;
789 let Inst{26-25} = 0b01;
791 let Inst{23-21} = op23_21;
792 let Inst{14-12} = 0b000; // imm3
793 let Inst{7-6} = 0b00; // imm2
794 let Inst{5-4} = 0b00; // type
797 def rs : T2sTwoRegShiftedReg<
798 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
799 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
800 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
801 Sched<[WriteALUsi, ReadALU]> {
802 let Inst{31-27} = 0b11101;
803 let Inst{26-25} = 0b01;
805 let Inst{23-21} = op23_21;
809 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
810 /// for a binary operation that produces a value and use the carry
811 /// bit. It's not predicable.
812 let Defs = [CPSR], Uses = [CPSR] in {
813 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
814 bit Commutable = 0> {
816 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
817 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
818 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
819 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
820 let Inst{31-27} = 0b11110;
822 let Inst{24-21} = opcod;
826 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
827 opc, ".w\t$Rd, $Rn, $Rm",
828 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
829 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
830 let isCommutable = Commutable;
831 let Inst{31-27} = 0b11101;
832 let Inst{26-25} = 0b01;
833 let Inst{24-21} = opcod;
834 let Inst{14-12} = 0b000; // imm3
835 let Inst{7-6} = 0b00; // imm2
836 let Inst{5-4} = 0b00; // type
839 def rs : T2sTwoRegShiftedReg<
840 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
841 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
842 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
843 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
844 let Inst{31-27} = 0b11101;
845 let Inst{26-25} = 0b01;
846 let Inst{24-21} = opcod;
851 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
852 // rotate operation that produces a value.
853 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
855 def ri : T2sTwoRegShiftImm<
856 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
857 opc, ".w\t$Rd, $Rm, $imm",
858 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
860 let Inst{31-27} = 0b11101;
861 let Inst{26-21} = 0b010010;
862 let Inst{19-16} = 0b1111; // Rn
863 let Inst{5-4} = opcod;
866 def rr : T2sThreeReg<
867 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
868 opc, ".w\t$Rd, $Rn, $Rm",
869 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
871 let Inst{31-27} = 0b11111;
872 let Inst{26-23} = 0b0100;
873 let Inst{22-21} = opcod;
874 let Inst{15-12} = 0b1111;
875 let Inst{7-4} = 0b0000;
878 // Optional destination register
879 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
880 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
882 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
883 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
886 // Assembler aliases w/o the ".w" suffix.
887 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
888 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
890 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
891 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
894 // and with the optional destination operand, too.
895 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
896 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
898 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
899 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
903 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
904 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
905 /// a explicit result, only implicitly set CPSR.
906 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
907 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
909 let isCompare = 1, Defs = [CPSR] in {
911 def ri : T2OneRegCmpImm<
912 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
913 opc, ".w\t$Rn, $imm",
914 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
915 let Inst{31-27} = 0b11110;
917 let Inst{24-21} = opcod;
918 let Inst{20} = 1; // The S bit.
920 let Inst{11-8} = 0b1111; // Rd
923 def rr : T2TwoRegCmp<
924 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
926 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
927 let Inst{31-27} = 0b11101;
928 let Inst{26-25} = 0b01;
929 let Inst{24-21} = opcod;
930 let Inst{20} = 1; // The S bit.
931 let Inst{14-12} = 0b000; // imm3
932 let Inst{11-8} = 0b1111; // Rd
933 let Inst{7-6} = 0b00; // imm2
934 let Inst{5-4} = 0b00; // type
937 def rs : T2OneRegCmpShiftedReg<
938 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
939 opc, ".w\t$Rn, $ShiftedRm",
940 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
941 Sched<[WriteCMPsi]> {
942 let Inst{31-27} = 0b11101;
943 let Inst{26-25} = 0b01;
944 let Inst{24-21} = opcod;
945 let Inst{20} = 1; // The S bit.
946 let Inst{11-8} = 0b1111; // Rd
950 // Assembler aliases w/o the ".w" suffix.
951 // No alias here for 'rr' version as not all instantiations of this
952 // multiclass want one (CMP in particular, does not).
953 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
954 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
955 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
956 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
959 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
960 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
961 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
963 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
964 opc, ".w\t$Rt, $addr",
965 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
968 let Inst{31-25} = 0b1111100;
969 let Inst{24} = signed;
971 let Inst{22-21} = opcod;
972 let Inst{20} = 1; // load
973 let Inst{19-16} = addr{16-13}; // Rn
974 let Inst{15-12} = Rt;
975 let Inst{11-0} = addr{11-0}; // imm
977 let DecoderMethod = "DecodeT2LoadImm12";
979 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
981 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
984 let Inst{31-27} = 0b11111;
985 let Inst{26-25} = 0b00;
986 let Inst{24} = signed;
988 let Inst{22-21} = opcod;
989 let Inst{20} = 1; // load
990 let Inst{19-16} = addr{12-9}; // Rn
991 let Inst{15-12} = Rt;
993 // Offset: index==TRUE, wback==FALSE
994 let Inst{10} = 1; // The P bit.
995 let Inst{9} = addr{8}; // U
996 let Inst{8} = 0; // The W bit.
997 let Inst{7-0} = addr{7-0}; // imm
999 let DecoderMethod = "DecodeT2LoadImm8";
1001 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1002 opc, ".w\t$Rt, $addr",
1003 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
1004 let Inst{31-27} = 0b11111;
1005 let Inst{26-25} = 0b00;
1006 let Inst{24} = signed;
1008 let Inst{22-21} = opcod;
1009 let Inst{20} = 1; // load
1010 let Inst{11-6} = 0b000000;
1013 let Inst{15-12} = Rt;
1016 let Inst{19-16} = addr{9-6}; // Rn
1017 let Inst{3-0} = addr{5-2}; // Rm
1018 let Inst{5-4} = addr{1-0}; // imm
1020 let DecoderMethod = "DecodeT2LoadShift";
1023 // pci variant is very similar to i12, but supports negative offsets
1025 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1026 opc, ".w\t$Rt, $addr",
1027 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
1028 let isReMaterializable = 1;
1029 let Inst{31-27} = 0b11111;
1030 let Inst{26-25} = 0b00;
1031 let Inst{24} = signed;
1032 let Inst{22-21} = opcod;
1033 let Inst{20} = 1; // load
1034 let Inst{19-16} = 0b1111; // Rn
1037 let Inst{15-12} = Rt{3-0};
1040 let Inst{23} = addr{12}; // add = (U == '1')
1041 let Inst{11-0} = addr{11-0};
1043 let DecoderMethod = "DecodeT2LoadLabel";
1047 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1048 multiclass T2I_st<bits<2> opcod, string opc,
1049 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1051 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1052 opc, ".w\t$Rt, $addr",
1053 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1054 let Inst{31-27} = 0b11111;
1055 let Inst{26-23} = 0b0001;
1056 let Inst{22-21} = opcod;
1057 let Inst{20} = 0; // !load
1060 let Inst{15-12} = Rt;
1063 let addr{12} = 1; // add = TRUE
1064 let Inst{19-16} = addr{16-13}; // Rn
1065 let Inst{23} = addr{12}; // U
1066 let Inst{11-0} = addr{11-0}; // imm
1068 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1069 opc, "\t$Rt, $addr",
1070 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1071 let Inst{31-27} = 0b11111;
1072 let Inst{26-23} = 0b0000;
1073 let Inst{22-21} = opcod;
1074 let Inst{20} = 0; // !load
1076 // Offset: index==TRUE, wback==FALSE
1077 let Inst{10} = 1; // The P bit.
1078 let Inst{8} = 0; // The W bit.
1081 let Inst{15-12} = Rt;
1084 let Inst{19-16} = addr{12-9}; // Rn
1085 let Inst{9} = addr{8}; // U
1086 let Inst{7-0} = addr{7-0}; // imm
1088 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1089 opc, ".w\t$Rt, $addr",
1090 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1091 let Inst{31-27} = 0b11111;
1092 let Inst{26-23} = 0b0000;
1093 let Inst{22-21} = opcod;
1094 let Inst{20} = 0; // !load
1095 let Inst{11-6} = 0b000000;
1098 let Inst{15-12} = Rt;
1101 let Inst{19-16} = addr{9-6}; // Rn
1102 let Inst{3-0} = addr{5-2}; // Rm
1103 let Inst{5-4} = addr{1-0}; // imm
1107 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1108 /// register and one whose operand is a register rotated by 8/16/24.
1109 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1110 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1111 opc, ".w\t$Rd, $Rm$rot",
1112 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1113 Requires<[IsThumb2]> {
1114 let Inst{31-27} = 0b11111;
1115 let Inst{26-23} = 0b0100;
1116 let Inst{22-20} = opcod;
1117 let Inst{19-16} = 0b1111; // Rn
1118 let Inst{15-12} = 0b1111;
1122 let Inst{5-4} = rot{1-0}; // rotate
1125 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1126 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1127 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1128 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1129 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1130 Requires<[HasT2ExtractPack, IsThumb2]> {
1132 let Inst{31-27} = 0b11111;
1133 let Inst{26-23} = 0b0100;
1134 let Inst{22-20} = opcod;
1135 let Inst{19-16} = 0b1111; // Rn
1136 let Inst{15-12} = 0b1111;
1138 let Inst{5-4} = rot;
1141 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1143 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1144 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1145 opc, "\t$Rd, $Rm$rot", []>,
1146 Requires<[IsThumb2, HasT2ExtractPack]> {
1148 let Inst{31-27} = 0b11111;
1149 let Inst{26-23} = 0b0100;
1150 let Inst{22-20} = opcod;
1151 let Inst{19-16} = 0b1111; // Rn
1152 let Inst{15-12} = 0b1111;
1154 let Inst{5-4} = rot;
1157 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1158 /// register and one whose operand is a register rotated by 8/16/24.
1159 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1160 : T2ThreeReg<(outs rGPR:$Rd),
1161 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1162 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1163 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1164 Requires<[HasT2ExtractPack, IsThumb2]> {
1166 let Inst{31-27} = 0b11111;
1167 let Inst{26-23} = 0b0100;
1168 let Inst{22-20} = opcod;
1169 let Inst{15-12} = 0b1111;
1171 let Inst{5-4} = rot;
1174 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1175 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1176 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1178 let Inst{31-27} = 0b11111;
1179 let Inst{26-23} = 0b0100;
1180 let Inst{22-20} = opcod;
1181 let Inst{15-12} = 0b1111;
1183 let Inst{5-4} = rot;
1186 //===----------------------------------------------------------------------===//
1188 //===----------------------------------------------------------------------===//
1190 //===----------------------------------------------------------------------===//
1191 // Miscellaneous Instructions.
1194 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1195 string asm, list<dag> pattern>
1196 : T2XI<oops, iops, itin, asm, pattern> {
1200 let Inst{11-8} = Rd;
1201 let Inst{26} = label{11};
1202 let Inst{14-12} = label{10-8};
1203 let Inst{7-0} = label{7-0};
1206 // LEApcrel - Load a pc-relative address into a register without offending the
1208 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1209 (ins t2adrlabel:$addr, pred:$p),
1210 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1211 Sched<[WriteALU, ReadALU]> {
1212 let Inst{31-27} = 0b11110;
1213 let Inst{25-24} = 0b10;
1214 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1217 let Inst{19-16} = 0b1111; // Rn
1222 let Inst{11-8} = Rd;
1223 let Inst{23} = addr{12};
1224 let Inst{21} = addr{12};
1225 let Inst{26} = addr{11};
1226 let Inst{14-12} = addr{10-8};
1227 let Inst{7-0} = addr{7-0};
1229 let DecoderMethod = "DecodeT2Adr";
1232 let neverHasSideEffects = 1, isReMaterializable = 1 in
1233 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1234 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1235 let hasSideEffects = 1 in
1236 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1237 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1239 []>, Sched<[WriteALU, ReadALU]>;
1242 //===----------------------------------------------------------------------===//
1243 // Load / store Instructions.
1247 let canFoldAsLoad = 1, isReMaterializable = 1 in
1248 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1249 UnOpFrag<(load node:$Src)>>;
1251 // Loads with zero extension
1252 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1253 GPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1254 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1255 GPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1257 // Loads with sign extension
1258 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1259 GPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1260 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1261 GPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1263 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1265 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1266 (ins t2addrmode_imm8s4:$addr),
1267 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1268 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1270 // zextload i1 -> zextload i8
1271 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1272 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1273 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1274 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1275 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1276 (t2LDRBs t2addrmode_so_reg:$addr)>;
1277 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1278 (t2LDRBpci tconstpool:$addr)>;
1280 // extload -> zextload
1281 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1283 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1284 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1285 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1286 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1287 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1288 (t2LDRBs t2addrmode_so_reg:$addr)>;
1289 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1290 (t2LDRBpci tconstpool:$addr)>;
1292 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1293 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1294 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1295 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1296 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1297 (t2LDRBs t2addrmode_so_reg:$addr)>;
1298 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1299 (t2LDRBpci tconstpool:$addr)>;
1301 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1302 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1303 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1304 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1305 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1306 (t2LDRHs t2addrmode_so_reg:$addr)>;
1307 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1308 (t2LDRHpci tconstpool:$addr)>;
1310 // FIXME: The destination register of the loads and stores can't be PC, but
1311 // can be SP. We need another regclass (similar to rGPR) to represent
1312 // that. Not a pressing issue since these are selected manually,
1317 let mayLoad = 1, neverHasSideEffects = 1 in {
1318 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1319 (ins t2addrmode_imm8_pre:$addr),
1320 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1321 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1323 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1326 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1327 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1328 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1329 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1331 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1332 (ins t2addrmode_imm8_pre:$addr),
1333 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1334 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1336 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1338 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1339 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1340 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1341 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1343 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1344 (ins t2addrmode_imm8_pre:$addr),
1345 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1346 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1348 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1350 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1351 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1352 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1353 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1355 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1356 (ins t2addrmode_imm8_pre:$addr),
1357 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1358 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1360 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1362 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1363 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1364 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1365 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1367 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1368 (ins t2addrmode_imm8_pre:$addr),
1369 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1370 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1372 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1374 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1375 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1376 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1377 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1378 } // mayLoad = 1, neverHasSideEffects = 1
1380 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1381 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1382 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1383 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1384 "\t$Rt, $addr", []> {
1387 let Inst{31-27} = 0b11111;
1388 let Inst{26-25} = 0b00;
1389 let Inst{24} = signed;
1391 let Inst{22-21} = type;
1392 let Inst{20} = 1; // load
1393 let Inst{19-16} = addr{12-9};
1394 let Inst{15-12} = Rt;
1396 let Inst{10-8} = 0b110; // PUW.
1397 let Inst{7-0} = addr{7-0};
1399 let DecoderMethod = "DecodeT2LoadT";
1402 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1403 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1404 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1405 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1406 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1409 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1410 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1411 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1412 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1413 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1414 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1417 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1418 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1419 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1420 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1424 let mayStore = 1, neverHasSideEffects = 1 in {
1425 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1426 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1427 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1428 "str", "\t$Rt, $addr!",
1429 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1430 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1432 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1433 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1434 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1435 "strh", "\t$Rt, $addr!",
1436 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1437 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1440 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1441 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1442 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1443 "strb", "\t$Rt, $addr!",
1444 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1445 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1447 } // mayStore = 1, neverHasSideEffects = 1
1449 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1450 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1451 t2am_imm8_offset:$offset),
1452 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1453 "str", "\t$Rt, $Rn$offset",
1454 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1455 [(set GPRnopc:$Rn_wb,
1456 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1457 t2am_imm8_offset:$offset))]>;
1459 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1460 (ins rGPR:$Rt, addr_offset_none:$Rn,
1461 t2am_imm8_offset:$offset),
1462 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1463 "strh", "\t$Rt, $Rn$offset",
1464 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1465 [(set GPRnopc:$Rn_wb,
1466 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1467 t2am_imm8_offset:$offset))]>;
1469 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1470 (ins rGPR:$Rt, addr_offset_none:$Rn,
1471 t2am_imm8_offset:$offset),
1472 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1473 "strb", "\t$Rt, $Rn$offset",
1474 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1475 [(set GPRnopc:$Rn_wb,
1476 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1477 t2am_imm8_offset:$offset))]>;
1479 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1480 // put the patterns on the instruction definitions directly as ISel wants
1481 // the address base and offset to be separate operands, not a single
1482 // complex operand like we represent the instructions themselves. The
1483 // pseudos map between the two.
1484 let usesCustomInserter = 1,
1485 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1486 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1487 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1489 [(set GPRnopc:$Rn_wb,
1490 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1491 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1492 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1494 [(set GPRnopc:$Rn_wb,
1495 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1496 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1497 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1499 [(set GPRnopc:$Rn_wb,
1500 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1503 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1505 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1506 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1507 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1508 "\t$Rt, $addr", []> {
1509 let Inst{31-27} = 0b11111;
1510 let Inst{26-25} = 0b00;
1511 let Inst{24} = 0; // not signed
1513 let Inst{22-21} = type;
1514 let Inst{20} = 0; // store
1516 let Inst{10-8} = 0b110; // PUW
1520 let Inst{15-12} = Rt;
1521 let Inst{19-16} = addr{12-9};
1522 let Inst{7-0} = addr{7-0};
1525 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1526 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1527 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1529 // ldrd / strd pre / post variants
1530 // For disassembly only.
1532 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1533 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1534 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1535 let AsmMatchConverter = "cvtT2LdrdPre";
1536 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1539 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1540 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1541 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1542 "$addr.base = $wb", []>;
1544 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1545 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1546 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1547 "$addr.base = $wb", []> {
1548 let AsmMatchConverter = "cvtT2StrdPre";
1549 let DecoderMethod = "DecodeT2STRDPreInstruction";
1552 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1553 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1554 t2am_imm8s4_offset:$imm),
1555 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1556 "$addr.base = $wb", []>;
1558 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1559 // data/instruction access.
1560 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1561 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1562 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1564 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1566 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1567 Sched<[WritePreLd]> {
1568 let Inst{31-25} = 0b1111100;
1569 let Inst{24} = instr;
1572 let Inst{21} = write;
1574 let Inst{15-12} = 0b1111;
1577 let Inst{19-16} = addr{16-13}; // Rn
1578 let Inst{11-0} = addr{11-0}; // imm12
1580 let DecoderMethod = "DecodeT2LoadImm12";
1583 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1585 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1586 Sched<[WritePreLd]> {
1587 let Inst{31-25} = 0b1111100;
1588 let Inst{24} = instr;
1589 let Inst{23} = 0; // U = 0
1591 let Inst{21} = write;
1593 let Inst{15-12} = 0b1111;
1594 let Inst{11-8} = 0b1100;
1597 let Inst{19-16} = addr{12-9}; // Rn
1598 let Inst{7-0} = addr{7-0}; // imm8
1600 let DecoderMethod = "DecodeT2LoadImm8";
1603 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1605 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1606 Sched<[WritePreLd]> {
1607 let Inst{31-25} = 0b1111100;
1608 let Inst{24} = instr;
1609 let Inst{23} = 0; // add = TRUE for T1
1611 let Inst{21} = write;
1613 let Inst{15-12} = 0b1111;
1614 let Inst{11-6} = 0b000000;
1617 let Inst{19-16} = addr{9-6}; // Rn
1618 let Inst{3-0} = addr{5-2}; // Rm
1619 let Inst{5-4} = addr{1-0}; // imm2
1621 let DecoderMethod = "DecodeT2LoadShift";
1624 // pci variant is very similar to i12, but supports negative offsets
1626 def pci : T2Iso<(outs), (ins t2ldrlabel:$addr), IIC_Preload, opc,
1628 [(ARMPreload (ARMWrapper tconstpool:$addr),
1629 (i32 write), (i32 instr))]>,
1630 Sched<[WritePreLd]> {
1631 let Inst{31-25} = 0b1111100;
1632 let Inst{24} = instr;
1634 let Inst{21} = write;
1636 let Inst{19-16} = 0b1111;
1637 let Inst{15-12} = 0b1111;
1640 let Inst{23} = addr{12}; // add = (U == '1')
1641 let Inst{11-0} = addr{11-0}; // imm12
1643 let DecoderMethod = "DecodeT2LoadLabel";
1647 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1648 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1649 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1651 //===----------------------------------------------------------------------===//
1652 // Load / store multiple Instructions.
1655 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1656 InstrItinClass itin_upd, bit L_bit> {
1658 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1659 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1663 let Inst{31-27} = 0b11101;
1664 let Inst{26-25} = 0b00;
1665 let Inst{24-23} = 0b01; // Increment After
1667 let Inst{21} = 0; // No writeback
1668 let Inst{20} = L_bit;
1669 let Inst{19-16} = Rn;
1670 let Inst{15-0} = regs;
1673 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1674 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1678 let Inst{31-27} = 0b11101;
1679 let Inst{26-25} = 0b00;
1680 let Inst{24-23} = 0b01; // Increment After
1682 let Inst{21} = 1; // Writeback
1683 let Inst{20} = L_bit;
1684 let Inst{19-16} = Rn;
1685 let Inst{15-0} = regs;
1688 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1689 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1693 let Inst{31-27} = 0b11101;
1694 let Inst{26-25} = 0b00;
1695 let Inst{24-23} = 0b10; // Decrement Before
1697 let Inst{21} = 0; // No writeback
1698 let Inst{20} = L_bit;
1699 let Inst{19-16} = Rn;
1700 let Inst{15-0} = regs;
1703 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1704 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1708 let Inst{31-27} = 0b11101;
1709 let Inst{26-25} = 0b00;
1710 let Inst{24-23} = 0b10; // Decrement Before
1712 let Inst{21} = 1; // Writeback
1713 let Inst{20} = L_bit;
1714 let Inst{19-16} = Rn;
1715 let Inst{15-0} = regs;
1719 let neverHasSideEffects = 1 in {
1721 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1722 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1724 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1725 InstrItinClass itin_upd, bit L_bit> {
1727 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1728 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1732 let Inst{31-27} = 0b11101;
1733 let Inst{26-25} = 0b00;
1734 let Inst{24-23} = 0b01; // Increment After
1736 let Inst{21} = 0; // No writeback
1737 let Inst{20} = L_bit;
1738 let Inst{19-16} = Rn;
1740 let Inst{14} = regs{14};
1742 let Inst{12-0} = regs{12-0};
1745 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1746 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1750 let Inst{31-27} = 0b11101;
1751 let Inst{26-25} = 0b00;
1752 let Inst{24-23} = 0b01; // Increment After
1754 let Inst{21} = 1; // Writeback
1755 let Inst{20} = L_bit;
1756 let Inst{19-16} = Rn;
1758 let Inst{14} = regs{14};
1760 let Inst{12-0} = regs{12-0};
1763 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1764 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1768 let Inst{31-27} = 0b11101;
1769 let Inst{26-25} = 0b00;
1770 let Inst{24-23} = 0b10; // Decrement Before
1772 let Inst{21} = 0; // No writeback
1773 let Inst{20} = L_bit;
1774 let Inst{19-16} = Rn;
1776 let Inst{14} = regs{14};
1778 let Inst{12-0} = regs{12-0};
1781 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1782 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1786 let Inst{31-27} = 0b11101;
1787 let Inst{26-25} = 0b00;
1788 let Inst{24-23} = 0b10; // Decrement Before
1790 let Inst{21} = 1; // Writeback
1791 let Inst{20} = L_bit;
1792 let Inst{19-16} = Rn;
1794 let Inst{14} = regs{14};
1796 let Inst{12-0} = regs{12-0};
1801 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1802 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1804 } // neverHasSideEffects
1807 //===----------------------------------------------------------------------===//
1808 // Move Instructions.
1811 let neverHasSideEffects = 1 in
1812 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1813 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1814 let Inst{31-27} = 0b11101;
1815 let Inst{26-25} = 0b01;
1816 let Inst{24-21} = 0b0010;
1817 let Inst{19-16} = 0b1111; // Rn
1818 let Inst{14-12} = 0b000;
1819 let Inst{7-4} = 0b0000;
1821 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1822 pred:$p, zero_reg)>;
1823 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1825 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1828 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1829 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1830 AddedComplexity = 1 in
1831 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1832 "mov", ".w\t$Rd, $imm",
1833 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1834 let Inst{31-27} = 0b11110;
1836 let Inst{24-21} = 0b0010;
1837 let Inst{19-16} = 0b1111; // Rn
1841 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1842 // Use aliases to get that to play nice here.
1843 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1845 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1848 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1849 pred:$p, zero_reg)>;
1850 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1851 pred:$p, zero_reg)>;
1853 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1854 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1855 "movw", "\t$Rd, $imm",
1856 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> {
1857 let Inst{31-27} = 0b11110;
1859 let Inst{24-21} = 0b0010;
1860 let Inst{20} = 0; // The S bit.
1866 let Inst{11-8} = Rd;
1867 let Inst{19-16} = imm{15-12};
1868 let Inst{26} = imm{11};
1869 let Inst{14-12} = imm{10-8};
1870 let Inst{7-0} = imm{7-0};
1871 let DecoderMethod = "DecodeT2MOVTWInstruction";
1874 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1875 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1877 let Constraints = "$src = $Rd" in {
1878 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1879 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1880 "movt", "\t$Rd, $imm",
1882 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1884 let Inst{31-27} = 0b11110;
1886 let Inst{24-21} = 0b0110;
1887 let Inst{20} = 0; // The S bit.
1893 let Inst{11-8} = Rd;
1894 let Inst{19-16} = imm{15-12};
1895 let Inst{26} = imm{11};
1896 let Inst{14-12} = imm{10-8};
1897 let Inst{7-0} = imm{7-0};
1898 let DecoderMethod = "DecodeT2MOVTWInstruction";
1901 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1902 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1906 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1908 //===----------------------------------------------------------------------===//
1909 // Extend Instructions.
1914 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1915 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1916 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1917 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1918 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1920 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1921 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1922 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1923 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1924 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1928 let AddedComplexity = 16 in {
1929 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1930 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1931 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1932 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1933 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1934 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1936 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1937 // The transformation should probably be done as a combiner action
1938 // instead so we can include a check for masking back in the upper
1939 // eight bits of the source into the lower eight bits of the result.
1940 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1941 // (t2UXTB16 rGPR:$Src, 3)>,
1942 // Requires<[HasT2ExtractPack, IsThumb2]>;
1943 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1944 (t2UXTB16 rGPR:$Src, 1)>,
1945 Requires<[HasT2ExtractPack, IsThumb2]>;
1947 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1948 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1949 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1950 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1951 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1954 //===----------------------------------------------------------------------===//
1955 // Arithmetic Instructions.
1958 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1959 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1960 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1961 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1963 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1965 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1966 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1967 // AdjustInstrPostInstrSelection where we determine whether or not to
1968 // set the "s" bit based on CPSR liveness.
1970 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1971 // support for an optional CPSR definition that corresponds to the DAG
1972 // node's second value. We can then eliminate the implicit def of CPSR.
1973 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1974 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1975 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1976 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1978 let hasPostISelHook = 1 in {
1979 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1980 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1981 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1982 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1986 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1987 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1989 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1990 // CPSR and the implicit def of CPSR is not needed.
1991 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1993 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1994 // The assume-no-carry-in form uses the negation of the input since add/sub
1995 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1996 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1998 // The AddedComplexity preferences the first variant over the others since
1999 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2000 let AddedComplexity = 1 in
2001 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2002 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2003 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2004 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2005 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2006 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2007 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2008 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2010 let AddedComplexity = 1 in
2011 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2012 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2013 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2014 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2015 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2016 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2017 // The with-carry-in form matches bitwise not instead of the negation.
2018 // Effectively, the inverse interpretation of the carry flag already accounts
2019 // for part of the negation.
2020 let AddedComplexity = 1 in
2021 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2022 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2023 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2024 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2025 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2026 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2028 // Select Bytes -- for disassembly only
2030 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2031 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
2032 Requires<[IsThumb2, HasThumb2DSP]> {
2033 let Inst{31-27} = 0b11111;
2034 let Inst{26-24} = 0b010;
2036 let Inst{22-20} = 0b010;
2037 let Inst{15-12} = 0b1111;
2039 let Inst{6-4} = 0b000;
2042 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2043 // And Miscellaneous operations -- for disassembly only
2044 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2045 list<dag> pat = [/* For disassembly only; pattern left blank */],
2046 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
2047 string asm = "\t$Rd, $Rn, $Rm">
2048 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2049 Requires<[IsThumb2, HasThumb2DSP]> {
2050 let Inst{31-27} = 0b11111;
2051 let Inst{26-23} = 0b0101;
2052 let Inst{22-20} = op22_20;
2053 let Inst{15-12} = 0b1111;
2054 let Inst{7-4} = op7_4;
2060 let Inst{11-8} = Rd;
2061 let Inst{19-16} = Rn;
2065 // Saturating add/subtract -- for disassembly only
2067 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2068 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
2069 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2070 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2071 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2072 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2073 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2074 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2075 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2076 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2077 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2078 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2079 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2080 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2081 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2082 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2083 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2084 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2085 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2086 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2087 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2088 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2090 // Signed/Unsigned add/subtract -- for disassembly only
2092 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2093 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2094 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2095 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2096 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2097 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2098 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2099 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2100 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2101 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2102 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2103 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2105 // Signed/Unsigned halving add/subtract -- for disassembly only
2107 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2108 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2109 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2110 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2111 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2112 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2113 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2114 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2115 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2116 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2117 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2118 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2120 // Helper class for disassembly only
2121 // A6.3.16 & A6.3.17
2122 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2123 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2124 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2125 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2126 let Inst{31-27} = 0b11111;
2127 let Inst{26-24} = 0b011;
2128 let Inst{23} = long;
2129 let Inst{22-20} = op22_20;
2130 let Inst{7-4} = op7_4;
2133 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2134 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2135 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2136 let Inst{31-27} = 0b11111;
2137 let Inst{26-24} = 0b011;
2138 let Inst{23} = long;
2139 let Inst{22-20} = op22_20;
2140 let Inst{7-4} = op7_4;
2143 // Unsigned Sum of Absolute Differences [and Accumulate].
2144 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2145 (ins rGPR:$Rn, rGPR:$Rm),
2146 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2147 Requires<[IsThumb2, HasThumb2DSP]> {
2148 let Inst{15-12} = 0b1111;
2150 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2151 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2152 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2153 Requires<[IsThumb2, HasThumb2DSP]>;
2155 // Signed/Unsigned saturate.
2156 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2157 string opc, string asm, list<dag> pattern>
2158 : T2I<oops, iops, itin, opc, asm, pattern> {
2164 let Inst{11-8} = Rd;
2165 let Inst{19-16} = Rn;
2166 let Inst{4-0} = sat_imm;
2167 let Inst{21} = sh{5};
2168 let Inst{14-12} = sh{4-2};
2169 let Inst{7-6} = sh{1-0};
2174 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2175 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2176 let Inst{31-27} = 0b11110;
2177 let Inst{25-22} = 0b1100;
2183 def t2SSAT16: T2SatI<
2184 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2185 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2186 Requires<[IsThumb2, HasThumb2DSP]> {
2187 let Inst{31-27} = 0b11110;
2188 let Inst{25-22} = 0b1100;
2191 let Inst{21} = 1; // sh = '1'
2192 let Inst{14-12} = 0b000; // imm3 = '000'
2193 let Inst{7-6} = 0b00; // imm2 = '00'
2194 let Inst{5-4} = 0b00;
2199 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2200 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2201 let Inst{31-27} = 0b11110;
2202 let Inst{25-22} = 0b1110;
2207 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2209 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2210 Requires<[IsThumb2, HasThumb2DSP]> {
2211 let Inst{31-22} = 0b1111001110;
2214 let Inst{21} = 1; // sh = '1'
2215 let Inst{14-12} = 0b000; // imm3 = '000'
2216 let Inst{7-6} = 0b00; // imm2 = '00'
2217 let Inst{5-4} = 0b00;
2220 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2221 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2223 //===----------------------------------------------------------------------===//
2224 // Shift and rotate Instructions.
2227 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2228 BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2229 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2230 BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2231 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2232 BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2233 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2234 BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2236 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2237 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2238 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2240 let Uses = [CPSR] in {
2241 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2242 "rrx", "\t$Rd, $Rm",
2243 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2244 let Inst{31-27} = 0b11101;
2245 let Inst{26-25} = 0b01;
2246 let Inst{24-21} = 0b0010;
2247 let Inst{19-16} = 0b1111; // Rn
2248 let Inst{14-12} = 0b000;
2249 let Inst{7-4} = 0b0011;
2253 let isCodeGenOnly = 1, Defs = [CPSR] in {
2254 def t2MOVsrl_flag : T2TwoRegShiftImm<
2255 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2256 "lsrs", ".w\t$Rd, $Rm, #1",
2257 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2259 let Inst{31-27} = 0b11101;
2260 let Inst{26-25} = 0b01;
2261 let Inst{24-21} = 0b0010;
2262 let Inst{20} = 1; // The S bit.
2263 let Inst{19-16} = 0b1111; // Rn
2264 let Inst{5-4} = 0b01; // Shift type.
2265 // Shift amount = Inst{14-12:7-6} = 1.
2266 let Inst{14-12} = 0b000;
2267 let Inst{7-6} = 0b01;
2269 def t2MOVsra_flag : T2TwoRegShiftImm<
2270 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2271 "asrs", ".w\t$Rd, $Rm, #1",
2272 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2274 let Inst{31-27} = 0b11101;
2275 let Inst{26-25} = 0b01;
2276 let Inst{24-21} = 0b0010;
2277 let Inst{20} = 1; // The S bit.
2278 let Inst{19-16} = 0b1111; // Rn
2279 let Inst{5-4} = 0b10; // Shift type.
2280 // Shift amount = Inst{14-12:7-6} = 1.
2281 let Inst{14-12} = 0b000;
2282 let Inst{7-6} = 0b01;
2286 //===----------------------------------------------------------------------===//
2287 // Bitwise Instructions.
2290 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2291 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2292 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2293 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2294 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2295 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2296 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2297 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2298 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2300 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2301 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2302 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2304 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2305 string opc, string asm, list<dag> pattern>
2306 : T2I<oops, iops, itin, opc, asm, pattern> {
2311 let Inst{11-8} = Rd;
2312 let Inst{4-0} = msb{4-0};
2313 let Inst{14-12} = lsb{4-2};
2314 let Inst{7-6} = lsb{1-0};
2317 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2318 string opc, string asm, list<dag> pattern>
2319 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2322 let Inst{19-16} = Rn;
2325 let Constraints = "$src = $Rd" in
2326 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2327 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2328 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2329 let Inst{31-27} = 0b11110;
2330 let Inst{26} = 0; // should be 0.
2332 let Inst{24-20} = 0b10110;
2333 let Inst{19-16} = 0b1111; // Rn
2335 let Inst{5} = 0; // should be 0.
2338 let msb{4-0} = imm{9-5};
2339 let lsb{4-0} = imm{4-0};
2342 def t2SBFX: T2TwoRegBitFI<
2343 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2344 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2345 let Inst{31-27} = 0b11110;
2347 let Inst{24-20} = 0b10100;
2351 def t2UBFX: T2TwoRegBitFI<
2352 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2353 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2354 let Inst{31-27} = 0b11110;
2356 let Inst{24-20} = 0b11100;
2360 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2361 let Constraints = "$src = $Rd" in {
2362 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2363 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2364 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2365 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2366 bf_inv_mask_imm:$imm))]> {
2367 let Inst{31-27} = 0b11110;
2368 let Inst{26} = 0; // should be 0.
2370 let Inst{24-20} = 0b10110;
2372 let Inst{5} = 0; // should be 0.
2375 let msb{4-0} = imm{9-5};
2376 let lsb{4-0} = imm{4-0};
2380 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2381 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2382 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2384 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2385 /// unary operation that produces a value. These are predicable and can be
2386 /// changed to modify CPSR.
2387 multiclass T2I_un_irs<bits<4> opcod, string opc,
2388 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2390 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2392 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2394 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2395 let isAsCheapAsAMove = Cheap;
2396 let isReMaterializable = ReMat;
2397 let isMoveImm = MoveImm;
2398 let Inst{31-27} = 0b11110;
2400 let Inst{24-21} = opcod;
2401 let Inst{19-16} = 0b1111; // Rn
2405 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2406 opc, ".w\t$Rd, $Rm",
2407 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2408 let Inst{31-27} = 0b11101;
2409 let Inst{26-25} = 0b01;
2410 let Inst{24-21} = opcod;
2411 let Inst{19-16} = 0b1111; // Rn
2412 let Inst{14-12} = 0b000; // imm3
2413 let Inst{7-6} = 0b00; // imm2
2414 let Inst{5-4} = 0b00; // type
2417 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2418 opc, ".w\t$Rd, $ShiftedRm",
2419 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2421 let Inst{31-27} = 0b11101;
2422 let Inst{26-25} = 0b01;
2423 let Inst{24-21} = opcod;
2424 let Inst{19-16} = 0b1111; // Rn
2428 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2429 let AddedComplexity = 1 in
2430 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2431 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2432 UnOpFrag<(not node:$Src)>, 1, 1, 1>;
2434 let AddedComplexity = 1 in
2435 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2436 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2438 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2439 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2440 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2443 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2444 // will match the extended, not the original bitWidth for $src.
2445 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2446 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2449 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2450 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2451 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2452 Requires<[IsThumb2]>;
2454 def : T2Pat<(t2_so_imm_not:$src),
2455 (t2MVNi t2_so_imm_not:$src)>;
2457 //===----------------------------------------------------------------------===//
2458 // Multiply Instructions.
2460 let isCommutable = 1 in
2461 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2462 "mul", "\t$Rd, $Rn, $Rm",
2463 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2464 let Inst{31-27} = 0b11111;
2465 let Inst{26-23} = 0b0110;
2466 let Inst{22-20} = 0b000;
2467 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2468 let Inst{7-4} = 0b0000; // Multiply
2471 def t2MLA: T2FourReg<
2472 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2473 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2474 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
2475 Requires<[IsThumb2, UseMulOps]> {
2476 let Inst{31-27} = 0b11111;
2477 let Inst{26-23} = 0b0110;
2478 let Inst{22-20} = 0b000;
2479 let Inst{7-4} = 0b0000; // Multiply
2482 def t2MLS: T2FourReg<
2483 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2484 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2485 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
2486 Requires<[IsThumb2, UseMulOps]> {
2487 let Inst{31-27} = 0b11111;
2488 let Inst{26-23} = 0b0110;
2489 let Inst{22-20} = 0b000;
2490 let Inst{7-4} = 0b0001; // Multiply and Subtract
2493 // Extra precision multiplies with low / high results
2494 let neverHasSideEffects = 1 in {
2495 let isCommutable = 1 in {
2496 def t2SMULL : T2MulLong<0b000, 0b0000,
2497 (outs rGPR:$RdLo, rGPR:$RdHi),
2498 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2499 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2501 def t2UMULL : T2MulLong<0b010, 0b0000,
2502 (outs rGPR:$RdLo, rGPR:$RdHi),
2503 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2504 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2507 // Multiply + accumulate
2508 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2509 (outs rGPR:$RdLo, rGPR:$RdHi),
2510 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2511 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2512 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2514 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2515 (outs rGPR:$RdLo, rGPR:$RdHi),
2516 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2517 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2518 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2520 def t2UMAAL : T2MulLong<0b110, 0b0110,
2521 (outs rGPR:$RdLo, rGPR:$RdHi),
2522 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2523 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2524 Requires<[IsThumb2, HasThumb2DSP]>;
2525 } // neverHasSideEffects
2527 // Rounding variants of the below included for disassembly only
2529 // Most significant word multiply
2530 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2531 "smmul", "\t$Rd, $Rn, $Rm",
2532 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2533 Requires<[IsThumb2, HasThumb2DSP]> {
2534 let Inst{31-27} = 0b11111;
2535 let Inst{26-23} = 0b0110;
2536 let Inst{22-20} = 0b101;
2537 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2538 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2541 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2542 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2543 Requires<[IsThumb2, HasThumb2DSP]> {
2544 let Inst{31-27} = 0b11111;
2545 let Inst{26-23} = 0b0110;
2546 let Inst{22-20} = 0b101;
2547 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2548 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2551 def t2SMMLA : T2FourReg<
2552 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2553 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2554 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2555 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2556 let Inst{31-27} = 0b11111;
2557 let Inst{26-23} = 0b0110;
2558 let Inst{22-20} = 0b101;
2559 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2562 def t2SMMLAR: T2FourReg<
2563 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2564 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2565 Requires<[IsThumb2, HasThumb2DSP]> {
2566 let Inst{31-27} = 0b11111;
2567 let Inst{26-23} = 0b0110;
2568 let Inst{22-20} = 0b101;
2569 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2572 def t2SMMLS: T2FourReg<
2573 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2574 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2575 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2576 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2577 let Inst{31-27} = 0b11111;
2578 let Inst{26-23} = 0b0110;
2579 let Inst{22-20} = 0b110;
2580 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2583 def t2SMMLSR:T2FourReg<
2584 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2585 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2586 Requires<[IsThumb2, HasThumb2DSP]> {
2587 let Inst{31-27} = 0b11111;
2588 let Inst{26-23} = 0b0110;
2589 let Inst{22-20} = 0b110;
2590 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2593 multiclass T2I_smul<string opc, PatFrag opnode> {
2594 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2595 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2596 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2597 (sext_inreg rGPR:$Rm, i16)))]>,
2598 Requires<[IsThumb2, HasThumb2DSP]> {
2599 let Inst{31-27} = 0b11111;
2600 let Inst{26-23} = 0b0110;
2601 let Inst{22-20} = 0b001;
2602 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2603 let Inst{7-6} = 0b00;
2604 let Inst{5-4} = 0b00;
2607 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2608 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2609 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2610 (sra rGPR:$Rm, (i32 16))))]>,
2611 Requires<[IsThumb2, HasThumb2DSP]> {
2612 let Inst{31-27} = 0b11111;
2613 let Inst{26-23} = 0b0110;
2614 let Inst{22-20} = 0b001;
2615 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2616 let Inst{7-6} = 0b00;
2617 let Inst{5-4} = 0b01;
2620 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2621 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2622 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2623 (sext_inreg rGPR:$Rm, i16)))]>,
2624 Requires<[IsThumb2, HasThumb2DSP]> {
2625 let Inst{31-27} = 0b11111;
2626 let Inst{26-23} = 0b0110;
2627 let Inst{22-20} = 0b001;
2628 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2629 let Inst{7-6} = 0b00;
2630 let Inst{5-4} = 0b10;
2633 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2634 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2635 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2636 (sra rGPR:$Rm, (i32 16))))]>,
2637 Requires<[IsThumb2, HasThumb2DSP]> {
2638 let Inst{31-27} = 0b11111;
2639 let Inst{26-23} = 0b0110;
2640 let Inst{22-20} = 0b001;
2641 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2642 let Inst{7-6} = 0b00;
2643 let Inst{5-4} = 0b11;
2646 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2647 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2648 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2649 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2650 Requires<[IsThumb2, HasThumb2DSP]> {
2651 let Inst{31-27} = 0b11111;
2652 let Inst{26-23} = 0b0110;
2653 let Inst{22-20} = 0b011;
2654 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2655 let Inst{7-6} = 0b00;
2656 let Inst{5-4} = 0b00;
2659 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2660 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2661 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2662 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2663 Requires<[IsThumb2, HasThumb2DSP]> {
2664 let Inst{31-27} = 0b11111;
2665 let Inst{26-23} = 0b0110;
2666 let Inst{22-20} = 0b011;
2667 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2668 let Inst{7-6} = 0b00;
2669 let Inst{5-4} = 0b01;
2674 multiclass T2I_smla<string opc, PatFrag opnode> {
2676 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2677 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2678 [(set rGPR:$Rd, (add rGPR:$Ra,
2679 (opnode (sext_inreg rGPR:$Rn, i16),
2680 (sext_inreg rGPR:$Rm, i16))))]>,
2681 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2682 let Inst{31-27} = 0b11111;
2683 let Inst{26-23} = 0b0110;
2684 let Inst{22-20} = 0b001;
2685 let Inst{7-6} = 0b00;
2686 let Inst{5-4} = 0b00;
2690 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2691 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2692 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2693 (sra rGPR:$Rm, (i32 16)))))]>,
2694 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2695 let Inst{31-27} = 0b11111;
2696 let Inst{26-23} = 0b0110;
2697 let Inst{22-20} = 0b001;
2698 let Inst{7-6} = 0b00;
2699 let Inst{5-4} = 0b01;
2703 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2704 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2705 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2706 (sext_inreg rGPR:$Rm, i16))))]>,
2707 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2708 let Inst{31-27} = 0b11111;
2709 let Inst{26-23} = 0b0110;
2710 let Inst{22-20} = 0b001;
2711 let Inst{7-6} = 0b00;
2712 let Inst{5-4} = 0b10;
2716 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2717 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2718 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2719 (sra rGPR:$Rm, (i32 16)))))]>,
2720 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2721 let Inst{31-27} = 0b11111;
2722 let Inst{26-23} = 0b0110;
2723 let Inst{22-20} = 0b001;
2724 let Inst{7-6} = 0b00;
2725 let Inst{5-4} = 0b11;
2729 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2730 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2731 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2732 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2733 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2734 let Inst{31-27} = 0b11111;
2735 let Inst{26-23} = 0b0110;
2736 let Inst{22-20} = 0b011;
2737 let Inst{7-6} = 0b00;
2738 let Inst{5-4} = 0b00;
2742 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2743 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2744 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2745 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2746 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2747 let Inst{31-27} = 0b11111;
2748 let Inst{26-23} = 0b0110;
2749 let Inst{22-20} = 0b011;
2750 let Inst{7-6} = 0b00;
2751 let Inst{5-4} = 0b01;
2755 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2756 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2758 // Halfword multiple accumulate long: SMLAL<x><y>
2759 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2760 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2761 [/* For disassembly only; pattern left blank */]>,
2762 Requires<[IsThumb2, HasThumb2DSP]>;
2763 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2764 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2765 [/* For disassembly only; pattern left blank */]>,
2766 Requires<[IsThumb2, HasThumb2DSP]>;
2767 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2768 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2769 [/* For disassembly only; pattern left blank */]>,
2770 Requires<[IsThumb2, HasThumb2DSP]>;
2771 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2772 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2773 [/* For disassembly only; pattern left blank */]>,
2774 Requires<[IsThumb2, HasThumb2DSP]>;
2776 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2777 def t2SMUAD: T2ThreeReg_mac<
2778 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2779 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2780 Requires<[IsThumb2, HasThumb2DSP]> {
2781 let Inst{15-12} = 0b1111;
2783 def t2SMUADX:T2ThreeReg_mac<
2784 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2785 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2786 Requires<[IsThumb2, HasThumb2DSP]> {
2787 let Inst{15-12} = 0b1111;
2789 def t2SMUSD: T2ThreeReg_mac<
2790 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2791 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2792 Requires<[IsThumb2, HasThumb2DSP]> {
2793 let Inst{15-12} = 0b1111;
2795 def t2SMUSDX:T2ThreeReg_mac<
2796 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2797 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2798 Requires<[IsThumb2, HasThumb2DSP]> {
2799 let Inst{15-12} = 0b1111;
2801 def t2SMLAD : T2FourReg_mac<
2802 0, 0b010, 0b0000, (outs rGPR:$Rd),
2803 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2804 "\t$Rd, $Rn, $Rm, $Ra", []>,
2805 Requires<[IsThumb2, HasThumb2DSP]>;
2806 def t2SMLADX : T2FourReg_mac<
2807 0, 0b010, 0b0001, (outs rGPR:$Rd),
2808 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2809 "\t$Rd, $Rn, $Rm, $Ra", []>,
2810 Requires<[IsThumb2, HasThumb2DSP]>;
2811 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2812 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2813 "\t$Rd, $Rn, $Rm, $Ra", []>,
2814 Requires<[IsThumb2, HasThumb2DSP]>;
2815 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2816 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2817 "\t$Rd, $Rn, $Rm, $Ra", []>,
2818 Requires<[IsThumb2, HasThumb2DSP]>;
2819 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2820 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2821 "\t$Ra, $Rd, $Rn, $Rm", []>,
2822 Requires<[IsThumb2, HasThumb2DSP]>;
2823 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2824 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2825 "\t$Ra, $Rd, $Rn, $Rm", []>,
2826 Requires<[IsThumb2, HasThumb2DSP]>;
2827 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2828 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2829 "\t$Ra, $Rd, $Rn, $Rm", []>,
2830 Requires<[IsThumb2, HasThumb2DSP]>;
2831 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2832 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2833 "\t$Ra, $Rd, $Rn, $Rm", []>,
2834 Requires<[IsThumb2, HasThumb2DSP]>;
2836 //===----------------------------------------------------------------------===//
2837 // Division Instructions.
2838 // Signed and unsigned division on v7-M
2840 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2841 "sdiv", "\t$Rd, $Rn, $Rm",
2842 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2843 Requires<[HasDivide, IsThumb2]> {
2844 let Inst{31-27} = 0b11111;
2845 let Inst{26-21} = 0b011100;
2847 let Inst{15-12} = 0b1111;
2848 let Inst{7-4} = 0b1111;
2851 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2852 "udiv", "\t$Rd, $Rn, $Rm",
2853 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2854 Requires<[HasDivide, IsThumb2]> {
2855 let Inst{31-27} = 0b11111;
2856 let Inst{26-21} = 0b011101;
2858 let Inst{15-12} = 0b1111;
2859 let Inst{7-4} = 0b1111;
2862 //===----------------------------------------------------------------------===//
2863 // Misc. Arithmetic Instructions.
2866 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2867 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2868 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2869 let Inst{31-27} = 0b11111;
2870 let Inst{26-22} = 0b01010;
2871 let Inst{21-20} = op1;
2872 let Inst{15-12} = 0b1111;
2873 let Inst{7-6} = 0b10;
2874 let Inst{5-4} = op2;
2878 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2879 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2882 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2883 "rbit", "\t$Rd, $Rm",
2884 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>,
2887 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2888 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2891 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2892 "rev16", ".w\t$Rd, $Rm",
2893 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2896 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2897 "revsh", ".w\t$Rd, $Rm",
2898 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2901 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2902 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2903 (t2REVSH rGPR:$Rm)>;
2905 def t2PKHBT : T2ThreeReg<
2906 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2907 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2908 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2909 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2911 Requires<[HasT2ExtractPack, IsThumb2]>,
2912 Sched<[WriteALUsi, ReadALU]> {
2913 let Inst{31-27} = 0b11101;
2914 let Inst{26-25} = 0b01;
2915 let Inst{24-20} = 0b01100;
2916 let Inst{5} = 0; // BT form
2920 let Inst{14-12} = sh{4-2};
2921 let Inst{7-6} = sh{1-0};
2924 // Alternate cases for PKHBT where identities eliminate some nodes.
2925 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2926 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2927 Requires<[HasT2ExtractPack, IsThumb2]>;
2928 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2929 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2930 Requires<[HasT2ExtractPack, IsThumb2]>;
2932 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2933 // will match the pattern below.
2934 def t2PKHTB : T2ThreeReg<
2935 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2936 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2937 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2938 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2940 Requires<[HasT2ExtractPack, IsThumb2]>,
2941 Sched<[WriteALUsi, ReadALU]> {
2942 let Inst{31-27} = 0b11101;
2943 let Inst{26-25} = 0b01;
2944 let Inst{24-20} = 0b01100;
2945 let Inst{5} = 1; // TB form
2949 let Inst{14-12} = sh{4-2};
2950 let Inst{7-6} = sh{1-0};
2953 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2954 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2955 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
2956 // pkhtb src1, src2, asr (17..31).
2957 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
2958 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
2959 Requires<[HasT2ExtractPack, IsThumb2]>;
2960 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
2961 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2962 Requires<[HasT2ExtractPack, IsThumb2]>;
2963 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2964 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2965 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2966 Requires<[HasT2ExtractPack, IsThumb2]>;
2968 //===----------------------------------------------------------------------===//
2969 // Comparison Instructions...
2971 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2972 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2973 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2975 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2976 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2977 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2978 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2979 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2980 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2982 let isCompare = 1, Defs = [CPSR] in {
2984 def t2CMNri : T2OneRegCmpImm<
2985 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
2986 "cmn", ".w\t$Rn, $imm",
2987 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
2988 Sched<[WriteCMP, ReadALU]> {
2989 let Inst{31-27} = 0b11110;
2991 let Inst{24-21} = 0b1000;
2992 let Inst{20} = 1; // The S bit.
2994 let Inst{11-8} = 0b1111; // Rd
2997 def t2CMNzrr : T2TwoRegCmp<
2998 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
2999 "cmn", ".w\t$Rn, $Rm",
3000 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3001 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
3002 let Inst{31-27} = 0b11101;
3003 let Inst{26-25} = 0b01;
3004 let Inst{24-21} = 0b1000;
3005 let Inst{20} = 1; // The S bit.
3006 let Inst{14-12} = 0b000; // imm3
3007 let Inst{11-8} = 0b1111; // Rd
3008 let Inst{7-6} = 0b00; // imm2
3009 let Inst{5-4} = 0b00; // type
3012 def t2CMNzrs : T2OneRegCmpShiftedReg<
3013 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
3014 "cmn", ".w\t$Rn, $ShiftedRm",
3015 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3016 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
3017 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3018 let Inst{31-27} = 0b11101;
3019 let Inst{26-25} = 0b01;
3020 let Inst{24-21} = 0b1000;
3021 let Inst{20} = 1; // The S bit.
3022 let Inst{11-8} = 0b1111; // Rd
3026 // Assembler aliases w/o the ".w" suffix.
3027 // No alias here for 'rr' version as not all instantiations of this multiclass
3028 // want one (CMP in particular, does not).
3029 def : t2InstAlias<"cmn${p} $Rn, $imm",
3030 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
3031 def : t2InstAlias<"cmn${p} $Rn, $shift",
3032 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
3034 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
3035 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
3037 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
3038 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
3040 defm t2TST : T2I_cmp_irs<0b0000, "tst",
3041 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3042 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3043 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
3044 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3045 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3047 // Conditional moves
3048 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3049 // a two-value operand where a dag node expects two operands. :(
3050 let neverHasSideEffects = 1 in {
3052 let isCommutable = 1, isSelect = 1 in
3053 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3054 (ins rGPR:$false, rGPR:$Rm, pred:$p),
3056 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3057 RegConstraint<"$false = $Rd">,
3060 let isMoveImm = 1 in
3061 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
3062 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
3064 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3065 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3067 // FIXME: Pseudo-ize these. For now, just mark codegen only.
3068 let isCodeGenOnly = 1 in {
3069 let isMoveImm = 1 in
3070 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
3072 "movw", "\t$Rd, $imm", []>,
3073 RegConstraint<"$false = $Rd">, Sched<[WriteALU]> {
3074 let Inst{31-27} = 0b11110;
3076 let Inst{24-21} = 0b0010;
3077 let Inst{20} = 0; // The S bit.
3083 let Inst{11-8} = Rd;
3084 let Inst{19-16} = imm{15-12};
3085 let Inst{26} = imm{11};
3086 let Inst{14-12} = imm{10-8};
3087 let Inst{7-0} = imm{7-0};
3090 let isMoveImm = 1 in
3091 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
3092 (ins rGPR:$false, i32imm:$src, pred:$p),
3093 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
3095 let isMoveImm = 1 in
3096 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
3097 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
3098 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
3099 imm:$cc, CCR:$ccr))*/]>,
3100 RegConstraint<"$false = $Rd">, Sched<[WriteALU]> {
3101 let Inst{31-27} = 0b11110;
3103 let Inst{24-21} = 0b0011;
3104 let Inst{20} = 0; // The S bit.
3105 let Inst{19-16} = 0b1111; // Rn
3109 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
3110 string opc, string asm, list<dag> pattern>
3111 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern>, Sched<[WriteALU]> {
3112 let Inst{31-27} = 0b11101;
3113 let Inst{26-25} = 0b01;
3114 let Inst{24-21} = 0b0010;
3115 let Inst{20} = 0; // The S bit.
3116 let Inst{19-16} = 0b1111; // Rn
3117 let Inst{5-4} = opcod; // Shift type.
3119 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
3120 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3121 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
3122 RegConstraint<"$false = $Rd">;
3123 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
3124 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3125 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
3126 RegConstraint<"$false = $Rd">;
3127 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
3128 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3129 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
3130 RegConstraint<"$false = $Rd">;
3131 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
3132 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3133 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
3134 RegConstraint<"$false = $Rd">;
3135 } // isCodeGenOnly = 1
3137 } // neverHasSideEffects
3139 //===----------------------------------------------------------------------===//
3140 // Atomic operations intrinsics
3143 // memory barriers protect the atomic sequences
3144 let hasSideEffects = 1 in {
3145 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3146 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3149 let Inst{31-4} = 0xf3bf8f5;
3150 let Inst{3-0} = opt;
3154 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3155 "dsb", "\t$opt", []>, Requires<[HasDB]> {
3157 let Inst{31-4} = 0xf3bf8f4;
3158 let Inst{3-0} = opt;
3161 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3162 "isb", "\t$opt", []>, Requires<[HasDB]> {
3164 let Inst{31-4} = 0xf3bf8f6;
3165 let Inst{3-0} = opt;
3168 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3169 InstrItinClass itin, string opc, string asm, string cstr,
3170 list<dag> pattern, bits<4> rt2 = 0b1111>
3171 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3172 let Inst{31-27} = 0b11101;
3173 let Inst{26-20} = 0b0001101;
3174 let Inst{11-8} = rt2;
3175 let Inst{7-6} = 0b01;
3176 let Inst{5-4} = opcod;
3177 let Inst{3-0} = 0b1111;
3181 let Inst{19-16} = addr;
3182 let Inst{15-12} = Rt;
3184 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3185 InstrItinClass itin, string opc, string asm, string cstr,
3186 list<dag> pattern, bits<4> rt2 = 0b1111>
3187 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3188 let Inst{31-27} = 0b11101;
3189 let Inst{26-20} = 0b0001100;
3190 let Inst{11-8} = rt2;
3191 let Inst{7-6} = 0b01;
3192 let Inst{5-4} = opcod;
3198 let Inst{19-16} = addr;
3199 let Inst{15-12} = Rt;
3202 let mayLoad = 1 in {
3203 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3204 AddrModeNone, 4, NoItinerary,
3205 "ldrexb", "\t$Rt, $addr", "",
3206 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
3207 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3208 AddrModeNone, 4, NoItinerary,
3209 "ldrexh", "\t$Rt, $addr", "",
3210 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
3211 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3212 AddrModeNone, 4, NoItinerary,
3213 "ldrex", "\t$Rt, $addr", "",
3214 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]> {
3217 let Inst{31-27} = 0b11101;
3218 let Inst{26-20} = 0b0000101;
3219 let Inst{19-16} = addr{11-8};
3220 let Inst{15-12} = Rt;
3221 let Inst{11-8} = 0b1111;
3222 let Inst{7-0} = addr{7-0};
3224 let hasExtraDefRegAllocReq = 1 in
3225 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3226 (ins addr_offset_none:$addr),
3227 AddrModeNone, 4, NoItinerary,
3228 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3231 let Inst{11-8} = Rt2;
3235 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3236 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3237 (ins rGPR:$Rt, addr_offset_none:$addr),
3238 AddrModeNone, 4, NoItinerary,
3239 "strexb", "\t$Rd, $Rt, $addr", "",
3240 [(set rGPR:$Rd, (strex_1 rGPR:$Rt,
3241 addr_offset_none:$addr))]>;
3242 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3243 (ins rGPR:$Rt, addr_offset_none:$addr),
3244 AddrModeNone, 4, NoItinerary,
3245 "strexh", "\t$Rd, $Rt, $addr", "",
3246 [(set rGPR:$Rd, (strex_2 rGPR:$Rt,
3247 addr_offset_none:$addr))]>;
3249 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3250 t2addrmode_imm0_1020s4:$addr),
3251 AddrModeNone, 4, NoItinerary,
3252 "strex", "\t$Rd, $Rt, $addr", "",
3253 [(set rGPR:$Rd, (strex_4 rGPR:$Rt,
3254 t2addrmode_imm0_1020s4:$addr))]> {
3258 let Inst{31-27} = 0b11101;
3259 let Inst{26-20} = 0b0000100;
3260 let Inst{19-16} = addr{11-8};
3261 let Inst{15-12} = Rt;
3262 let Inst{11-8} = Rd;
3263 let Inst{7-0} = addr{7-0};
3265 let hasExtraSrcRegAllocReq = 1 in
3266 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3267 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3268 AddrModeNone, 4, NoItinerary,
3269 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3272 let Inst{11-8} = Rt2;
3276 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
3277 Requires<[IsThumb2, HasV7]> {
3278 let Inst{31-16} = 0xf3bf;
3279 let Inst{15-14} = 0b10;
3282 let Inst{11-8} = 0b1111;
3283 let Inst{7-4} = 0b0010;
3284 let Inst{3-0} = 0b1111;
3287 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3288 (t2LDREXB addr_offset_none:$addr)>;
3289 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3290 (t2LDREXH addr_offset_none:$addr)>;
3291 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3292 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>;
3293 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3294 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>;
3296 //===----------------------------------------------------------------------===//
3297 // SJLJ Exception handling intrinsics
3298 // eh_sjlj_setjmp() is an instruction sequence to store the return
3299 // address and save #0 in R0 for the non-longjmp case.
3300 // Since by its nature we may be coming from some other function to get
3301 // here, and we're using the stack frame for the containing function to
3302 // save/restore registers, we can't keep anything live in regs across
3303 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3304 // when we get here from a longjmp(). We force everything out of registers
3305 // except for our own input by listing the relevant registers in Defs. By
3306 // doing so, we also cause the prologue/epilogue code to actively preserve
3307 // all of the callee-saved resgisters, which is exactly what we want.
3308 // $val is a scratch register for our use.
3310 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3311 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3312 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3313 usesCustomInserter = 1 in {
3314 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3315 AddrModeNone, 0, NoItinerary, "", "",
3316 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3317 Requires<[IsThumb2, HasVFP2]>;
3321 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3322 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3323 usesCustomInserter = 1 in {
3324 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3325 AddrModeNone, 0, NoItinerary, "", "",
3326 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3327 Requires<[IsThumb2, NoVFP]>;
3331 //===----------------------------------------------------------------------===//
3332 // Control-Flow Instructions
3335 // FIXME: remove when we have a way to marking a MI with these properties.
3336 // FIXME: Should pc be an implicit operand like PICADD, etc?
3337 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3338 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3339 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3340 reglist:$regs, variable_ops),
3341 4, IIC_iLoad_mBr, [],
3342 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3343 RegConstraint<"$Rn = $wb">;
3345 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3346 let isPredicable = 1 in
3347 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3349 [(br bb:$target)]>, Sched<[WriteBr]> {
3350 let Inst{31-27} = 0b11110;
3351 let Inst{15-14} = 0b10;
3355 let Inst{26} = target{19};
3356 let Inst{11} = target{18};
3357 let Inst{13} = target{17};
3358 let Inst{25-16} = target{20-11};
3359 let Inst{10-0} = target{10-0};
3360 let DecoderMethod = "DecodeT2BInstruction";
3363 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3364 def t2BR_JT : t2PseudoInst<(outs),
3365 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3367 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>,
3370 // FIXME: Add a non-pc based case that can be predicated.
3371 def t2TBB_JT : t2PseudoInst<(outs),
3372 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3375 def t2TBH_JT : t2PseudoInst<(outs),
3376 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3379 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3380 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3383 let Inst{31-20} = 0b111010001101;
3384 let Inst{19-16} = Rn;
3385 let Inst{15-5} = 0b11110000000;
3386 let Inst{4} = 0; // B form
3389 let DecoderMethod = "DecodeThumbTableBranch";
3392 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3393 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3396 let Inst{31-20} = 0b111010001101;
3397 let Inst{19-16} = Rn;
3398 let Inst{15-5} = 0b11110000000;
3399 let Inst{4} = 1; // H form
3402 let DecoderMethod = "DecodeThumbTableBranch";
3404 } // isNotDuplicable, isIndirectBranch
3406 } // isBranch, isTerminator, isBarrier
3408 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3409 // a two-value operand where a dag node expects ", "two operands. :(
3410 let isBranch = 1, isTerminator = 1 in
3411 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3413 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3414 let Inst{31-27} = 0b11110;
3415 let Inst{15-14} = 0b10;
3419 let Inst{25-22} = p;
3422 let Inst{26} = target{20};
3423 let Inst{11} = target{19};
3424 let Inst{13} = target{18};
3425 let Inst{21-16} = target{17-12};
3426 let Inst{10-0} = target{11-1};
3428 let DecoderMethod = "DecodeThumb2BCCInstruction";
3431 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3433 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3436 def tTAILJMPd: tPseudoExpand<(outs),
3437 (ins uncondbrtarget:$dst, pred:$p),
3439 (t2B uncondbrtarget:$dst, pred:$p)>,
3440 Requires<[IsThumb2, IsIOS]>, Sched<[WriteBr]>;
3444 let Defs = [ITSTATE] in
3445 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3446 AddrModeNone, 2, IIC_iALUx,
3447 "it$mask\t$cc", "", []> {
3448 // 16-bit instruction.
3449 let Inst{31-16} = 0x0000;
3450 let Inst{15-8} = 0b10111111;
3455 let Inst{3-0} = mask;
3457 let DecoderMethod = "DecodeIT";
3460 // Branch and Exchange Jazelle -- for disassembly only
3462 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []>,
3465 let Inst{31-27} = 0b11110;
3467 let Inst{25-20} = 0b111100;
3468 let Inst{19-16} = func;
3469 let Inst{15-0} = 0b1000111100000000;
3472 // Compare and branch on zero / non-zero
3473 let isBranch = 1, isTerminator = 1 in {
3474 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3475 "cbz\t$Rn, $target", []>,
3476 T1Misc<{0,0,?,1,?,?,?}>,
3477 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3481 let Inst{9} = target{5};
3482 let Inst{7-3} = target{4-0};
3486 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3487 "cbnz\t$Rn, $target", []>,
3488 T1Misc<{1,0,?,1,?,?,?}>,
3489 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3493 let Inst{9} = target{5};
3494 let Inst{7-3} = target{4-0};
3500 // Change Processor State is a system instruction.
3501 // FIXME: Since the asm parser has currently no clean way to handle optional
3502 // operands, create 3 versions of the same instruction. Once there's a clean
3503 // framework to represent optional operands, change this behavior.
3504 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3505 !strconcat("cps", asm_op), []> {
3511 let Inst{31-11} = 0b111100111010111110000;
3512 let Inst{10-9} = imod;
3514 let Inst{7-5} = iflags;
3515 let Inst{4-0} = mode;
3516 let DecoderMethod = "DecodeT2CPSInstruction";
3520 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3521 "$imod.w\t$iflags, $mode">;
3522 let mode = 0, M = 0 in
3523 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3524 "$imod.w\t$iflags">;
3525 let imod = 0, iflags = 0, M = 1 in
3526 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3528 // A6.3.4 Branches and miscellaneous control
3529 // Table A6-14 Change Processor State, and hint instructions
3530 def t2HINT : T2I<(outs), (ins imm0_4:$imm), NoItinerary, "hint", "\t$imm",[]> {
3532 let Inst{31-3} = 0b11110011101011111000000000000;
3533 let Inst{2-0} = imm;
3536 def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_4:$imm, pred:$p)>;
3537 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3538 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3539 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3540 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3541 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3543 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3545 let Inst{31-20} = 0b111100111010;
3546 let Inst{19-16} = 0b1111;
3547 let Inst{15-8} = 0b10000000;
3548 let Inst{7-4} = 0b1111;
3549 let Inst{3-0} = opt;
3552 // Secure Monitor Call is a system instruction.
3553 // Option = Inst{19-16}
3554 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3555 []>, Requires<[IsThumb2, HasTrustZone]> {
3556 let Inst{31-27} = 0b11110;
3557 let Inst{26-20} = 0b1111111;
3558 let Inst{15-12} = 0b1000;
3561 let Inst{19-16} = opt;
3564 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3565 string opc, string asm, list<dag> pattern>
3566 : T2I<oops, iops, itin, opc, asm, pattern> {
3568 let Inst{31-25} = 0b1110100;
3569 let Inst{24-23} = Op;
3572 let Inst{20-16} = 0b01101;
3573 let Inst{15-5} = 0b11000000000;
3574 let Inst{4-0} = mode{4-0};
3577 // Store Return State is a system instruction.
3578 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3579 "srsdb", "\tsp!, $mode", []>;
3580 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3581 "srsdb","\tsp, $mode", []>;
3582 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3583 "srsia","\tsp!, $mode", []>;
3584 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3585 "srsia","\tsp, $mode", []>;
3588 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3589 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3591 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3592 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3594 // Return From Exception is a system instruction.
3595 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3596 string opc, string asm, list<dag> pattern>
3597 : T2I<oops, iops, itin, opc, asm, pattern> {
3598 let Inst{31-20} = op31_20{11-0};
3601 let Inst{19-16} = Rn;
3602 let Inst{15-0} = 0xc000;
3605 def t2RFEDBW : T2RFE<0b111010000011,
3606 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3607 [/* For disassembly only; pattern left blank */]>;
3608 def t2RFEDB : T2RFE<0b111010000001,
3609 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3610 [/* For disassembly only; pattern left blank */]>;
3611 def t2RFEIAW : T2RFE<0b111010011011,
3612 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3613 [/* For disassembly only; pattern left blank */]>;
3614 def t2RFEIA : T2RFE<0b111010011001,
3615 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3616 [/* For disassembly only; pattern left blank */]>;
3618 //===----------------------------------------------------------------------===//
3619 // Non-Instruction Patterns
3622 // 32-bit immediate using movw + movt.
3623 // This is a single pseudo instruction to make it re-materializable.
3624 // FIXME: Remove this when we can do generalized remat.
3625 let isReMaterializable = 1, isMoveImm = 1 in
3626 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3627 [(set rGPR:$dst, (i32 imm:$src))]>,
3628 Requires<[IsThumb, HasV6T2]>;
3630 // Pseudo instruction that combines movw + movt + add pc (if pic).
3631 // It also makes it possible to rematerialize the instructions.
3632 // FIXME: Remove this when we can do generalized remat and when machine licm
3633 // can properly the instructions.
3634 let isReMaterializable = 1 in {
3635 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3637 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3638 Requires<[IsThumb2, UseMovt]>;
3640 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3642 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3643 Requires<[IsThumb2, UseMovt]>;
3646 // ConstantPool, GlobalAddress, and JumpTable
3647 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3648 Requires<[IsThumb2, DontUseMovt]>;
3649 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3650 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3651 Requires<[IsThumb2, UseMovt]>;
3653 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3654 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3656 // Pseudo instruction that combines ldr from constpool and add pc. This should
3657 // be expanded into two instructions late to allow if-conversion and
3659 let canFoldAsLoad = 1, isReMaterializable = 1 in
3660 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3662 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3664 Requires<[IsThumb2]>;
3666 // Pseudo isntruction that combines movs + predicated rsbmi
3667 // to implement integer ABS
3668 let usesCustomInserter = 1, Defs = [CPSR] in {
3669 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3670 NoItinerary, []>, Requires<[IsThumb2]>;
3673 //===----------------------------------------------------------------------===//
3674 // Coprocessor load/store -- for disassembly only
3676 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3677 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3678 let Inst{31-28} = op31_28;
3679 let Inst{27-25} = 0b110;
3682 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3683 def _OFFSET : T2CI<op31_28,
3684 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3685 asm, "\t$cop, $CRd, $addr"> {
3689 let Inst{24} = 1; // P = 1
3690 let Inst{23} = addr{8};
3691 let Inst{22} = Dbit;
3692 let Inst{21} = 0; // W = 0
3693 let Inst{20} = load;
3694 let Inst{19-16} = addr{12-9};
3695 let Inst{15-12} = CRd;
3696 let Inst{11-8} = cop;
3697 let Inst{7-0} = addr{7-0};
3698 let DecoderMethod = "DecodeCopMemInstruction";
3700 def _PRE : T2CI<op31_28,
3701 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3702 asm, "\t$cop, $CRd, $addr!"> {
3706 let Inst{24} = 1; // P = 1
3707 let Inst{23} = addr{8};
3708 let Inst{22} = Dbit;
3709 let Inst{21} = 1; // W = 1
3710 let Inst{20} = load;
3711 let Inst{19-16} = addr{12-9};
3712 let Inst{15-12} = CRd;
3713 let Inst{11-8} = cop;
3714 let Inst{7-0} = addr{7-0};
3715 let DecoderMethod = "DecodeCopMemInstruction";
3717 def _POST: T2CI<op31_28,
3718 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3719 postidx_imm8s4:$offset),
3720 asm, "\t$cop, $CRd, $addr, $offset"> {
3725 let Inst{24} = 0; // P = 0
3726 let Inst{23} = offset{8};
3727 let Inst{22} = Dbit;
3728 let Inst{21} = 1; // W = 1
3729 let Inst{20} = load;
3730 let Inst{19-16} = addr;
3731 let Inst{15-12} = CRd;
3732 let Inst{11-8} = cop;
3733 let Inst{7-0} = offset{7-0};
3734 let DecoderMethod = "DecodeCopMemInstruction";
3736 def _OPTION : T2CI<op31_28, (outs),
3737 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3738 coproc_option_imm:$option),
3739 asm, "\t$cop, $CRd, $addr, $option"> {
3744 let Inst{24} = 0; // P = 0
3745 let Inst{23} = 1; // U = 1
3746 let Inst{22} = Dbit;
3747 let Inst{21} = 0; // W = 0
3748 let Inst{20} = load;
3749 let Inst{19-16} = addr;
3750 let Inst{15-12} = CRd;
3751 let Inst{11-8} = cop;
3752 let Inst{7-0} = option;
3753 let DecoderMethod = "DecodeCopMemInstruction";
3757 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3758 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3759 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3760 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3761 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3762 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3763 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3764 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3767 //===----------------------------------------------------------------------===//
3768 // Move between special register and ARM core register -- for disassembly only
3770 // Move to ARM core register from Special Register
3774 // A/R class can only move from CPSR or SPSR.
3775 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3776 []>, Requires<[IsThumb2,IsARClass]> {
3778 let Inst{31-12} = 0b11110011111011111000;
3779 let Inst{11-8} = Rd;
3780 let Inst{7-0} = 0b0000;
3783 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3785 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3786 []>, Requires<[IsThumb2,IsARClass]> {
3788 let Inst{31-12} = 0b11110011111111111000;
3789 let Inst{11-8} = Rd;
3790 let Inst{7-0} = 0b0000;
3795 // This MRS has a mask field in bits 7-0 and can take more values than
3796 // the A/R class (a full msr_mask).
3797 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3798 "mrs", "\t$Rd, $mask", []>,
3799 Requires<[IsThumb,IsMClass]> {
3802 let Inst{31-12} = 0b11110011111011111000;
3803 let Inst{11-8} = Rd;
3804 let Inst{19-16} = 0b1111;
3805 let Inst{7-0} = mask;
3809 // Move from ARM core register to Special Register
3813 // No need to have both system and application versions, the encodings are the
3814 // same and the assembly parser has no way to distinguish between them. The mask
3815 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3816 // the mask with the fields to be accessed in the special register.
3817 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3818 NoItinerary, "msr", "\t$mask, $Rn", []>,
3819 Requires<[IsThumb2,IsARClass]> {
3822 let Inst{31-21} = 0b11110011100;
3823 let Inst{20} = mask{4}; // R Bit
3824 let Inst{19-16} = Rn;
3825 let Inst{15-12} = 0b1000;
3826 let Inst{11-8} = mask{3-0};
3832 // Move from ARM core register to Special Register
3833 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3834 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3835 Requires<[IsThumb,IsMClass]> {
3838 let Inst{31-21} = 0b11110011100;
3840 let Inst{19-16} = Rn;
3841 let Inst{15-12} = 0b1000;
3842 let Inst{11-0} = SYSm;
3846 //===----------------------------------------------------------------------===//
3847 // Move between coprocessor and ARM core register
3850 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3852 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3854 let Inst{27-24} = 0b1110;
3855 let Inst{20} = direction;
3865 let Inst{15-12} = Rt;
3866 let Inst{11-8} = cop;
3867 let Inst{23-21} = opc1;
3868 let Inst{7-5} = opc2;
3869 let Inst{3-0} = CRm;
3870 let Inst{19-16} = CRn;
3873 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3874 list<dag> pattern = []>
3876 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3877 opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3878 let Inst{27-24} = 0b1100;
3879 let Inst{23-21} = 0b010;
3880 let Inst{20} = direction;
3888 let Inst{15-12} = Rt;
3889 let Inst{19-16} = Rt2;
3890 let Inst{11-8} = cop;
3891 let Inst{7-4} = opc1;
3892 let Inst{3-0} = CRm;
3895 /* from ARM core register to coprocessor */
3896 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3898 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3899 c_imm:$CRm, imm0_7:$opc2),
3900 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3901 imm:$CRm, imm:$opc2)]>;
3902 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
3903 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3904 c_imm:$CRm, 0, pred:$p)>;
3905 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3906 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3907 c_imm:$CRm, imm0_7:$opc2),
3908 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3909 imm:$CRm, imm:$opc2)]>;
3910 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
3911 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3912 c_imm:$CRm, 0, pred:$p)>;
3914 /* from coprocessor to ARM core register */
3915 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3916 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3917 c_imm:$CRm, imm0_7:$opc2), []>;
3918 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
3919 (t2MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3920 c_imm:$CRm, 0, pred:$p)>;
3922 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3923 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3924 c_imm:$CRm, imm0_7:$opc2), []>;
3925 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
3926 (t2MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3927 c_imm:$CRm, 0, pred:$p)>;
3929 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3930 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3932 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3933 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3936 /* from ARM core register to coprocessor */
3937 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3938 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3940 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3941 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3942 GPR:$Rt2, imm:$CRm)]>;
3943 /* from coprocessor to ARM core register */
3944 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3946 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3948 //===----------------------------------------------------------------------===//
3949 // Other Coprocessor Instructions.
3952 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3953 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3954 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3955 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3956 imm:$CRm, imm:$opc2)]> {
3957 let Inst{27-24} = 0b1110;
3966 let Inst{3-0} = CRm;
3968 let Inst{7-5} = opc2;
3969 let Inst{11-8} = cop;
3970 let Inst{15-12} = CRd;
3971 let Inst{19-16} = CRn;
3972 let Inst{23-20} = opc1;
3975 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3976 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3977 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3978 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3979 imm:$CRm, imm:$opc2)]> {
3980 let Inst{27-24} = 0b1110;
3989 let Inst{3-0} = CRm;
3991 let Inst{7-5} = opc2;
3992 let Inst{11-8} = cop;
3993 let Inst{15-12} = CRd;
3994 let Inst{19-16} = CRn;
3995 let Inst{23-20} = opc1;
4000 //===----------------------------------------------------------------------===//
4001 // Non-Instruction Patterns
4004 // SXT/UXT with no rotate
4005 let AddedComplexity = 16 in {
4006 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4007 Requires<[IsThumb2]>;
4008 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4009 Requires<[IsThumb2]>;
4010 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4011 Requires<[HasT2ExtractPack, IsThumb2]>;
4012 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4013 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4014 Requires<[HasT2ExtractPack, IsThumb2]>;
4015 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4016 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4017 Requires<[HasT2ExtractPack, IsThumb2]>;
4020 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4021 Requires<[IsThumb2]>;
4022 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4023 Requires<[IsThumb2]>;
4024 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4025 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4026 Requires<[HasT2ExtractPack, IsThumb2]>;
4027 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4028 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4029 Requires<[HasT2ExtractPack, IsThumb2]>;
4031 // Atomic load/store patterns
4032 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4033 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4034 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4035 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4036 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4037 (t2LDRBs t2addrmode_so_reg:$addr)>;
4038 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4039 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4040 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4041 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4042 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4043 (t2LDRHs t2addrmode_so_reg:$addr)>;
4044 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4045 (t2LDRi12 t2addrmode_imm12:$addr)>;
4046 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4047 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4048 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4049 (t2LDRs t2addrmode_so_reg:$addr)>;
4050 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4051 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4052 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4053 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4054 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4055 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4056 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4057 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4058 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4059 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4060 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4061 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4062 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4063 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4064 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4065 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4066 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4067 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4070 //===----------------------------------------------------------------------===//
4071 // Assembler aliases
4074 // Aliases for ADC without the ".w" optional width specifier.
4075 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4076 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4077 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4078 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4079 pred:$p, cc_out:$s)>;
4081 // Aliases for SBC without the ".w" optional width specifier.
4082 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4083 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4084 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4085 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4086 pred:$p, cc_out:$s)>;
4088 // Aliases for ADD without the ".w" optional width specifier.
4089 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4090 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4091 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4092 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4093 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4094 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4095 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4096 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4097 pred:$p, cc_out:$s)>;
4098 // ... and with the destination and source register combined.
4099 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4100 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4101 def : t2InstAlias<"add${p} $Rdn, $imm",
4102 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4103 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4104 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4105 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4106 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4107 pred:$p, cc_out:$s)>;
4109 // add w/ negative immediates is just a sub.
4110 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4111 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4113 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4114 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4115 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4116 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4118 def : t2InstAlias<"add${p} $Rdn, $imm",
4119 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4121 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4122 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4124 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4125 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4126 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4127 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4129 def : t2InstAlias<"addw${p} $Rdn, $imm",
4130 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4133 // Aliases for SUB without the ".w" optional width specifier.
4134 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4135 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4136 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4137 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4138 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4139 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4140 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4141 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4142 pred:$p, cc_out:$s)>;
4143 // ... and with the destination and source register combined.
4144 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4145 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4146 def : t2InstAlias<"sub${p} $Rdn, $imm",
4147 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4148 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4149 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4150 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4151 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4152 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4153 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4154 pred:$p, cc_out:$s)>;
4156 // Alias for compares without the ".w" optional width specifier.
4157 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4158 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4159 def : t2InstAlias<"teq${p} $Rn, $Rm",
4160 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4161 def : t2InstAlias<"tst${p} $Rn, $Rm",
4162 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4165 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
4166 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
4167 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p)>, Requires<[IsThumb2, HasDB]>;
4169 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4171 def : t2InstAlias<"ldr${p} $Rt, $addr",
4172 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4173 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4174 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4175 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4176 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4177 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4178 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4179 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4180 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4182 def : t2InstAlias<"ldr${p} $Rt, $addr",
4183 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4184 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4185 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4186 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4187 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4188 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4189 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4190 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4191 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4193 def : t2InstAlias<"ldr${p} $Rt, $addr",
4194 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4195 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4196 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4197 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4198 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4199 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4200 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4201 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4202 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4204 // Alias for MVN with(out) the ".w" optional width specifier.
4205 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4206 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4207 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4208 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4209 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4210 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4212 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4213 // shift amount is zero (i.e., unspecified).
4214 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4215 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4216 Requires<[HasT2ExtractPack, IsThumb2]>;
4217 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4218 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4219 Requires<[HasT2ExtractPack, IsThumb2]>;
4221 // PUSH/POP aliases for STM/LDM
4222 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4223 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4224 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4225 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4227 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4228 def : t2InstAlias<"stm${p} $Rn, $regs",
4229 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4230 def : t2InstAlias<"stm${p} $Rn!, $regs",
4231 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4233 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4234 def : t2InstAlias<"ldm${p} $Rn, $regs",
4235 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4236 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4237 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4239 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4240 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4241 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4242 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4243 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4245 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4246 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4247 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4248 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4249 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4251 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4252 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4253 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4254 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4257 // Alias for RSB without the ".w" optional width specifier, and with optional
4258 // implied destination register.
4259 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4260 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4261 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4262 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4263 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4264 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4265 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4266 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4269 // SSAT/USAT optional shift operand.
4270 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4271 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4272 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4273 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4275 // STM w/o the .w suffix.
4276 def : t2InstAlias<"stm${p} $Rn, $regs",
4277 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4279 // Alias for STR, STRB, and STRH without the ".w" optional
4281 def : t2InstAlias<"str${p} $Rt, $addr",
4282 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4283 def : t2InstAlias<"strb${p} $Rt, $addr",
4284 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4285 def : t2InstAlias<"strh${p} $Rt, $addr",
4286 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4288 def : t2InstAlias<"str${p} $Rt, $addr",
4289 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4290 def : t2InstAlias<"strb${p} $Rt, $addr",
4291 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4292 def : t2InstAlias<"strh${p} $Rt, $addr",
4293 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4295 // Extend instruction optional rotate operand.
4296 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4297 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4298 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4299 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4300 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4301 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4303 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4304 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4305 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4306 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4307 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4308 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4309 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4310 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4311 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4312 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4314 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4315 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4316 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4317 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4318 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4319 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4320 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4321 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4322 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4323 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4324 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4325 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4327 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4328 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4329 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4330 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4332 // Extend instruction w/o the ".w" optional width specifier.
4333 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4334 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4335 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4336 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4337 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4338 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4340 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4341 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4342 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4343 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4344 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4345 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4348 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4350 def : t2InstAlias<"mov${p} $Rd, $imm",
4351 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4352 def : t2InstAlias<"mvn${p} $Rd, $imm",
4353 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4354 // Same for AND <--> BIC
4355 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4356 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4357 pred:$p, cc_out:$s)>;
4358 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4359 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4360 pred:$p, cc_out:$s)>;
4361 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4362 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4363 pred:$p, cc_out:$s)>;
4364 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4365 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4366 pred:$p, cc_out:$s)>;
4367 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4368 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4369 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4370 pred:$p, cc_out:$s)>;
4371 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4372 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4373 pred:$p, cc_out:$s)>;
4374 // Same for CMP <--> CMN via t2_so_imm_neg
4375 def : t2InstAlias<"cmp${p} $Rd, $imm",
4376 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4377 def : t2InstAlias<"cmn${p} $Rd, $imm",
4378 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4381 // Wide 'mul' encoding can be specified with only two operands.
4382 def : t2InstAlias<"mul${p} $Rn, $Rm",
4383 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4385 // "neg" is and alias for "rsb rd, rn, #0"
4386 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4387 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4389 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4390 // these, unfortunately.
4391 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4392 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4393 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4394 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4396 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4397 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4398 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4399 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4401 // ADR w/o the .w suffix
4402 def : t2InstAlias<"adr${p} $Rd, $addr",
4403 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4405 // LDR(literal) w/ alternate [pc, #imm] syntax.
4406 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4407 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4408 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4409 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4410 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4411 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4412 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4413 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4414 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4415 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4416 // Version w/ the .w suffix.
4417 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4418 (t2LDRpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4419 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4420 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4421 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4422 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4423 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4424 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4425 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4426 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4428 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4429 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
4431 // PLI with alternate literal form.
4432 def : t2InstAlias<"pli${p} $addr", (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p)>;