1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
53 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 def imm0_255_neg : PatLeaf<(i32 imm), [{
87 return (uint32_t)(-N->getZExtValue()) < 255;
90 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
92 def imm0_65535 : PatLeaf<(i32 imm), [{
93 return (uint32_t)N->getZExtValue() < 65536;
96 /// Split a 32-bit immediate into two 16 bit parts.
97 def t2_lo16 : SDNodeXForm<imm, [{
98 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
102 def t2_hi16 : SDNodeXForm<imm, [{
103 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
106 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
107 // Returns true if all low 16-bits are 0.
108 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
112 // Define Thumb2 specific addressing modes.
114 // t2addrmode_imm12 := reg + imm12
115 def t2addrmode_imm12 : Operand<i32>,
116 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
117 let PrintMethod = "printT2AddrModeImm12Operand";
118 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
121 // t2addrmode_imm8 := reg - imm8
122 def t2addrmode_imm8 : Operand<i32>,
123 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
124 let PrintMethod = "printT2AddrModeImm8Operand";
125 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
128 def t2am_imm8_offset : Operand<i32>,
129 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
130 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
133 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
134 def t2addrmode_imm8s4 : Operand<i32>,
135 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
136 let PrintMethod = "printT2AddrModeImm8s4Operand";
137 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
140 // t2addrmode_so_reg := reg + (reg << imm2)
141 def t2addrmode_so_reg : Operand<i32>,
142 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
143 let PrintMethod = "printT2AddrModeSoRegOperand";
144 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
148 //===----------------------------------------------------------------------===//
149 // Multiclass helpers...
152 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
153 /// unary operation that produces a value. These are predicable and can be
154 /// changed to modify CPSR.
155 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
157 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iALU,
159 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
160 let isAsCheapAsAMove = Cheap;
161 let isReMaterializable = ReMat;
164 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
165 opc, ".w $dst, $src",
166 [(set GPR:$dst, (opnode GPR:$src))]>;
168 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iALU,
169 opc, ".w $dst, $src",
170 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
173 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
174 // binary operation that produces a value. These are predicable and can be
175 /// changed to modify CPSR.
176 multiclass T2I_bin_irs<string opc, PatFrag opnode,
177 bit Commutable = 0, string wide =""> {
179 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
180 opc, " $dst, $lhs, $rhs",
181 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
183 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
184 opc, !strconcat(wide, " $dst, $lhs, $rhs"),
185 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
186 let isCommutable = Commutable;
189 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
190 opc, !strconcat(wide, " $dst, $lhs, $rhs"),
191 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
194 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
195 // the ".w" prefix to indicate that they are wide.
196 multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> :
197 T2I_bin_irs<opc, opnode, Commutable, ".w">;
199 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
200 /// reversed. It doesn't define the 'rr' form since it's handled by its
201 /// T2I_bin_irs counterpart.
202 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
204 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALU,
205 opc, ".w $dst, $rhs, $lhs",
206 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
208 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALU,
209 opc, " $dst, $rhs, $lhs",
210 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
213 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
214 /// instruction modifies the CPSR register.
215 let Defs = [CPSR] in {
216 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
218 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
219 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
220 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
222 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
223 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
224 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
225 let isCommutable = Commutable;
228 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
229 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
230 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
234 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
235 /// patterns for a binary operation that produces a value.
236 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
238 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
239 opc, ".w $dst, $lhs, $rhs",
240 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
242 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
243 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
244 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
246 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
247 opc, ".w $dst, $lhs, $rhs",
248 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
249 let isCommutable = Commutable;
252 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
253 opc, ".w $dst, $lhs, $rhs",
254 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
257 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
258 /// binary operation that produces a value and use and define the carry bit.
259 /// It's not predicable.
260 let Uses = [CPSR] in {
261 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
263 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
264 opc, " $dst, $lhs, $rhs",
265 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
266 Requires<[IsThumb2, CarryDefIsUnused]>;
268 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
269 opc, ".w $dst, $lhs, $rhs",
270 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
271 Requires<[IsThumb2, CarryDefIsUnused]> {
272 let isCommutable = Commutable;
275 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
276 opc, ".w $dst, $lhs, $rhs",
277 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
278 Requires<[IsThumb2, CarryDefIsUnused]>;
279 // Carry setting variants
281 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
282 !strconcat(opc, "s $dst, $lhs, $rhs"),
283 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
284 Requires<[IsThumb2, CarryDefIsUsed]> {
288 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
289 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
290 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
291 Requires<[IsThumb2, CarryDefIsUsed]> {
293 let isCommutable = Commutable;
296 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
297 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
298 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
299 Requires<[IsThumb2, CarryDefIsUsed]> {
305 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
306 let Defs = [CPSR] in {
307 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
309 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), IIC_iALU,
310 !strconcat(opc, "${s}.w $dst, $rhs, $lhs"),
311 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
313 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), IIC_iALU,
314 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
315 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
319 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
320 // rotate operation that produces a value.
321 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
324 opc, ".w $dst, $lhs, $rhs",
325 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
327 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
328 opc, ".w $dst, $lhs, $rhs",
329 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
332 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
333 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
334 /// a explicit result, only implicitly set CPSR.
335 let Defs = [CPSR] in {
336 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
338 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
339 opc, ".w $lhs, $rhs",
340 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
342 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
343 opc, ".w $lhs, $rhs",
344 [(opnode GPR:$lhs, GPR:$rhs)]>;
346 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
347 opc, ".w $lhs, $rhs",
348 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
352 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
353 multiclass T2I_ld<string opc, PatFrag opnode> {
354 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoad,
355 opc, ".w $dst, $addr",
356 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
357 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoad,
359 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
360 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoad,
361 opc, ".w $dst, $addr",
362 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
363 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoad,
364 opc, ".w $dst, $addr",
365 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
368 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
369 multiclass T2I_st<string opc, PatFrag opnode> {
370 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStore,
371 opc, ".w $src, $addr",
372 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
373 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStore,
375 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
376 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStore,
377 opc, ".w $src, $addr",
378 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
381 /// T2I_picld - Defines the PIC load pattern.
382 class T2I_picld<string opc, PatFrag opnode> :
383 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoad,
384 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
385 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
387 /// T2I_picst - Defines the PIC store pattern.
388 class T2I_picst<string opc, PatFrag opnode> :
389 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStore,
390 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
391 [(opnode GPR:$src, addrmodepc:$addr)]>;
394 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
395 /// register and one whose operand is a register rotated by 8/16/24.
396 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
397 def r : T2I<(outs GPR:$dst), (ins GPR:$Src), IIC_iALU,
398 opc, ".w $dst, $Src",
399 [(set GPR:$dst, (opnode GPR:$Src))]>;
400 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), IIC_iALU,
401 opc, ".w $dst, $Src, ror $rot",
402 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
405 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
406 /// register and one whose operand is a register rotated by 8/16/24.
407 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
408 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALU,
409 opc, " $dst, $LHS, $RHS",
410 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
411 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
412 IIC_iALU, opc, " $dst, $LHS, $RHS, ror $rot",
413 [(set GPR:$dst, (opnode GPR:$LHS,
414 (rotr GPR:$RHS, rot_imm:$rot)))]>;
417 //===----------------------------------------------------------------------===//
419 //===----------------------------------------------------------------------===//
421 //===----------------------------------------------------------------------===//
422 // Miscellaneous Instructions.
425 // LEApcrel - Load a pc-relative address into a register without offending the
427 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALU,
428 "adr$p.w $dst, #$label", []>;
430 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
431 (ins i32imm:$label, i32imm:$id, pred:$p), IIC_iALU,
432 "adr$p.w $dst, #${label}_${id:no_hash}", []>;
434 //===----------------------------------------------------------------------===//
435 // Load / store Instructions.
439 let canFoldAsLoad = 1 in
440 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
442 // Loads with zero extension
443 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
444 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
446 // Loads with sign extension
447 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
448 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
452 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
453 IIC_iLoad, "ldrd", " $dst, $addr", []>;
454 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoad,
455 "ldrd", " $dst, $addr", []>;
458 // zextload i1 -> zextload i8
459 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
460 (t2LDRBi12 t2addrmode_imm12:$addr)>;
461 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
462 (t2LDRBi8 t2addrmode_imm8:$addr)>;
463 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
464 (t2LDRBs t2addrmode_so_reg:$addr)>;
465 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
466 (t2LDRBpci tconstpool:$addr)>;
468 // extload -> zextload
469 // FIXME: Reduce the number of patterns by legalizing extload to zextload
471 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
472 (t2LDRBi12 t2addrmode_imm12:$addr)>;
473 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
474 (t2LDRBi8 t2addrmode_imm8:$addr)>;
475 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
476 (t2LDRBs t2addrmode_so_reg:$addr)>;
477 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
478 (t2LDRBpci tconstpool:$addr)>;
480 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
481 (t2LDRBi12 t2addrmode_imm12:$addr)>;
482 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
483 (t2LDRBi8 t2addrmode_imm8:$addr)>;
484 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
485 (t2LDRBs t2addrmode_so_reg:$addr)>;
486 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
487 (t2LDRBpci tconstpool:$addr)>;
489 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
490 (t2LDRHi12 t2addrmode_imm12:$addr)>;
491 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
492 (t2LDRHi8 t2addrmode_imm8:$addr)>;
493 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
494 (t2LDRHs t2addrmode_so_reg:$addr)>;
495 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
496 (t2LDRHpci tconstpool:$addr)>;
500 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
501 (ins t2addrmode_imm8:$addr),
502 AddrModeT2_i8, IndexModePre, IIC_iLoad,
503 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
506 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
507 (ins GPR:$base, t2am_imm8_offset:$offset),
508 AddrModeT2_i8, IndexModePost, IIC_iLoad,
509 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
512 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
513 (ins t2addrmode_imm8:$addr),
514 AddrModeT2_i8, IndexModePre, IIC_iLoad,
515 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
517 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
518 (ins GPR:$base, t2am_imm8_offset:$offset),
519 AddrModeT2_i8, IndexModePost, IIC_iLoad,
520 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
523 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
524 (ins t2addrmode_imm8:$addr),
525 AddrModeT2_i8, IndexModePre, IIC_iLoad,
526 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
528 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
529 (ins GPR:$base, t2am_imm8_offset:$offset),
530 AddrModeT2_i8, IndexModePost, IIC_iLoad,
531 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
534 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
535 (ins t2addrmode_imm8:$addr),
536 AddrModeT2_i8, IndexModePre, IIC_iLoad,
537 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
539 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
540 (ins GPR:$base, t2am_imm8_offset:$offset),
541 AddrModeT2_i8, IndexModePost, IIC_iLoad,
542 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
545 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
546 (ins t2addrmode_imm8:$addr),
547 AddrModeT2_i8, IndexModePre, IIC_iLoad,
548 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
550 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
551 (ins GPR:$base, t2am_imm8_offset:$offset),
552 AddrModeT2_i8, IndexModePost, IIC_iLoad,
553 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
558 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
559 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
560 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
564 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr), IIC_iStore,
565 "strd", " $src, $addr", []>;
568 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
569 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
570 AddrModeT2_i8, IndexModePre, IIC_iStore,
571 "str", " $src, [$base, $offset]!", "$base = $base_wb",
573 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
575 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
576 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
577 AddrModeT2_i8, IndexModePost, IIC_iStore,
578 "str", " $src, [$base], $offset", "$base = $base_wb",
580 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
582 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
583 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
584 AddrModeT2_i8, IndexModePre, IIC_iStore,
585 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
587 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
589 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
590 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
591 AddrModeT2_i8, IndexModePost, IIC_iStore,
592 "strh", " $src, [$base], $offset", "$base = $base_wb",
594 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
596 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
597 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
598 AddrModeT2_i8, IndexModePre, IIC_iStore,
599 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
601 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
603 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
604 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
605 AddrModeT2_i8, IndexModePost, IIC_iStore,
606 "strb", " $src, [$base], $offset", "$base = $base_wb",
608 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
611 // FIXME: ldrd / strd pre / post variants
613 //===----------------------------------------------------------------------===//
614 // Load / store multiple Instructions.
618 def t2LDM : T2XI<(outs),
619 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
620 IIC_iLoad, "ldm${addr:submode}${p} $addr, $dst1", []>;
623 def t2STM : T2XI<(outs),
624 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
625 IIC_iStore, "stm${addr:submode}${p} $addr, $src1", []>;
627 //===----------------------------------------------------------------------===//
628 // Move Instructions.
631 let neverHasSideEffects = 1 in
632 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
633 "mov", ".w $dst, $src", []>;
635 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
636 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iALU,
637 "mov", ".w $dst, $src",
638 [(set GPR:$dst, t2_so_imm:$src)]>;
640 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
641 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iALU,
642 "movw", " $dst, $src",
643 [(set GPR:$dst, imm0_65535:$src)]>;
645 // FIXME: Also available in ARM mode.
646 let Constraints = "$src = $dst" in
647 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iALU,
648 "movt", " $dst, $imm",
650 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
652 //===----------------------------------------------------------------------===//
653 // Extend Instructions.
658 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
659 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
661 defm t2SXTAB : T2I_bin_rrot<"sxtab",
662 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
663 defm t2SXTAH : T2I_bin_rrot<"sxtah",
664 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
666 // TODO: SXT(A){B|H}16
670 let AddedComplexity = 16 in {
671 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
672 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
673 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
675 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
676 (t2UXTB16r_rot GPR:$Src, 24)>;
677 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
678 (t2UXTB16r_rot GPR:$Src, 8)>;
680 defm t2UXTAB : T2I_bin_rrot<"uxtab",
681 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
682 defm t2UXTAH : T2I_bin_rrot<"uxtah",
683 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
686 //===----------------------------------------------------------------------===//
687 // Arithmetic Instructions.
690 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
691 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
693 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
694 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
695 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
697 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
698 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
701 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
702 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
704 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
705 let AddedComplexity = 1 in
706 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
707 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
708 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
709 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
710 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
711 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
714 //===----------------------------------------------------------------------===//
715 // Shift and rotate Instructions.
718 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
719 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
720 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
721 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
723 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
724 "rrx", ".w $dst, $src",
725 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
727 let Defs = [CPSR] in {
728 def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
729 "lsrs.w $dst, $src, #1",
730 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
731 def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
732 "asrs.w $dst, $src, #1",
733 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
736 //===----------------------------------------------------------------------===//
737 // Bitwise Instructions.
740 defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
741 defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
742 defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
744 defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
746 let Constraints = "$src = $dst" in
747 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), IIC_iALU,
748 "bfc", " $dst, $imm",
749 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
751 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
754 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
756 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
757 def t2ORNri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
758 "orn", " $dst, $lhs, $rhs",
759 [(set GPR:$dst, (or GPR:$lhs, (not t2_so_imm:$rhs)))]>,
760 Requires<[IsThumb2, IsNotDarwin]>;
762 def t2ORNrr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
763 "orn", " $dst, $lhs, $rhs",
764 [(set GPR:$dst, (or GPR:$lhs, (not GPR:$rhs)))]>;
765 def t2ORNrs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
766 "orn", " $dst, $lhs, $rhs",
767 [(set GPR:$dst, (or GPR:$lhs, (not t2_so_reg:$rhs)))]>;
769 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
770 let AddedComplexity = 1 in
771 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
774 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
775 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
777 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
778 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
779 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
780 Requires<[IsThumb2, IsNotDarwin]>;
782 def : T2Pat<(t2_so_imm_not:$src),
783 (t2MVNi t2_so_imm_not:$src)>;
785 //===----------------------------------------------------------------------===//
786 // Multiply Instructions.
788 let isCommutable = 1 in
789 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU,
790 "mul", " $dst, $a, $b",
791 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
793 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iALU,
794 "mla", " $dst, $a, $b, $c",
795 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
797 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iALU,
798 "mls", " $dst, $a, $b, $c",
799 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
801 // Extra precision multiplies with low / high results
802 let neverHasSideEffects = 1 in {
803 let isCommutable = 1 in {
804 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU,
805 "smull", " $ldst, $hdst, $a, $b", []>;
807 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU,
808 "umull", " $ldst, $hdst, $a, $b", []>;
811 // Multiply + accumulate
812 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU,
813 "smlal", " $ldst, $hdst, $a, $b", []>;
815 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU,
816 "umlal", " $ldst, $hdst, $a, $b", []>;
818 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iALU,
819 "umaal", " $ldst, $hdst, $a, $b", []>;
820 } // neverHasSideEffects
822 // Most significant word multiply
823 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU,
824 "smmul", " $dst, $a, $b",
825 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
827 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iALU,
828 "smmla", " $dst, $a, $b, $c",
829 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
832 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iALU,
833 "smmls", " $dst, $a, $b, $c",
834 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
836 multiclass T2I_smul<string opc, PatFrag opnode> {
837 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU,
838 !strconcat(opc, "bb"), " $dst, $a, $b",
839 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
840 (sext_inreg GPR:$b, i16)))]>;
842 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU,
843 !strconcat(opc, "bt"), " $dst, $a, $b",
844 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
845 (sra GPR:$b, (i32 16))))]>;
847 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU,
848 !strconcat(opc, "tb"), " $dst, $a, $b",
849 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
850 (sext_inreg GPR:$b, i16)))]>;
852 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU,
853 !strconcat(opc, "tt"), " $dst, $a, $b",
854 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
855 (sra GPR:$b, (i32 16))))]>;
857 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU,
858 !strconcat(opc, "wb"), " $dst, $a, $b",
859 [(set GPR:$dst, (sra (opnode GPR:$a,
860 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
862 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU,
863 !strconcat(opc, "wt"), " $dst, $a, $b",
864 [(set GPR:$dst, (sra (opnode GPR:$a,
865 (sra GPR:$b, (i32 16))), (i32 16)))]>;
869 multiclass T2I_smla<string opc, PatFrag opnode> {
870 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU,
871 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
872 [(set GPR:$dst, (add GPR:$acc,
873 (opnode (sext_inreg GPR:$a, i16),
874 (sext_inreg GPR:$b, i16))))]>;
876 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU,
877 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
878 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
879 (sra GPR:$b, (i32 16)))))]>;
881 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU,
882 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
883 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
884 (sext_inreg GPR:$b, i16))))]>;
886 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU,
887 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
888 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
889 (sra GPR:$b, (i32 16)))))]>;
891 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU,
892 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
893 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
894 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
896 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iALU,
897 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
898 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
899 (sra GPR:$b, (i32 16))), (i32 16))))]>;
902 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
903 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
905 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
906 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
909 //===----------------------------------------------------------------------===//
910 // Misc. Arithmetic Instructions.
913 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
914 "clz", " $dst, $src",
915 [(set GPR:$dst, (ctlz GPR:$src))]>;
917 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
918 "rev", ".w $dst, $src",
919 [(set GPR:$dst, (bswap GPR:$src))]>;
921 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
922 "rev16", ".w $dst, $src",
924 (or (and (srl GPR:$src, (i32 8)), 0xFF),
925 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
926 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
927 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
929 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
930 "revsh", ".w $dst, $src",
933 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
934 (shl GPR:$src, (i32 8))), i16))]>;
936 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
937 IIC_iALU, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
938 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
939 (and (shl GPR:$src2, (i32 imm:$shamt)),
942 // Alternate cases for PKHBT where identities eliminate some nodes.
943 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
944 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
945 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
946 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
948 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
949 IIC_iALU, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
950 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
951 (and (sra GPR:$src2, imm16_31:$shamt),
954 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
955 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
956 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
957 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
958 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
959 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
960 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
962 //===----------------------------------------------------------------------===//
963 // Comparison Instructions...
966 defm t2CMP : T2I_cmp_is<"cmp",
967 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
968 defm t2CMPz : T2I_cmp_is<"cmp",
969 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
971 defm t2CMN : T2I_cmp_is<"cmn",
972 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
973 defm t2CMNz : T2I_cmp_is<"cmn",
974 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
976 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
977 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
979 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
980 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
982 defm t2TST : T2I_cmp_is<"tst",
983 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
984 defm t2TEQ : T2I_cmp_is<"teq",
985 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
987 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
988 // Short range conditional branch. Looks awesome for loops. Need to figure
989 // out how to use this one.
993 // FIXME: should be able to write a pattern for ARMcmov, but can't use
994 // a two-value operand where a dag node expects two operands. :(
995 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iALU,
996 "mov", ".w $dst, $true",
997 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
998 RegConstraint<"$false = $dst">;
1000 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), IIC_iALU,
1001 "mov", ".w $dst, $true",
1002 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1003 RegConstraint<"$false = $dst">;
1005 def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1006 IIC_iALU, "lsl", ".w $dst, $true, $rhs", []>,
1007 RegConstraint<"$false = $dst">;
1008 def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1009 IIC_iALU, "lsr", ".w $dst, $true, $rhs", []>,
1010 RegConstraint<"$false = $dst">;
1011 def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1012 IIC_iALU, "asr", ".w $dst, $true, $rhs", []>,
1013 RegConstraint<"$false = $dst">;
1014 def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1015 IIC_iALU, "ror", ".w $dst, $true, $rhs", []>,
1016 RegConstraint<"$false = $dst">;
1018 //===----------------------------------------------------------------------===//
1022 // __aeabi_read_tp preserves the registers r1-r3.
1024 Defs = [R0, R12, LR, CPSR] in {
1025 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
1026 "bl __aeabi_read_tp",
1027 [(set R0, ARMthread_pointer)]>;
1030 //===----------------------------------------------------------------------===//
1031 // Control-Flow Instructions
1034 // FIXME: remove when we have a way to marking a MI with these properties.
1035 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1037 // FIXME: Should pc be an implicit operand like PICADD, etc?
1038 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
1039 def t2LDM_RET : T2XI<(outs),
1040 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
1041 IIC_iLoad, "ldm${addr:submode}${p} $addr, $dst1",
1044 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1045 let isPredicable = 1 in
1046 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
1050 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1053 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
1054 IIC_Br, "mov pc, $target\n$jt",
1055 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
1057 // FIXME: Add a non-pc based case that can be predicated.
1060 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1061 IIC_Br, "tbb $index\n$jt", []>;
1065 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1066 IIC_Br, "tbh $index\n$jt", []>;
1067 } // isNotDuplicable, isIndirectBranch
1069 } // isBranch, isTerminator, isBarrier
1071 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1072 // a two-value operand where a dag node expects two operands. :(
1073 let isBranch = 1, isTerminator = 1 in
1074 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
1076 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1080 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1081 AddrModeNone, Size2Bytes, IIC_iALU,
1082 "it$mask $cc", "", []>;
1084 //===----------------------------------------------------------------------===//
1085 // Non-Instruction Patterns
1088 // ConstantPool, GlobalAddress, and JumpTable
1089 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1090 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1091 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1092 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1094 // Large immediate handling.
1096 def : T2Pat<(i32 imm:$src),
1097 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;