1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 // Define Thumb2 specific addressing modes.
127 // t2addrmode_imm12 := reg + imm12
128 def t2addrmode_imm12 : Operand<i32>,
129 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
130 let PrintMethod = "printT2AddrModeImm12Operand";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
134 // t2addrmode_imm8 := reg - imm8
135 def t2addrmode_imm8 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137 let PrintMethod = "printT2AddrModeImm8Operand";
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141 def t2am_imm8_offset : Operand<i32>,
142 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
143 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
147 def t2addrmode_imm8s4 : Operand<i32>,
148 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
149 let PrintMethod = "printT2AddrModeImm8s4Operand";
150 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
153 // t2addrmode_so_reg := reg + (reg << imm2)
154 def t2addrmode_so_reg : Operand<i32>,
155 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
156 let PrintMethod = "printT2AddrModeSoRegOperand";
157 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
161 //===----------------------------------------------------------------------===//
162 // Multiclass helpers...
165 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
166 /// unary operation that produces a value. These are predicable and can be
167 /// changed to modify CPSR.
168 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
169 bit Cheap = 0, bit ReMat = 0> {
171 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
173 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
174 let isAsCheapAsAMove = Cheap;
175 let isReMaterializable = ReMat;
176 let Inst{31-27} = 0b11110;
178 let Inst{24-21} = opcod;
179 let Inst{20} = ?; // The S bit.
180 let Inst{19-16} = 0b1111; // Rn
184 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
185 opc, ".w\t$dst, $src",
186 [(set GPR:$dst, (opnode GPR:$src))]> {
187 let Inst{31-27} = 0b11101;
188 let Inst{26-25} = 0b01;
189 let Inst{24-21} = opcod;
190 let Inst{20} = ?; // The S bit.
191 let Inst{19-16} = 0b1111; // Rn
192 let Inst{14-12} = 0b000; // imm3
193 let Inst{7-6} = 0b00; // imm2
194 let Inst{5-4} = 0b00; // type
197 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
198 opc, ".w\t$dst, $src",
199 [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
200 let Inst{31-27} = 0b11101;
201 let Inst{26-25} = 0b01;
202 let Inst{24-21} = opcod;
203 let Inst{20} = ?; // The S bit.
204 let Inst{19-16} = 0b1111; // Rn
208 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
209 // binary operation that produces a value. These are predicable and can be
210 /// changed to modify CPSR.
211 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
212 bit Commutable = 0, string wide =""> {
214 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
215 opc, "\t$dst, $lhs, $rhs",
216 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
217 let Inst{31-27} = 0b11110;
219 let Inst{24-21} = opcod;
220 let Inst{20} = ?; // The S bit.
224 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
225 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
226 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
227 let isCommutable = Commutable;
228 let Inst{31-27} = 0b11101;
229 let Inst{26-25} = 0b01;
230 let Inst{24-21} = opcod;
231 let Inst{20} = ?; // The S bit.
232 let Inst{14-12} = 0b000; // imm3
233 let Inst{7-6} = 0b00; // imm2
234 let Inst{5-4} = 0b00; // type
237 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
238 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
239 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
240 let Inst{31-27} = 0b11101;
241 let Inst{26-25} = 0b01;
242 let Inst{24-21} = opcod;
243 let Inst{20} = ?; // The S bit.
247 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
248 // the ".w" prefix to indicate that they are wide.
249 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
250 bit Commutable = 0> :
251 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
253 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
254 /// reversed. It doesn't define the 'rr' form since it's handled by its
255 /// T2I_bin_irs counterpart.
256 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
258 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
259 opc, ".w\t$dst, $rhs, $lhs",
260 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
261 let Inst{31-27} = 0b11110;
263 let Inst{24-21} = opcod;
264 let Inst{20} = 0; // The S bit.
268 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
269 opc, "\t$dst, $rhs, $lhs",
270 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
271 let Inst{31-27} = 0b11101;
272 let Inst{26-25} = 0b01;
273 let Inst{24-21} = opcod;
274 let Inst{20} = 0; // The S bit.
278 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
279 /// instruction modifies the CPSR register.
280 let Defs = [CPSR] in {
281 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
282 bit Commutable = 0> {
284 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
285 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
286 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
287 let Inst{31-27} = 0b11110;
289 let Inst{24-21} = opcod;
290 let Inst{20} = 1; // The S bit.
294 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
295 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
296 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
297 let isCommutable = Commutable;
298 let Inst{31-27} = 0b11101;
299 let Inst{26-25} = 0b01;
300 let Inst{24-21} = opcod;
301 let Inst{20} = 1; // The S bit.
302 let Inst{14-12} = 0b000; // imm3
303 let Inst{7-6} = 0b00; // imm2
304 let Inst{5-4} = 0b00; // type
307 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
308 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
309 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
310 let Inst{31-27} = 0b11101;
311 let Inst{26-25} = 0b01;
312 let Inst{24-21} = opcod;
313 let Inst{20} = 1; // The S bit.
318 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
319 /// patterns for a binary operation that produces a value.
320 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
321 bit Commutable = 0> {
323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
324 opc, ".w\t$dst, $lhs, $rhs",
325 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
326 let Inst{31-27} = 0b11110;
329 let Inst{23-21} = op23_21;
330 let Inst{20} = 0; // The S bit.
334 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
335 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
336 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
337 let Inst{31-27} = 0b11110;
340 let Inst{23-21} = op23_21;
341 let Inst{20} = 0; // The S bit.
345 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
346 opc, ".w\t$dst, $lhs, $rhs",
347 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
348 let isCommutable = Commutable;
349 let Inst{31-27} = 0b11101;
350 let Inst{26-25} = 0b01;
352 let Inst{23-21} = op23_21;
353 let Inst{20} = 0; // The S bit.
354 let Inst{14-12} = 0b000; // imm3
355 let Inst{7-6} = 0b00; // imm2
356 let Inst{5-4} = 0b00; // type
359 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
360 opc, ".w\t$dst, $lhs, $rhs",
361 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
362 let Inst{31-27} = 0b11101;
363 let Inst{26-25} = 0b01;
365 let Inst{23-21} = op23_21;
366 let Inst{20} = 0; // The S bit.
370 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
371 /// for a binary operation that produces a value and use the carry
372 /// bit. It's not predicable.
373 let Uses = [CPSR] in {
374 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
375 bit Commutable = 0> {
377 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
378 opc, "\t$dst, $lhs, $rhs",
379 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
380 Requires<[IsThumb2]> {
381 let Inst{31-27} = 0b11110;
383 let Inst{24-21} = opcod;
384 let Inst{20} = 0; // The S bit.
388 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
389 opc, ".w\t$dst, $lhs, $rhs",
390 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
391 Requires<[IsThumb2]> {
392 let isCommutable = Commutable;
393 let Inst{31-27} = 0b11101;
394 let Inst{26-25} = 0b01;
395 let Inst{24-21} = opcod;
396 let Inst{20} = 0; // The S bit.
397 let Inst{14-12} = 0b000; // imm3
398 let Inst{7-6} = 0b00; // imm2
399 let Inst{5-4} = 0b00; // type
402 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
403 opc, ".w\t$dst, $lhs, $rhs",
404 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
405 Requires<[IsThumb2]> {
406 let Inst{31-27} = 0b11101;
407 let Inst{26-25} = 0b01;
408 let Inst{24-21} = opcod;
409 let Inst{20} = 0; // The S bit.
413 // Carry setting variants
414 let Defs = [CPSR] in {
415 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
416 bit Commutable = 0> {
418 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
419 opc, "\t$dst, $lhs, $rhs",
420 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
421 Requires<[IsThumb2]> {
422 let Inst{31-27} = 0b11110;
424 let Inst{24-21} = opcod;
425 let Inst{20} = 1; // The S bit.
429 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
430 opc, ".w\t$dst, $lhs, $rhs",
431 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
432 Requires<[IsThumb2]> {
433 let isCommutable = Commutable;
434 let Inst{31-27} = 0b11101;
435 let Inst{26-25} = 0b01;
436 let Inst{24-21} = opcod;
437 let Inst{20} = 1; // The S bit.
438 let Inst{14-12} = 0b000; // imm3
439 let Inst{7-6} = 0b00; // imm2
440 let Inst{5-4} = 0b00; // type
443 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
444 opc, ".w\t$dst, $lhs, $rhs",
445 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
446 Requires<[IsThumb2]> {
447 let Inst{31-27} = 0b11101;
448 let Inst{26-25} = 0b01;
449 let Inst{24-21} = opcod;
450 let Inst{20} = 1; // The S bit.
456 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
457 let Defs = [CPSR] in {
458 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
460 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
462 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"),
463 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
464 let Inst{31-27} = 0b11110;
466 let Inst{24-21} = opcod;
467 let Inst{20} = 1; // The S bit.
471 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
473 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"),
474 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
475 let Inst{31-27} = 0b11101;
476 let Inst{26-25} = 0b01;
477 let Inst{24-21} = opcod;
478 let Inst{20} = 1; // The S bit.
483 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
484 // rotate operation that produces a value.
485 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
487 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
488 opc, ".w\t$dst, $lhs, $rhs",
489 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
490 let Inst{31-27} = 0b11101;
491 let Inst{26-21} = 0b010010;
492 let Inst{19-16} = 0b1111; // Rn
493 let Inst{5-4} = opcod;
496 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
497 opc, ".w\t$dst, $lhs, $rhs",
498 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
499 let Inst{31-27} = 0b11111;
500 let Inst{26-23} = 0b0100;
501 let Inst{22-21} = opcod;
502 let Inst{15-12} = 0b1111;
503 let Inst{7-4} = 0b0000;
507 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
508 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
509 /// a explicit result, only implicitly set CPSR.
510 let Defs = [CPSR] in {
511 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
513 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
514 opc, ".w\t$lhs, $rhs",
515 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
516 let Inst{31-27} = 0b11110;
518 let Inst{24-21} = opcod;
519 let Inst{20} = 1; // The S bit.
521 let Inst{11-8} = 0b1111; // Rd
524 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
525 opc, ".w\t$lhs, $rhs",
526 [(opnode GPR:$lhs, GPR:$rhs)]> {
527 let Inst{31-27} = 0b11101;
528 let Inst{26-25} = 0b01;
529 let Inst{24-21} = opcod;
530 let Inst{20} = 1; // The S bit.
531 let Inst{14-12} = 0b000; // imm3
532 let Inst{11-8} = 0b1111; // Rd
533 let Inst{7-6} = 0b00; // imm2
534 let Inst{5-4} = 0b00; // type
537 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
538 opc, ".w\t$lhs, $rhs",
539 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
540 let Inst{31-27} = 0b11101;
541 let Inst{26-25} = 0b01;
542 let Inst{24-21} = opcod;
543 let Inst{20} = 1; // The S bit.
544 let Inst{11-8} = 0b1111; // Rd
549 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
550 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
551 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
552 opc, ".w\t$dst, $addr",
553 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
554 let Inst{31-27} = 0b11111;
555 let Inst{26-25} = 0b00;
556 let Inst{24} = signed;
558 let Inst{22-21} = opcod;
559 let Inst{20} = 1; // load
561 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
562 opc, "\t$dst, $addr",
563 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
564 let Inst{31-27} = 0b11111;
565 let Inst{26-25} = 0b00;
566 let Inst{24} = signed;
568 let Inst{22-21} = opcod;
569 let Inst{20} = 1; // load
571 // Offset: index==TRUE, wback==FALSE
572 let Inst{10} = 1; // The P bit.
573 let Inst{8} = 0; // The W bit.
575 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
576 opc, ".w\t$dst, $addr",
577 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
578 let Inst{31-27} = 0b11111;
579 let Inst{26-25} = 0b00;
580 let Inst{24} = signed;
582 let Inst{22-21} = opcod;
583 let Inst{20} = 1; // load
584 let Inst{11-6} = 0b000000;
586 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
587 opc, ".w\t$dst, $addr",
588 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
589 let isReMaterializable = 1;
590 let Inst{31-27} = 0b11111;
591 let Inst{26-25} = 0b00;
592 let Inst{24} = signed;
593 let Inst{23} = ?; // add = (U == '1')
594 let Inst{22-21} = opcod;
595 let Inst{20} = 1; // load
596 let Inst{19-16} = 0b1111; // Rn
600 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
601 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
602 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
603 opc, ".w\t$src, $addr",
604 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
605 let Inst{31-27} = 0b11111;
606 let Inst{26-23} = 0b0001;
607 let Inst{22-21} = opcod;
608 let Inst{20} = 0; // !load
610 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
611 opc, "\t$src, $addr",
612 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
613 let Inst{31-27} = 0b11111;
614 let Inst{26-23} = 0b0000;
615 let Inst{22-21} = opcod;
616 let Inst{20} = 0; // !load
618 // Offset: index==TRUE, wback==FALSE
619 let Inst{10} = 1; // The P bit.
620 let Inst{8} = 0; // The W bit.
622 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
623 opc, ".w\t$src, $addr",
624 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
625 let Inst{31-27} = 0b11111;
626 let Inst{26-23} = 0b0000;
627 let Inst{22-21} = opcod;
628 let Inst{20} = 0; // !load
629 let Inst{11-6} = 0b000000;
633 /// T2I_picld - Defines the PIC load pattern.
634 class T2I_picld<string opc, PatFrag opnode> :
635 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi,
636 !strconcat("\n${addr:label}:\n\t", opc), "\t$dst, $addr",
637 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
639 /// T2I_picst - Defines the PIC store pattern.
640 class T2I_picst<string opc, PatFrag opnode> :
641 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer,
642 !strconcat("\n${addr:label}:\n\t", opc), "\t$src, $addr",
643 [(opnode GPR:$src, addrmodepc:$addr)]>;
646 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
647 /// register and one whose operand is a register rotated by 8/16/24.
648 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
649 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
650 opc, ".w\t$dst, $src",
651 [(set GPR:$dst, (opnode GPR:$src))]> {
652 let Inst{31-27} = 0b11111;
653 let Inst{26-23} = 0b0100;
654 let Inst{22-20} = opcod;
655 let Inst{19-16} = 0b1111; // Rn
656 let Inst{15-12} = 0b1111;
658 let Inst{5-4} = 0b00; // rotate
660 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
661 opc, ".w\t$dst, $src, ror $rot",
662 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
663 let Inst{31-27} = 0b11111;
664 let Inst{26-23} = 0b0100;
665 let Inst{22-20} = opcod;
666 let Inst{19-16} = 0b1111; // Rn
667 let Inst{15-12} = 0b1111;
669 let Inst{5-4} = {?,?}; // rotate
673 // DO variant - disassembly only, no pattern
675 multiclass T2I_unary_rrot_DO<bits<3> opcod, string opc> {
676 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
677 opc, "\t$dst, $src", []> {
678 let Inst{31-27} = 0b11111;
679 let Inst{26-23} = 0b0100;
680 let Inst{22-20} = opcod;
681 let Inst{19-16} = 0b1111; // Rn
682 let Inst{15-12} = 0b1111;
684 let Inst{5-4} = 0b00; // rotate
686 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
687 opc, "\t$dst, $src, ror $rot", []> {
688 let Inst{31-27} = 0b11111;
689 let Inst{26-23} = 0b0100;
690 let Inst{22-20} = opcod;
691 let Inst{19-16} = 0b1111; // Rn
692 let Inst{15-12} = 0b1111;
694 let Inst{5-4} = {?,?}; // rotate
698 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
699 /// register and one whose operand is a register rotated by 8/16/24.
700 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
701 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
702 opc, "\t$dst, $LHS, $RHS",
703 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]> {
704 let Inst{31-27} = 0b11111;
705 let Inst{26-23} = 0b0100;
706 let Inst{22-20} = opcod;
707 let Inst{15-12} = 0b1111;
709 let Inst{5-4} = 0b00; // rotate
711 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
712 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
713 [(set GPR:$dst, (opnode GPR:$LHS,
714 (rotr GPR:$RHS, rot_imm:$rot)))]> {
715 let Inst{31-27} = 0b11111;
716 let Inst{26-23} = 0b0100;
717 let Inst{22-20} = opcod;
718 let Inst{15-12} = 0b1111;
720 let Inst{5-4} = {?,?}; // rotate
724 // DO variant - disassembly only, no pattern
726 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
727 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
728 opc, "\t$dst, $LHS, $RHS", []> {
729 let Inst{31-27} = 0b11111;
730 let Inst{26-23} = 0b0100;
731 let Inst{22-20} = opcod;
732 let Inst{15-12} = 0b1111;
734 let Inst{5-4} = 0b00; // rotate
736 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
737 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
738 let Inst{31-27} = 0b11111;
739 let Inst{26-23} = 0b0100;
740 let Inst{22-20} = opcod;
741 let Inst{15-12} = 0b1111;
743 let Inst{5-4} = {?,?}; // rotate
747 //===----------------------------------------------------------------------===//
749 //===----------------------------------------------------------------------===//
751 //===----------------------------------------------------------------------===//
752 // Miscellaneous Instructions.
755 // LEApcrel - Load a pc-relative address into a register without offending the
757 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
758 "adr$p.w\t$dst, #$label", []> {
759 let Inst{31-27} = 0b11110;
760 let Inst{25-24} = 0b10;
761 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
764 let Inst{19-16} = 0b1111; // Rn
767 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
768 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
769 "adr$p.w\t$dst, #${label}_${id}", []> {
770 let Inst{31-27} = 0b11110;
771 let Inst{25-24} = 0b10;
772 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
775 let Inst{19-16} = 0b1111; // Rn
779 // ADD r, sp, {so_imm|i12}
780 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
781 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
782 let Inst{31-27} = 0b11110;
784 let Inst{24-21} = 0b1000;
785 let Inst{20} = ?; // The S bit.
786 let Inst{19-16} = 0b1101; // Rn = sp
789 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
790 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
791 let Inst{31-27} = 0b11110;
793 let Inst{24-21} = 0b0000;
794 let Inst{20} = 0; // The S bit.
795 let Inst{19-16} = 0b1101; // Rn = sp
800 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
801 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
802 let Inst{31-27} = 0b11101;
803 let Inst{26-25} = 0b01;
804 let Inst{24-21} = 0b1000;
805 let Inst{20} = ?; // The S bit.
806 let Inst{19-16} = 0b1101; // Rn = sp
810 // SUB r, sp, {so_imm|i12}
811 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
812 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
813 let Inst{31-27} = 0b11110;
815 let Inst{24-21} = 0b1101;
816 let Inst{20} = ?; // The S bit.
817 let Inst{19-16} = 0b1101; // Rn = sp
820 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
821 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
822 let Inst{31-27} = 0b11110;
824 let Inst{24-21} = 0b0101;
825 let Inst{20} = 0; // The S bit.
826 let Inst{19-16} = 0b1101; // Rn = sp
831 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
833 "sub", "\t$dst, $sp, $rhs", []> {
834 let Inst{31-27} = 0b11101;
835 let Inst{26-25} = 0b01;
836 let Inst{24-21} = 0b1101;
837 let Inst{20} = ?; // The S bit.
838 let Inst{19-16} = 0b1101; // Rn = sp
842 // Signed and unsigned division, for disassembly only
843 def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
844 "sdiv", "\t$dst, $a, $b", []> {
845 let Inst{31-27} = 0b11111;
846 let Inst{26-21} = 0b011100;
848 let Inst{15-12} = 0b1111;
849 let Inst{7-4} = 0b1111;
852 def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
853 "udiv", "\t$dst, $a, $b", []> {
854 let Inst{31-27} = 0b11111;
855 let Inst{26-21} = 0b011101;
857 let Inst{15-12} = 0b1111;
858 let Inst{7-4} = 0b1111;
861 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
862 let usesCustomInserter = 1 in { // Expanded after instruction selection.
863 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
864 NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
865 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
866 NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
867 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
868 NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
869 } // usesCustomInserter
872 //===----------------------------------------------------------------------===//
873 // Load / store Instructions.
877 let canFoldAsLoad = 1, isReMaterializable = 1 in
878 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
880 // Loads with zero extension
881 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
882 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
884 // Loads with sign extension
885 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
886 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
888 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
890 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
891 (ins t2addrmode_imm8s4:$addr),
892 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
893 def t2LDRDpci : T2Ii8s4<?, ?, 1, (outs GPR:$dst1, GPR:$dst2),
894 (ins i32imm:$addr), IIC_iLoadi,
895 "ldrd", "\t$dst1, $addr", []> {
896 let Inst{19-16} = 0b1111; // Rn
900 // zextload i1 -> zextload i8
901 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
902 (t2LDRBi12 t2addrmode_imm12:$addr)>;
903 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
904 (t2LDRBi8 t2addrmode_imm8:$addr)>;
905 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
906 (t2LDRBs t2addrmode_so_reg:$addr)>;
907 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
908 (t2LDRBpci tconstpool:$addr)>;
910 // extload -> zextload
911 // FIXME: Reduce the number of patterns by legalizing extload to zextload
913 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
914 (t2LDRBi12 t2addrmode_imm12:$addr)>;
915 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
916 (t2LDRBi8 t2addrmode_imm8:$addr)>;
917 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
918 (t2LDRBs t2addrmode_so_reg:$addr)>;
919 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
920 (t2LDRBpci tconstpool:$addr)>;
922 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
923 (t2LDRBi12 t2addrmode_imm12:$addr)>;
924 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
925 (t2LDRBi8 t2addrmode_imm8:$addr)>;
926 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
927 (t2LDRBs t2addrmode_so_reg:$addr)>;
928 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
929 (t2LDRBpci tconstpool:$addr)>;
931 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
932 (t2LDRHi12 t2addrmode_imm12:$addr)>;
933 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
934 (t2LDRHi8 t2addrmode_imm8:$addr)>;
935 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
936 (t2LDRHs t2addrmode_so_reg:$addr)>;
937 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
938 (t2LDRHpci tconstpool:$addr)>;
942 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
943 (ins t2addrmode_imm8:$addr),
944 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
945 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
948 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
949 (ins GPR:$base, t2am_imm8_offset:$offset),
950 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
951 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
954 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
955 (ins t2addrmode_imm8:$addr),
956 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
957 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
959 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
960 (ins GPR:$base, t2am_imm8_offset:$offset),
961 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
962 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
965 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
966 (ins t2addrmode_imm8:$addr),
967 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
968 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
970 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
971 (ins GPR:$base, t2am_imm8_offset:$offset),
972 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
973 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
976 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
977 (ins t2addrmode_imm8:$addr),
978 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
979 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
981 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
982 (ins GPR:$base, t2am_imm8_offset:$offset),
983 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
984 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
987 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
988 (ins t2addrmode_imm8:$addr),
989 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
990 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
992 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
993 (ins GPR:$base, t2am_imm8_offset:$offset),
994 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
995 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1000 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1001 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1002 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1005 let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
1006 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1007 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1008 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1011 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1012 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1013 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1014 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1016 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1018 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1019 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1020 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1021 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1023 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1025 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1026 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1027 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1028 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1030 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1032 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1033 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1034 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1035 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1037 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1039 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1040 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1041 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1042 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1044 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1046 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1047 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1048 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1049 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1051 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1054 // FIXME: ldrd / strd pre / post variants
1056 //===----------------------------------------------------------------------===//
1057 // Load / store multiple Instructions.
1060 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1061 def t2LDM : T2XI<(outs),
1062 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1063 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1064 let Inst{31-27} = 0b11101;
1065 let Inst{26-25} = 0b00;
1066 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1068 let Inst{21} = ?; // The W bit.
1069 let Inst{20} = 1; // Load
1072 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1073 def t2STM : T2XI<(outs),
1074 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1075 IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1076 let Inst{31-27} = 0b11101;
1077 let Inst{26-25} = 0b00;
1078 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1080 let Inst{21} = ?; // The W bit.
1081 let Inst{20} = 0; // Store
1084 //===----------------------------------------------------------------------===//
1085 // Move Instructions.
1088 let neverHasSideEffects = 1 in
1089 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1090 "mov", ".w\t$dst, $src", []> {
1091 let Inst{31-27} = 0b11101;
1092 let Inst{26-25} = 0b01;
1093 let Inst{24-21} = 0b0010;
1094 let Inst{20} = ?; // The S bit.
1095 let Inst{19-16} = 0b1111; // Rn
1096 let Inst{14-12} = 0b000;
1097 let Inst{7-4} = 0b0000;
1100 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1101 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1102 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1103 "mov", ".w\t$dst, $src",
1104 [(set GPR:$dst, t2_so_imm:$src)]> {
1105 let Inst{31-27} = 0b11110;
1107 let Inst{24-21} = 0b0010;
1108 let Inst{20} = ?; // The S bit.
1109 let Inst{19-16} = 0b1111; // Rn
1113 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1114 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1115 "movw", "\t$dst, $src",
1116 [(set GPR:$dst, imm0_65535:$src)]> {
1117 let Inst{31-27} = 0b11110;
1119 let Inst{24-21} = 0b0010;
1120 let Inst{20} = 0; // The S bit.
1124 let Constraints = "$src = $dst" in
1125 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
1126 "movt", "\t$dst, $imm",
1128 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
1129 let Inst{31-27} = 0b11110;
1131 let Inst{24-21} = 0b0110;
1132 let Inst{20} = 0; // The S bit.
1136 def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
1138 //===----------------------------------------------------------------------===//
1139 // Extend Instructions.
1144 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1145 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1146 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1147 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1148 defm t2SXTB16 : T2I_unary_rrot_DO<0b010, "sxtb16">;
1150 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1151 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1152 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1153 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1154 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1156 // TODO: SXT(A){B|H}16 - done for disassembly only
1160 let AddedComplexity = 16 in {
1161 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1162 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1163 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1164 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1165 defm t2UXTB16 : T2I_unary_rrot<0b011, "uxtb16",
1166 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1168 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1169 (t2UXTB16r_rot GPR:$Src, 24)>;
1170 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1171 (t2UXTB16r_rot GPR:$Src, 8)>;
1173 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1174 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1175 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1176 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1177 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1180 //===----------------------------------------------------------------------===//
1181 // Arithmetic Instructions.
1184 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1185 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1186 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1187 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1189 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1190 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1191 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1192 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1193 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1195 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1196 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1197 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1198 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1199 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1200 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1201 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1202 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1205 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1206 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1207 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1208 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1210 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1211 let AddedComplexity = 1 in
1212 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1213 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1214 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1215 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1216 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1217 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1219 // Select Bytes -- for disassembly only
1221 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1222 "\t$dst, $a, $b", []> {
1223 let Inst{31-27} = 0b11111;
1224 let Inst{26-24} = 0b010;
1226 let Inst{22-20} = 0b010;
1227 let Inst{15-12} = 0b1111;
1229 let Inst{6-4} = 0b000;
1232 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1233 // And Miscellaneous operations -- for disassembly only
1234 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc>
1235 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
1236 "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> {
1237 let Inst{31-27} = 0b11111;
1238 let Inst{26-23} = 0b0101;
1239 let Inst{22-20} = op22_20;
1240 let Inst{15-12} = 0b1111;
1241 let Inst{7-4} = op7_4;
1244 // Saturating add/subtract -- for disassembly only
1246 def t2QADD : T2I_pam<0b000, 0b1000, "qadd">;
1247 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1248 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1249 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1250 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1251 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1252 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1253 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">;
1254 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1255 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1256 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1257 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1258 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1259 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1260 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1261 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1263 // Signed/Unsigned add/subtract -- for disassembly only
1265 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1266 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1267 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1268 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1269 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1270 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1271 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1272 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1273 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1274 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1275 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1276 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1278 // Signed/Unsigned halving add/subtract -- for disassembly only
1280 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1281 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1282 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1283 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1284 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1285 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1286 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1287 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1288 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1289 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1290 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1291 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1293 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1295 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1296 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1297 let Inst{15-12} = 0b1111;
1299 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst),
1300 (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8",
1301 "\t$dst, $a, $b, $acc", []>;
1303 // Signed/Unsigned saturate -- for disassembly only
1305 def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1306 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1307 [/* For disassembly only; pattern left blank */]> {
1308 let Inst{31-27} = 0b11110;
1309 let Inst{25-22} = 0b1100;
1312 let Inst{21} = 0; // sh = '0'
1315 def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1316 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1317 [/* For disassembly only; pattern left blank */]> {
1318 let Inst{31-27} = 0b11110;
1319 let Inst{25-22} = 0b1100;
1322 let Inst{21} = 1; // sh = '1'
1325 def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1326 "ssat16", "\t$dst, $bit_pos, $a",
1327 [/* For disassembly only; pattern left blank */]> {
1328 let Inst{31-27} = 0b11110;
1329 let Inst{25-22} = 0b1100;
1332 let Inst{21} = 1; // sh = '1'
1333 let Inst{14-12} = 0b000; // imm3 = '000'
1334 let Inst{7-6} = 0b00; // imm2 = '00'
1337 def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1338 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1339 [/* For disassembly only; pattern left blank */]> {
1340 let Inst{31-27} = 0b11110;
1341 let Inst{25-22} = 0b1110;
1344 let Inst{21} = 0; // sh = '0'
1347 def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1348 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1349 [/* For disassembly only; pattern left blank */]> {
1350 let Inst{31-27} = 0b11110;
1351 let Inst{25-22} = 0b1110;
1354 let Inst{21} = 1; // sh = '1'
1357 def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1358 "usat16", "\t$dst, $bit_pos, $a",
1359 [/* For disassembly only; pattern left blank */]> {
1360 let Inst{31-27} = 0b11110;
1361 let Inst{25-22} = 0b1110;
1364 let Inst{21} = 1; // sh = '1'
1365 let Inst{14-12} = 0b000; // imm3 = '000'
1366 let Inst{7-6} = 0b00; // imm2 = '00'
1369 //===----------------------------------------------------------------------===//
1370 // Shift and rotate Instructions.
1373 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1374 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1375 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1376 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1378 let Uses = [CPSR] in {
1379 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1380 "rrx", "\t$dst, $src",
1381 [(set GPR:$dst, (ARMrrx GPR:$src))]> {
1382 let Inst{31-27} = 0b11101;
1383 let Inst{26-25} = 0b01;
1384 let Inst{24-21} = 0b0010;
1385 let Inst{20} = ?; // The S bit.
1386 let Inst{19-16} = 0b1111; // Rn
1387 let Inst{14-12} = 0b000;
1388 let Inst{7-4} = 0b0011;
1392 let Defs = [CPSR] in {
1393 def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1394 "lsrs.w\t$dst, $src, #1",
1395 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
1396 let Inst{31-27} = 0b11101;
1397 let Inst{26-25} = 0b01;
1398 let Inst{24-21} = 0b0010;
1399 let Inst{20} = 1; // The S bit.
1400 let Inst{19-16} = 0b1111; // Rn
1401 let Inst{5-4} = 0b01; // Shift type.
1402 // Shift amount = Inst{14-12:7-6} = 1.
1403 let Inst{14-12} = 0b000;
1404 let Inst{7-6} = 0b01;
1406 def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1407 "asrs.w\t$dst, $src, #1",
1408 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
1409 let Inst{31-27} = 0b11101;
1410 let Inst{26-25} = 0b01;
1411 let Inst{24-21} = 0b0010;
1412 let Inst{20} = 1; // The S bit.
1413 let Inst{19-16} = 0b1111; // Rn
1414 let Inst{5-4} = 0b10; // Shift type.
1415 // Shift amount = Inst{14-12:7-6} = 1.
1416 let Inst{14-12} = 0b000;
1417 let Inst{7-6} = 0b01;
1421 //===----------------------------------------------------------------------===//
1422 // Bitwise Instructions.
1425 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1426 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1427 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1428 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1429 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1430 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1432 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1433 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1435 let Constraints = "$src = $dst" in
1436 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1437 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1438 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
1439 let Inst{31-27} = 0b11110;
1441 let Inst{24-20} = 0b10110;
1442 let Inst{19-16} = 0b1111; // Rn
1446 def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1447 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1448 let Inst{31-27} = 0b11110;
1450 let Inst{24-20} = 0b10100;
1454 def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1455 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1456 let Inst{31-27} = 0b11110;
1458 let Inst{24-20} = 0b11100;
1462 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1463 // Added for disassembler with the pattern field purposely left blank.
1464 // FIXME: Utilize this instruction in codgen.
1465 def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1466 IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> {
1467 let Inst{31-27} = 0b11110;
1469 let Inst{24-20} = 0b10110;
1473 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1476 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1477 let AddedComplexity = 1 in
1478 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1481 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
1482 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
1484 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1485 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
1486 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
1487 Requires<[IsThumb2]>;
1489 def : T2Pat<(t2_so_imm_not:$src),
1490 (t2MVNi t2_so_imm_not:$src)>;
1492 //===----------------------------------------------------------------------===//
1493 // Multiply Instructions.
1495 let isCommutable = 1 in
1496 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1497 "mul", "\t$dst, $a, $b",
1498 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
1499 let Inst{31-27} = 0b11111;
1500 let Inst{26-23} = 0b0110;
1501 let Inst{22-20} = 0b000;
1502 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1503 let Inst{7-4} = 0b0000; // Multiply
1506 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1507 "mla", "\t$dst, $a, $b, $c",
1508 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
1509 let Inst{31-27} = 0b11111;
1510 let Inst{26-23} = 0b0110;
1511 let Inst{22-20} = 0b000;
1512 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1513 let Inst{7-4} = 0b0000; // Multiply
1516 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1517 "mls", "\t$dst, $a, $b, $c",
1518 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
1519 let Inst{31-27} = 0b11111;
1520 let Inst{26-23} = 0b0110;
1521 let Inst{22-20} = 0b000;
1522 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1523 let Inst{7-4} = 0b0001; // Multiply and Subtract
1526 // Extra precision multiplies with low / high results
1527 let neverHasSideEffects = 1 in {
1528 let isCommutable = 1 in {
1529 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1530 "smull", "\t$ldst, $hdst, $a, $b", []> {
1531 let Inst{31-27} = 0b11111;
1532 let Inst{26-23} = 0b0111;
1533 let Inst{22-20} = 0b000;
1534 let Inst{7-4} = 0b0000;
1537 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1538 "umull", "\t$ldst, $hdst, $a, $b", []> {
1539 let Inst{31-27} = 0b11111;
1540 let Inst{26-23} = 0b0111;
1541 let Inst{22-20} = 0b010;
1542 let Inst{7-4} = 0b0000;
1546 // Multiply + accumulate
1547 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1548 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1549 let Inst{31-27} = 0b11111;
1550 let Inst{26-23} = 0b0111;
1551 let Inst{22-20} = 0b100;
1552 let Inst{7-4} = 0b0000;
1555 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1556 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1557 let Inst{31-27} = 0b11111;
1558 let Inst{26-23} = 0b0111;
1559 let Inst{22-20} = 0b110;
1560 let Inst{7-4} = 0b0000;
1563 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1564 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1565 let Inst{31-27} = 0b11111;
1566 let Inst{26-23} = 0b0111;
1567 let Inst{22-20} = 0b110;
1568 let Inst{7-4} = 0b0110;
1570 } // neverHasSideEffects
1572 // Rounding variants of the below included for disassembly only
1574 // Most significant word multiply
1575 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1576 "smmul", "\t$dst, $a, $b",
1577 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
1578 let Inst{31-27} = 0b11111;
1579 let Inst{26-23} = 0b0110;
1580 let Inst{22-20} = 0b101;
1581 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1582 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1585 def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1586 "smmulr", "\t$dst, $a, $b", []> {
1587 let Inst{31-27} = 0b11111;
1588 let Inst{26-23} = 0b0110;
1589 let Inst{22-20} = 0b101;
1590 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1591 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1594 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1595 "smmla", "\t$dst, $a, $b, $c",
1596 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
1597 let Inst{31-27} = 0b11111;
1598 let Inst{26-23} = 0b0110;
1599 let Inst{22-20} = 0b101;
1600 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1601 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1604 def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1605 "smmlar", "\t$dst, $a, $b, $c", []> {
1606 let Inst{31-27} = 0b11111;
1607 let Inst{26-23} = 0b0110;
1608 let Inst{22-20} = 0b101;
1609 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1610 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1613 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1614 "smmls", "\t$dst, $a, $b, $c",
1615 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
1616 let Inst{31-27} = 0b11111;
1617 let Inst{26-23} = 0b0110;
1618 let Inst{22-20} = 0b110;
1619 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1620 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1623 def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1624 "smmlsr", "\t$dst, $a, $b, $c", []> {
1625 let Inst{31-27} = 0b11111;
1626 let Inst{26-23} = 0b0110;
1627 let Inst{22-20} = 0b110;
1628 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1629 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1632 multiclass T2I_smul<string opc, PatFrag opnode> {
1633 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1634 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1635 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1636 (sext_inreg GPR:$b, i16)))]> {
1637 let Inst{31-27} = 0b11111;
1638 let Inst{26-23} = 0b0110;
1639 let Inst{22-20} = 0b001;
1640 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1641 let Inst{7-6} = 0b00;
1642 let Inst{5-4} = 0b00;
1645 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1646 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1647 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1648 (sra GPR:$b, (i32 16))))]> {
1649 let Inst{31-27} = 0b11111;
1650 let Inst{26-23} = 0b0110;
1651 let Inst{22-20} = 0b001;
1652 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1653 let Inst{7-6} = 0b00;
1654 let Inst{5-4} = 0b01;
1657 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1658 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1659 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1660 (sext_inreg GPR:$b, i16)))]> {
1661 let Inst{31-27} = 0b11111;
1662 let Inst{26-23} = 0b0110;
1663 let Inst{22-20} = 0b001;
1664 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1665 let Inst{7-6} = 0b00;
1666 let Inst{5-4} = 0b10;
1669 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1670 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1671 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1672 (sra GPR:$b, (i32 16))))]> {
1673 let Inst{31-27} = 0b11111;
1674 let Inst{26-23} = 0b0110;
1675 let Inst{22-20} = 0b001;
1676 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1677 let Inst{7-6} = 0b00;
1678 let Inst{5-4} = 0b11;
1681 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1682 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1683 [(set GPR:$dst, (sra (opnode GPR:$a,
1684 (sext_inreg GPR:$b, i16)), (i32 16)))]> {
1685 let Inst{31-27} = 0b11111;
1686 let Inst{26-23} = 0b0110;
1687 let Inst{22-20} = 0b011;
1688 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1689 let Inst{7-6} = 0b00;
1690 let Inst{5-4} = 0b00;
1693 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1694 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1695 [(set GPR:$dst, (sra (opnode GPR:$a,
1696 (sra GPR:$b, (i32 16))), (i32 16)))]> {
1697 let Inst{31-27} = 0b11111;
1698 let Inst{26-23} = 0b0110;
1699 let Inst{22-20} = 0b011;
1700 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1701 let Inst{7-6} = 0b00;
1702 let Inst{5-4} = 0b01;
1707 multiclass T2I_smla<string opc, PatFrag opnode> {
1708 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1709 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1710 [(set GPR:$dst, (add GPR:$acc,
1711 (opnode (sext_inreg GPR:$a, i16),
1712 (sext_inreg GPR:$b, i16))))]> {
1713 let Inst{31-27} = 0b11111;
1714 let Inst{26-23} = 0b0110;
1715 let Inst{22-20} = 0b001;
1716 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1717 let Inst{7-6} = 0b00;
1718 let Inst{5-4} = 0b00;
1721 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1722 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1723 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1724 (sra GPR:$b, (i32 16)))))]> {
1725 let Inst{31-27} = 0b11111;
1726 let Inst{26-23} = 0b0110;
1727 let Inst{22-20} = 0b001;
1728 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1729 let Inst{7-6} = 0b00;
1730 let Inst{5-4} = 0b01;
1733 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1734 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1735 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1736 (sext_inreg GPR:$b, i16))))]> {
1737 let Inst{31-27} = 0b11111;
1738 let Inst{26-23} = 0b0110;
1739 let Inst{22-20} = 0b001;
1740 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1741 let Inst{7-6} = 0b00;
1742 let Inst{5-4} = 0b10;
1745 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1746 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1747 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1748 (sra GPR:$b, (i32 16)))))]> {
1749 let Inst{31-27} = 0b11111;
1750 let Inst{26-23} = 0b0110;
1751 let Inst{22-20} = 0b001;
1752 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1753 let Inst{7-6} = 0b00;
1754 let Inst{5-4} = 0b11;
1757 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1758 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1759 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1760 (sext_inreg GPR:$b, i16)), (i32 16))))]> {
1761 let Inst{31-27} = 0b11111;
1762 let Inst{26-23} = 0b0110;
1763 let Inst{22-20} = 0b011;
1764 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1765 let Inst{7-6} = 0b00;
1766 let Inst{5-4} = 0b00;
1769 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1770 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1771 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1772 (sra GPR:$b, (i32 16))), (i32 16))))]> {
1773 let Inst{31-27} = 0b11111;
1774 let Inst{26-23} = 0b0110;
1775 let Inst{22-20} = 0b011;
1776 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1777 let Inst{7-6} = 0b00;
1778 let Inst{5-4} = 0b01;
1782 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1783 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1785 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
1786 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst),
1787 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1788 [/* For disassembly only; pattern left blank */]>;
1789 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst),
1790 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1791 [/* For disassembly only; pattern left blank */]>;
1792 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst),
1793 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
1794 [/* For disassembly only; pattern left blank */]>;
1795 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst),
1796 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
1797 [/* For disassembly only; pattern left blank */]>;
1799 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1800 // These are for disassembly only.
1802 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1803 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
1804 let Inst{15-12} = 0b1111;
1806 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1807 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
1808 let Inst{15-12} = 0b1111;
1810 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1811 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
1812 let Inst{15-12} = 0b1111;
1814 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1815 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
1816 let Inst{15-12} = 0b1111;
1818 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst),
1819 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad",
1820 "\t$dst, $a, $b, $acc", []>;
1821 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst),
1822 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx",
1823 "\t$dst, $a, $b, $acc", []>;
1824 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst),
1825 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd",
1826 "\t$dst, $a, $b, $acc", []>;
1827 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst),
1828 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx",
1829 "\t$dst, $a, $b, $acc", []>;
1830 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst),
1831 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald",
1832 "\t$ldst, $hdst, $a, $b", []>;
1833 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst),
1834 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx",
1835 "\t$ldst, $hdst, $a, $b", []>;
1836 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst),
1837 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld",
1838 "\t$ldst, $hdst, $a, $b", []>;
1839 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst),
1840 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx",
1841 "\t$ldst, $hdst, $a, $b", []>;
1843 //===----------------------------------------------------------------------===//
1844 // Misc. Arithmetic Instructions.
1847 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
1848 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1849 : T2I<oops, iops, itin, opc, asm, pattern> {
1850 let Inst{31-27} = 0b11111;
1851 let Inst{26-22} = 0b01010;
1852 let Inst{21-20} = op1;
1853 let Inst{15-12} = 0b1111;
1854 let Inst{7-6} = 0b10;
1855 let Inst{5-4} = op2;
1858 def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1859 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
1861 def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1862 "rbit", "\t$dst, $src",
1863 [(set GPR:$dst, (ARMrbit GPR:$src))]>;
1865 def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1866 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
1868 def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1869 "rev16", ".w\t$dst, $src",
1871 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1872 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1873 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1874 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
1876 def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1877 "revsh", ".w\t$dst, $src",
1880 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1881 (shl GPR:$src, (i32 8))), i16))]>;
1883 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1884 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
1885 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1886 (and (shl GPR:$src2, (i32 imm:$shamt)),
1888 let Inst{31-27} = 0b11101;
1889 let Inst{26-25} = 0b01;
1890 let Inst{24-20} = 0b01100;
1891 let Inst{5} = 0; // BT form
1895 // Alternate cases for PKHBT where identities eliminate some nodes.
1896 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1897 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
1898 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1899 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1901 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1902 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
1903 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1904 (and (sra GPR:$src2, imm16_31:$shamt),
1906 let Inst{31-27} = 0b11101;
1907 let Inst{26-25} = 0b01;
1908 let Inst{24-20} = 0b01100;
1909 let Inst{5} = 1; // TB form
1913 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1914 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1915 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1916 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
1917 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
1918 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1919 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1921 //===----------------------------------------------------------------------===//
1922 // Comparison Instructions...
1925 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
1926 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1927 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
1928 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1930 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
1931 // Compare-to-zero still works out, just not the relationals
1932 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
1933 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1934 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
1935 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1937 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1938 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1940 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1941 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
1943 defm t2TST : T2I_cmp_irs<0b0000, "tst",
1944 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1945 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
1946 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1948 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1949 // Short range conditional branch. Looks awesome for loops. Need to figure
1950 // out how to use this one.
1953 // Conditional moves
1954 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1955 // a two-value operand where a dag node expects two operands. :(
1956 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
1957 "mov", ".w\t$dst, $true",
1958 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1959 RegConstraint<"$false = $dst"> {
1960 let Inst{31-27} = 0b11101;
1961 let Inst{26-25} = 0b01;
1962 let Inst{24-21} = 0b0010;
1963 let Inst{20} = 0; // The S bit.
1964 let Inst{19-16} = 0b1111; // Rn
1965 let Inst{14-12} = 0b000;
1966 let Inst{7-4} = 0b0000;
1969 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1970 IIC_iCMOVi, "mov", ".w\t$dst, $true",
1971 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1972 RegConstraint<"$false = $dst"> {
1973 let Inst{31-27} = 0b11110;
1975 let Inst{24-21} = 0b0010;
1976 let Inst{20} = 0; // The S bit.
1977 let Inst{19-16} = 0b1111; // Rn
1981 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
1982 string opc, string asm, list<dag> pattern>
1983 : T2I<oops, iops, itin, opc, asm, pattern> {
1984 let Inst{31-27} = 0b11101;
1985 let Inst{26-25} = 0b01;
1986 let Inst{24-21} = 0b0010;
1987 let Inst{20} = 0; // The S bit.
1988 let Inst{19-16} = 0b1111; // Rn
1989 let Inst{5-4} = opcod; // Shift type.
1991 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
1992 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1993 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
1994 RegConstraint<"$false = $dst">;
1995 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
1996 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1997 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
1998 RegConstraint<"$false = $dst">;
1999 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
2000 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2001 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2002 RegConstraint<"$false = $dst">;
2003 def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
2004 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2005 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2006 RegConstraint<"$false = $dst">;
2008 //===----------------------------------------------------------------------===//
2009 // Atomic operations intrinsics
2012 // memory barriers protect the atomic sequences
2013 let hasSideEffects = 1 in {
2014 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
2015 Pseudo, NoItinerary,
2017 [(ARMMemBarrierV7)]>,
2018 Requires<[IsThumb2]> {
2019 let Inst{31-4} = 0xF3BF8F5;
2020 // FIXME: add support for options other than a full system DMB
2021 let Inst{3-0} = 0b1111;
2024 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
2025 Pseudo, NoItinerary,
2027 [(ARMSyncBarrierV7)]>,
2028 Requires<[IsThumb2]> {
2029 let Inst{31-4} = 0xF3BF8F4;
2030 // FIXME: add support for options other than a full system DSB
2031 let Inst{3-0} = 0b1111;
2035 // Helper class for multiclass T2MemB -- for disassembly only
2036 class T2I_memb<string opc, string asm>
2037 : T2I<(outs), (ins), NoItinerary, opc, asm,
2038 [/* For disassembly only; pattern left blank */]>,
2039 Requires<[IsThumb2, HasV7]> {
2040 let Inst{31-20} = 0xf3b;
2041 let Inst{15-14} = 0b10;
2045 multiclass T2MemB<bits<4> op7_4, string opc> {
2047 def st : T2I_memb<opc, "\tst"> {
2048 let Inst{7-4} = op7_4;
2049 let Inst{3-0} = 0b1110;
2052 def ish : T2I_memb<opc, "\tish"> {
2053 let Inst{7-4} = op7_4;
2054 let Inst{3-0} = 0b1011;
2057 def ishst : T2I_memb<opc, "\tishst"> {
2058 let Inst{7-4} = op7_4;
2059 let Inst{3-0} = 0b1010;
2062 def nsh : T2I_memb<opc, "\tnsh"> {
2063 let Inst{7-4} = op7_4;
2064 let Inst{3-0} = 0b0111;
2067 def nshst : T2I_memb<opc, "\tnshst"> {
2068 let Inst{7-4} = op7_4;
2069 let Inst{3-0} = 0b0110;
2072 def osh : T2I_memb<opc, "\tosh"> {
2073 let Inst{7-4} = op7_4;
2074 let Inst{3-0} = 0b0011;
2077 def oshst : T2I_memb<opc, "\toshst"> {
2078 let Inst{7-4} = op7_4;
2079 let Inst{3-0} = 0b0010;
2083 // These DMB variants are for disassembly only.
2084 defm t2DMB : T2MemB<0b0101, "dmb">;
2086 // These DSB variants are for disassembly only.
2087 defm t2DSB : T2MemB<0b0100, "dsb">;
2089 // ISB has only full system option -- for disassembly only
2090 def t2ISBsy : T2I_memb<"isb", ""> {
2091 let Inst{7-4} = 0b0110;
2092 let Inst{3-0} = 0b1111;
2095 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2096 InstrItinClass itin, string opc, string asm, string cstr,
2097 list<dag> pattern, bits<4> rt2 = 0b1111>
2098 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2099 let Inst{31-27} = 0b11101;
2100 let Inst{26-20} = 0b0001101;
2101 let Inst{11-8} = rt2;
2102 let Inst{7-6} = 0b01;
2103 let Inst{5-4} = opcod;
2104 let Inst{3-0} = 0b1111;
2106 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2107 InstrItinClass itin, string opc, string asm, string cstr,
2108 list<dag> pattern, bits<4> rt2 = 0b1111>
2109 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2110 let Inst{31-27} = 0b11101;
2111 let Inst{26-20} = 0b0001100;
2112 let Inst{11-8} = rt2;
2113 let Inst{7-6} = 0b01;
2114 let Inst{5-4} = opcod;
2117 let mayLoad = 1 in {
2118 def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2119 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2121 def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2122 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2124 def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2125 Size4Bytes, NoItinerary,
2126 "ldrex", "\t$dest, [$ptr]", "",
2128 let Inst{31-27} = 0b11101;
2129 let Inst{26-20} = 0b0000101;
2130 let Inst{11-8} = 0b1111;
2131 let Inst{7-0} = 0b00000000; // imm8 = 0
2133 def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2134 AddrModeNone, Size4Bytes, NoItinerary,
2135 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2139 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2140 def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2141 AddrModeNone, Size4Bytes, NoItinerary,
2142 "strexb", "\t$success, $src, [$ptr]", "", []>;
2143 def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2144 AddrModeNone, Size4Bytes, NoItinerary,
2145 "strexh", "\t$success, $src, [$ptr]", "", []>;
2146 def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2147 AddrModeNone, Size4Bytes, NoItinerary,
2148 "strex", "\t$success, $src, [$ptr]", "",
2150 let Inst{31-27} = 0b11101;
2151 let Inst{26-20} = 0b0000100;
2152 let Inst{7-0} = 0b00000000; // imm8 = 0
2154 def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
2155 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2156 AddrModeNone, Size4Bytes, NoItinerary,
2157 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2161 // Clear-Exclusive is for disassembly only.
2162 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2163 [/* For disassembly only; pattern left blank */]>,
2164 Requires<[IsARM, HasV7]> {
2165 let Inst{31-20} = 0xf3b;
2166 let Inst{15-14} = 0b10;
2168 let Inst{7-4} = 0b0010;
2171 //===----------------------------------------------------------------------===//
2175 // __aeabi_read_tp preserves the registers r1-r3.
2177 Defs = [R0, R12, LR, CPSR] in {
2178 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2179 "bl\t__aeabi_read_tp",
2180 [(set R0, ARMthread_pointer)]> {
2181 let Inst{31-27} = 0b11110;
2182 let Inst{15-14} = 0b11;
2187 //===----------------------------------------------------------------------===//
2188 // SJLJ Exception handling intrinsics
2189 // eh_sjlj_setjmp() is an instruction sequence to store the return
2190 // address and save #0 in R0 for the non-longjmp case.
2191 // Since by its nature we may be coming from some other function to get
2192 // here, and we're using the stack frame for the containing function to
2193 // save/restore registers, we can't keep anything live in regs across
2194 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2195 // when we get here from a longjmp(). We force everthing out of registers
2196 // except for our own input by listing the relevant registers in Defs. By
2197 // doing so, we also cause the prologue/epilogue code to actively preserve
2198 // all of the callee-saved resgisters, which is exactly what we want.
2199 // The current SP is passed in $val, and we reuse the reg as a scratch.
2201 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2202 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2203 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2205 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2206 AddrModeNone, SizeSpecial, NoItinerary,
2207 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
2209 "\tadds\t$val, #9\n"
2210 "\tstr\t$val, [$src, #4]\n"
2213 "\tmovs\tr0, #1\t@ end eh.setjmp\n"
2215 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>;
2220 //===----------------------------------------------------------------------===//
2221 // Control-Flow Instructions
2224 // FIXME: remove when we have a way to marking a MI with these properties.
2225 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2227 // FIXME: Should pc be an implicit operand like PICADD, etc?
2228 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2229 hasExtraDefRegAllocReq = 1 in
2230 def t2LDM_RET : T2XI<(outs),
2231 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
2232 IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb",
2234 let Inst{31-27} = 0b11101;
2235 let Inst{26-25} = 0b00;
2236 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2238 let Inst{21} = ?; // The W bit.
2239 let Inst{20} = 1; // Load
2242 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2243 let isPredicable = 1 in
2244 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2246 [(br bb:$target)]> {
2247 let Inst{31-27} = 0b11110;
2248 let Inst{15-14} = 0b10;
2252 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2255 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2256 IIC_Br, "mov\tpc, $target\n$jt",
2257 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2258 let Inst{31-27} = 0b11101;
2259 let Inst{26-20} = 0b0100100;
2260 let Inst{19-16} = 0b1111;
2261 let Inst{14-12} = 0b000;
2262 let Inst{11-8} = 0b1111; // Rd = pc
2263 let Inst{7-4} = 0b0000;
2266 // FIXME: Add a non-pc based case that can be predicated.
2269 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2270 IIC_Br, "tbb\t$index\n$jt", []> {
2271 let Inst{31-27} = 0b11101;
2272 let Inst{26-20} = 0b0001101;
2273 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2274 let Inst{15-8} = 0b11110000;
2275 let Inst{7-4} = 0b0000; // B form
2280 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2281 IIC_Br, "tbh\t$index\n$jt", []> {
2282 let Inst{31-27} = 0b11101;
2283 let Inst{26-20} = 0b0001101;
2284 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2285 let Inst{15-8} = 0b11110000;
2286 let Inst{7-4} = 0b0001; // H form
2289 // Generic versions of the above two instructions, for disassembly only
2291 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2292 "tbb", "\t[$a, $b]", []>{
2293 let Inst{31-27} = 0b11101;
2294 let Inst{26-20} = 0b0001101;
2295 let Inst{15-8} = 0b11110000;
2296 let Inst{7-4} = 0b0000; // B form
2299 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2300 "tbh", "\t[$a, $b, lsl #1]", []> {
2301 let Inst{31-27} = 0b11101;
2302 let Inst{26-20} = 0b0001101;
2303 let Inst{15-8} = 0b11110000;
2304 let Inst{7-4} = 0b0001; // H form
2306 } // isNotDuplicable, isIndirectBranch
2308 } // isBranch, isTerminator, isBarrier
2310 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2311 // a two-value operand where a dag node expects two operands. :(
2312 let isBranch = 1, isTerminator = 1 in
2313 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2315 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2316 let Inst{31-27} = 0b11110;
2317 let Inst{15-14} = 0b10;
2323 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2324 AddrModeNone, Size2Bytes, IIC_iALUx,
2325 "it$mask\t$cc", "", []> {
2326 // 16-bit instruction.
2327 let Inst{31-16} = 0x0000;
2328 let Inst{15-8} = 0b10111111;
2331 // Branch and Exchange Jazelle -- for disassembly only
2333 def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2334 [/* For disassembly only; pattern left blank */]> {
2335 let Inst{31-27} = 0b11110;
2337 let Inst{25-20} = 0b111100;
2338 let Inst{15-14} = 0b10;
2342 // Change Processor State is a system instruction -- for disassembly only.
2343 // The singleton $opt operand contains the following information:
2344 // opt{4-0} = mode from Inst{4-0}
2345 // opt{5} = changemode from Inst{17}
2346 // opt{8-6} = AIF from Inst{8-6}
2347 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2348 def t2CPS : T2XI<(outs),(ins i32imm:$opt), NoItinerary, "cps${opt:cps}",
2349 [/* For disassembly only; pattern left blank */]> {
2350 let Inst{31-27} = 0b11110;
2352 let Inst{25-20} = 0b111010;
2353 let Inst{15-14} = 0b10;
2357 // Secure Monitor Call is a system instruction -- for disassembly only
2358 // Option = Inst{19-16}
2359 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2360 [/* For disassembly only; pattern left blank */]> {
2361 let Inst{31-27} = 0b11110;
2362 let Inst{26-20} = 0b1111111;
2363 let Inst{15-12} = 0b1000;
2366 // Store Return State is a system instruction -- for disassembly only
2367 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2368 [/* For disassembly only; pattern left blank */]> {
2369 let Inst{31-27} = 0b11101;
2370 let Inst{26-20} = 0b0000010; // W = 1
2373 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2374 [/* For disassembly only; pattern left blank */]> {
2375 let Inst{31-27} = 0b11101;
2376 let Inst{26-20} = 0b0000000; // W = 0
2379 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2380 [/* For disassembly only; pattern left blank */]> {
2381 let Inst{31-27} = 0b11101;
2382 let Inst{26-20} = 0b0011010; // W = 1
2385 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2386 [/* For disassembly only; pattern left blank */]> {
2387 let Inst{31-27} = 0b11101;
2388 let Inst{26-20} = 0b0011000; // W = 0
2391 // Return From Exception is a system instruction -- for disassembly only
2392 def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!",
2393 [/* For disassembly only; pattern left blank */]> {
2394 let Inst{31-27} = 0b11101;
2395 let Inst{26-20} = 0b0000011; // W = 1
2398 def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base",
2399 [/* For disassembly only; pattern left blank */]> {
2400 let Inst{31-27} = 0b11101;
2401 let Inst{26-20} = 0b0000001; // W = 0
2404 def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!",
2405 [/* For disassembly only; pattern left blank */]> {
2406 let Inst{31-27} = 0b11101;
2407 let Inst{26-20} = 0b0011011; // W = 1
2410 def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base",
2411 [/* For disassembly only; pattern left blank */]> {
2412 let Inst{31-27} = 0b11101;
2413 let Inst{26-20} = 0b0011001; // W = 0
2416 //===----------------------------------------------------------------------===//
2417 // Non-Instruction Patterns
2420 // Two piece so_imms.
2421 def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
2422 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2423 (t2_so_imm2part_2 imm:$RHS))>;
2424 def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
2425 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2426 (t2_so_imm2part_2 imm:$RHS))>;
2427 def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
2428 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2429 (t2_so_imm2part_2 imm:$RHS))>;
2430 def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS),
2431 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2432 (t2_so_neg_imm2part_2 imm:$RHS))>;
2434 // 32-bit immediate using movw + movt.
2435 // This is a single pseudo instruction to make it re-materializable. Remove
2436 // when we can do generalized remat.
2437 let isReMaterializable = 1 in
2438 def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2439 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2440 [(set GPR:$dst, (i32 imm:$src))]>;
2442 // ConstantPool, GlobalAddress, and JumpTable
2443 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2444 Requires<[IsThumb2, DontUseMovt]>;
2445 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2446 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2447 Requires<[IsThumb2, UseMovt]>;
2449 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2450 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2452 // Pseudo instruction that combines ldr from constpool and add pc. This should
2453 // be expanded into two instructions late to allow if-conversion and
2455 let canFoldAsLoad = 1, isReMaterializable = 1 in
2456 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2457 NoItinerary, "@ ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2458 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2460 Requires<[IsThumb2]>;
2462 //===----------------------------------------------------------------------===//
2463 // Move between special register and ARM core register -- for disassembly only
2467 def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2468 [/* For disassembly only; pattern left blank */]> {
2469 let Inst{31-27} = 0b11110;
2471 let Inst{25-21} = 0b11111;
2472 let Inst{20} = 0; // The R bit.
2473 let Inst{15-14} = 0b10;
2478 def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2479 [/* For disassembly only; pattern left blank */]> {
2480 let Inst{31-27} = 0b11110;
2482 let Inst{25-21} = 0b11111;
2483 let Inst{20} = 1; // The R bit.
2484 let Inst{15-14} = 0b10;
2488 // FIXME: mask is ignored for the time being.
2490 def t2MSR : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tcpsr, $src",
2491 [/* For disassembly only; pattern left blank */]> {
2492 let Inst{31-27} = 0b11110;
2494 let Inst{25-21} = 0b11100;
2495 let Inst{20} = 0; // The R bit.
2496 let Inst{15-14} = 0b10;
2500 // FIXME: mask is ignored for the time being.
2502 def t2MSRsys : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tspsr, $src",
2503 [/* For disassembly only; pattern left blank */]> {
2504 let Inst{31-27} = 0b11110;
2506 let Inst{25-21} = 0b11100;
2507 let Inst{20} = 1; // The R bit.
2508 let Inst{15-14} = 0b10;