1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // Shifted operands. No register controlled shifts for Thumb2.
32 // Note: We do not support rrx shifted operands yet.
33 def t2_so_reg : Operand<i32>, // reg imm
34 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
36 let EncoderMethod = "getT2SORegOpValue";
37 let PrintMethod = "printT2SOOperand";
38 let DecoderMethod = "DecodeSORegImmOperand";
39 let ParserMatchClass = ShiftedImmAsmOperand;
40 let MIOperandInfo = (ops rGPR, i32imm);
43 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
44 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
48 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
49 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
50 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
53 // t2_so_imm - Match a 32-bit immediate operand, which is an
54 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
55 // immediate splatted into multiple bytes of the word.
56 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
57 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
58 return ARM_AM::getT2SOImmVal(Imm) != -1;
60 let ParserMatchClass = t2_so_imm_asmoperand;
61 let EncoderMethod = "getT2SOImmOpValue";
62 let DecoderMethod = "DecodeT2SOImm";
65 // t2_so_imm_not - Match an immediate that is a complement
67 def t2_so_imm_not : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
70 }], t2_so_imm_not_XFORM>;
72 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
73 def t2_so_imm_neg : Operand<i32>,
75 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
76 }], t2_so_imm_neg_XFORM>;
78 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
79 def imm0_4095 : Operand<i32>,
81 return Imm >= 0 && Imm < 4096;
84 def imm0_4095_neg : PatLeaf<(i32 imm), [{
85 return (uint32_t)(-N->getZExtValue()) < 4096;
88 def imm0_255_neg : PatLeaf<(i32 imm), [{
89 return (uint32_t)(-N->getZExtValue()) < 255;
92 def imm0_255_not : PatLeaf<(i32 imm), [{
93 return (uint32_t)(~N->getZExtValue()) < 255;
96 def lo5AllOne : PatLeaf<(i32 imm), [{
97 // Returns true if all low 5-bits are 1.
98 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
101 // Define Thumb2 specific addressing modes.
103 // t2addrmode_imm12 := reg + imm12
104 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
105 def t2addrmode_imm12 : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
107 let PrintMethod = "printAddrModeImm12Operand";
108 let EncoderMethod = "getAddrModeImm12OpValue";
109 let DecoderMethod = "DecodeT2AddrModeImm12";
110 let ParserMatchClass = t2addrmode_imm12_asmoperand;
111 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
114 // t2ldrlabel := imm12
115 def t2ldrlabel : Operand<i32> {
116 let EncoderMethod = "getAddrModeImm12OpValue";
120 // ADR instruction labels.
121 def t2adrlabel : Operand<i32> {
122 let EncoderMethod = "getT2AdrLabelOpValue";
126 // t2addrmode_posimm8 := reg + imm8
127 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
128 def t2addrmode_posimm8 : Operand<i32> {
129 let PrintMethod = "printT2AddrModeImm8Operand";
130 let EncoderMethod = "getT2AddrModeImm8OpValue";
131 let DecoderMethod = "DecodeT2AddrModeImm8";
132 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
133 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
136 // t2addrmode_negimm8 := reg - imm8
137 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
138 def t2addrmode_negimm8 : Operand<i32>,
139 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
140 let PrintMethod = "printT2AddrModeImm8Operand";
141 let EncoderMethod = "getT2AddrModeImm8OpValue";
142 let DecoderMethod = "DecodeT2AddrModeImm8";
143 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
144 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
147 // t2addrmode_imm8 := reg +/- imm8
148 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
149 def t2addrmode_imm8 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
151 let PrintMethod = "printT2AddrModeImm8Operand";
152 let EncoderMethod = "getT2AddrModeImm8OpValue";
153 let DecoderMethod = "DecodeT2AddrModeImm8";
154 let ParserMatchClass = MemImm8OffsetAsmOperand;
155 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
158 def t2am_imm8_offset : Operand<i32>,
159 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
160 [], [SDNPWantRoot]> {
161 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
162 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
163 let DecoderMethod = "DecodeT2Imm8";
166 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
167 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
168 def t2addrmode_imm8s4 : Operand<i32> {
169 let PrintMethod = "printT2AddrModeImm8s4Operand";
170 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
171 let DecoderMethod = "DecodeT2AddrModeImm8s4";
172 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
173 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
176 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
177 def t2am_imm8s4_offset : Operand<i32> {
178 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
179 let EncoderMethod = "getT2Imm8s4OpValue";
180 let DecoderMethod = "DecodeT2Imm8S4";
183 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
184 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
185 let Name = "MemImm0_1020s4Offset";
187 def t2addrmode_imm0_1020s4 : Operand<i32> {
188 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
189 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
190 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
191 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
192 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
195 // t2addrmode_so_reg := reg + (reg << imm2)
196 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
197 def t2addrmode_so_reg : Operand<i32>,
198 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
199 let PrintMethod = "printT2AddrModeSoRegOperand";
200 let EncoderMethod = "getT2AddrModeSORegOpValue";
201 let DecoderMethod = "DecodeT2AddrModeSOReg";
202 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
203 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
206 //===----------------------------------------------------------------------===//
207 // Multiclass helpers...
211 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
212 string opc, string asm, list<dag> pattern>
213 : T2I<oops, iops, itin, opc, asm, pattern> {
218 let Inst{26} = imm{11};
219 let Inst{14-12} = imm{10-8};
220 let Inst{7-0} = imm{7-0};
224 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
225 string opc, string asm, list<dag> pattern>
226 : T2sI<oops, iops, itin, opc, asm, pattern> {
232 let Inst{26} = imm{11};
233 let Inst{14-12} = imm{10-8};
234 let Inst{7-0} = imm{7-0};
237 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
238 string opc, string asm, list<dag> pattern>
239 : T2I<oops, iops, itin, opc, asm, pattern> {
243 let Inst{19-16} = Rn;
244 let Inst{26} = imm{11};
245 let Inst{14-12} = imm{10-8};
246 let Inst{7-0} = imm{7-0};
250 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
251 string opc, string asm, list<dag> pattern>
252 : T2I<oops, iops, itin, opc, asm, pattern> {
257 let Inst{3-0} = ShiftedRm{3-0};
258 let Inst{5-4} = ShiftedRm{6-5};
259 let Inst{14-12} = ShiftedRm{11-9};
260 let Inst{7-6} = ShiftedRm{8-7};
263 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
264 string opc, string asm, list<dag> pattern>
265 : T2sI<oops, iops, itin, opc, asm, pattern> {
270 let Inst{3-0} = ShiftedRm{3-0};
271 let Inst{5-4} = ShiftedRm{6-5};
272 let Inst{14-12} = ShiftedRm{11-9};
273 let Inst{7-6} = ShiftedRm{8-7};
276 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
277 string opc, string asm, list<dag> pattern>
278 : T2I<oops, iops, itin, opc, asm, pattern> {
282 let Inst{19-16} = Rn;
283 let Inst{3-0} = ShiftedRm{3-0};
284 let Inst{5-4} = ShiftedRm{6-5};
285 let Inst{14-12} = ShiftedRm{11-9};
286 let Inst{7-6} = ShiftedRm{8-7};
289 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
290 string opc, string asm, list<dag> pattern>
291 : T2I<oops, iops, itin, opc, asm, pattern> {
299 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
300 string opc, string asm, list<dag> pattern>
301 : T2sI<oops, iops, itin, opc, asm, pattern> {
309 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
310 string opc, string asm, list<dag> pattern>
311 : T2I<oops, iops, itin, opc, asm, pattern> {
315 let Inst{19-16} = Rn;
320 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
321 string opc, string asm, list<dag> pattern>
322 : T2I<oops, iops, itin, opc, asm, pattern> {
328 let Inst{19-16} = Rn;
329 let Inst{26} = imm{11};
330 let Inst{14-12} = imm{10-8};
331 let Inst{7-0} = imm{7-0};
334 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
335 string opc, string asm, list<dag> pattern>
336 : T2sI<oops, iops, itin, opc, asm, pattern> {
342 let Inst{19-16} = Rn;
343 let Inst{26} = imm{11};
344 let Inst{14-12} = imm{10-8};
345 let Inst{7-0} = imm{7-0};
348 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
349 string opc, string asm, list<dag> pattern>
350 : T2I<oops, iops, itin, opc, asm, pattern> {
357 let Inst{14-12} = imm{4-2};
358 let Inst{7-6} = imm{1-0};
361 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
362 string opc, string asm, list<dag> pattern>
363 : T2sI<oops, iops, itin, opc, asm, pattern> {
370 let Inst{14-12} = imm{4-2};
371 let Inst{7-6} = imm{1-0};
374 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
375 string opc, string asm, list<dag> pattern>
376 : T2I<oops, iops, itin, opc, asm, pattern> {
382 let Inst{19-16} = Rn;
386 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
387 string opc, string asm, list<dag> pattern>
388 : T2sI<oops, iops, itin, opc, asm, pattern> {
394 let Inst{19-16} = Rn;
398 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
399 string opc, string asm, list<dag> pattern>
400 : T2I<oops, iops, itin, opc, asm, pattern> {
406 let Inst{19-16} = Rn;
407 let Inst{3-0} = ShiftedRm{3-0};
408 let Inst{5-4} = ShiftedRm{6-5};
409 let Inst{14-12} = ShiftedRm{11-9};
410 let Inst{7-6} = ShiftedRm{8-7};
413 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
414 string opc, string asm, list<dag> pattern>
415 : T2sI<oops, iops, itin, opc, asm, pattern> {
421 let Inst{19-16} = Rn;
422 let Inst{3-0} = ShiftedRm{3-0};
423 let Inst{5-4} = ShiftedRm{6-5};
424 let Inst{14-12} = ShiftedRm{11-9};
425 let Inst{7-6} = ShiftedRm{8-7};
428 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
429 string opc, string asm, list<dag> pattern>
430 : T2I<oops, iops, itin, opc, asm, pattern> {
436 let Inst{19-16} = Rn;
437 let Inst{15-12} = Ra;
442 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
443 dag oops, dag iops, InstrItinClass itin,
444 string opc, string asm, list<dag> pattern>
445 : T2I<oops, iops, itin, opc, asm, pattern> {
451 let Inst{31-23} = 0b111110111;
452 let Inst{22-20} = opc22_20;
453 let Inst{19-16} = Rn;
454 let Inst{15-12} = RdLo;
455 let Inst{11-8} = RdHi;
456 let Inst{7-4} = opc7_4;
461 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
462 /// unary operation that produces a value. These are predicable and can be
463 /// changed to modify CPSR.
464 multiclass T2I_un_irs<bits<4> opcod, string opc,
465 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
466 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
468 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
470 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
471 let isAsCheapAsAMove = Cheap;
472 let isReMaterializable = ReMat;
473 let Inst{31-27} = 0b11110;
475 let Inst{24-21} = opcod;
476 let Inst{19-16} = 0b1111; // Rn
480 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
482 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
483 let Inst{31-27} = 0b11101;
484 let Inst{26-25} = 0b01;
485 let Inst{24-21} = opcod;
486 let Inst{19-16} = 0b1111; // Rn
487 let Inst{14-12} = 0b000; // imm3
488 let Inst{7-6} = 0b00; // imm2
489 let Inst{5-4} = 0b00; // type
492 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
493 opc, ".w\t$Rd, $ShiftedRm",
494 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
495 let Inst{31-27} = 0b11101;
496 let Inst{26-25} = 0b01;
497 let Inst{24-21} = opcod;
498 let Inst{19-16} = 0b1111; // Rn
502 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
503 /// binary operation that produces a value. These are predicable and can be
504 /// changed to modify CPSR.
505 multiclass T2I_bin_irs<bits<4> opcod, string opc,
506 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
507 PatFrag opnode, string baseOpc, bit Commutable = 0,
510 def ri : T2sTwoRegImm<
511 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
512 opc, "\t$Rd, $Rn, $imm",
513 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
514 let Inst{31-27} = 0b11110;
516 let Inst{24-21} = opcod;
520 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
521 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
522 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
523 let isCommutable = Commutable;
524 let Inst{31-27} = 0b11101;
525 let Inst{26-25} = 0b01;
526 let Inst{24-21} = opcod;
527 let Inst{14-12} = 0b000; // imm3
528 let Inst{7-6} = 0b00; // imm2
529 let Inst{5-4} = 0b00; // type
532 def rs : T2sTwoRegShiftedReg<
533 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
534 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
535 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
536 let Inst{31-27} = 0b11101;
537 let Inst{26-25} = 0b01;
538 let Inst{24-21} = opcod;
540 // Assembly aliases for optional destination operand when it's the same
541 // as the source operand.
542 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
543 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
544 t2_so_imm:$imm, pred:$p,
546 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
547 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
550 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
551 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
552 t2_so_reg:$shift, pred:$p,
556 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
557 // the ".w" suffix to indicate that they are wide.
558 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
559 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
560 PatFrag opnode, string baseOpc, bit Commutable = 0> :
561 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
562 // Assembler aliases w/o the ".w" suffix.
563 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
564 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
567 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
568 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
569 t2_so_reg:$shift, pred:$p,
572 // and with the optional destination operand, too.
573 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
574 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
577 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
578 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
579 t2_so_reg:$shift, pred:$p,
583 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
584 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
585 /// it is equivalent to the T2I_bin_irs counterpart.
586 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
588 def ri : T2sTwoRegImm<
589 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
590 opc, ".w\t$Rd, $Rn, $imm",
591 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
592 let Inst{31-27} = 0b11110;
594 let Inst{24-21} = opcod;
598 def rr : T2sThreeReg<
599 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
600 opc, "\t$Rd, $Rn, $Rm",
601 [/* For disassembly only; pattern left blank */]> {
602 let Inst{31-27} = 0b11101;
603 let Inst{26-25} = 0b01;
604 let Inst{24-21} = opcod;
605 let Inst{14-12} = 0b000; // imm3
606 let Inst{7-6} = 0b00; // imm2
607 let Inst{5-4} = 0b00; // type
610 def rs : T2sTwoRegShiftedReg<
611 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
612 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
613 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
614 let Inst{31-27} = 0b11101;
615 let Inst{26-25} = 0b01;
616 let Inst{24-21} = opcod;
620 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
621 /// instruction modifies the CPSR register.
622 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
623 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
624 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
625 PatFrag opnode, bit Commutable = 0> {
627 def ri : T2sTwoRegImm<
628 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
629 opc, ".w\t$Rd, $Rn, $imm",
630 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
631 let Inst{31-27} = 0b11110;
633 let Inst{24-21} = opcod;
637 def rr : T2sThreeReg<
638 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
639 opc, ".w\t$Rd, $Rn, $Rm",
640 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
641 let isCommutable = Commutable;
642 let Inst{31-27} = 0b11101;
643 let Inst{26-25} = 0b01;
644 let Inst{24-21} = opcod;
645 let Inst{14-12} = 0b000; // imm3
646 let Inst{7-6} = 0b00; // imm2
647 let Inst{5-4} = 0b00; // type
650 def rs : T2sTwoRegShiftedReg<
651 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
652 opc, ".w\t$Rd, $Rn, $ShiftedRm",
653 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
654 let Inst{31-27} = 0b11101;
655 let Inst{26-25} = 0b01;
656 let Inst{24-21} = opcod;
661 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
662 /// patterns for a binary operation that produces a value.
663 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
664 bit Commutable = 0> {
666 // The register-immediate version is re-materializable. This is useful
667 // in particular for taking the address of a local.
668 let isReMaterializable = 1 in {
669 def ri : T2sTwoRegImm<
670 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
671 opc, ".w\t$Rd, $Rn, $imm",
672 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
673 let Inst{31-27} = 0b11110;
676 let Inst{23-21} = op23_21;
682 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
683 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
684 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
688 let Inst{31-27} = 0b11110;
689 let Inst{26} = imm{11};
690 let Inst{25-24} = 0b10;
691 let Inst{23-21} = op23_21;
692 let Inst{20} = 0; // The S bit.
693 let Inst{19-16} = Rn;
695 let Inst{14-12} = imm{10-8};
697 let Inst{7-0} = imm{7-0};
700 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
701 opc, ".w\t$Rd, $Rn, $Rm",
702 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
703 let isCommutable = Commutable;
704 let Inst{31-27} = 0b11101;
705 let Inst{26-25} = 0b01;
707 let Inst{23-21} = op23_21;
708 let Inst{14-12} = 0b000; // imm3
709 let Inst{7-6} = 0b00; // imm2
710 let Inst{5-4} = 0b00; // type
713 def rs : T2sTwoRegShiftedReg<
714 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
715 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
716 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
717 let Inst{31-27} = 0b11101;
718 let Inst{26-25} = 0b01;
720 let Inst{23-21} = op23_21;
724 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
725 /// for a binary operation that produces a value and use the carry
726 /// bit. It's not predicable.
727 let Defs = [CPSR], Uses = [CPSR] in {
728 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
729 bit Commutable = 0> {
731 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
732 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
733 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
734 Requires<[IsThumb2]> {
735 let Inst{31-27} = 0b11110;
737 let Inst{24-21} = opcod;
741 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
742 opc, ".w\t$Rd, $Rn, $Rm",
743 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
744 Requires<[IsThumb2]> {
745 let isCommutable = Commutable;
746 let Inst{31-27} = 0b11101;
747 let Inst{26-25} = 0b01;
748 let Inst{24-21} = opcod;
749 let Inst{14-12} = 0b000; // imm3
750 let Inst{7-6} = 0b00; // imm2
751 let Inst{5-4} = 0b00; // type
754 def rs : T2sTwoRegShiftedReg<
755 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
756 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
757 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
758 Requires<[IsThumb2]> {
759 let Inst{31-27} = 0b11101;
760 let Inst{26-25} = 0b01;
761 let Inst{24-21} = opcod;
766 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
767 /// version is not needed since this is only for codegen.
768 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
769 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
771 def ri : T2sTwoRegImm<
772 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
773 opc, ".w\t$Rd, $Rn, $imm",
774 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
775 let Inst{31-27} = 0b11110;
777 let Inst{24-21} = opcod;
781 def rs : T2sTwoRegShiftedReg<
782 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
783 IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
784 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
785 let Inst{31-27} = 0b11101;
786 let Inst{26-25} = 0b01;
787 let Inst{24-21} = opcod;
792 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
793 // rotate operation that produces a value.
794 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
797 def ri : T2sTwoRegShiftImm<
798 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
799 opc, ".w\t$Rd, $Rm, $imm",
800 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
801 let Inst{31-27} = 0b11101;
802 let Inst{26-21} = 0b010010;
803 let Inst{19-16} = 0b1111; // Rn
804 let Inst{5-4} = opcod;
807 def rr : T2sThreeReg<
808 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
809 opc, ".w\t$Rd, $Rn, $Rm",
810 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
811 let Inst{31-27} = 0b11111;
812 let Inst{26-23} = 0b0100;
813 let Inst{22-21} = opcod;
814 let Inst{15-12} = 0b1111;
815 let Inst{7-4} = 0b0000;
818 // Optional destination register
819 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
820 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
823 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
824 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
828 // Assembler aliases w/o the ".w" suffix.
829 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
830 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
833 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
834 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
838 // and with the optional destination operand, too.
839 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
840 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
843 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
844 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
849 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
850 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
851 /// a explicit result, only implicitly set CPSR.
852 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
853 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
854 PatFrag opnode, string baseOpc> {
855 let isCompare = 1, Defs = [CPSR] in {
857 def ri : T2OneRegCmpImm<
858 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
859 opc, ".w\t$Rn, $imm",
860 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
861 let Inst{31-27} = 0b11110;
863 let Inst{24-21} = opcod;
864 let Inst{20} = 1; // The S bit.
866 let Inst{11-8} = 0b1111; // Rd
869 def rr : T2TwoRegCmp<
870 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
872 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
873 let Inst{31-27} = 0b11101;
874 let Inst{26-25} = 0b01;
875 let Inst{24-21} = opcod;
876 let Inst{20} = 1; // The S bit.
877 let Inst{14-12} = 0b000; // imm3
878 let Inst{11-8} = 0b1111; // Rd
879 let Inst{7-6} = 0b00; // imm2
880 let Inst{5-4} = 0b00; // type
883 def rs : T2OneRegCmpShiftedReg<
884 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
885 opc, ".w\t$Rn, $ShiftedRm",
886 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
887 let Inst{31-27} = 0b11101;
888 let Inst{26-25} = 0b01;
889 let Inst{24-21} = opcod;
890 let Inst{20} = 1; // The S bit.
891 let Inst{11-8} = 0b1111; // Rd
895 // Assembler aliases w/o the ".w" suffix.
896 // No alias here for 'rr' version as not all instantiations of this
897 // multiclass want one (CMP in particular, does not).
898 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
899 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
900 t2_so_imm:$imm, pred:$p)>;
901 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
902 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
907 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
908 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
909 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
911 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
912 opc, ".w\t$Rt, $addr",
913 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
916 let Inst{31-25} = 0b1111100;
917 let Inst{24} = signed;
919 let Inst{22-21} = opcod;
920 let Inst{20} = 1; // load
921 let Inst{19-16} = addr{16-13}; // Rn
922 let Inst{15-12} = Rt;
923 let Inst{11-0} = addr{11-0}; // imm
925 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
927 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
930 let Inst{31-27} = 0b11111;
931 let Inst{26-25} = 0b00;
932 let Inst{24} = signed;
934 let Inst{22-21} = opcod;
935 let Inst{20} = 1; // load
936 let Inst{19-16} = addr{12-9}; // Rn
937 let Inst{15-12} = Rt;
939 // Offset: index==TRUE, wback==FALSE
940 let Inst{10} = 1; // The P bit.
941 let Inst{9} = addr{8}; // U
942 let Inst{8} = 0; // The W bit.
943 let Inst{7-0} = addr{7-0}; // imm
945 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
946 opc, ".w\t$Rt, $addr",
947 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
948 let Inst{31-27} = 0b11111;
949 let Inst{26-25} = 0b00;
950 let Inst{24} = signed;
952 let Inst{22-21} = opcod;
953 let Inst{20} = 1; // load
954 let Inst{11-6} = 0b000000;
957 let Inst{15-12} = Rt;
960 let Inst{19-16} = addr{9-6}; // Rn
961 let Inst{3-0} = addr{5-2}; // Rm
962 let Inst{5-4} = addr{1-0}; // imm
964 let DecoderMethod = "DecodeT2LoadShift";
967 // FIXME: Is the pci variant actually needed?
968 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
969 opc, ".w\t$Rt, $addr",
970 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
971 let isReMaterializable = 1;
972 let Inst{31-27} = 0b11111;
973 let Inst{26-25} = 0b00;
974 let Inst{24} = signed;
975 let Inst{23} = ?; // add = (U == '1')
976 let Inst{22-21} = opcod;
977 let Inst{20} = 1; // load
978 let Inst{19-16} = 0b1111; // Rn
981 let Inst{15-12} = Rt{3-0};
982 let Inst{11-0} = addr{11-0};
986 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
987 multiclass T2I_st<bits<2> opcod, string opc,
988 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
990 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
991 opc, ".w\t$Rt, $addr",
992 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
993 let Inst{31-27} = 0b11111;
994 let Inst{26-23} = 0b0001;
995 let Inst{22-21} = opcod;
996 let Inst{20} = 0; // !load
999 let Inst{15-12} = Rt;
1002 let addr{12} = 1; // add = TRUE
1003 let Inst{19-16} = addr{16-13}; // Rn
1004 let Inst{23} = addr{12}; // U
1005 let Inst{11-0} = addr{11-0}; // imm
1007 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1008 opc, "\t$Rt, $addr",
1009 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1010 let Inst{31-27} = 0b11111;
1011 let Inst{26-23} = 0b0000;
1012 let Inst{22-21} = opcod;
1013 let Inst{20} = 0; // !load
1015 // Offset: index==TRUE, wback==FALSE
1016 let Inst{10} = 1; // The P bit.
1017 let Inst{8} = 0; // The W bit.
1020 let Inst{15-12} = Rt;
1023 let Inst{19-16} = addr{12-9}; // Rn
1024 let Inst{9} = addr{8}; // U
1025 let Inst{7-0} = addr{7-0}; // imm
1027 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1028 opc, ".w\t$Rt, $addr",
1029 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1030 let Inst{31-27} = 0b11111;
1031 let Inst{26-23} = 0b0000;
1032 let Inst{22-21} = opcod;
1033 let Inst{20} = 0; // !load
1034 let Inst{11-6} = 0b000000;
1037 let Inst{15-12} = Rt;
1040 let Inst{19-16} = addr{9-6}; // Rn
1041 let Inst{3-0} = addr{5-2}; // Rm
1042 let Inst{5-4} = addr{1-0}; // imm
1046 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1047 /// register and one whose operand is a register rotated by 8/16/24.
1048 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1049 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1050 opc, ".w\t$Rd, $Rm$rot",
1051 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1052 Requires<[IsThumb2]> {
1053 let Inst{31-27} = 0b11111;
1054 let Inst{26-23} = 0b0100;
1055 let Inst{22-20} = opcod;
1056 let Inst{19-16} = 0b1111; // Rn
1057 let Inst{15-12} = 0b1111;
1061 let Inst{5-4} = rot{1-0}; // rotate
1064 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1065 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1066 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1067 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1068 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1069 Requires<[HasT2ExtractPack, IsThumb2]> {
1071 let Inst{31-27} = 0b11111;
1072 let Inst{26-23} = 0b0100;
1073 let Inst{22-20} = opcod;
1074 let Inst{19-16} = 0b1111; // Rn
1075 let Inst{15-12} = 0b1111;
1077 let Inst{5-4} = rot;
1080 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1082 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1083 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1084 opc, "\t$Rd, $Rm$rot", []>,
1085 Requires<[IsThumb2, HasT2ExtractPack]> {
1087 let Inst{31-27} = 0b11111;
1088 let Inst{26-23} = 0b0100;
1089 let Inst{22-20} = opcod;
1090 let Inst{19-16} = 0b1111; // Rn
1091 let Inst{15-12} = 0b1111;
1093 let Inst{5-4} = rot;
1096 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1097 /// register and one whose operand is a register rotated by 8/16/24.
1098 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1099 : T2ThreeReg<(outs rGPR:$Rd),
1100 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1101 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1102 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1103 Requires<[HasT2ExtractPack, IsThumb2]> {
1105 let Inst{31-27} = 0b11111;
1106 let Inst{26-23} = 0b0100;
1107 let Inst{22-20} = opcod;
1108 let Inst{15-12} = 0b1111;
1110 let Inst{5-4} = rot;
1113 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1114 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1115 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1117 let Inst{31-27} = 0b11111;
1118 let Inst{26-23} = 0b0100;
1119 let Inst{22-20} = opcod;
1120 let Inst{15-12} = 0b1111;
1122 let Inst{5-4} = rot;
1125 //===----------------------------------------------------------------------===//
1127 //===----------------------------------------------------------------------===//
1129 //===----------------------------------------------------------------------===//
1130 // Miscellaneous Instructions.
1133 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1134 string asm, list<dag> pattern>
1135 : T2XI<oops, iops, itin, asm, pattern> {
1139 let Inst{11-8} = Rd;
1140 let Inst{26} = label{11};
1141 let Inst{14-12} = label{10-8};
1142 let Inst{7-0} = label{7-0};
1145 // LEApcrel - Load a pc-relative address into a register without offending the
1147 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1148 (ins t2adrlabel:$addr, pred:$p),
1149 IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1150 let Inst{31-27} = 0b11110;
1151 let Inst{25-24} = 0b10;
1152 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1155 let Inst{19-16} = 0b1111; // Rn
1160 let Inst{11-8} = Rd;
1161 let Inst{23} = addr{12};
1162 let Inst{21} = addr{12};
1163 let Inst{26} = addr{11};
1164 let Inst{14-12} = addr{10-8};
1165 let Inst{7-0} = addr{7-0};
1168 let neverHasSideEffects = 1, isReMaterializable = 1 in
1169 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1171 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1172 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1177 //===----------------------------------------------------------------------===//
1178 // Load / store Instructions.
1182 let canFoldAsLoad = 1, isReMaterializable = 1 in
1183 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1184 UnOpFrag<(load node:$Src)>>;
1186 // Loads with zero extension
1187 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1188 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1189 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1190 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1192 // Loads with sign extension
1193 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1194 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1195 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1196 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1198 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1200 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1201 (ins t2addrmode_imm8s4:$addr),
1202 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1203 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1205 // zextload i1 -> zextload i8
1206 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1207 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1208 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1209 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1210 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1211 (t2LDRBs t2addrmode_so_reg:$addr)>;
1212 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1213 (t2LDRBpci tconstpool:$addr)>;
1215 // extload -> zextload
1216 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1218 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1219 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1220 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1221 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1222 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1223 (t2LDRBs t2addrmode_so_reg:$addr)>;
1224 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1225 (t2LDRBpci tconstpool:$addr)>;
1227 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1228 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1229 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1230 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1231 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1232 (t2LDRBs t2addrmode_so_reg:$addr)>;
1233 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1234 (t2LDRBpci tconstpool:$addr)>;
1236 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1237 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1238 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1239 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1240 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1241 (t2LDRHs t2addrmode_so_reg:$addr)>;
1242 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1243 (t2LDRHpci tconstpool:$addr)>;
1245 // FIXME: The destination register of the loads and stores can't be PC, but
1246 // can be SP. We need another regclass (similar to rGPR) to represent
1247 // that. Not a pressing issue since these are selected manually,
1252 let mayLoad = 1, neverHasSideEffects = 1 in {
1253 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1254 (ins t2addrmode_imm8:$addr),
1255 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1256 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1258 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1261 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1262 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1263 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1264 "ldr", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1266 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1267 (ins t2addrmode_imm8:$addr),
1268 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1269 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1271 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1273 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1274 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1275 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1276 "ldrb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1278 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1279 (ins t2addrmode_imm8:$addr),
1280 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1281 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1283 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1285 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1286 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1287 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1288 "ldrh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1290 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1291 (ins t2addrmode_imm8:$addr),
1292 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1293 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1295 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1297 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1298 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1299 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1300 "ldrsb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1302 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1303 (ins t2addrmode_imm8:$addr),
1304 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1305 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1307 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1309 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1310 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1311 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1312 "ldrsh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1313 } // mayLoad = 1, neverHasSideEffects = 1
1315 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1316 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1317 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1318 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1319 "\t$Rt, $addr", []> {
1322 let Inst{31-27} = 0b11111;
1323 let Inst{26-25} = 0b00;
1324 let Inst{24} = signed;
1326 let Inst{22-21} = type;
1327 let Inst{20} = 1; // load
1328 let Inst{19-16} = addr{12-9};
1329 let Inst{15-12} = Rt;
1331 let Inst{10-8} = 0b110; // PUW.
1332 let Inst{7-0} = addr{7-0};
1335 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1336 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1337 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1338 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1339 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1342 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1343 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1344 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1345 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1346 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1347 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1350 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1351 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1352 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1353 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1356 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1357 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1358 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1359 "str", "\t$Rt, [$Rn, $addr]!",
1360 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1361 [(set GPRnopc:$Rn_wb,
1362 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1364 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1365 (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1366 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1367 "str", "\t$Rt, $Rn, $offset",
1368 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1369 [(set GPRnopc:$Rn_wb,
1370 (post_store rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
1372 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1373 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1374 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1375 "strh", "\t$Rt, [$Rn, $addr]!",
1376 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1377 [(set GPRnopc:$Rn_wb,
1378 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1380 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1381 (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1382 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1383 "strh", "\t$Rt, $Rn, $offset",
1384 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1385 [(set GPRnopc:$Rn_wb,
1386 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
1388 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1389 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1390 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1391 "strb", "\t$Rt, [$Rn, $addr]!",
1392 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1393 [(set GPRnopc:$Rn_wb,
1394 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1396 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1397 (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1398 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1399 "strb", "\t$Rt, $Rn, $offset",
1400 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1401 [(set GPRnopc:$Rn_wb,
1402 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
1404 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1406 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1407 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1408 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1409 "\t$Rt, $addr", []> {
1410 let Inst{31-27} = 0b11111;
1411 let Inst{26-25} = 0b00;
1412 let Inst{24} = 0; // not signed
1414 let Inst{22-21} = type;
1415 let Inst{20} = 0; // store
1417 let Inst{10-8} = 0b110; // PUW
1421 let Inst{15-12} = Rt;
1422 let Inst{19-16} = addr{12-9};
1423 let Inst{7-0} = addr{7-0};
1426 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1427 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1428 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1430 // ldrd / strd pre / post variants
1431 // For disassembly only.
1433 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1434 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1435 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1436 let AsmMatchConverter = "cvtT2LdrdPre";
1437 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1440 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1441 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1442 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr, $imm",
1443 "$addr.base = $wb", []>;
1445 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1446 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1447 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1448 "$addr.base = $wb", []> {
1449 let AsmMatchConverter = "cvtT2StrdPre";
1450 let DecoderMethod = "DecodeT2STRDPreInstruction";
1453 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1454 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1455 t2am_imm8s4_offset:$imm),
1456 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr, $imm",
1457 "$addr.base = $wb", []>;
1459 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1460 // data/instruction access. These are for disassembly only.
1461 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1462 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1463 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1465 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1467 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1468 let Inst{31-25} = 0b1111100;
1469 let Inst{24} = instr;
1471 let Inst{21} = write;
1473 let Inst{15-12} = 0b1111;
1476 let addr{12} = 1; // add = TRUE
1477 let Inst{19-16} = addr{16-13}; // Rn
1478 let Inst{23} = addr{12}; // U
1479 let Inst{11-0} = addr{11-0}; // imm12
1482 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1484 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1485 let Inst{31-25} = 0b1111100;
1486 let Inst{24} = instr;
1487 let Inst{23} = 0; // U = 0
1489 let Inst{21} = write;
1491 let Inst{15-12} = 0b1111;
1492 let Inst{11-8} = 0b1100;
1495 let Inst{19-16} = addr{12-9}; // Rn
1496 let Inst{7-0} = addr{7-0}; // imm8
1499 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1501 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1502 let Inst{31-25} = 0b1111100;
1503 let Inst{24} = instr;
1504 let Inst{23} = 0; // add = TRUE for T1
1506 let Inst{21} = write;
1508 let Inst{15-12} = 0b1111;
1509 let Inst{11-6} = 0000000;
1512 let Inst{19-16} = addr{9-6}; // Rn
1513 let Inst{3-0} = addr{5-2}; // Rm
1514 let Inst{5-4} = addr{1-0}; // imm2
1516 let DecoderMethod = "DecodeT2LoadShift";
1520 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1521 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1522 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1524 //===----------------------------------------------------------------------===//
1525 // Load / store multiple Instructions.
1528 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1529 InstrItinClass itin_upd, bit L_bit> {
1531 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1532 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1536 let Inst{31-27} = 0b11101;
1537 let Inst{26-25} = 0b00;
1538 let Inst{24-23} = 0b01; // Increment After
1540 let Inst{21} = 0; // No writeback
1541 let Inst{20} = L_bit;
1542 let Inst{19-16} = Rn;
1543 let Inst{15-0} = regs;
1546 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1547 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1551 let Inst{31-27} = 0b11101;
1552 let Inst{26-25} = 0b00;
1553 let Inst{24-23} = 0b01; // Increment After
1555 let Inst{21} = 1; // Writeback
1556 let Inst{20} = L_bit;
1557 let Inst{19-16} = Rn;
1558 let Inst{15-0} = regs;
1561 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1562 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1566 let Inst{31-27} = 0b11101;
1567 let Inst{26-25} = 0b00;
1568 let Inst{24-23} = 0b10; // Decrement Before
1570 let Inst{21} = 0; // No writeback
1571 let Inst{20} = L_bit;
1572 let Inst{19-16} = Rn;
1573 let Inst{15-0} = regs;
1576 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1577 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1581 let Inst{31-27} = 0b11101;
1582 let Inst{26-25} = 0b00;
1583 let Inst{24-23} = 0b10; // Decrement Before
1585 let Inst{21} = 1; // Writeback
1586 let Inst{20} = L_bit;
1587 let Inst{19-16} = Rn;
1588 let Inst{15-0} = regs;
1592 let neverHasSideEffects = 1 in {
1594 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1595 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1597 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1598 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1600 } // neverHasSideEffects
1603 //===----------------------------------------------------------------------===//
1604 // Move Instructions.
1607 let neverHasSideEffects = 1 in
1608 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1609 "mov", ".w\t$Rd, $Rm", []> {
1610 let Inst{31-27} = 0b11101;
1611 let Inst{26-25} = 0b01;
1612 let Inst{24-21} = 0b0010;
1613 let Inst{19-16} = 0b1111; // Rn
1614 let Inst{14-12} = 0b000;
1615 let Inst{7-4} = 0b0000;
1618 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1619 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1620 AddedComplexity = 1 in
1621 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1622 "mov", ".w\t$Rd, $imm",
1623 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1624 let Inst{31-27} = 0b11110;
1626 let Inst{24-21} = 0b0010;
1627 let Inst{19-16} = 0b1111; // Rn
1631 def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1632 pred:$p, cc_out:$s)>;
1634 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1635 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1636 "movw", "\t$Rd, $imm",
1637 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1638 let Inst{31-27} = 0b11110;
1640 let Inst{24-21} = 0b0010;
1641 let Inst{20} = 0; // The S bit.
1647 let Inst{11-8} = Rd;
1648 let Inst{19-16} = imm{15-12};
1649 let Inst{26} = imm{11};
1650 let Inst{14-12} = imm{10-8};
1651 let Inst{7-0} = imm{7-0};
1654 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1655 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1657 let Constraints = "$src = $Rd" in {
1658 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1659 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1660 "movt", "\t$Rd, $imm",
1662 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1663 let Inst{31-27} = 0b11110;
1665 let Inst{24-21} = 0b0110;
1666 let Inst{20} = 0; // The S bit.
1672 let Inst{11-8} = Rd;
1673 let Inst{19-16} = imm{15-12};
1674 let Inst{26} = imm{11};
1675 let Inst{14-12} = imm{10-8};
1676 let Inst{7-0} = imm{7-0};
1679 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1680 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1683 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1685 //===----------------------------------------------------------------------===//
1686 // Extend Instructions.
1691 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1692 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1693 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1694 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1695 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1697 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1698 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1699 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1700 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1701 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1703 // TODO: SXT(A){B|H}16
1707 let AddedComplexity = 16 in {
1708 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1709 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1710 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1711 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1712 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1713 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1715 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1716 // The transformation should probably be done as a combiner action
1717 // instead so we can include a check for masking back in the upper
1718 // eight bits of the source into the lower eight bits of the result.
1719 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1720 // (t2UXTB16 rGPR:$Src, 3)>,
1721 // Requires<[HasT2ExtractPack, IsThumb2]>;
1722 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1723 (t2UXTB16 rGPR:$Src, 1)>,
1724 Requires<[HasT2ExtractPack, IsThumb2]>;
1726 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1727 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1728 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1729 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1730 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1733 //===----------------------------------------------------------------------===//
1734 // Arithmetic Instructions.
1737 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1738 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1739 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1740 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1742 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1743 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1744 // CPSR and the implicit def of CPSR is not needed.
1745 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1746 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1747 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1748 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1749 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1750 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1752 let hasPostISelHook = 1 in {
1753 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1754 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1755 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1756 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1760 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1761 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1763 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1764 // CPSR and the implicit def of CPSR is not needed.
1765 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1766 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1768 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1769 // The assume-no-carry-in form uses the negation of the input since add/sub
1770 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1771 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1773 // The AddedComplexity preferences the first variant over the others since
1774 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1775 let AddedComplexity = 1 in
1776 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1777 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1778 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1779 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1780 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1781 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1782 let AddedComplexity = 1 in
1783 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1784 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1785 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1786 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1787 // The with-carry-in form matches bitwise not instead of the negation.
1788 // Effectively, the inverse interpretation of the carry flag already accounts
1789 // for part of the negation.
1790 let AddedComplexity = 1 in
1791 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1792 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1793 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1794 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1796 // Select Bytes -- for disassembly only
1798 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1799 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1800 Requires<[IsThumb2, HasThumb2DSP]> {
1801 let Inst{31-27} = 0b11111;
1802 let Inst{26-24} = 0b010;
1804 let Inst{22-20} = 0b010;
1805 let Inst{15-12} = 0b1111;
1807 let Inst{6-4} = 0b000;
1810 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1811 // And Miscellaneous operations -- for disassembly only
1812 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1813 list<dag> pat = [/* For disassembly only; pattern left blank */],
1814 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1815 string asm = "\t$Rd, $Rn, $Rm">
1816 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1817 Requires<[IsThumb2, HasThumb2DSP]> {
1818 let Inst{31-27} = 0b11111;
1819 let Inst{26-23} = 0b0101;
1820 let Inst{22-20} = op22_20;
1821 let Inst{15-12} = 0b1111;
1822 let Inst{7-4} = op7_4;
1828 let Inst{11-8} = Rd;
1829 let Inst{19-16} = Rn;
1833 // Saturating add/subtract -- for disassembly only
1835 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1836 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1837 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1838 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1839 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1840 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1841 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1842 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1843 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1844 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1845 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1846 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1847 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1848 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1849 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1850 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1851 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1852 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1853 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1854 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1855 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1856 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1858 // Signed/Unsigned add/subtract -- for disassembly only
1860 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1861 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1862 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1863 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1864 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1865 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1866 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1867 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1868 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1869 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1870 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1871 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1873 // Signed/Unsigned halving add/subtract -- for disassembly only
1875 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1876 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1877 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1878 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1879 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1880 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1881 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1882 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1883 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1884 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1885 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1886 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1888 // Helper class for disassembly only
1889 // A6.3.16 & A6.3.17
1890 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1891 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1892 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1893 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1894 let Inst{31-27} = 0b11111;
1895 let Inst{26-24} = 0b011;
1896 let Inst{23} = long;
1897 let Inst{22-20} = op22_20;
1898 let Inst{7-4} = op7_4;
1901 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1902 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1903 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1904 let Inst{31-27} = 0b11111;
1905 let Inst{26-24} = 0b011;
1906 let Inst{23} = long;
1907 let Inst{22-20} = op22_20;
1908 let Inst{7-4} = op7_4;
1911 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1913 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1914 (ins rGPR:$Rn, rGPR:$Rm),
1915 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1916 Requires<[IsThumb2, HasThumb2DSP]> {
1917 let Inst{15-12} = 0b1111;
1919 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1920 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1921 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1922 Requires<[IsThumb2, HasThumb2DSP]>;
1924 // Signed/Unsigned saturate -- for disassembly only
1926 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1927 string opc, string asm, list<dag> pattern>
1928 : T2I<oops, iops, itin, opc, asm, pattern> {
1934 let Inst{11-8} = Rd;
1935 let Inst{19-16} = Rn;
1936 let Inst{4-0} = sat_imm;
1937 let Inst{21} = sh{5};
1938 let Inst{14-12} = sh{4-2};
1939 let Inst{7-6} = sh{1-0};
1943 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1944 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1945 [/* For disassembly only; pattern left blank */]> {
1946 let Inst{31-27} = 0b11110;
1947 let Inst{25-22} = 0b1100;
1952 def t2SSAT16: T2SatI<
1953 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
1954 "ssat16", "\t$Rd, $sat_imm, $Rn",
1955 [/* For disassembly only; pattern left blank */]>,
1956 Requires<[IsThumb2, HasThumb2DSP]> {
1957 let Inst{31-27} = 0b11110;
1958 let Inst{25-22} = 0b1100;
1961 let Inst{21} = 1; // sh = '1'
1962 let Inst{14-12} = 0b000; // imm3 = '000'
1963 let Inst{7-6} = 0b00; // imm2 = '00'
1967 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1968 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1969 [/* For disassembly only; pattern left blank */]> {
1970 let Inst{31-27} = 0b11110;
1971 let Inst{25-22} = 0b1110;
1976 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn),
1978 "usat16", "\t$Rd, $sat_imm, $Rn",
1979 [/* For disassembly only; pattern left blank */]>,
1980 Requires<[IsThumb2, HasThumb2DSP]> {
1981 let Inst{31-27} = 0b11110;
1982 let Inst{25-22} = 0b1110;
1985 let Inst{21} = 1; // sh = '1'
1986 let Inst{14-12} = 0b000; // imm3 = '000'
1987 let Inst{7-6} = 0b00; // imm2 = '00'
1990 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1991 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1993 //===----------------------------------------------------------------------===//
1994 // Shift and rotate Instructions.
1997 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
1998 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
1999 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2000 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2001 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2002 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2003 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2004 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2006 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2007 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2008 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2010 let Uses = [CPSR] in {
2011 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2012 "rrx", "\t$Rd, $Rm",
2013 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2014 let Inst{31-27} = 0b11101;
2015 let Inst{26-25} = 0b01;
2016 let Inst{24-21} = 0b0010;
2017 let Inst{19-16} = 0b1111; // Rn
2018 let Inst{14-12} = 0b000;
2019 let Inst{7-4} = 0b0011;
2023 let isCodeGenOnly = 1, Defs = [CPSR] in {
2024 def t2MOVsrl_flag : T2TwoRegShiftImm<
2025 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2026 "lsrs", ".w\t$Rd, $Rm, #1",
2027 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2028 let Inst{31-27} = 0b11101;
2029 let Inst{26-25} = 0b01;
2030 let Inst{24-21} = 0b0010;
2031 let Inst{20} = 1; // The S bit.
2032 let Inst{19-16} = 0b1111; // Rn
2033 let Inst{5-4} = 0b01; // Shift type.
2034 // Shift amount = Inst{14-12:7-6} = 1.
2035 let Inst{14-12} = 0b000;
2036 let Inst{7-6} = 0b01;
2038 def t2MOVsra_flag : T2TwoRegShiftImm<
2039 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2040 "asrs", ".w\t$Rd, $Rm, #1",
2041 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2042 let Inst{31-27} = 0b11101;
2043 let Inst{26-25} = 0b01;
2044 let Inst{24-21} = 0b0010;
2045 let Inst{20} = 1; // The S bit.
2046 let Inst{19-16} = 0b1111; // Rn
2047 let Inst{5-4} = 0b10; // Shift type.
2048 // Shift amount = Inst{14-12:7-6} = 1.
2049 let Inst{14-12} = 0b000;
2050 let Inst{7-6} = 0b01;
2054 //===----------------------------------------------------------------------===//
2055 // Bitwise Instructions.
2058 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2059 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2060 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2061 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2062 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2063 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2064 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2065 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2066 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2068 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2069 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2070 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2073 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2074 string opc, string asm, list<dag> pattern>
2075 : T2I<oops, iops, itin, opc, asm, pattern> {
2080 let Inst{11-8} = Rd;
2081 let Inst{4-0} = msb{4-0};
2082 let Inst{14-12} = lsb{4-2};
2083 let Inst{7-6} = lsb{1-0};
2086 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2087 string opc, string asm, list<dag> pattern>
2088 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2091 let Inst{19-16} = Rn;
2094 let Constraints = "$src = $Rd" in
2095 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2096 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2097 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2098 let Inst{31-27} = 0b11110;
2099 let Inst{26} = 0; // should be 0.
2101 let Inst{24-20} = 0b10110;
2102 let Inst{19-16} = 0b1111; // Rn
2104 let Inst{5} = 0; // should be 0.
2107 let msb{4-0} = imm{9-5};
2108 let lsb{4-0} = imm{4-0};
2111 def t2SBFX: T2TwoRegBitFI<
2112 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2113 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2114 let Inst{31-27} = 0b11110;
2116 let Inst{24-20} = 0b10100;
2120 def t2UBFX: T2TwoRegBitFI<
2121 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2122 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2123 let Inst{31-27} = 0b11110;
2125 let Inst{24-20} = 0b11100;
2129 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2130 let Constraints = "$src = $Rd" in {
2131 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2132 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2133 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2134 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2135 bf_inv_mask_imm:$imm))]> {
2136 let Inst{31-27} = 0b11110;
2137 let Inst{26} = 0; // should be 0.
2139 let Inst{24-20} = 0b10110;
2141 let Inst{5} = 0; // should be 0.
2144 let msb{4-0} = imm{9-5};
2145 let lsb{4-0} = imm{4-0};
2148 // GNU as only supports this form of bfi (w/ 4 arguments)
2149 let isAsmParserOnly = 1 in
2150 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2151 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2153 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2155 let Inst{31-27} = 0b11110;
2156 let Inst{26} = 0; // should be 0.
2158 let Inst{24-20} = 0b10110;
2160 let Inst{5} = 0; // should be 0.
2164 let msb{4-0} = width; // Custom encoder => lsb+width-1
2165 let lsb{4-0} = lsbit;
2169 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2170 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2171 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2174 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2175 let AddedComplexity = 1 in
2176 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2177 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2178 UnOpFrag<(not node:$Src)>, 1, 1>;
2181 let AddedComplexity = 1 in
2182 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2183 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2185 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2186 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2187 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2188 Requires<[IsThumb2]>;
2190 def : T2Pat<(t2_so_imm_not:$src),
2191 (t2MVNi t2_so_imm_not:$src)>;
2193 //===----------------------------------------------------------------------===//
2194 // Multiply Instructions.
2196 let isCommutable = 1 in
2197 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2198 "mul", "\t$Rd, $Rn, $Rm",
2199 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2200 let Inst{31-27} = 0b11111;
2201 let Inst{26-23} = 0b0110;
2202 let Inst{22-20} = 0b000;
2203 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2204 let Inst{7-4} = 0b0000; // Multiply
2207 def t2MLA: T2FourReg<
2208 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2209 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2210 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2211 let Inst{31-27} = 0b11111;
2212 let Inst{26-23} = 0b0110;
2213 let Inst{22-20} = 0b000;
2214 let Inst{7-4} = 0b0000; // Multiply
2217 def t2MLS: T2FourReg<
2218 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2219 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2220 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2221 let Inst{31-27} = 0b11111;
2222 let Inst{26-23} = 0b0110;
2223 let Inst{22-20} = 0b000;
2224 let Inst{7-4} = 0b0001; // Multiply and Subtract
2227 // Extra precision multiplies with low / high results
2228 let neverHasSideEffects = 1 in {
2229 let isCommutable = 1 in {
2230 def t2SMULL : T2MulLong<0b000, 0b0000,
2231 (outs rGPR:$RdLo, rGPR:$RdHi),
2232 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2233 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2235 def t2UMULL : T2MulLong<0b010, 0b0000,
2236 (outs rGPR:$RdLo, rGPR:$RdHi),
2237 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2238 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2241 // Multiply + accumulate
2242 def t2SMLAL : T2MulLong<0b100, 0b0000,
2243 (outs rGPR:$RdLo, rGPR:$RdHi),
2244 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2245 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2247 def t2UMLAL : T2MulLong<0b110, 0b0000,
2248 (outs rGPR:$RdLo, rGPR:$RdHi),
2249 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2250 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2252 def t2UMAAL : T2MulLong<0b110, 0b0110,
2253 (outs rGPR:$RdLo, rGPR:$RdHi),
2254 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2255 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2256 Requires<[IsThumb2, HasThumb2DSP]>;
2257 } // neverHasSideEffects
2259 // Rounding variants of the below included for disassembly only
2261 // Most significant word multiply
2262 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2263 "smmul", "\t$Rd, $Rn, $Rm",
2264 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2265 Requires<[IsThumb2, HasThumb2DSP]> {
2266 let Inst{31-27} = 0b11111;
2267 let Inst{26-23} = 0b0110;
2268 let Inst{22-20} = 0b101;
2269 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2270 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2273 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2274 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2275 Requires<[IsThumb2, HasThumb2DSP]> {
2276 let Inst{31-27} = 0b11111;
2277 let Inst{26-23} = 0b0110;
2278 let Inst{22-20} = 0b101;
2279 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2280 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2283 def t2SMMLA : T2FourReg<
2284 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2285 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2286 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2287 Requires<[IsThumb2, HasThumb2DSP]> {
2288 let Inst{31-27} = 0b11111;
2289 let Inst{26-23} = 0b0110;
2290 let Inst{22-20} = 0b101;
2291 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2294 def t2SMMLAR: T2FourReg<
2295 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2296 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2297 Requires<[IsThumb2, HasThumb2DSP]> {
2298 let Inst{31-27} = 0b11111;
2299 let Inst{26-23} = 0b0110;
2300 let Inst{22-20} = 0b101;
2301 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2304 def t2SMMLS: T2FourReg<
2305 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2306 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2307 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2308 Requires<[IsThumb2, HasThumb2DSP]> {
2309 let Inst{31-27} = 0b11111;
2310 let Inst{26-23} = 0b0110;
2311 let Inst{22-20} = 0b110;
2312 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2315 def t2SMMLSR:T2FourReg<
2316 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2317 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2318 Requires<[IsThumb2, HasThumb2DSP]> {
2319 let Inst{31-27} = 0b11111;
2320 let Inst{26-23} = 0b0110;
2321 let Inst{22-20} = 0b110;
2322 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2325 multiclass T2I_smul<string opc, PatFrag opnode> {
2326 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2327 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2328 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2329 (sext_inreg rGPR:$Rm, i16)))]>,
2330 Requires<[IsThumb2, HasThumb2DSP]> {
2331 let Inst{31-27} = 0b11111;
2332 let Inst{26-23} = 0b0110;
2333 let Inst{22-20} = 0b001;
2334 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2335 let Inst{7-6} = 0b00;
2336 let Inst{5-4} = 0b00;
2339 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2340 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2341 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2342 (sra rGPR:$Rm, (i32 16))))]>,
2343 Requires<[IsThumb2, HasThumb2DSP]> {
2344 let Inst{31-27} = 0b11111;
2345 let Inst{26-23} = 0b0110;
2346 let Inst{22-20} = 0b001;
2347 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2348 let Inst{7-6} = 0b00;
2349 let Inst{5-4} = 0b01;
2352 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2353 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2354 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2355 (sext_inreg rGPR:$Rm, i16)))]>,
2356 Requires<[IsThumb2, HasThumb2DSP]> {
2357 let Inst{31-27} = 0b11111;
2358 let Inst{26-23} = 0b0110;
2359 let Inst{22-20} = 0b001;
2360 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2361 let Inst{7-6} = 0b00;
2362 let Inst{5-4} = 0b10;
2365 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2366 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2367 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2368 (sra rGPR:$Rm, (i32 16))))]>,
2369 Requires<[IsThumb2, HasThumb2DSP]> {
2370 let Inst{31-27} = 0b11111;
2371 let Inst{26-23} = 0b0110;
2372 let Inst{22-20} = 0b001;
2373 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2374 let Inst{7-6} = 0b00;
2375 let Inst{5-4} = 0b11;
2378 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2379 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2380 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2381 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2382 Requires<[IsThumb2, HasThumb2DSP]> {
2383 let Inst{31-27} = 0b11111;
2384 let Inst{26-23} = 0b0110;
2385 let Inst{22-20} = 0b011;
2386 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2387 let Inst{7-6} = 0b00;
2388 let Inst{5-4} = 0b00;
2391 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2392 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2393 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2394 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2395 Requires<[IsThumb2, HasThumb2DSP]> {
2396 let Inst{31-27} = 0b11111;
2397 let Inst{26-23} = 0b0110;
2398 let Inst{22-20} = 0b011;
2399 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2400 let Inst{7-6} = 0b00;
2401 let Inst{5-4} = 0b01;
2406 multiclass T2I_smla<string opc, PatFrag opnode> {
2408 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2409 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2410 [(set rGPR:$Rd, (add rGPR:$Ra,
2411 (opnode (sext_inreg rGPR:$Rn, i16),
2412 (sext_inreg rGPR:$Rm, i16))))]>,
2413 Requires<[IsThumb2, HasThumb2DSP]> {
2414 let Inst{31-27} = 0b11111;
2415 let Inst{26-23} = 0b0110;
2416 let Inst{22-20} = 0b001;
2417 let Inst{7-6} = 0b00;
2418 let Inst{5-4} = 0b00;
2422 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2423 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2424 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2425 (sra rGPR:$Rm, (i32 16)))))]>,
2426 Requires<[IsThumb2, HasThumb2DSP]> {
2427 let Inst{31-27} = 0b11111;
2428 let Inst{26-23} = 0b0110;
2429 let Inst{22-20} = 0b001;
2430 let Inst{7-6} = 0b00;
2431 let Inst{5-4} = 0b01;
2435 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2436 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2437 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2438 (sext_inreg rGPR:$Rm, i16))))]>,
2439 Requires<[IsThumb2, HasThumb2DSP]> {
2440 let Inst{31-27} = 0b11111;
2441 let Inst{26-23} = 0b0110;
2442 let Inst{22-20} = 0b001;
2443 let Inst{7-6} = 0b00;
2444 let Inst{5-4} = 0b10;
2448 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2449 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2450 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2451 (sra rGPR:$Rm, (i32 16)))))]>,
2452 Requires<[IsThumb2, HasThumb2DSP]> {
2453 let Inst{31-27} = 0b11111;
2454 let Inst{26-23} = 0b0110;
2455 let Inst{22-20} = 0b001;
2456 let Inst{7-6} = 0b00;
2457 let Inst{5-4} = 0b11;
2461 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2462 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2463 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2464 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2465 Requires<[IsThumb2, HasThumb2DSP]> {
2466 let Inst{31-27} = 0b11111;
2467 let Inst{26-23} = 0b0110;
2468 let Inst{22-20} = 0b011;
2469 let Inst{7-6} = 0b00;
2470 let Inst{5-4} = 0b00;
2474 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2475 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2476 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2477 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2478 Requires<[IsThumb2, HasThumb2DSP]> {
2479 let Inst{31-27} = 0b11111;
2480 let Inst{26-23} = 0b0110;
2481 let Inst{22-20} = 0b011;
2482 let Inst{7-6} = 0b00;
2483 let Inst{5-4} = 0b01;
2487 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2488 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2490 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2491 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2492 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2493 [/* For disassembly only; pattern left blank */]>,
2494 Requires<[IsThumb2, HasThumb2DSP]>;
2495 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2496 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2497 [/* For disassembly only; pattern left blank */]>,
2498 Requires<[IsThumb2, HasThumb2DSP]>;
2499 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2500 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2501 [/* For disassembly only; pattern left blank */]>,
2502 Requires<[IsThumb2, HasThumb2DSP]>;
2503 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2504 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2505 [/* For disassembly only; pattern left blank */]>,
2506 Requires<[IsThumb2, HasThumb2DSP]>;
2508 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2509 // These are for disassembly only.
2511 def t2SMUAD: T2ThreeReg_mac<
2512 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2513 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2514 Requires<[IsThumb2, HasThumb2DSP]> {
2515 let Inst{15-12} = 0b1111;
2517 def t2SMUADX:T2ThreeReg_mac<
2518 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2519 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2520 Requires<[IsThumb2, HasThumb2DSP]> {
2521 let Inst{15-12} = 0b1111;
2523 def t2SMUSD: T2ThreeReg_mac<
2524 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2525 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2526 Requires<[IsThumb2, HasThumb2DSP]> {
2527 let Inst{15-12} = 0b1111;
2529 def t2SMUSDX:T2ThreeReg_mac<
2530 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2531 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2532 Requires<[IsThumb2, HasThumb2DSP]> {
2533 let Inst{15-12} = 0b1111;
2535 def t2SMLAD : T2FourReg_mac<
2536 0, 0b010, 0b0000, (outs rGPR:$Rd),
2537 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2538 "\t$Rd, $Rn, $Rm, $Ra", []>,
2539 Requires<[IsThumb2, HasThumb2DSP]>;
2540 def t2SMLADX : T2FourReg_mac<
2541 0, 0b010, 0b0001, (outs rGPR:$Rd),
2542 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2543 "\t$Rd, $Rn, $Rm, $Ra", []>,
2544 Requires<[IsThumb2, HasThumb2DSP]>;
2545 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2546 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2547 "\t$Rd, $Rn, $Rm, $Ra", []>,
2548 Requires<[IsThumb2, HasThumb2DSP]>;
2549 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2550 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2551 "\t$Rd, $Rn, $Rm, $Ra", []>,
2552 Requires<[IsThumb2, HasThumb2DSP]>;
2553 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2554 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2555 "\t$Ra, $Rd, $Rm, $Rn", []>,
2556 Requires<[IsThumb2, HasThumb2DSP]>;
2557 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2558 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2559 "\t$Ra, $Rd, $Rm, $Rn", []>,
2560 Requires<[IsThumb2, HasThumb2DSP]>;
2561 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2562 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2563 "\t$Ra, $Rd, $Rm, $Rn", []>,
2564 Requires<[IsThumb2, HasThumb2DSP]>;
2565 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2566 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2567 "\t$Ra, $Rd, $Rm, $Rn", []>,
2568 Requires<[IsThumb2, HasThumb2DSP]>;
2570 //===----------------------------------------------------------------------===//
2571 // Division Instructions.
2572 // Signed and unsigned division on v7-M
2574 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2575 "sdiv", "\t$Rd, $Rn, $Rm",
2576 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2577 Requires<[HasDivide, IsThumb2]> {
2578 let Inst{31-27} = 0b11111;
2579 let Inst{26-21} = 0b011100;
2581 let Inst{15-12} = 0b1111;
2582 let Inst{7-4} = 0b1111;
2585 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2586 "udiv", "\t$Rd, $Rn, $Rm",
2587 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2588 Requires<[HasDivide, IsThumb2]> {
2589 let Inst{31-27} = 0b11111;
2590 let Inst{26-21} = 0b011101;
2592 let Inst{15-12} = 0b1111;
2593 let Inst{7-4} = 0b1111;
2596 //===----------------------------------------------------------------------===//
2597 // Misc. Arithmetic Instructions.
2600 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2601 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2602 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2603 let Inst{31-27} = 0b11111;
2604 let Inst{26-22} = 0b01010;
2605 let Inst{21-20} = op1;
2606 let Inst{15-12} = 0b1111;
2607 let Inst{7-6} = 0b10;
2608 let Inst{5-4} = op2;
2612 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2613 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2615 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2616 "rbit", "\t$Rd, $Rm",
2617 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2619 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2620 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2622 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2623 "rev16", ".w\t$Rd, $Rm",
2624 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2626 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2627 "revsh", ".w\t$Rd, $Rm",
2628 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2630 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2631 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2632 (t2REVSH rGPR:$Rm)>;
2634 def t2PKHBT : T2ThreeReg<
2635 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2636 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
2637 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2638 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2640 Requires<[HasT2ExtractPack, IsThumb2]> {
2641 let Inst{31-27} = 0b11101;
2642 let Inst{26-25} = 0b01;
2643 let Inst{24-20} = 0b01100;
2644 let Inst{5} = 0; // BT form
2648 let Inst{14-12} = sh{4-2};
2649 let Inst{7-6} = sh{1-0};
2652 // Alternate cases for PKHBT where identities eliminate some nodes.
2653 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2654 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2655 Requires<[HasT2ExtractPack, IsThumb2]>;
2656 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2657 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2658 Requires<[HasT2ExtractPack, IsThumb2]>;
2660 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2661 // will match the pattern below.
2662 def t2PKHTB : T2ThreeReg<
2663 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2664 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
2665 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2666 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2668 Requires<[HasT2ExtractPack, IsThumb2]> {
2669 let Inst{31-27} = 0b11101;
2670 let Inst{26-25} = 0b01;
2671 let Inst{24-20} = 0b01100;
2672 let Inst{5} = 1; // TB form
2676 let Inst{14-12} = sh{4-2};
2677 let Inst{7-6} = sh{1-0};
2680 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2681 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2682 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2683 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2684 Requires<[HasT2ExtractPack, IsThumb2]>;
2685 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2686 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2687 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2688 Requires<[HasT2ExtractPack, IsThumb2]>;
2690 //===----------------------------------------------------------------------===//
2691 // Comparison Instructions...
2693 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2694 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2695 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2697 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2698 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2699 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2700 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2701 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2702 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2704 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2705 // Compare-to-zero still works out, just not the relationals
2706 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2707 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2708 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2709 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2710 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2713 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2714 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2716 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2717 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2719 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2720 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2721 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2723 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2724 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2725 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2728 // Conditional moves
2729 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2730 // a two-value operand where a dag node expects two operands. :(
2731 let neverHasSideEffects = 1 in {
2732 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2733 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2735 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2736 RegConstraint<"$false = $Rd">;
2738 let isMoveImm = 1 in
2739 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2740 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2742 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2743 RegConstraint<"$false = $Rd">;
2745 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2746 let isCodeGenOnly = 1 in {
2747 let isMoveImm = 1 in
2748 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2750 "movw", "\t$Rd, $imm", []>,
2751 RegConstraint<"$false = $Rd"> {
2752 let Inst{31-27} = 0b11110;
2754 let Inst{24-21} = 0b0010;
2755 let Inst{20} = 0; // The S bit.
2761 let Inst{11-8} = Rd;
2762 let Inst{19-16} = imm{15-12};
2763 let Inst{26} = imm{11};
2764 let Inst{14-12} = imm{10-8};
2765 let Inst{7-0} = imm{7-0};
2768 let isMoveImm = 1 in
2769 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2770 (ins rGPR:$false, i32imm:$src, pred:$p),
2771 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2773 let isMoveImm = 1 in
2774 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2775 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2776 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2777 imm:$cc, CCR:$ccr))*/]>,
2778 RegConstraint<"$false = $Rd"> {
2779 let Inst{31-27} = 0b11110;
2781 let Inst{24-21} = 0b0011;
2782 let Inst{20} = 0; // The S bit.
2783 let Inst{19-16} = 0b1111; // Rn
2787 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2788 string opc, string asm, list<dag> pattern>
2789 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2790 let Inst{31-27} = 0b11101;
2791 let Inst{26-25} = 0b01;
2792 let Inst{24-21} = 0b0010;
2793 let Inst{20} = 0; // The S bit.
2794 let Inst{19-16} = 0b1111; // Rn
2795 let Inst{5-4} = opcod; // Shift type.
2797 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2798 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2799 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2800 RegConstraint<"$false = $Rd">;
2801 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2802 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2803 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2804 RegConstraint<"$false = $Rd">;
2805 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2806 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2807 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2808 RegConstraint<"$false = $Rd">;
2809 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2810 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2811 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2812 RegConstraint<"$false = $Rd">;
2813 } // isCodeGenOnly = 1
2814 } // neverHasSideEffects
2816 //===----------------------------------------------------------------------===//
2817 // Atomic operations intrinsics
2820 // memory barriers protect the atomic sequences
2821 let hasSideEffects = 1 in {
2822 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2823 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2824 Requires<[IsThumb, HasDB]> {
2826 let Inst{31-4} = 0xf3bf8f5;
2827 let Inst{3-0} = opt;
2831 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2832 "dsb", "\t$opt", []>,
2833 Requires<[IsThumb, HasDB]> {
2835 let Inst{31-4} = 0xf3bf8f4;
2836 let Inst{3-0} = opt;
2839 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2841 []>, Requires<[IsThumb2, HasDB]> {
2843 let Inst{31-4} = 0xf3bf8f6;
2844 let Inst{3-0} = opt;
2847 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2848 InstrItinClass itin, string opc, string asm, string cstr,
2849 list<dag> pattern, bits<4> rt2 = 0b1111>
2850 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2851 let Inst{31-27} = 0b11101;
2852 let Inst{26-20} = 0b0001101;
2853 let Inst{11-8} = rt2;
2854 let Inst{7-6} = 0b01;
2855 let Inst{5-4} = opcod;
2856 let Inst{3-0} = 0b1111;
2860 let Inst{19-16} = addr;
2861 let Inst{15-12} = Rt;
2863 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2864 InstrItinClass itin, string opc, string asm, string cstr,
2865 list<dag> pattern, bits<4> rt2 = 0b1111>
2866 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2867 let Inst{31-27} = 0b11101;
2868 let Inst{26-20} = 0b0001100;
2869 let Inst{11-8} = rt2;
2870 let Inst{7-6} = 0b01;
2871 let Inst{5-4} = opcod;
2877 let Inst{19-16} = addr;
2878 let Inst{15-12} = Rt;
2881 let mayLoad = 1 in {
2882 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2883 AddrModeNone, 4, NoItinerary,
2884 "ldrexb", "\t$Rt, $addr", "", []>;
2885 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2886 AddrModeNone, 4, NoItinerary,
2887 "ldrexh", "\t$Rt, $addr", "", []>;
2888 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
2889 AddrModeNone, 4, NoItinerary,
2890 "ldrex", "\t$Rt, $addr", "", []> {
2893 let Inst{31-27} = 0b11101;
2894 let Inst{26-20} = 0b0000101;
2895 let Inst{19-16} = addr{11-8};
2896 let Inst{15-12} = Rt;
2897 let Inst{11-8} = 0b1111;
2898 let Inst{7-0} = addr{7-0};
2900 let hasExtraDefRegAllocReq = 1 in
2901 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2902 (ins addr_offset_none:$addr),
2903 AddrModeNone, 4, NoItinerary,
2904 "ldrexd", "\t$Rt, $Rt2, $addr", "",
2907 let Inst{11-8} = Rt2;
2911 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2912 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2913 (ins rGPR:$Rt, addr_offset_none:$addr),
2914 AddrModeNone, 4, NoItinerary,
2915 "strexb", "\t$Rd, $Rt, $addr", "", []>;
2916 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2917 (ins rGPR:$Rt, addr_offset_none:$addr),
2918 AddrModeNone, 4, NoItinerary,
2919 "strexh", "\t$Rd, $Rt, $addr", "", []>;
2920 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
2921 t2addrmode_imm0_1020s4:$addr),
2922 AddrModeNone, 4, NoItinerary,
2923 "strex", "\t$Rd, $Rt, $addr", "",
2928 let Inst{31-27} = 0b11101;
2929 let Inst{26-20} = 0b0000100;
2930 let Inst{19-16} = addr{11-8};
2931 let Inst{15-12} = Rt;
2932 let Inst{11-8} = Rd;
2933 let Inst{7-0} = addr{7-0};
2937 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2938 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2939 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
2940 AddrModeNone, 4, NoItinerary,
2941 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2944 let Inst{11-8} = Rt2;
2947 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
2948 Requires<[IsThumb2, HasV7]> {
2949 let Inst{31-16} = 0xf3bf;
2950 let Inst{15-14} = 0b10;
2953 let Inst{11-8} = 0b1111;
2954 let Inst{7-4} = 0b0010;
2955 let Inst{3-0} = 0b1111;
2958 //===----------------------------------------------------------------------===//
2959 // SJLJ Exception handling intrinsics
2960 // eh_sjlj_setjmp() is an instruction sequence to store the return
2961 // address and save #0 in R0 for the non-longjmp case.
2962 // Since by its nature we may be coming from some other function to get
2963 // here, and we're using the stack frame for the containing function to
2964 // save/restore registers, we can't keep anything live in regs across
2965 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2966 // when we get here from a longjmp(). We force everything out of registers
2967 // except for our own input by listing the relevant registers in Defs. By
2968 // doing so, we also cause the prologue/epilogue code to actively preserve
2969 // all of the callee-saved resgisters, which is exactly what we want.
2970 // $val is a scratch register for our use.
2972 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
2973 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2974 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2975 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2976 AddrModeNone, 0, NoItinerary, "", "",
2977 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2978 Requires<[IsThumb2, HasVFP2]>;
2982 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
2983 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2984 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2985 AddrModeNone, 0, NoItinerary, "", "",
2986 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2987 Requires<[IsThumb2, NoVFP]>;
2991 //===----------------------------------------------------------------------===//
2992 // Control-Flow Instructions
2995 // FIXME: remove when we have a way to marking a MI with these properties.
2996 // FIXME: Should pc be an implicit operand like PICADD, etc?
2997 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2998 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2999 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3000 reglist:$regs, variable_ops),
3001 4, IIC_iLoad_mBr, [],
3002 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3003 RegConstraint<"$Rn = $wb">;
3005 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3006 let isPredicable = 1 in
3007 def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
3009 [(br bb:$target)]> {
3010 let Inst{31-27} = 0b11110;
3011 let Inst{15-14} = 0b10;
3015 let Inst{26} = target{19};
3016 let Inst{11} = target{18};
3017 let Inst{13} = target{17};
3018 let Inst{21-16} = target{16-11};
3019 let Inst{10-0} = target{10-0};
3022 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3023 def t2BR_JT : t2PseudoInst<(outs),
3024 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3026 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3028 // FIXME: Add a non-pc based case that can be predicated.
3029 def t2TBB_JT : t2PseudoInst<(outs),
3030 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3033 def t2TBH_JT : t2PseudoInst<(outs),
3034 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3037 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3038 "tbb", "\t[$Rn, $Rm]", []> {
3041 let Inst{31-20} = 0b111010001101;
3042 let Inst{19-16} = Rn;
3043 let Inst{15-5} = 0b11110000000;
3044 let Inst{4} = 0; // B form
3048 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3049 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3052 let Inst{31-20} = 0b111010001101;
3053 let Inst{19-16} = Rn;
3054 let Inst{15-5} = 0b11110000000;
3055 let Inst{4} = 1; // H form
3058 } // isNotDuplicable, isIndirectBranch
3060 } // isBranch, isTerminator, isBarrier
3062 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3063 // a two-value operand where a dag node expects two operands. :(
3064 let isBranch = 1, isTerminator = 1 in
3065 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3067 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3068 let Inst{31-27} = 0b11110;
3069 let Inst{15-14} = 0b10;
3073 let Inst{25-22} = p;
3076 let Inst{26} = target{20};
3077 let Inst{11} = target{19};
3078 let Inst{13} = target{18};
3079 let Inst{21-16} = target{17-12};
3080 let Inst{10-0} = target{11-1};
3082 let DecoderMethod = "DecodeThumb2BCCInstruction";
3085 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3087 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3089 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3091 def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
3093 (t2B uncondbrtarget:$dst)>,
3094 Requires<[IsThumb2, IsDarwin]>;
3098 let Defs = [ITSTATE] in
3099 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3100 AddrModeNone, 2, IIC_iALUx,
3101 "it$mask\t$cc", "", []> {
3102 // 16-bit instruction.
3103 let Inst{31-16} = 0x0000;
3104 let Inst{15-8} = 0b10111111;
3109 let Inst{3-0} = mask;
3111 let DecoderMethod = "DecodeIT";
3114 // Branch and Exchange Jazelle -- for disassembly only
3116 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3118 let Inst{31-27} = 0b11110;
3120 let Inst{25-20} = 0b111100;
3121 let Inst{19-16} = func;
3122 let Inst{15-0} = 0b1000111100000000;
3125 // Compare and branch on zero / non-zero
3126 let isBranch = 1, isTerminator = 1 in {
3127 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3128 "cbz\t$Rn, $target", []>,
3129 T1Misc<{0,0,?,1,?,?,?}>,
3130 Requires<[IsThumb2]> {
3134 let Inst{9} = target{5};
3135 let Inst{7-3} = target{4-0};
3139 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3140 "cbnz\t$Rn, $target", []>,
3141 T1Misc<{1,0,?,1,?,?,?}>,
3142 Requires<[IsThumb2]> {
3146 let Inst{9} = target{5};
3147 let Inst{7-3} = target{4-0};
3153 // Change Processor State is a system instruction -- for disassembly and
3155 // FIXME: Since the asm parser has currently no clean way to handle optional
3156 // operands, create 3 versions of the same instruction. Once there's a clean
3157 // framework to represent optional operands, change this behavior.
3158 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3159 !strconcat("cps", asm_op),
3160 [/* For disassembly only; pattern left blank */]> {
3166 let Inst{31-27} = 0b11110;
3168 let Inst{25-20} = 0b111010;
3169 let Inst{19-16} = 0b1111;
3170 let Inst{15-14} = 0b10;
3172 let Inst{10-9} = imod;
3174 let Inst{7-5} = iflags;
3175 let Inst{4-0} = mode;
3176 let DecoderMethod = "DecodeT2CPSInstruction";
3180 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3181 "$imod.w\t$iflags, $mode">;
3182 let mode = 0, M = 0 in
3183 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3184 "$imod.w\t$iflags">;
3185 let imod = 0, iflags = 0, M = 1 in
3186 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3188 // A6.3.4 Branches and miscellaneous control
3189 // Table A6-14 Change Processor State, and hint instructions
3190 // Helper class for disassembly only.
3191 class T2I_hint<bits<8> op7_0, string opc, string asm>
3192 : T2I<(outs), (ins), NoItinerary, opc, asm,
3193 [/* For disassembly only; pattern left blank */]> {
3194 let Inst{31-20} = 0xf3a;
3195 let Inst{19-16} = 0b1111;
3196 let Inst{15-14} = 0b10;
3198 let Inst{10-8} = 0b000;
3199 let Inst{7-0} = op7_0;
3202 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3203 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3204 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3205 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3206 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3208 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3210 let Inst{31-20} = 0b111100111010;
3211 let Inst{19-16} = 0b1111;
3212 let Inst{15-8} = 0b10000000;
3213 let Inst{7-4} = 0b1111;
3214 let Inst{3-0} = opt;
3217 // Secure Monitor Call is a system instruction -- for disassembly only
3218 // Option = Inst{19-16}
3219 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3220 [/* For disassembly only; pattern left blank */]> {
3221 let Inst{31-27} = 0b11110;
3222 let Inst{26-20} = 0b1111111;
3223 let Inst{15-12} = 0b1000;
3226 let Inst{19-16} = opt;
3229 class T2SRS<bits<12> op31_20,
3230 dag oops, dag iops, InstrItinClass itin,
3231 string opc, string asm, list<dag> pattern>
3232 : T2I<oops, iops, itin, opc, asm, pattern> {
3233 let Inst{31-20} = op31_20{11-0};
3236 let Inst{4-0} = mode{4-0};
3239 // Store Return State is a system instruction -- for disassembly only
3240 def t2SRSDBW : T2SRS<0b111010000010,
3241 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3242 [/* For disassembly only; pattern left blank */]>;
3243 def t2SRSDB : T2SRS<0b111010000000,
3244 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3245 [/* For disassembly only; pattern left blank */]>;
3246 def t2SRSIAW : T2SRS<0b111010011010,
3247 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3248 [/* For disassembly only; pattern left blank */]>;
3249 def t2SRSIA : T2SRS<0b111010011000,
3250 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3251 [/* For disassembly only; pattern left blank */]>;
3253 // Return From Exception is a system instruction -- for disassembly only
3255 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3256 string opc, string asm, list<dag> pattern>
3257 : T2I<oops, iops, itin, opc, asm, pattern> {
3258 let Inst{31-20} = op31_20{11-0};
3261 let Inst{19-16} = Rn;
3262 let Inst{15-0} = 0xc000;
3265 def t2RFEDBW : T2RFE<0b111010000011,
3266 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3267 [/* For disassembly only; pattern left blank */]>;
3268 def t2RFEDB : T2RFE<0b111010000001,
3269 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3270 [/* For disassembly only; pattern left blank */]>;
3271 def t2RFEIAW : T2RFE<0b111010011011,
3272 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3273 [/* For disassembly only; pattern left blank */]>;
3274 def t2RFEIA : T2RFE<0b111010011001,
3275 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3276 [/* For disassembly only; pattern left blank */]>;
3278 //===----------------------------------------------------------------------===//
3279 // Non-Instruction Patterns
3282 // 32-bit immediate using movw + movt.
3283 // This is a single pseudo instruction to make it re-materializable.
3284 // FIXME: Remove this when we can do generalized remat.
3285 let isReMaterializable = 1, isMoveImm = 1 in
3286 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3287 [(set rGPR:$dst, (i32 imm:$src))]>,
3288 Requires<[IsThumb, HasV6T2]>;
3290 // Pseudo instruction that combines movw + movt + add pc (if pic).
3291 // It also makes it possible to rematerialize the instructions.
3292 // FIXME: Remove this when we can do generalized remat and when machine licm
3293 // can properly the instructions.
3294 let isReMaterializable = 1 in {
3295 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3297 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3298 Requires<[IsThumb2, UseMovt]>;
3300 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3302 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3303 Requires<[IsThumb2, UseMovt]>;
3306 // ConstantPool, GlobalAddress, and JumpTable
3307 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3308 Requires<[IsThumb2, DontUseMovt]>;
3309 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3310 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3311 Requires<[IsThumb2, UseMovt]>;
3313 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3314 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3316 // Pseudo instruction that combines ldr from constpool and add pc. This should
3317 // be expanded into two instructions late to allow if-conversion and
3319 let canFoldAsLoad = 1, isReMaterializable = 1 in
3320 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3322 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3324 Requires<[IsThumb2]>;
3325 //===----------------------------------------------------------------------===//
3326 // Coprocessor load/store -- for disassembly only
3328 class T2CI<dag oops, dag iops, string opc, string asm>
3329 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3330 let Inst{27-25} = 0b110;
3333 multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
3334 def _OFFSET : T2CI<(outs),
3335 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3336 opc, "\tp$cop, cr$CRd, $addr"> {
3337 let Inst{31-28} = op31_28;
3338 let Inst{24} = 1; // P = 1
3339 let Inst{21} = 0; // W = 0
3340 let Inst{22} = 0; // D = 0
3341 let Inst{20} = load;
3342 let DecoderMethod = "DecodeCopMemInstruction";
3345 def _PRE : T2CI<(outs),
3346 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3347 opc, "\tp$cop, cr$CRd, $addr!"> {
3348 let Inst{31-28} = op31_28;
3349 let Inst{24} = 1; // P = 1
3350 let Inst{21} = 1; // W = 1
3351 let Inst{22} = 0; // D = 0
3352 let Inst{20} = load;
3353 let DecoderMethod = "DecodeCopMemInstruction";
3356 def _POST : T2CI<(outs),
3357 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3358 opc, "\tp$cop, cr$CRd, $addr"> {
3359 let Inst{31-28} = op31_28;
3360 let Inst{24} = 0; // P = 0
3361 let Inst{21} = 1; // W = 1
3362 let Inst{22} = 0; // D = 0
3363 let Inst{20} = load;
3364 let DecoderMethod = "DecodeCopMemInstruction";
3367 def _OPTION : T2CI<(outs),
3368 (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3369 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3370 let Inst{31-28} = op31_28;
3371 let Inst{24} = 0; // P = 0
3372 let Inst{23} = 1; // U = 1
3373 let Inst{21} = 0; // W = 0
3374 let Inst{22} = 0; // D = 0
3375 let Inst{20} = load;
3376 let DecoderMethod = "DecodeCopMemInstruction";
3379 def L_OFFSET : T2CI<(outs),
3380 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3381 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3382 let Inst{31-28} = op31_28;
3383 let Inst{24} = 1; // P = 1
3384 let Inst{21} = 0; // W = 0
3385 let Inst{22} = 1; // D = 1
3386 let Inst{20} = load;
3387 let DecoderMethod = "DecodeCopMemInstruction";
3390 def L_PRE : T2CI<(outs),
3391 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3392 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3393 let Inst{31-28} = op31_28;
3394 let Inst{24} = 1; // P = 1
3395 let Inst{21} = 1; // W = 1
3396 let Inst{22} = 1; // D = 1
3397 let Inst{20} = load;
3398 let DecoderMethod = "DecodeCopMemInstruction";
3401 def L_POST : T2CI<(outs),
3402 (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
3403 postidx_imm8s4:$offset),
3404 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
3405 let Inst{31-28} = op31_28;
3406 let Inst{24} = 0; // P = 0
3407 let Inst{21} = 1; // W = 1
3408 let Inst{22} = 1; // D = 1
3409 let Inst{20} = load;
3410 let DecoderMethod = "DecodeCopMemInstruction";
3413 def L_OPTION : T2CI<(outs),
3414 (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3415 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3416 let Inst{31-28} = op31_28;
3417 let Inst{24} = 0; // P = 0
3418 let Inst{23} = 1; // U = 1
3419 let Inst{21} = 0; // W = 0
3420 let Inst{22} = 1; // D = 1
3421 let Inst{20} = load;
3422 let DecoderMethod = "DecodeCopMemInstruction";
3426 defm t2LDC : T2LdStCop<0b1111, 1, "ldc">;
3427 defm t2STC : T2LdStCop<0b1111, 0, "stc">;
3430 //===----------------------------------------------------------------------===//
3431 // Move between special register and ARM core register -- for disassembly only
3434 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3435 dag oops, dag iops, InstrItinClass itin,
3436 string opc, string asm, list<dag> pattern>
3437 : T2I<oops, iops, itin, opc, asm, pattern> {
3438 let Inst{31-20} = op31_20{11-0};
3439 let Inst{15-14} = op15_14{1-0};
3441 let Inst{12} = op12{0};
3445 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3446 dag oops, dag iops, InstrItinClass itin,
3447 string opc, string asm, list<dag> pattern>
3448 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3450 let Inst{11-8} = Rd;
3451 let Inst{19-16} = 0b1111;
3454 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3455 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3456 [/* For disassembly only; pattern left blank */]>;
3457 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3458 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3459 [/* For disassembly only; pattern left blank */]>;
3461 // Move from ARM core register to Special Register
3463 // No need to have both system and application versions, the encodings are the
3464 // same and the assembly parser has no way to distinguish between them. The mask
3465 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3466 // the mask with the fields to be accessed in the special register.
3467 def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3468 0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3469 NoItinerary, "msr", "\t$mask, $Rn",
3470 [/* For disassembly only; pattern left blank */]> {
3473 let Inst{19-16} = Rn;
3474 let Inst{20} = mask{4}; // R Bit
3475 let Inst{11-8} = mask{3-0};
3478 //===----------------------------------------------------------------------===//
3479 // Move between coprocessor and ARM core register
3482 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3484 : T2Cop<Op, oops, iops,
3485 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3487 let Inst{27-24} = 0b1110;
3488 let Inst{20} = direction;
3498 let Inst{15-12} = Rt;
3499 let Inst{11-8} = cop;
3500 let Inst{23-21} = opc1;
3501 let Inst{7-5} = opc2;
3502 let Inst{3-0} = CRm;
3503 let Inst{19-16} = CRn;
3506 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3507 list<dag> pattern = []>
3509 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3510 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3511 let Inst{27-24} = 0b1100;
3512 let Inst{23-21} = 0b010;
3513 let Inst{20} = direction;
3521 let Inst{15-12} = Rt;
3522 let Inst{19-16} = Rt2;
3523 let Inst{11-8} = cop;
3524 let Inst{7-4} = opc1;
3525 let Inst{3-0} = CRm;
3528 /* from ARM core register to coprocessor */
3529 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3531 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3532 c_imm:$CRm, imm0_7:$opc2),
3533 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3534 imm:$CRm, imm:$opc2)]>;
3535 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3536 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3537 c_imm:$CRm, imm0_7:$opc2),
3538 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3539 imm:$CRm, imm:$opc2)]>;
3541 /* from coprocessor to ARM core register */
3542 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3543 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3544 c_imm:$CRm, imm0_7:$opc2), []>;
3546 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3547 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3548 c_imm:$CRm, imm0_7:$opc2), []>;
3550 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3551 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3553 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3554 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3557 /* from ARM core register to coprocessor */
3558 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3559 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3561 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3562 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3563 GPR:$Rt2, imm:$CRm)]>;
3564 /* from coprocessor to ARM core register */
3565 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3567 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3569 //===----------------------------------------------------------------------===//
3570 // Other Coprocessor Instructions.
3573 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3574 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3575 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3576 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3577 imm:$CRm, imm:$opc2)]> {
3578 let Inst{27-24} = 0b1110;
3587 let Inst{3-0} = CRm;
3589 let Inst{7-5} = opc2;
3590 let Inst{11-8} = cop;
3591 let Inst{15-12} = CRd;
3592 let Inst{19-16} = CRn;
3593 let Inst{23-20} = opc1;
3596 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3597 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3598 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3599 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3600 imm:$CRm, imm:$opc2)]> {
3601 let Inst{27-24} = 0b1110;
3610 let Inst{3-0} = CRm;
3612 let Inst{7-5} = opc2;
3613 let Inst{11-8} = cop;
3614 let Inst{15-12} = CRd;
3615 let Inst{19-16} = CRn;
3616 let Inst{23-20} = opc1;
3621 //===----------------------------------------------------------------------===//
3622 // Non-Instruction Patterns
3625 // SXT/UXT with no rotate
3626 let AddedComplexity = 16 in {
3627 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3628 Requires<[IsThumb2]>;
3629 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3630 Requires<[IsThumb2]>;
3631 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3632 Requires<[HasT2ExtractPack, IsThumb2]>;
3633 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3634 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3635 Requires<[HasT2ExtractPack, IsThumb2]>;
3636 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3637 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3638 Requires<[HasT2ExtractPack, IsThumb2]>;
3641 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3642 Requires<[IsThumb2]>;
3643 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3644 Requires<[IsThumb2]>;
3645 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3646 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3647 Requires<[HasT2ExtractPack, IsThumb2]>;
3648 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3649 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3650 Requires<[HasT2ExtractPack, IsThumb2]>;
3652 // Atomic load/store patterns
3653 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3654 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3655 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3656 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3657 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3658 (t2LDRBs t2addrmode_so_reg:$addr)>;
3659 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3660 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3661 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3662 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3663 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3664 (t2LDRHs t2addrmode_so_reg:$addr)>;
3665 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3666 (t2LDRi12 t2addrmode_imm12:$addr)>;
3667 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3668 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3669 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3670 (t2LDRs t2addrmode_so_reg:$addr)>;
3671 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3672 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3673 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3674 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3675 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3676 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3677 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3678 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3679 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3680 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3681 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3682 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3683 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3684 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3685 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3686 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3687 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3688 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3691 //===----------------------------------------------------------------------===//
3692 // Assembler aliases
3695 // Aliases for ADC without the ".w" optional width specifier.
3696 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3697 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3698 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3699 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3700 pred:$p, cc_out:$s)>;
3702 // Aliases for SBC without the ".w" optional width specifier.
3703 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3704 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3705 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3706 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3707 pred:$p, cc_out:$s)>;
3709 // Aliases for ADD without the ".w" optional width specifier.
3710 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3711 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3712 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3713 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3714 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3715 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3716 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3717 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3718 pred:$p, cc_out:$s)>;
3720 // Alias for compares without the ".w" optional width specifier.
3721 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3722 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3723 def : t2InstAlias<"teq${p} $Rn, $Rm",
3724 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3725 def : t2InstAlias<"tst${p} $Rn, $Rm",
3726 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3729 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3730 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3731 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3733 // Alias for LDR, LDRB, LDRH without the ".w" optional width specifier.
3734 def : t2InstAlias<"ldr${p} $Rt, $addr",
3735 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3736 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3737 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3738 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3739 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3740 def : t2InstAlias<"ldr${p} $Rt, $addr",
3741 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3742 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3743 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3744 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3745 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;