1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 // Define Thumb2 specific addressing modes.
127 // t2addrmode_imm12 := reg + imm12
128 def t2addrmode_imm12 : Operand<i32>,
129 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
130 let PrintMethod = "printT2AddrModeImm12Operand";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
134 // t2addrmode_imm8 := reg - imm8
135 def t2addrmode_imm8 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137 let PrintMethod = "printT2AddrModeImm8Operand";
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141 def t2am_imm8_offset : Operand<i32>,
142 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
143 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
147 def t2addrmode_imm8s4 : Operand<i32>,
148 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
149 let PrintMethod = "printT2AddrModeImm8s4Operand";
150 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
153 // t2addrmode_so_reg := reg + (reg << imm2)
154 def t2addrmode_so_reg : Operand<i32>,
155 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
156 let PrintMethod = "printT2AddrModeSoRegOperand";
157 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
161 //===----------------------------------------------------------------------===//
162 // Multiclass helpers...
165 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
166 /// unary operation that produces a value. These are predicable and can be
167 /// changed to modify CPSR.
168 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
169 bit Cheap = 0, bit ReMat = 0> {
171 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
173 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
174 let isAsCheapAsAMove = Cheap;
175 let isReMaterializable = ReMat;
176 let Inst{31-27} = 0b11110;
178 let Inst{24-21} = opcod;
179 let Inst{20} = ?; // The S bit.
180 let Inst{19-16} = 0b1111; // Rn
184 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
185 opc, ".w\t$dst, $src",
186 [(set GPR:$dst, (opnode GPR:$src))]> {
187 let Inst{31-27} = 0b11101;
188 let Inst{26-25} = 0b01;
189 let Inst{24-21} = opcod;
190 let Inst{20} = ?; // The S bit.
191 let Inst{19-16} = 0b1111; // Rn
192 let Inst{14-12} = 0b000; // imm3
193 let Inst{7-6} = 0b00; // imm2
194 let Inst{5-4} = 0b00; // type
197 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
198 opc, ".w\t$dst, $src",
199 [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
200 let Inst{31-27} = 0b11101;
201 let Inst{26-25} = 0b01;
202 let Inst{24-21} = opcod;
203 let Inst{20} = ?; // The S bit.
204 let Inst{19-16} = 0b1111; // Rn
208 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
209 // binary operation that produces a value. These are predicable and can be
210 /// changed to modify CPSR.
211 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
212 bit Commutable = 0, string wide =""> {
214 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
215 opc, "\t$dst, $lhs, $rhs",
216 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
217 let Inst{31-27} = 0b11110;
219 let Inst{24-21} = opcod;
220 let Inst{20} = ?; // The S bit.
224 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
225 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
226 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
227 let isCommutable = Commutable;
228 let Inst{31-27} = 0b11101;
229 let Inst{26-25} = 0b01;
230 let Inst{24-21} = opcod;
231 let Inst{20} = ?; // The S bit.
232 let Inst{14-12} = 0b000; // imm3
233 let Inst{7-6} = 0b00; // imm2
234 let Inst{5-4} = 0b00; // type
237 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
238 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
239 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
240 let Inst{31-27} = 0b11101;
241 let Inst{26-25} = 0b01;
242 let Inst{24-21} = opcod;
243 let Inst{20} = ?; // The S bit.
247 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
248 // the ".w" prefix to indicate that they are wide.
249 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
250 bit Commutable = 0> :
251 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
253 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
254 /// reversed. It doesn't define the 'rr' form since it's handled by its
255 /// T2I_bin_irs counterpart.
256 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
258 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
259 opc, ".w\t$dst, $rhs, $lhs",
260 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
261 let Inst{31-27} = 0b11110;
263 let Inst{24-21} = opcod;
264 let Inst{20} = 0; // The S bit.
268 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
269 opc, "\t$dst, $rhs, $lhs",
270 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
271 let Inst{31-27} = 0b11101;
272 let Inst{26-25} = 0b01;
273 let Inst{24-21} = opcod;
274 let Inst{20} = 0; // The S bit.
278 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
279 /// instruction modifies the CPSR register.
280 let Defs = [CPSR] in {
281 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
282 bit Commutable = 0> {
284 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
285 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
286 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
287 let Inst{31-27} = 0b11110;
289 let Inst{24-21} = opcod;
290 let Inst{20} = 1; // The S bit.
294 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
295 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
296 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
297 let isCommutable = Commutable;
298 let Inst{31-27} = 0b11101;
299 let Inst{26-25} = 0b01;
300 let Inst{24-21} = opcod;
301 let Inst{20} = 1; // The S bit.
302 let Inst{14-12} = 0b000; // imm3
303 let Inst{7-6} = 0b00; // imm2
304 let Inst{5-4} = 0b00; // type
307 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
308 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
309 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
310 let Inst{31-27} = 0b11101;
311 let Inst{26-25} = 0b01;
312 let Inst{24-21} = opcod;
313 let Inst{20} = 1; // The S bit.
318 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
319 /// patterns for a binary operation that produces a value.
320 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
321 bit Commutable = 0> {
323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
324 opc, ".w\t$dst, $lhs, $rhs",
325 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
326 let Inst{31-27} = 0b11110;
329 let Inst{23-21} = op23_21;
330 let Inst{20} = 0; // The S bit.
334 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
335 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
336 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
337 let Inst{31-27} = 0b11110;
340 let Inst{23-21} = op23_21;
341 let Inst{20} = 0; // The S bit.
345 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
346 opc, ".w\t$dst, $lhs, $rhs",
347 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
348 let isCommutable = Commutable;
349 let Inst{31-27} = 0b11101;
350 let Inst{26-25} = 0b01;
352 let Inst{23-21} = op23_21;
353 let Inst{20} = 0; // The S bit.
354 let Inst{14-12} = 0b000; // imm3
355 let Inst{7-6} = 0b00; // imm2
356 let Inst{5-4} = 0b00; // type
359 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
360 opc, ".w\t$dst, $lhs, $rhs",
361 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
362 let Inst{31-27} = 0b11101;
363 let Inst{26-25} = 0b01;
365 let Inst{23-21} = op23_21;
366 let Inst{20} = 0; // The S bit.
370 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
371 /// for a binary operation that produces a value and use the carry
372 /// bit. It's not predicable.
373 let Uses = [CPSR] in {
374 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
375 bit Commutable = 0> {
377 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
378 opc, "\t$dst, $lhs, $rhs",
379 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
380 Requires<[IsThumb2]> {
381 let Inst{31-27} = 0b11110;
383 let Inst{24-21} = opcod;
384 let Inst{20} = 0; // The S bit.
388 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
389 opc, ".w\t$dst, $lhs, $rhs",
390 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
391 Requires<[IsThumb2]> {
392 let isCommutable = Commutable;
393 let Inst{31-27} = 0b11101;
394 let Inst{26-25} = 0b01;
395 let Inst{24-21} = opcod;
396 let Inst{20} = 0; // The S bit.
397 let Inst{14-12} = 0b000; // imm3
398 let Inst{7-6} = 0b00; // imm2
399 let Inst{5-4} = 0b00; // type
402 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
403 opc, ".w\t$dst, $lhs, $rhs",
404 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
405 Requires<[IsThumb2]> {
406 let Inst{31-27} = 0b11101;
407 let Inst{26-25} = 0b01;
408 let Inst{24-21} = opcod;
409 let Inst{20} = 0; // The S bit.
413 // Carry setting variants
414 let Defs = [CPSR] in {
415 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
416 bit Commutable = 0> {
418 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
419 opc, "\t$dst, $lhs, $rhs",
420 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
421 Requires<[IsThumb2]> {
422 let Inst{31-27} = 0b11110;
424 let Inst{24-21} = opcod;
425 let Inst{20} = 1; // The S bit.
429 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
430 opc, ".w\t$dst, $lhs, $rhs",
431 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
432 Requires<[IsThumb2]> {
433 let isCommutable = Commutable;
434 let Inst{31-27} = 0b11101;
435 let Inst{26-25} = 0b01;
436 let Inst{24-21} = opcod;
437 let Inst{20} = 1; // The S bit.
438 let Inst{14-12} = 0b000; // imm3
439 let Inst{7-6} = 0b00; // imm2
440 let Inst{5-4} = 0b00; // type
443 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
444 opc, ".w\t$dst, $lhs, $rhs",
445 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
446 Requires<[IsThumb2]> {
447 let Inst{31-27} = 0b11101;
448 let Inst{26-25} = 0b01;
449 let Inst{24-21} = opcod;
450 let Inst{20} = 1; // The S bit.
456 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
457 let Defs = [CPSR] in {
458 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
460 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
462 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"),
463 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
464 let Inst{31-27} = 0b11110;
466 let Inst{24-21} = opcod;
467 let Inst{20} = 1; // The S bit.
471 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
473 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"),
474 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
475 let Inst{31-27} = 0b11101;
476 let Inst{26-25} = 0b01;
477 let Inst{24-21} = opcod;
478 let Inst{20} = 1; // The S bit.
483 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
484 // rotate operation that produces a value.
485 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
487 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
488 opc, ".w\t$dst, $lhs, $rhs",
489 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
490 let Inst{31-27} = 0b11101;
491 let Inst{26-21} = 0b010010;
492 let Inst{19-16} = 0b1111; // Rn
493 let Inst{5-4} = opcod;
496 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
497 opc, ".w\t$dst, $lhs, $rhs",
498 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
499 let Inst{31-27} = 0b11111;
500 let Inst{26-23} = 0b0100;
501 let Inst{22-21} = opcod;
502 let Inst{15-12} = 0b1111;
503 let Inst{7-4} = 0b0000;
507 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
508 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
509 /// a explicit result, only implicitly set CPSR.
510 let Defs = [CPSR] in {
511 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
513 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
514 opc, ".w\t$lhs, $rhs",
515 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
516 let Inst{31-27} = 0b11110;
518 let Inst{24-21} = opcod;
519 let Inst{20} = 1; // The S bit.
521 let Inst{11-8} = 0b1111; // Rd
524 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
525 opc, ".w\t$lhs, $rhs",
526 [(opnode GPR:$lhs, GPR:$rhs)]> {
527 let Inst{31-27} = 0b11101;
528 let Inst{26-25} = 0b01;
529 let Inst{24-21} = opcod;
530 let Inst{20} = 1; // The S bit.
531 let Inst{14-12} = 0b000; // imm3
532 let Inst{11-8} = 0b1111; // Rd
533 let Inst{7-6} = 0b00; // imm2
534 let Inst{5-4} = 0b00; // type
537 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
538 opc, ".w\t$lhs, $rhs",
539 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
540 let Inst{31-27} = 0b11101;
541 let Inst{26-25} = 0b01;
542 let Inst{24-21} = opcod;
543 let Inst{20} = 1; // The S bit.
544 let Inst{11-8} = 0b1111; // Rd
549 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
550 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
551 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
552 opc, ".w\t$dst, $addr",
553 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
554 let Inst{31-27} = 0b11111;
555 let Inst{26-25} = 0b00;
556 let Inst{24} = signed;
558 let Inst{22-21} = opcod;
559 let Inst{20} = 1; // load
561 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
562 opc, "\t$dst, $addr",
563 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
564 let Inst{31-27} = 0b11111;
565 let Inst{26-25} = 0b00;
566 let Inst{24} = signed;
568 let Inst{22-21} = opcod;
569 let Inst{20} = 1; // load
571 // Offset: index==TRUE, wback==FALSE
572 let Inst{10} = 1; // The P bit.
573 let Inst{8} = 0; // The W bit.
575 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
576 opc, ".w\t$dst, $addr",
577 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
578 let Inst{31-27} = 0b11111;
579 let Inst{26-25} = 0b00;
580 let Inst{24} = signed;
582 let Inst{22-21} = opcod;
583 let Inst{20} = 1; // load
584 let Inst{11-6} = 0b000000;
586 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
587 opc, ".w\t$dst, $addr",
588 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
589 let isReMaterializable = 1;
590 let Inst{31-27} = 0b11111;
591 let Inst{26-25} = 0b00;
592 let Inst{24} = signed;
593 let Inst{23} = ?; // add = (U == '1')
594 let Inst{22-21} = opcod;
595 let Inst{20} = 1; // load
596 let Inst{19-16} = 0b1111; // Rn
600 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
601 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
602 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
603 opc, ".w\t$src, $addr",
604 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
605 let Inst{31-27} = 0b11111;
606 let Inst{26-23} = 0b0001;
607 let Inst{22-21} = opcod;
608 let Inst{20} = 0; // !load
610 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
611 opc, "\t$src, $addr",
612 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
613 let Inst{31-27} = 0b11111;
614 let Inst{26-23} = 0b0000;
615 let Inst{22-21} = opcod;
616 let Inst{20} = 0; // !load
618 // Offset: index==TRUE, wback==FALSE
619 let Inst{10} = 1; // The P bit.
620 let Inst{8} = 0; // The W bit.
622 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
623 opc, ".w\t$src, $addr",
624 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
625 let Inst{31-27} = 0b11111;
626 let Inst{26-23} = 0b0000;
627 let Inst{22-21} = opcod;
628 let Inst{20} = 0; // !load
629 let Inst{11-6} = 0b000000;
633 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
634 /// register and one whose operand is a register rotated by 8/16/24.
635 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
636 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
637 opc, ".w\t$dst, $src",
638 [(set GPR:$dst, (opnode GPR:$src))]> {
639 let Inst{31-27} = 0b11111;
640 let Inst{26-23} = 0b0100;
641 let Inst{22-20} = opcod;
642 let Inst{19-16} = 0b1111; // Rn
643 let Inst{15-12} = 0b1111;
645 let Inst{5-4} = 0b00; // rotate
647 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
648 opc, ".w\t$dst, $src, ror $rot",
649 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
650 let Inst{31-27} = 0b11111;
651 let Inst{26-23} = 0b0100;
652 let Inst{22-20} = opcod;
653 let Inst{19-16} = 0b1111; // Rn
654 let Inst{15-12} = 0b1111;
656 let Inst{5-4} = {?,?}; // rotate
660 // DO variant - disassembly only, no pattern
662 multiclass T2I_unary_rrot_DO<bits<3> opcod, string opc> {
663 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
664 opc, "\t$dst, $src", []> {
665 let Inst{31-27} = 0b11111;
666 let Inst{26-23} = 0b0100;
667 let Inst{22-20} = opcod;
668 let Inst{19-16} = 0b1111; // Rn
669 let Inst{15-12} = 0b1111;
671 let Inst{5-4} = 0b00; // rotate
673 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
674 opc, "\t$dst, $src, ror $rot", []> {
675 let Inst{31-27} = 0b11111;
676 let Inst{26-23} = 0b0100;
677 let Inst{22-20} = opcod;
678 let Inst{19-16} = 0b1111; // Rn
679 let Inst{15-12} = 0b1111;
681 let Inst{5-4} = {?,?}; // rotate
685 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
686 /// register and one whose operand is a register rotated by 8/16/24.
687 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
688 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
689 opc, "\t$dst, $LHS, $RHS",
690 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]> {
691 let Inst{31-27} = 0b11111;
692 let Inst{26-23} = 0b0100;
693 let Inst{22-20} = opcod;
694 let Inst{15-12} = 0b1111;
696 let Inst{5-4} = 0b00; // rotate
698 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
699 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
700 [(set GPR:$dst, (opnode GPR:$LHS,
701 (rotr GPR:$RHS, rot_imm:$rot)))]> {
702 let Inst{31-27} = 0b11111;
703 let Inst{26-23} = 0b0100;
704 let Inst{22-20} = opcod;
705 let Inst{15-12} = 0b1111;
707 let Inst{5-4} = {?,?}; // rotate
711 // DO variant - disassembly only, no pattern
713 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
714 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
715 opc, "\t$dst, $LHS, $RHS", []> {
716 let Inst{31-27} = 0b11111;
717 let Inst{26-23} = 0b0100;
718 let Inst{22-20} = opcod;
719 let Inst{15-12} = 0b1111;
721 let Inst{5-4} = 0b00; // rotate
723 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
724 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
725 let Inst{31-27} = 0b11111;
726 let Inst{26-23} = 0b0100;
727 let Inst{22-20} = opcod;
728 let Inst{15-12} = 0b1111;
730 let Inst{5-4} = {?,?}; // rotate
734 //===----------------------------------------------------------------------===//
736 //===----------------------------------------------------------------------===//
738 //===----------------------------------------------------------------------===//
739 // Miscellaneous Instructions.
742 // LEApcrel - Load a pc-relative address into a register without offending the
744 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
745 "adr$p.w\t$dst, #$label", []> {
746 let Inst{31-27} = 0b11110;
747 let Inst{25-24} = 0b10;
748 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
751 let Inst{19-16} = 0b1111; // Rn
754 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
755 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
756 "adr$p.w\t$dst, #${label}_${id}", []> {
757 let Inst{31-27} = 0b11110;
758 let Inst{25-24} = 0b10;
759 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
762 let Inst{19-16} = 0b1111; // Rn
766 // ADD r, sp, {so_imm|i12}
767 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
768 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
769 let Inst{31-27} = 0b11110;
771 let Inst{24-21} = 0b1000;
772 let Inst{20} = ?; // The S bit.
773 let Inst{19-16} = 0b1101; // Rn = sp
776 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
777 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
778 let Inst{31-27} = 0b11110;
780 let Inst{24-21} = 0b0000;
781 let Inst{20} = 0; // The S bit.
782 let Inst{19-16} = 0b1101; // Rn = sp
787 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
788 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
789 let Inst{31-27} = 0b11101;
790 let Inst{26-25} = 0b01;
791 let Inst{24-21} = 0b1000;
792 let Inst{20} = ?; // The S bit.
793 let Inst{19-16} = 0b1101; // Rn = sp
797 // SUB r, sp, {so_imm|i12}
798 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
799 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
800 let Inst{31-27} = 0b11110;
802 let Inst{24-21} = 0b1101;
803 let Inst{20} = ?; // The S bit.
804 let Inst{19-16} = 0b1101; // Rn = sp
807 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
808 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
809 let Inst{31-27} = 0b11110;
811 let Inst{24-21} = 0b0101;
812 let Inst{20} = 0; // The S bit.
813 let Inst{19-16} = 0b1101; // Rn = sp
818 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
820 "sub", "\t$dst, $sp, $rhs", []> {
821 let Inst{31-27} = 0b11101;
822 let Inst{26-25} = 0b01;
823 let Inst{24-21} = 0b1101;
824 let Inst{20} = ?; // The S bit.
825 let Inst{19-16} = 0b1101; // Rn = sp
829 // Signed and unsigned division, for disassembly only
830 def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
831 "sdiv", "\t$dst, $a, $b", []> {
832 let Inst{31-27} = 0b11111;
833 let Inst{26-21} = 0b011100;
835 let Inst{15-12} = 0b1111;
836 let Inst{7-4} = 0b1111;
839 def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
840 "udiv", "\t$dst, $a, $b", []> {
841 let Inst{31-27} = 0b11111;
842 let Inst{26-21} = 0b011101;
844 let Inst{15-12} = 0b1111;
845 let Inst{7-4} = 0b1111;
848 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
849 let usesCustomInserter = 1 in { // Expanded after instruction selection.
850 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
851 NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
852 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
853 NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
854 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
855 NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
856 } // usesCustomInserter
859 //===----------------------------------------------------------------------===//
860 // Load / store Instructions.
864 let canFoldAsLoad = 1, isReMaterializable = 1 in
865 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
867 // Loads with zero extension
868 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
869 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
871 // Loads with sign extension
872 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
873 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
875 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
877 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
878 (ins t2addrmode_imm8s4:$addr),
879 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
880 def t2LDRDpci : T2Ii8s4<?, ?, 1, (outs GPR:$dst1, GPR:$dst2),
881 (ins i32imm:$addr), IIC_iLoadi,
882 "ldrd", "\t$dst1, $addr", []> {
883 let Inst{19-16} = 0b1111; // Rn
887 // zextload i1 -> zextload i8
888 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
889 (t2LDRBi12 t2addrmode_imm12:$addr)>;
890 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
891 (t2LDRBi8 t2addrmode_imm8:$addr)>;
892 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
893 (t2LDRBs t2addrmode_so_reg:$addr)>;
894 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
895 (t2LDRBpci tconstpool:$addr)>;
897 // extload -> zextload
898 // FIXME: Reduce the number of patterns by legalizing extload to zextload
900 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
901 (t2LDRBi12 t2addrmode_imm12:$addr)>;
902 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
903 (t2LDRBi8 t2addrmode_imm8:$addr)>;
904 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
905 (t2LDRBs t2addrmode_so_reg:$addr)>;
906 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
907 (t2LDRBpci tconstpool:$addr)>;
909 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
910 (t2LDRBi12 t2addrmode_imm12:$addr)>;
911 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
912 (t2LDRBi8 t2addrmode_imm8:$addr)>;
913 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
914 (t2LDRBs t2addrmode_so_reg:$addr)>;
915 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
916 (t2LDRBpci tconstpool:$addr)>;
918 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
919 (t2LDRHi12 t2addrmode_imm12:$addr)>;
920 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
921 (t2LDRHi8 t2addrmode_imm8:$addr)>;
922 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
923 (t2LDRHs t2addrmode_so_reg:$addr)>;
924 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
925 (t2LDRHpci tconstpool:$addr)>;
929 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
930 (ins t2addrmode_imm8:$addr),
931 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
932 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
935 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
936 (ins GPR:$base, t2am_imm8_offset:$offset),
937 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
938 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
941 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
942 (ins t2addrmode_imm8:$addr),
943 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
944 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
946 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
947 (ins GPR:$base, t2am_imm8_offset:$offset),
948 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
949 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
952 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
953 (ins t2addrmode_imm8:$addr),
954 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
955 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
957 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
958 (ins GPR:$base, t2am_imm8_offset:$offset),
959 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
960 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
963 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
964 (ins t2addrmode_imm8:$addr),
965 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
966 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
968 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
969 (ins GPR:$base, t2am_imm8_offset:$offset),
970 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
971 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
974 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
975 (ins t2addrmode_imm8:$addr),
976 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
977 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
979 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
980 (ins GPR:$base, t2am_imm8_offset:$offset),
981 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
982 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
987 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
988 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
989 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
992 let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
993 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
994 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
995 IIC_iStorer, "strd", "\t$src1, $addr", []>;
998 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
999 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1000 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1001 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1003 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1005 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1006 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1007 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1008 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1010 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1012 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1013 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1014 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1015 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1017 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1019 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1020 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1021 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1022 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1024 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1026 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1027 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1028 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1029 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1031 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1033 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1034 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1035 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1036 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1038 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1041 // FIXME: ldrd / strd pre / post variants
1043 //===----------------------------------------------------------------------===//
1044 // Load / store multiple Instructions.
1047 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1048 def t2LDM : T2XI<(outs),
1049 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1050 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1051 let Inst{31-27} = 0b11101;
1052 let Inst{26-25} = 0b00;
1053 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1055 let Inst{21} = ?; // The W bit.
1056 let Inst{20} = 1; // Load
1059 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1060 def t2STM : T2XI<(outs),
1061 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1062 IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1063 let Inst{31-27} = 0b11101;
1064 let Inst{26-25} = 0b00;
1065 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1067 let Inst{21} = ?; // The W bit.
1068 let Inst{20} = 0; // Store
1071 //===----------------------------------------------------------------------===//
1072 // Move Instructions.
1075 let neverHasSideEffects = 1 in
1076 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1077 "mov", ".w\t$dst, $src", []> {
1078 let Inst{31-27} = 0b11101;
1079 let Inst{26-25} = 0b01;
1080 let Inst{24-21} = 0b0010;
1081 let Inst{20} = ?; // The S bit.
1082 let Inst{19-16} = 0b1111; // Rn
1083 let Inst{14-12} = 0b000;
1084 let Inst{7-4} = 0b0000;
1087 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1088 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1089 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1090 "mov", ".w\t$dst, $src",
1091 [(set GPR:$dst, t2_so_imm:$src)]> {
1092 let Inst{31-27} = 0b11110;
1094 let Inst{24-21} = 0b0010;
1095 let Inst{20} = ?; // The S bit.
1096 let Inst{19-16} = 0b1111; // Rn
1100 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1101 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1102 "movw", "\t$dst, $src",
1103 [(set GPR:$dst, imm0_65535:$src)]> {
1104 let Inst{31-27} = 0b11110;
1106 let Inst{24-21} = 0b0010;
1107 let Inst{20} = 0; // The S bit.
1111 let Constraints = "$src = $dst" in
1112 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
1113 "movt", "\t$dst, $imm",
1115 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
1116 let Inst{31-27} = 0b11110;
1118 let Inst{24-21} = 0b0110;
1119 let Inst{20} = 0; // The S bit.
1123 def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
1125 //===----------------------------------------------------------------------===//
1126 // Extend Instructions.
1131 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1132 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1133 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1134 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1135 defm t2SXTB16 : T2I_unary_rrot_DO<0b010, "sxtb16">;
1137 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1138 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1139 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1140 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1141 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1143 // TODO: SXT(A){B|H}16 - done for disassembly only
1147 let AddedComplexity = 16 in {
1148 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1149 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1150 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1151 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1152 defm t2UXTB16 : T2I_unary_rrot<0b011, "uxtb16",
1153 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1155 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1156 (t2UXTB16r_rot GPR:$Src, 24)>;
1157 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1158 (t2UXTB16r_rot GPR:$Src, 8)>;
1160 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1161 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1162 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1163 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1164 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1167 //===----------------------------------------------------------------------===//
1168 // Arithmetic Instructions.
1171 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1172 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1173 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1174 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1176 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1177 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1178 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1179 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1180 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1182 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1183 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1184 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1185 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1186 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1187 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1188 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1189 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1192 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1193 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1194 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1195 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1197 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1198 let AddedComplexity = 1 in
1199 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1200 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1201 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1202 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1203 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1204 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1206 // Select Bytes -- for disassembly only
1208 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1209 "\t$dst, $a, $b", []> {
1210 let Inst{31-27} = 0b11111;
1211 let Inst{26-24} = 0b010;
1213 let Inst{22-20} = 0b010;
1214 let Inst{15-12} = 0b1111;
1216 let Inst{6-4} = 0b000;
1219 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1220 // And Miscellaneous operations -- for disassembly only
1221 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc>
1222 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
1223 "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> {
1224 let Inst{31-27} = 0b11111;
1225 let Inst{26-23} = 0b0101;
1226 let Inst{22-20} = op22_20;
1227 let Inst{15-12} = 0b1111;
1228 let Inst{7-4} = op7_4;
1231 // Saturating add/subtract -- for disassembly only
1233 def t2QADD : T2I_pam<0b000, 0b1000, "qadd">;
1234 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1235 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1236 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1237 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1238 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1239 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1240 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">;
1241 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1242 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1243 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1244 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1245 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1246 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1247 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1248 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1250 // Signed/Unsigned add/subtract -- for disassembly only
1252 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1253 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1254 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1255 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1256 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1257 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1258 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1259 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1260 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1261 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1262 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1263 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1265 // Signed/Unsigned halving add/subtract -- for disassembly only
1267 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1268 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1269 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1270 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1271 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1272 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1273 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1274 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1275 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1276 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1277 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1278 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1280 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1282 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1283 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1284 let Inst{15-12} = 0b1111;
1286 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst),
1287 (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8",
1288 "\t$dst, $a, $b, $acc", []>;
1290 // Signed/Unsigned saturate -- for disassembly only
1292 def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1293 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1294 [/* For disassembly only; pattern left blank */]> {
1295 let Inst{31-27} = 0b11110;
1296 let Inst{25-22} = 0b1100;
1299 let Inst{21} = 0; // sh = '0'
1302 def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1303 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1304 [/* For disassembly only; pattern left blank */]> {
1305 let Inst{31-27} = 0b11110;
1306 let Inst{25-22} = 0b1100;
1309 let Inst{21} = 1; // sh = '1'
1312 def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1313 "ssat16", "\t$dst, $bit_pos, $a",
1314 [/* For disassembly only; pattern left blank */]> {
1315 let Inst{31-27} = 0b11110;
1316 let Inst{25-22} = 0b1100;
1319 let Inst{21} = 1; // sh = '1'
1320 let Inst{14-12} = 0b000; // imm3 = '000'
1321 let Inst{7-6} = 0b00; // imm2 = '00'
1324 def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1325 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1326 [/* For disassembly only; pattern left blank */]> {
1327 let Inst{31-27} = 0b11110;
1328 let Inst{25-22} = 0b1110;
1331 let Inst{21} = 0; // sh = '0'
1334 def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1335 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1336 [/* For disassembly only; pattern left blank */]> {
1337 let Inst{31-27} = 0b11110;
1338 let Inst{25-22} = 0b1110;
1341 let Inst{21} = 1; // sh = '1'
1344 def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1345 "usat16", "\t$dst, $bit_pos, $a",
1346 [/* For disassembly only; pattern left blank */]> {
1347 let Inst{31-27} = 0b11110;
1348 let Inst{25-22} = 0b1110;
1351 let Inst{21} = 1; // sh = '1'
1352 let Inst{14-12} = 0b000; // imm3 = '000'
1353 let Inst{7-6} = 0b00; // imm2 = '00'
1356 //===----------------------------------------------------------------------===//
1357 // Shift and rotate Instructions.
1360 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1361 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1362 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1363 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1365 let Uses = [CPSR] in {
1366 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1367 "rrx", "\t$dst, $src",
1368 [(set GPR:$dst, (ARMrrx GPR:$src))]> {
1369 let Inst{31-27} = 0b11101;
1370 let Inst{26-25} = 0b01;
1371 let Inst{24-21} = 0b0010;
1372 let Inst{20} = ?; // The S bit.
1373 let Inst{19-16} = 0b1111; // Rn
1374 let Inst{14-12} = 0b000;
1375 let Inst{7-4} = 0b0011;
1379 let Defs = [CPSR] in {
1380 def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1381 "lsrs.w\t$dst, $src, #1",
1382 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
1383 let Inst{31-27} = 0b11101;
1384 let Inst{26-25} = 0b01;
1385 let Inst{24-21} = 0b0010;
1386 let Inst{20} = 1; // The S bit.
1387 let Inst{19-16} = 0b1111; // Rn
1388 let Inst{5-4} = 0b01; // Shift type.
1389 // Shift amount = Inst{14-12:7-6} = 1.
1390 let Inst{14-12} = 0b000;
1391 let Inst{7-6} = 0b01;
1393 def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1394 "asrs.w\t$dst, $src, #1",
1395 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
1396 let Inst{31-27} = 0b11101;
1397 let Inst{26-25} = 0b01;
1398 let Inst{24-21} = 0b0010;
1399 let Inst{20} = 1; // The S bit.
1400 let Inst{19-16} = 0b1111; // Rn
1401 let Inst{5-4} = 0b10; // Shift type.
1402 // Shift amount = Inst{14-12:7-6} = 1.
1403 let Inst{14-12} = 0b000;
1404 let Inst{7-6} = 0b01;
1408 //===----------------------------------------------------------------------===//
1409 // Bitwise Instructions.
1412 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1413 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1414 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1415 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1416 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1417 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1419 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1420 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1422 let Constraints = "$src = $dst" in
1423 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1424 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1425 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
1426 let Inst{31-27} = 0b11110;
1428 let Inst{24-20} = 0b10110;
1429 let Inst{19-16} = 0b1111; // Rn
1433 def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1434 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1435 let Inst{31-27} = 0b11110;
1437 let Inst{24-20} = 0b10100;
1441 def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1442 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1443 let Inst{31-27} = 0b11110;
1445 let Inst{24-20} = 0b11100;
1449 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1450 // Added for disassembler with the pattern field purposely left blank.
1451 // FIXME: Utilize this instruction in codgen.
1452 def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1453 IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> {
1454 let Inst{31-27} = 0b11110;
1456 let Inst{24-20} = 0b10110;
1460 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1463 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1464 let AddedComplexity = 1 in
1465 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1468 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
1469 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
1471 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1472 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
1473 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
1474 Requires<[IsThumb2]>;
1476 def : T2Pat<(t2_so_imm_not:$src),
1477 (t2MVNi t2_so_imm_not:$src)>;
1479 //===----------------------------------------------------------------------===//
1480 // Multiply Instructions.
1482 let isCommutable = 1 in
1483 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1484 "mul", "\t$dst, $a, $b",
1485 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
1486 let Inst{31-27} = 0b11111;
1487 let Inst{26-23} = 0b0110;
1488 let Inst{22-20} = 0b000;
1489 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1490 let Inst{7-4} = 0b0000; // Multiply
1493 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1494 "mla", "\t$dst, $a, $b, $c",
1495 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
1496 let Inst{31-27} = 0b11111;
1497 let Inst{26-23} = 0b0110;
1498 let Inst{22-20} = 0b000;
1499 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1500 let Inst{7-4} = 0b0000; // Multiply
1503 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1504 "mls", "\t$dst, $a, $b, $c",
1505 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
1506 let Inst{31-27} = 0b11111;
1507 let Inst{26-23} = 0b0110;
1508 let Inst{22-20} = 0b000;
1509 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1510 let Inst{7-4} = 0b0001; // Multiply and Subtract
1513 // Extra precision multiplies with low / high results
1514 let neverHasSideEffects = 1 in {
1515 let isCommutable = 1 in {
1516 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1517 "smull", "\t$ldst, $hdst, $a, $b", []> {
1518 let Inst{31-27} = 0b11111;
1519 let Inst{26-23} = 0b0111;
1520 let Inst{22-20} = 0b000;
1521 let Inst{7-4} = 0b0000;
1524 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1525 "umull", "\t$ldst, $hdst, $a, $b", []> {
1526 let Inst{31-27} = 0b11111;
1527 let Inst{26-23} = 0b0111;
1528 let Inst{22-20} = 0b010;
1529 let Inst{7-4} = 0b0000;
1533 // Multiply + accumulate
1534 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1535 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1536 let Inst{31-27} = 0b11111;
1537 let Inst{26-23} = 0b0111;
1538 let Inst{22-20} = 0b100;
1539 let Inst{7-4} = 0b0000;
1542 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1543 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1544 let Inst{31-27} = 0b11111;
1545 let Inst{26-23} = 0b0111;
1546 let Inst{22-20} = 0b110;
1547 let Inst{7-4} = 0b0000;
1550 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1551 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1552 let Inst{31-27} = 0b11111;
1553 let Inst{26-23} = 0b0111;
1554 let Inst{22-20} = 0b110;
1555 let Inst{7-4} = 0b0110;
1557 } // neverHasSideEffects
1559 // Rounding variants of the below included for disassembly only
1561 // Most significant word multiply
1562 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1563 "smmul", "\t$dst, $a, $b",
1564 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
1565 let Inst{31-27} = 0b11111;
1566 let Inst{26-23} = 0b0110;
1567 let Inst{22-20} = 0b101;
1568 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1569 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1572 def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1573 "smmulr", "\t$dst, $a, $b", []> {
1574 let Inst{31-27} = 0b11111;
1575 let Inst{26-23} = 0b0110;
1576 let Inst{22-20} = 0b101;
1577 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1578 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1581 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1582 "smmla", "\t$dst, $a, $b, $c",
1583 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
1584 let Inst{31-27} = 0b11111;
1585 let Inst{26-23} = 0b0110;
1586 let Inst{22-20} = 0b101;
1587 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1588 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1591 def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1592 "smmlar", "\t$dst, $a, $b, $c", []> {
1593 let Inst{31-27} = 0b11111;
1594 let Inst{26-23} = 0b0110;
1595 let Inst{22-20} = 0b101;
1596 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1597 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1600 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1601 "smmls", "\t$dst, $a, $b, $c",
1602 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
1603 let Inst{31-27} = 0b11111;
1604 let Inst{26-23} = 0b0110;
1605 let Inst{22-20} = 0b110;
1606 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1607 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1610 def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1611 "smmlsr", "\t$dst, $a, $b, $c", []> {
1612 let Inst{31-27} = 0b11111;
1613 let Inst{26-23} = 0b0110;
1614 let Inst{22-20} = 0b110;
1615 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1616 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1619 multiclass T2I_smul<string opc, PatFrag opnode> {
1620 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1621 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1622 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1623 (sext_inreg GPR:$b, i16)))]> {
1624 let Inst{31-27} = 0b11111;
1625 let Inst{26-23} = 0b0110;
1626 let Inst{22-20} = 0b001;
1627 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1628 let Inst{7-6} = 0b00;
1629 let Inst{5-4} = 0b00;
1632 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1633 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1634 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1635 (sra GPR:$b, (i32 16))))]> {
1636 let Inst{31-27} = 0b11111;
1637 let Inst{26-23} = 0b0110;
1638 let Inst{22-20} = 0b001;
1639 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1640 let Inst{7-6} = 0b00;
1641 let Inst{5-4} = 0b01;
1644 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1645 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1646 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1647 (sext_inreg GPR:$b, i16)))]> {
1648 let Inst{31-27} = 0b11111;
1649 let Inst{26-23} = 0b0110;
1650 let Inst{22-20} = 0b001;
1651 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1652 let Inst{7-6} = 0b00;
1653 let Inst{5-4} = 0b10;
1656 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1657 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1658 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1659 (sra GPR:$b, (i32 16))))]> {
1660 let Inst{31-27} = 0b11111;
1661 let Inst{26-23} = 0b0110;
1662 let Inst{22-20} = 0b001;
1663 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1664 let Inst{7-6} = 0b00;
1665 let Inst{5-4} = 0b11;
1668 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1669 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1670 [(set GPR:$dst, (sra (opnode GPR:$a,
1671 (sext_inreg GPR:$b, i16)), (i32 16)))]> {
1672 let Inst{31-27} = 0b11111;
1673 let Inst{26-23} = 0b0110;
1674 let Inst{22-20} = 0b011;
1675 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1676 let Inst{7-6} = 0b00;
1677 let Inst{5-4} = 0b00;
1680 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1681 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1682 [(set GPR:$dst, (sra (opnode GPR:$a,
1683 (sra GPR:$b, (i32 16))), (i32 16)))]> {
1684 let Inst{31-27} = 0b11111;
1685 let Inst{26-23} = 0b0110;
1686 let Inst{22-20} = 0b011;
1687 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1688 let Inst{7-6} = 0b00;
1689 let Inst{5-4} = 0b01;
1694 multiclass T2I_smla<string opc, PatFrag opnode> {
1695 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1696 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1697 [(set GPR:$dst, (add GPR:$acc,
1698 (opnode (sext_inreg GPR:$a, i16),
1699 (sext_inreg GPR:$b, i16))))]> {
1700 let Inst{31-27} = 0b11111;
1701 let Inst{26-23} = 0b0110;
1702 let Inst{22-20} = 0b001;
1703 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1704 let Inst{7-6} = 0b00;
1705 let Inst{5-4} = 0b00;
1708 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1709 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1710 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1711 (sra GPR:$b, (i32 16)))))]> {
1712 let Inst{31-27} = 0b11111;
1713 let Inst{26-23} = 0b0110;
1714 let Inst{22-20} = 0b001;
1715 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1716 let Inst{7-6} = 0b00;
1717 let Inst{5-4} = 0b01;
1720 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1721 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1722 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1723 (sext_inreg GPR:$b, i16))))]> {
1724 let Inst{31-27} = 0b11111;
1725 let Inst{26-23} = 0b0110;
1726 let Inst{22-20} = 0b001;
1727 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1728 let Inst{7-6} = 0b00;
1729 let Inst{5-4} = 0b10;
1732 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1733 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1734 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1735 (sra GPR:$b, (i32 16)))))]> {
1736 let Inst{31-27} = 0b11111;
1737 let Inst{26-23} = 0b0110;
1738 let Inst{22-20} = 0b001;
1739 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1740 let Inst{7-6} = 0b00;
1741 let Inst{5-4} = 0b11;
1744 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1745 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1746 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1747 (sext_inreg GPR:$b, i16)), (i32 16))))]> {
1748 let Inst{31-27} = 0b11111;
1749 let Inst{26-23} = 0b0110;
1750 let Inst{22-20} = 0b011;
1751 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1752 let Inst{7-6} = 0b00;
1753 let Inst{5-4} = 0b00;
1756 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1757 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1758 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1759 (sra GPR:$b, (i32 16))), (i32 16))))]> {
1760 let Inst{31-27} = 0b11111;
1761 let Inst{26-23} = 0b0110;
1762 let Inst{22-20} = 0b011;
1763 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1764 let Inst{7-6} = 0b00;
1765 let Inst{5-4} = 0b01;
1769 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1770 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1772 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
1773 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst),
1774 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1775 [/* For disassembly only; pattern left blank */]>;
1776 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst),
1777 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1778 [/* For disassembly only; pattern left blank */]>;
1779 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst),
1780 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
1781 [/* For disassembly only; pattern left blank */]>;
1782 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst),
1783 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
1784 [/* For disassembly only; pattern left blank */]>;
1786 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1787 // These are for disassembly only.
1789 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1790 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
1791 let Inst{15-12} = 0b1111;
1793 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1794 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
1795 let Inst{15-12} = 0b1111;
1797 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1798 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
1799 let Inst{15-12} = 0b1111;
1801 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1802 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
1803 let Inst{15-12} = 0b1111;
1805 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst),
1806 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad",
1807 "\t$dst, $a, $b, $acc", []>;
1808 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst),
1809 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx",
1810 "\t$dst, $a, $b, $acc", []>;
1811 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst),
1812 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd",
1813 "\t$dst, $a, $b, $acc", []>;
1814 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst),
1815 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx",
1816 "\t$dst, $a, $b, $acc", []>;
1817 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst),
1818 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald",
1819 "\t$ldst, $hdst, $a, $b", []>;
1820 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst),
1821 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx",
1822 "\t$ldst, $hdst, $a, $b", []>;
1823 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst),
1824 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld",
1825 "\t$ldst, $hdst, $a, $b", []>;
1826 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst),
1827 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx",
1828 "\t$ldst, $hdst, $a, $b", []>;
1830 //===----------------------------------------------------------------------===//
1831 // Misc. Arithmetic Instructions.
1834 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
1835 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1836 : T2I<oops, iops, itin, opc, asm, pattern> {
1837 let Inst{31-27} = 0b11111;
1838 let Inst{26-22} = 0b01010;
1839 let Inst{21-20} = op1;
1840 let Inst{15-12} = 0b1111;
1841 let Inst{7-6} = 0b10;
1842 let Inst{5-4} = op2;
1845 def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1846 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
1848 def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1849 "rbit", "\t$dst, $src",
1850 [(set GPR:$dst, (ARMrbit GPR:$src))]>;
1852 def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1853 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
1855 def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1856 "rev16", ".w\t$dst, $src",
1858 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1859 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1860 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1861 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
1863 def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1864 "revsh", ".w\t$dst, $src",
1867 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1868 (shl GPR:$src, (i32 8))), i16))]>;
1870 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1871 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
1872 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1873 (and (shl GPR:$src2, (i32 imm:$shamt)),
1875 let Inst{31-27} = 0b11101;
1876 let Inst{26-25} = 0b01;
1877 let Inst{24-20} = 0b01100;
1878 let Inst{5} = 0; // BT form
1882 // Alternate cases for PKHBT where identities eliminate some nodes.
1883 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1884 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
1885 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1886 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1888 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1889 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
1890 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1891 (and (sra GPR:$src2, imm16_31:$shamt),
1893 let Inst{31-27} = 0b11101;
1894 let Inst{26-25} = 0b01;
1895 let Inst{24-20} = 0b01100;
1896 let Inst{5} = 1; // TB form
1900 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1901 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1902 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1903 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
1904 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
1905 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1906 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1908 //===----------------------------------------------------------------------===//
1909 // Comparison Instructions...
1912 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
1913 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1914 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
1915 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1917 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
1918 // Compare-to-zero still works out, just not the relationals
1919 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
1920 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1921 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
1922 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1924 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1925 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1927 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1928 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
1930 defm t2TST : T2I_cmp_irs<0b0000, "tst",
1931 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1932 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
1933 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1935 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1936 // Short range conditional branch. Looks awesome for loops. Need to figure
1937 // out how to use this one.
1940 // Conditional moves
1941 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1942 // a two-value operand where a dag node expects two operands. :(
1943 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
1944 "mov", ".w\t$dst, $true",
1945 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1946 RegConstraint<"$false = $dst"> {
1947 let Inst{31-27} = 0b11101;
1948 let Inst{26-25} = 0b01;
1949 let Inst{24-21} = 0b0010;
1950 let Inst{20} = 0; // The S bit.
1951 let Inst{19-16} = 0b1111; // Rn
1952 let Inst{14-12} = 0b000;
1953 let Inst{7-4} = 0b0000;
1956 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1957 IIC_iCMOVi, "mov", ".w\t$dst, $true",
1958 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1959 RegConstraint<"$false = $dst"> {
1960 let Inst{31-27} = 0b11110;
1962 let Inst{24-21} = 0b0010;
1963 let Inst{20} = 0; // The S bit.
1964 let Inst{19-16} = 0b1111; // Rn
1968 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
1969 string opc, string asm, list<dag> pattern>
1970 : T2I<oops, iops, itin, opc, asm, pattern> {
1971 let Inst{31-27} = 0b11101;
1972 let Inst{26-25} = 0b01;
1973 let Inst{24-21} = 0b0010;
1974 let Inst{20} = 0; // The S bit.
1975 let Inst{19-16} = 0b1111; // Rn
1976 let Inst{5-4} = opcod; // Shift type.
1978 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
1979 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1980 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
1981 RegConstraint<"$false = $dst">;
1982 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
1983 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1984 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
1985 RegConstraint<"$false = $dst">;
1986 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
1987 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1988 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
1989 RegConstraint<"$false = $dst">;
1990 def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
1991 (ins GPR:$false, GPR:$true, i32imm:$rhs),
1992 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
1993 RegConstraint<"$false = $dst">;
1995 //===----------------------------------------------------------------------===//
1996 // Atomic operations intrinsics
1999 // memory barriers protect the atomic sequences
2000 let hasSideEffects = 1 in {
2001 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
2002 Pseudo, NoItinerary,
2004 [(ARMMemBarrierV7)]>,
2005 Requires<[IsThumb2]> {
2006 let Inst{31-4} = 0xF3BF8F5;
2007 // FIXME: add support for options other than a full system DMB
2008 let Inst{3-0} = 0b1111;
2011 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
2012 Pseudo, NoItinerary,
2014 [(ARMSyncBarrierV7)]>,
2015 Requires<[IsThumb2]> {
2016 let Inst{31-4} = 0xF3BF8F4;
2017 // FIXME: add support for options other than a full system DSB
2018 let Inst{3-0} = 0b1111;
2022 // Helper class for multiclass T2MemB -- for disassembly only
2023 class T2I_memb<string opc, string asm>
2024 : T2I<(outs), (ins), NoItinerary, opc, asm,
2025 [/* For disassembly only; pattern left blank */]>,
2026 Requires<[IsThumb2, HasV7]> {
2027 let Inst{31-20} = 0xf3b;
2028 let Inst{15-14} = 0b10;
2032 multiclass T2MemB<bits<4> op7_4, string opc> {
2034 def st : T2I_memb<opc, "\tst"> {
2035 let Inst{7-4} = op7_4;
2036 let Inst{3-0} = 0b1110;
2039 def ish : T2I_memb<opc, "\tish"> {
2040 let Inst{7-4} = op7_4;
2041 let Inst{3-0} = 0b1011;
2044 def ishst : T2I_memb<opc, "\tishst"> {
2045 let Inst{7-4} = op7_4;
2046 let Inst{3-0} = 0b1010;
2049 def nsh : T2I_memb<opc, "\tnsh"> {
2050 let Inst{7-4} = op7_4;
2051 let Inst{3-0} = 0b0111;
2054 def nshst : T2I_memb<opc, "\tnshst"> {
2055 let Inst{7-4} = op7_4;
2056 let Inst{3-0} = 0b0110;
2059 def osh : T2I_memb<opc, "\tosh"> {
2060 let Inst{7-4} = op7_4;
2061 let Inst{3-0} = 0b0011;
2064 def oshst : T2I_memb<opc, "\toshst"> {
2065 let Inst{7-4} = op7_4;
2066 let Inst{3-0} = 0b0010;
2070 // These DMB variants are for disassembly only.
2071 defm t2DMB : T2MemB<0b0101, "dmb">;
2073 // These DSB variants are for disassembly only.
2074 defm t2DSB : T2MemB<0b0100, "dsb">;
2076 // ISB has only full system option -- for disassembly only
2077 def t2ISBsy : T2I_memb<"isb", ""> {
2078 let Inst{7-4} = 0b0110;
2079 let Inst{3-0} = 0b1111;
2082 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2083 InstrItinClass itin, string opc, string asm, string cstr,
2084 list<dag> pattern, bits<4> rt2 = 0b1111>
2085 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2086 let Inst{31-27} = 0b11101;
2087 let Inst{26-20} = 0b0001101;
2088 let Inst{11-8} = rt2;
2089 let Inst{7-6} = 0b01;
2090 let Inst{5-4} = opcod;
2091 let Inst{3-0} = 0b1111;
2093 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2094 InstrItinClass itin, string opc, string asm, string cstr,
2095 list<dag> pattern, bits<4> rt2 = 0b1111>
2096 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2097 let Inst{31-27} = 0b11101;
2098 let Inst{26-20} = 0b0001100;
2099 let Inst{11-8} = rt2;
2100 let Inst{7-6} = 0b01;
2101 let Inst{5-4} = opcod;
2104 let mayLoad = 1 in {
2105 def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2106 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2108 def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2109 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2111 def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2112 Size4Bytes, NoItinerary,
2113 "ldrex", "\t$dest, [$ptr]", "",
2115 let Inst{31-27} = 0b11101;
2116 let Inst{26-20} = 0b0000101;
2117 let Inst{11-8} = 0b1111;
2118 let Inst{7-0} = 0b00000000; // imm8 = 0
2120 def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2121 AddrModeNone, Size4Bytes, NoItinerary,
2122 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2126 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2127 def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2128 AddrModeNone, Size4Bytes, NoItinerary,
2129 "strexb", "\t$success, $src, [$ptr]", "", []>;
2130 def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2131 AddrModeNone, Size4Bytes, NoItinerary,
2132 "strexh", "\t$success, $src, [$ptr]", "", []>;
2133 def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2134 AddrModeNone, Size4Bytes, NoItinerary,
2135 "strex", "\t$success, $src, [$ptr]", "",
2137 let Inst{31-27} = 0b11101;
2138 let Inst{26-20} = 0b0000100;
2139 let Inst{7-0} = 0b00000000; // imm8 = 0
2141 def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
2142 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2143 AddrModeNone, Size4Bytes, NoItinerary,
2144 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2148 // Clear-Exclusive is for disassembly only.
2149 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2150 [/* For disassembly only; pattern left blank */]>,
2151 Requires<[IsARM, HasV7]> {
2152 let Inst{31-20} = 0xf3b;
2153 let Inst{15-14} = 0b10;
2155 let Inst{7-4} = 0b0010;
2158 //===----------------------------------------------------------------------===//
2162 // __aeabi_read_tp preserves the registers r1-r3.
2164 Defs = [R0, R12, LR, CPSR] in {
2165 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2166 "bl\t__aeabi_read_tp",
2167 [(set R0, ARMthread_pointer)]> {
2168 let Inst{31-27} = 0b11110;
2169 let Inst{15-14} = 0b11;
2174 //===----------------------------------------------------------------------===//
2175 // SJLJ Exception handling intrinsics
2176 // eh_sjlj_setjmp() is an instruction sequence to store the return
2177 // address and save #0 in R0 for the non-longjmp case.
2178 // Since by its nature we may be coming from some other function to get
2179 // here, and we're using the stack frame for the containing function to
2180 // save/restore registers, we can't keep anything live in regs across
2181 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2182 // when we get here from a longjmp(). We force everthing out of registers
2183 // except for our own input by listing the relevant registers in Defs. By
2184 // doing so, we also cause the prologue/epilogue code to actively preserve
2185 // all of the callee-saved resgisters, which is exactly what we want.
2186 // The current SP is passed in $val, and we reuse the reg as a scratch.
2188 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2189 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2190 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2192 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2193 AddrModeNone, SizeSpecial, NoItinerary,
2194 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
2196 "\tadds\t$val, #9\n"
2197 "\tstr\t$val, [$src, #4]\n"
2200 "\tmovs\tr0, #1\t@ end eh.setjmp\n"
2202 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>;
2207 //===----------------------------------------------------------------------===//
2208 // Control-Flow Instructions
2211 // FIXME: remove when we have a way to marking a MI with these properties.
2212 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2214 // FIXME: Should pc be an implicit operand like PICADD, etc?
2215 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2216 hasExtraDefRegAllocReq = 1 in
2217 def t2LDM_RET : T2XI<(outs),
2218 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
2219 IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb",
2221 let Inst{31-27} = 0b11101;
2222 let Inst{26-25} = 0b00;
2223 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2225 let Inst{21} = ?; // The W bit.
2226 let Inst{20} = 1; // Load
2229 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2230 let isPredicable = 1 in
2231 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2233 [(br bb:$target)]> {
2234 let Inst{31-27} = 0b11110;
2235 let Inst{15-14} = 0b10;
2239 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2242 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2243 IIC_Br, "mov\tpc, $target\n$jt",
2244 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2245 let Inst{31-27} = 0b11101;
2246 let Inst{26-20} = 0b0100100;
2247 let Inst{19-16} = 0b1111;
2248 let Inst{14-12} = 0b000;
2249 let Inst{11-8} = 0b1111; // Rd = pc
2250 let Inst{7-4} = 0b0000;
2253 // FIXME: Add a non-pc based case that can be predicated.
2256 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2257 IIC_Br, "tbb\t$index\n$jt", []> {
2258 let Inst{31-27} = 0b11101;
2259 let Inst{26-20} = 0b0001101;
2260 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2261 let Inst{15-8} = 0b11110000;
2262 let Inst{7-4} = 0b0000; // B form
2267 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2268 IIC_Br, "tbh\t$index\n$jt", []> {
2269 let Inst{31-27} = 0b11101;
2270 let Inst{26-20} = 0b0001101;
2271 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2272 let Inst{15-8} = 0b11110000;
2273 let Inst{7-4} = 0b0001; // H form
2276 // Generic versions of the above two instructions, for disassembly only
2278 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2279 "tbb", "\t[$a, $b]", []>{
2280 let Inst{31-27} = 0b11101;
2281 let Inst{26-20} = 0b0001101;
2282 let Inst{15-8} = 0b11110000;
2283 let Inst{7-4} = 0b0000; // B form
2286 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2287 "tbh", "\t[$a, $b, lsl #1]", []> {
2288 let Inst{31-27} = 0b11101;
2289 let Inst{26-20} = 0b0001101;
2290 let Inst{15-8} = 0b11110000;
2291 let Inst{7-4} = 0b0001; // H form
2293 } // isNotDuplicable, isIndirectBranch
2295 } // isBranch, isTerminator, isBarrier
2297 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2298 // a two-value operand where a dag node expects two operands. :(
2299 let isBranch = 1, isTerminator = 1 in
2300 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2302 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2303 let Inst{31-27} = 0b11110;
2304 let Inst{15-14} = 0b10;
2310 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2311 AddrModeNone, Size2Bytes, IIC_iALUx,
2312 "it$mask\t$cc", "", []> {
2313 // 16-bit instruction.
2314 let Inst{31-16} = 0x0000;
2315 let Inst{15-8} = 0b10111111;
2318 // Branch and Exchange Jazelle -- for disassembly only
2320 def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2321 [/* For disassembly only; pattern left blank */]> {
2322 let Inst{31-27} = 0b11110;
2324 let Inst{25-20} = 0b111100;
2325 let Inst{15-14} = 0b10;
2329 // Change Processor State is a system instruction -- for disassembly only.
2330 // The singleton $opt operand contains the following information:
2331 // opt{4-0} = mode from Inst{4-0}
2332 // opt{5} = changemode from Inst{17}
2333 // opt{8-6} = AIF from Inst{8-6}
2334 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2335 def t2CPS : T2XI<(outs),(ins i32imm:$opt), NoItinerary, "cps${opt:cps}",
2336 [/* For disassembly only; pattern left blank */]> {
2337 let Inst{31-27} = 0b11110;
2339 let Inst{25-20} = 0b111010;
2340 let Inst{15-14} = 0b10;
2344 // Secure Monitor Call is a system instruction -- for disassembly only
2345 // Option = Inst{19-16}
2346 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2347 [/* For disassembly only; pattern left blank */]> {
2348 let Inst{31-27} = 0b11110;
2349 let Inst{26-20} = 0b1111111;
2350 let Inst{15-12} = 0b1000;
2353 // Store Return State is a system instruction -- for disassembly only
2354 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2355 [/* For disassembly only; pattern left blank */]> {
2356 let Inst{31-27} = 0b11101;
2357 let Inst{26-20} = 0b0000010; // W = 1
2360 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2361 [/* For disassembly only; pattern left blank */]> {
2362 let Inst{31-27} = 0b11101;
2363 let Inst{26-20} = 0b0000000; // W = 0
2366 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2367 [/* For disassembly only; pattern left blank */]> {
2368 let Inst{31-27} = 0b11101;
2369 let Inst{26-20} = 0b0011010; // W = 1
2372 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2373 [/* For disassembly only; pattern left blank */]> {
2374 let Inst{31-27} = 0b11101;
2375 let Inst{26-20} = 0b0011000; // W = 0
2378 // Return From Exception is a system instruction -- for disassembly only
2379 def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!",
2380 [/* For disassembly only; pattern left blank */]> {
2381 let Inst{31-27} = 0b11101;
2382 let Inst{26-20} = 0b0000011; // W = 1
2385 def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base",
2386 [/* For disassembly only; pattern left blank */]> {
2387 let Inst{31-27} = 0b11101;
2388 let Inst{26-20} = 0b0000001; // W = 0
2391 def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!",
2392 [/* For disassembly only; pattern left blank */]> {
2393 let Inst{31-27} = 0b11101;
2394 let Inst{26-20} = 0b0011011; // W = 1
2397 def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base",
2398 [/* For disassembly only; pattern left blank */]> {
2399 let Inst{31-27} = 0b11101;
2400 let Inst{26-20} = 0b0011001; // W = 0
2403 //===----------------------------------------------------------------------===//
2404 // Non-Instruction Patterns
2407 // Two piece so_imms.
2408 def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
2409 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2410 (t2_so_imm2part_2 imm:$RHS))>;
2411 def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
2412 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2413 (t2_so_imm2part_2 imm:$RHS))>;
2414 def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
2415 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2416 (t2_so_imm2part_2 imm:$RHS))>;
2417 def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS),
2418 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2419 (t2_so_neg_imm2part_2 imm:$RHS))>;
2421 // 32-bit immediate using movw + movt.
2422 // This is a single pseudo instruction to make it re-materializable. Remove
2423 // when we can do generalized remat.
2424 let isReMaterializable = 1 in
2425 def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2426 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2427 [(set GPR:$dst, (i32 imm:$src))]>;
2429 // ConstantPool, GlobalAddress, and JumpTable
2430 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2431 Requires<[IsThumb2, DontUseMovt]>;
2432 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2433 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2434 Requires<[IsThumb2, UseMovt]>;
2436 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2437 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2439 // Pseudo instruction that combines ldr from constpool and add pc. This should
2440 // be expanded into two instructions late to allow if-conversion and
2442 let canFoldAsLoad = 1, isReMaterializable = 1 in
2443 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2444 NoItinerary, "@ ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2445 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2447 Requires<[IsThumb2]>;
2449 //===----------------------------------------------------------------------===//
2450 // Move between special register and ARM core register -- for disassembly only
2454 def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2455 [/* For disassembly only; pattern left blank */]> {
2456 let Inst{31-27} = 0b11110;
2458 let Inst{25-21} = 0b11111;
2459 let Inst{20} = 0; // The R bit.
2460 let Inst{15-14} = 0b10;
2465 def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2466 [/* For disassembly only; pattern left blank */]> {
2467 let Inst{31-27} = 0b11110;
2469 let Inst{25-21} = 0b11111;
2470 let Inst{20} = 1; // The R bit.
2471 let Inst{15-14} = 0b10;
2475 // FIXME: mask is ignored for the time being.
2477 def t2MSR : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tcpsr, $src",
2478 [/* For disassembly only; pattern left blank */]> {
2479 let Inst{31-27} = 0b11110;
2481 let Inst{25-21} = 0b11100;
2482 let Inst{20} = 0; // The R bit.
2483 let Inst{15-14} = 0b10;
2487 // FIXME: mask is ignored for the time being.
2489 def t2MSRsys : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tspsr, $src",
2490 [/* For disassembly only; pattern left blank */]> {
2491 let Inst{31-27} = 0b11110;
2493 let Inst{25-21} = 0b11100;
2494 let Inst{20} = 1; // The R bit.
2495 let Inst{15-14} = 0b10;