1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
73 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
74 // to get the first/second pieces.
75 def t2_so_imm2part : Operand<i32>,
77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
81 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
83 return CurDAG->getTargetConstant(V, MVT::i32);
86 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
88 return CurDAG->getTargetConstant(V, MVT::i32);
91 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
96 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
98 return CurDAG->getTargetConstant(V, MVT::i32);
101 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
107 def imm1_31 : PatLeaf<(i32 imm), [{
108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
111 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
112 def imm0_4095 : Operand<i32>,
113 PatLeaf<(i32 imm), [{
114 return (uint32_t)N->getZExtValue() < 4096;
117 def imm0_4095_neg : PatLeaf<(i32 imm), [{
118 return (uint32_t)(-N->getZExtValue()) < 4096;
121 def imm0_255_neg : PatLeaf<(i32 imm), [{
122 return (uint32_t)(-N->getZExtValue()) < 255;
125 // Define Thumb2 specific addressing modes.
127 // t2addrmode_imm12 := reg + imm12
128 def t2addrmode_imm12 : Operand<i32>,
129 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
130 let PrintMethod = "printT2AddrModeImm12Operand";
131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
134 // t2addrmode_imm8 := reg - imm8
135 def t2addrmode_imm8 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137 let PrintMethod = "printT2AddrModeImm8Operand";
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141 def t2am_imm8_offset : Operand<i32>,
142 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
143 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
147 def t2addrmode_imm8s4 : Operand<i32>,
148 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
149 let PrintMethod = "printT2AddrModeImm8s4Operand";
150 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
153 // t2addrmode_so_reg := reg + (reg << imm2)
154 def t2addrmode_so_reg : Operand<i32>,
155 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
156 let PrintMethod = "printT2AddrModeSoRegOperand";
157 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
161 //===----------------------------------------------------------------------===//
162 // Multiclass helpers...
165 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
166 /// unary operation that produces a value. These are predicable and can be
167 /// changed to modify CPSR.
168 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
169 bit Cheap = 0, bit ReMat = 0> {
171 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
173 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
174 let isAsCheapAsAMove = Cheap;
175 let isReMaterializable = ReMat;
176 let Inst{31-27} = 0b11110;
178 let Inst{24-21} = opcod;
179 let Inst{20} = ?; // The S bit.
180 let Inst{19-16} = 0b1111; // Rn
184 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
185 opc, ".w\t$dst, $src",
186 [(set GPR:$dst, (opnode GPR:$src))]> {
187 let Inst{31-27} = 0b11101;
188 let Inst{26-25} = 0b01;
189 let Inst{24-21} = opcod;
190 let Inst{20} = ?; // The S bit.
191 let Inst{19-16} = 0b1111; // Rn
192 let Inst{14-12} = 0b000; // imm3
193 let Inst{7-6} = 0b00; // imm2
194 let Inst{5-4} = 0b00; // type
197 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
198 opc, ".w\t$dst, $src",
199 [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
200 let Inst{31-27} = 0b11101;
201 let Inst{26-25} = 0b01;
202 let Inst{24-21} = opcod;
203 let Inst{20} = ?; // The S bit.
204 let Inst{19-16} = 0b1111; // Rn
208 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
209 // binary operation that produces a value. These are predicable and can be
210 /// changed to modify CPSR.
211 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
212 bit Commutable = 0, string wide =""> {
214 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
215 opc, "\t$dst, $lhs, $rhs",
216 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
217 let Inst{31-27} = 0b11110;
219 let Inst{24-21} = opcod;
220 let Inst{20} = ?; // The S bit.
224 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
225 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
226 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
227 let isCommutable = Commutable;
228 let Inst{31-27} = 0b11101;
229 let Inst{26-25} = 0b01;
230 let Inst{24-21} = opcod;
231 let Inst{20} = ?; // The S bit.
232 let Inst{14-12} = 0b000; // imm3
233 let Inst{7-6} = 0b00; // imm2
234 let Inst{5-4} = 0b00; // type
237 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
238 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
239 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
240 let Inst{31-27} = 0b11101;
241 let Inst{26-25} = 0b01;
242 let Inst{24-21} = opcod;
243 let Inst{20} = ?; // The S bit.
247 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
248 // the ".w" prefix to indicate that they are wide.
249 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
250 bit Commutable = 0> :
251 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
253 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
254 /// reversed. It doesn't define the 'rr' form since it's handled by its
255 /// T2I_bin_irs counterpart.
256 multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
258 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
259 opc, ".w\t$dst, $rhs, $lhs",
260 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
261 let Inst{31-27} = 0b11110;
263 let Inst{24-21} = opcod;
264 let Inst{20} = 0; // The S bit.
268 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
269 opc, "\t$dst, $rhs, $lhs",
270 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
271 let Inst{31-27} = 0b11101;
272 let Inst{26-25} = 0b01;
273 let Inst{24-21} = opcod;
274 let Inst{20} = 0; // The S bit.
278 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
279 /// instruction modifies the CPSR register.
280 let Defs = [CPSR] in {
281 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
282 bit Commutable = 0> {
284 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
285 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
286 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
287 let Inst{31-27} = 0b11110;
289 let Inst{24-21} = opcod;
290 let Inst{20} = 1; // The S bit.
294 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
295 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
296 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
297 let isCommutable = Commutable;
298 let Inst{31-27} = 0b11101;
299 let Inst{26-25} = 0b01;
300 let Inst{24-21} = opcod;
301 let Inst{20} = 1; // The S bit.
302 let Inst{14-12} = 0b000; // imm3
303 let Inst{7-6} = 0b00; // imm2
304 let Inst{5-4} = 0b00; // type
307 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
308 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
309 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
310 let Inst{31-27} = 0b11101;
311 let Inst{26-25} = 0b01;
312 let Inst{24-21} = opcod;
313 let Inst{20} = 1; // The S bit.
318 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
319 /// patterns for a binary operation that produces a value.
320 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
321 bit Commutable = 0> {
323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
324 opc, ".w\t$dst, $lhs, $rhs",
325 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
326 let Inst{31-27} = 0b11110;
329 let Inst{23-21} = op23_21;
330 let Inst{20} = 0; // The S bit.
334 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
335 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
336 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
337 let Inst{31-27} = 0b11110;
340 let Inst{23-21} = op23_21;
341 let Inst{20} = 0; // The S bit.
345 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
346 opc, ".w\t$dst, $lhs, $rhs",
347 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
348 let isCommutable = Commutable;
349 let Inst{31-27} = 0b11101;
350 let Inst{26-25} = 0b01;
352 let Inst{23-21} = op23_21;
353 let Inst{20} = 0; // The S bit.
354 let Inst{14-12} = 0b000; // imm3
355 let Inst{7-6} = 0b00; // imm2
356 let Inst{5-4} = 0b00; // type
359 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
360 opc, ".w\t$dst, $lhs, $rhs",
361 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
362 let Inst{31-27} = 0b11101;
363 let Inst{26-25} = 0b01;
365 let Inst{23-21} = op23_21;
366 let Inst{20} = 0; // The S bit.
370 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
371 /// for a binary operation that produces a value and use the carry
372 /// bit. It's not predicable.
373 let Uses = [CPSR] in {
374 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
375 bit Commutable = 0> {
377 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
378 opc, "\t$dst, $lhs, $rhs",
379 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
380 Requires<[IsThumb2]> {
381 let Inst{31-27} = 0b11110;
383 let Inst{24-21} = opcod;
384 let Inst{20} = 0; // The S bit.
388 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
389 opc, ".w\t$dst, $lhs, $rhs",
390 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
391 Requires<[IsThumb2]> {
392 let isCommutable = Commutable;
393 let Inst{31-27} = 0b11101;
394 let Inst{26-25} = 0b01;
395 let Inst{24-21} = opcod;
396 let Inst{20} = 0; // The S bit.
397 let Inst{14-12} = 0b000; // imm3
398 let Inst{7-6} = 0b00; // imm2
399 let Inst{5-4} = 0b00; // type
402 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
403 opc, ".w\t$dst, $lhs, $rhs",
404 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
405 Requires<[IsThumb2]> {
406 let Inst{31-27} = 0b11101;
407 let Inst{26-25} = 0b01;
408 let Inst{24-21} = opcod;
409 let Inst{20} = 0; // The S bit.
413 // Carry setting variants
414 let Defs = [CPSR] in {
415 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
416 bit Commutable = 0> {
418 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
419 opc, "\t$dst, $lhs, $rhs",
420 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
421 Requires<[IsThumb2]> {
422 let Inst{31-27} = 0b11110;
424 let Inst{24-21} = opcod;
425 let Inst{20} = 1; // The S bit.
429 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
430 opc, ".w\t$dst, $lhs, $rhs",
431 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
432 Requires<[IsThumb2]> {
433 let isCommutable = Commutable;
434 let Inst{31-27} = 0b11101;
435 let Inst{26-25} = 0b01;
436 let Inst{24-21} = opcod;
437 let Inst{20} = 1; // The S bit.
438 let Inst{14-12} = 0b000; // imm3
439 let Inst{7-6} = 0b00; // imm2
440 let Inst{5-4} = 0b00; // type
443 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
444 opc, ".w\t$dst, $lhs, $rhs",
445 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
446 Requires<[IsThumb2]> {
447 let Inst{31-27} = 0b11101;
448 let Inst{26-25} = 0b01;
449 let Inst{24-21} = opcod;
450 let Inst{20} = 1; // The S bit.
456 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
457 let Defs = [CPSR] in {
458 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
460 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
462 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"),
463 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
464 let Inst{31-27} = 0b11110;
466 let Inst{24-21} = opcod;
467 let Inst{20} = 1; // The S bit.
471 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
473 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"),
474 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
475 let Inst{31-27} = 0b11101;
476 let Inst{26-25} = 0b01;
477 let Inst{24-21} = opcod;
478 let Inst{20} = 1; // The S bit.
483 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
484 // rotate operation that produces a value.
485 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
487 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
488 opc, ".w\t$dst, $lhs, $rhs",
489 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
490 let Inst{31-27} = 0b11101;
491 let Inst{26-21} = 0b010010;
492 let Inst{19-16} = 0b1111; // Rn
493 let Inst{5-4} = opcod;
496 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
497 opc, ".w\t$dst, $lhs, $rhs",
498 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
499 let Inst{31-27} = 0b11111;
500 let Inst{26-23} = 0b0100;
501 let Inst{22-21} = opcod;
502 let Inst{15-12} = 0b1111;
503 let Inst{7-4} = 0b0000;
507 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
508 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
509 /// a explicit result, only implicitly set CPSR.
510 let Defs = [CPSR] in {
511 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
513 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
514 opc, ".w\t$lhs, $rhs",
515 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
516 let Inst{31-27} = 0b11110;
518 let Inst{24-21} = opcod;
519 let Inst{20} = 1; // The S bit.
521 let Inst{11-8} = 0b1111; // Rd
524 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
525 opc, ".w\t$lhs, $rhs",
526 [(opnode GPR:$lhs, GPR:$rhs)]> {
527 let Inst{31-27} = 0b11101;
528 let Inst{26-25} = 0b01;
529 let Inst{24-21} = opcod;
530 let Inst{20} = 1; // The S bit.
531 let Inst{14-12} = 0b000; // imm3
532 let Inst{11-8} = 0b1111; // Rd
533 let Inst{7-6} = 0b00; // imm2
534 let Inst{5-4} = 0b00; // type
537 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
538 opc, ".w\t$lhs, $rhs",
539 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
540 let Inst{31-27} = 0b11101;
541 let Inst{26-25} = 0b01;
542 let Inst{24-21} = opcod;
543 let Inst{20} = 1; // The S bit.
544 let Inst{11-8} = 0b1111; // Rd
549 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
550 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
551 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
552 opc, ".w\t$dst, $addr",
553 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
554 let Inst{31-27} = 0b11111;
555 let Inst{26-25} = 0b00;
556 let Inst{24} = signed;
558 let Inst{22-21} = opcod;
559 let Inst{20} = 1; // load
561 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
562 opc, "\t$dst, $addr",
563 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
564 let Inst{31-27} = 0b11111;
565 let Inst{26-25} = 0b00;
566 let Inst{24} = signed;
568 let Inst{22-21} = opcod;
569 let Inst{20} = 1; // load
571 // Offset: index==TRUE, wback==FALSE
572 let Inst{10} = 1; // The P bit.
573 let Inst{8} = 0; // The W bit.
575 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
576 opc, ".w\t$dst, $addr",
577 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
578 let Inst{31-27} = 0b11111;
579 let Inst{26-25} = 0b00;
580 let Inst{24} = signed;
582 let Inst{22-21} = opcod;
583 let Inst{20} = 1; // load
584 let Inst{11-6} = 0b000000;
586 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
587 opc, ".w\t$dst, $addr",
588 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
589 let isReMaterializable = 1;
590 let Inst{31-27} = 0b11111;
591 let Inst{26-25} = 0b00;
592 let Inst{24} = signed;
593 let Inst{23} = ?; // add = (U == '1')
594 let Inst{22-21} = opcod;
595 let Inst{20} = 1; // load
596 let Inst{19-16} = 0b1111; // Rn
600 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
601 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
602 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
603 opc, ".w\t$src, $addr",
604 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
605 let Inst{31-27} = 0b11111;
606 let Inst{26-23} = 0b0001;
607 let Inst{22-21} = opcod;
608 let Inst{20} = 0; // !load
610 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
611 opc, "\t$src, $addr",
612 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
613 let Inst{31-27} = 0b11111;
614 let Inst{26-23} = 0b0000;
615 let Inst{22-21} = opcod;
616 let Inst{20} = 0; // !load
618 // Offset: index==TRUE, wback==FALSE
619 let Inst{10} = 1; // The P bit.
620 let Inst{8} = 0; // The W bit.
622 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
623 opc, ".w\t$src, $addr",
624 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
625 let Inst{31-27} = 0b11111;
626 let Inst{26-23} = 0b0000;
627 let Inst{22-21} = opcod;
628 let Inst{20} = 0; // !load
629 let Inst{11-6} = 0b000000;
633 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
634 /// register and one whose operand is a register rotated by 8/16/24.
635 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
636 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
637 opc, ".w\t$dst, $src",
638 [(set GPR:$dst, (opnode GPR:$src))]> {
639 let Inst{31-27} = 0b11111;
640 let Inst{26-23} = 0b0100;
641 let Inst{22-20} = opcod;
642 let Inst{19-16} = 0b1111; // Rn
643 let Inst{15-12} = 0b1111;
645 let Inst{5-4} = 0b00; // rotate
647 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
648 opc, ".w\t$dst, $src, ror $rot",
649 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
650 let Inst{31-27} = 0b11111;
651 let Inst{26-23} = 0b0100;
652 let Inst{22-20} = opcod;
653 let Inst{19-16} = 0b1111; // Rn
654 let Inst{15-12} = 0b1111;
656 let Inst{5-4} = {?,?}; // rotate
660 // DO variant - disassembly only, no pattern
662 multiclass T2I_unary_rrot_DO<bits<3> opcod, string opc> {
663 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
664 opc, "\t$dst, $src", []> {
665 let Inst{31-27} = 0b11111;
666 let Inst{26-23} = 0b0100;
667 let Inst{22-20} = opcod;
668 let Inst{19-16} = 0b1111; // Rn
669 let Inst{15-12} = 0b1111;
671 let Inst{5-4} = 0b00; // rotate
673 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
674 opc, "\t$dst, $src, ror $rot", []> {
675 let Inst{31-27} = 0b11111;
676 let Inst{26-23} = 0b0100;
677 let Inst{22-20} = opcod;
678 let Inst{19-16} = 0b1111; // Rn
679 let Inst{15-12} = 0b1111;
681 let Inst{5-4} = {?,?}; // rotate
685 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
686 /// register and one whose operand is a register rotated by 8/16/24.
687 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
688 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
689 opc, "\t$dst, $LHS, $RHS",
690 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]> {
691 let Inst{31-27} = 0b11111;
692 let Inst{26-23} = 0b0100;
693 let Inst{22-20} = opcod;
694 let Inst{15-12} = 0b1111;
696 let Inst{5-4} = 0b00; // rotate
698 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
699 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
700 [(set GPR:$dst, (opnode GPR:$LHS,
701 (rotr GPR:$RHS, rot_imm:$rot)))]> {
702 let Inst{31-27} = 0b11111;
703 let Inst{26-23} = 0b0100;
704 let Inst{22-20} = opcod;
705 let Inst{15-12} = 0b1111;
707 let Inst{5-4} = {?,?}; // rotate
711 // DO variant - disassembly only, no pattern
713 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
714 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
715 opc, "\t$dst, $LHS, $RHS", []> {
716 let Inst{31-27} = 0b11111;
717 let Inst{26-23} = 0b0100;
718 let Inst{22-20} = opcod;
719 let Inst{15-12} = 0b1111;
721 let Inst{5-4} = 0b00; // rotate
723 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
724 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
725 let Inst{31-27} = 0b11111;
726 let Inst{26-23} = 0b0100;
727 let Inst{22-20} = opcod;
728 let Inst{15-12} = 0b1111;
730 let Inst{5-4} = {?,?}; // rotate
734 //===----------------------------------------------------------------------===//
736 //===----------------------------------------------------------------------===//
738 //===----------------------------------------------------------------------===//
739 // Miscellaneous Instructions.
742 // LEApcrel - Load a pc-relative address into a register without offending the
744 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
745 "adr$p.w\t$dst, #$label", []> {
746 let Inst{31-27} = 0b11110;
747 let Inst{25-24} = 0b10;
748 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
751 let Inst{19-16} = 0b1111; // Rn
754 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
755 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
756 "adr$p.w\t$dst, #${label}_${id}", []> {
757 let Inst{31-27} = 0b11110;
758 let Inst{25-24} = 0b10;
759 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
762 let Inst{19-16} = 0b1111; // Rn
766 // ADD r, sp, {so_imm|i12}
767 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
768 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
769 let Inst{31-27} = 0b11110;
771 let Inst{24-21} = 0b1000;
772 let Inst{20} = ?; // The S bit.
773 let Inst{19-16} = 0b1101; // Rn = sp
776 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
777 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
778 let Inst{31-27} = 0b11110;
780 let Inst{24-21} = 0b0000;
781 let Inst{20} = 0; // The S bit.
782 let Inst{19-16} = 0b1101; // Rn = sp
787 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
788 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
789 let Inst{31-27} = 0b11101;
790 let Inst{26-25} = 0b01;
791 let Inst{24-21} = 0b1000;
792 let Inst{20} = ?; // The S bit.
793 let Inst{19-16} = 0b1101; // Rn = sp
797 // SUB r, sp, {so_imm|i12}
798 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
799 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
800 let Inst{31-27} = 0b11110;
802 let Inst{24-21} = 0b1101;
803 let Inst{20} = ?; // The S bit.
804 let Inst{19-16} = 0b1101; // Rn = sp
807 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
808 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
809 let Inst{31-27} = 0b11110;
811 let Inst{24-21} = 0b0101;
812 let Inst{20} = 0; // The S bit.
813 let Inst{19-16} = 0b1101; // Rn = sp
818 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
820 "sub", "\t$dst, $sp, $rhs", []> {
821 let Inst{31-27} = 0b11101;
822 let Inst{26-25} = 0b01;
823 let Inst{24-21} = 0b1101;
824 let Inst{20} = ?; // The S bit.
825 let Inst{19-16} = 0b1101; // Rn = sp
829 // Signed and unsigned division, for disassembly only
830 def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
831 "sdiv", "\t$dst, $a, $b", []> {
832 let Inst{31-27} = 0b11111;
833 let Inst{26-21} = 0b011100;
835 let Inst{15-12} = 0b1111;
836 let Inst{7-4} = 0b1111;
839 def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
840 "udiv", "\t$dst, $a, $b", []> {
841 let Inst{31-27} = 0b11111;
842 let Inst{26-21} = 0b011101;
844 let Inst{15-12} = 0b1111;
845 let Inst{7-4} = 0b1111;
848 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
849 let usesCustomInserter = 1 in { // Expanded after instruction selection.
850 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
851 NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
852 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
853 NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
854 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
855 NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
856 } // usesCustomInserter
859 //===----------------------------------------------------------------------===//
860 // Load / store Instructions.
864 let canFoldAsLoad = 1, isReMaterializable = 1 in
865 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
867 // Loads with zero extension
868 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
869 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
871 // Loads with sign extension
872 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
873 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
875 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
877 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
878 (ins t2addrmode_imm8s4:$addr),
879 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
880 def t2LDRDpci : T2Ii8s4<?, ?, 1, (outs GPR:$dst1, GPR:$dst2),
881 (ins i32imm:$addr), IIC_iLoadi,
882 "ldrd", "\t$dst1, $addr", []> {
883 let Inst{19-16} = 0b1111; // Rn
887 // zextload i1 -> zextload i8
888 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
889 (t2LDRBi12 t2addrmode_imm12:$addr)>;
890 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
891 (t2LDRBi8 t2addrmode_imm8:$addr)>;
892 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
893 (t2LDRBs t2addrmode_so_reg:$addr)>;
894 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
895 (t2LDRBpci tconstpool:$addr)>;
897 // extload -> zextload
898 // FIXME: Reduce the number of patterns by legalizing extload to zextload
900 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
901 (t2LDRBi12 t2addrmode_imm12:$addr)>;
902 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
903 (t2LDRBi8 t2addrmode_imm8:$addr)>;
904 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
905 (t2LDRBs t2addrmode_so_reg:$addr)>;
906 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
907 (t2LDRBpci tconstpool:$addr)>;
909 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
910 (t2LDRBi12 t2addrmode_imm12:$addr)>;
911 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
912 (t2LDRBi8 t2addrmode_imm8:$addr)>;
913 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
914 (t2LDRBs t2addrmode_so_reg:$addr)>;
915 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
916 (t2LDRBpci tconstpool:$addr)>;
918 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
919 (t2LDRHi12 t2addrmode_imm12:$addr)>;
920 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
921 (t2LDRHi8 t2addrmode_imm8:$addr)>;
922 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
923 (t2LDRHs t2addrmode_so_reg:$addr)>;
924 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
925 (t2LDRHpci tconstpool:$addr)>;
929 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
930 (ins t2addrmode_imm8:$addr),
931 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
932 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
935 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
936 (ins GPR:$base, t2am_imm8_offset:$offset),
937 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
938 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
941 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
942 (ins t2addrmode_imm8:$addr),
943 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
944 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
946 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
947 (ins GPR:$base, t2am_imm8_offset:$offset),
948 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
949 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
952 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
953 (ins t2addrmode_imm8:$addr),
954 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
955 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
957 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
958 (ins GPR:$base, t2am_imm8_offset:$offset),
959 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
960 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
963 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
964 (ins t2addrmode_imm8:$addr),
965 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
966 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
968 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
969 (ins GPR:$base, t2am_imm8_offset:$offset),
970 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
971 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
974 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
975 (ins t2addrmode_imm8:$addr),
976 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
977 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
979 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
980 (ins GPR:$base, t2am_imm8_offset:$offset),
981 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
982 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
986 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
987 // for disassembly only.
988 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
989 class T2IldT<bit signed, bits<2> type, string opc>
990 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
991 "\t$dst, $addr", []> {
992 let Inst{31-27} = 0b11111;
993 let Inst{26-25} = 0b00;
994 let Inst{24} = signed;
996 let Inst{22-21} = type;
997 let Inst{20} = 1; // load
999 let Inst{10-8} = 0b110; // PUW.
1002 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1003 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1004 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1005 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1006 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1009 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1010 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1011 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1014 let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
1015 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1016 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1017 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1020 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1021 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1022 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1023 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1025 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1027 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1028 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1029 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1030 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1032 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1034 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1035 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1036 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1037 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1039 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1041 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1042 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1043 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1044 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1046 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1048 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1049 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1050 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1051 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1053 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1055 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1056 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1057 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1058 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1060 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1062 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1064 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1065 class T2IstT<bits<2> type, string opc>
1066 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1067 "\t$src, $addr", []> {
1068 let Inst{31-27} = 0b11111;
1069 let Inst{26-25} = 0b00;
1070 let Inst{24} = 0; // not signed
1072 let Inst{22-21} = type;
1073 let Inst{20} = 0; // store
1075 let Inst{10-8} = 0b110; // PUW
1078 def t2STRT : T2IstT<0b10, "strt">;
1079 def t2STRBT : T2IstT<0b00, "strbt">;
1080 def t2STRHT : T2IstT<0b01, "strht">;
1082 // FIXME: ldrd / strd pre / post variants
1084 //===----------------------------------------------------------------------===//
1085 // Load / store multiple Instructions.
1088 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1089 def t2LDM : T2XI<(outs),
1090 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1091 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1092 let Inst{31-27} = 0b11101;
1093 let Inst{26-25} = 0b00;
1094 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1096 let Inst{21} = ?; // The W bit.
1097 let Inst{20} = 1; // Load
1100 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1101 def t2STM : T2XI<(outs),
1102 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1103 IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
1104 let Inst{31-27} = 0b11101;
1105 let Inst{26-25} = 0b00;
1106 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1108 let Inst{21} = ?; // The W bit.
1109 let Inst{20} = 0; // Store
1112 //===----------------------------------------------------------------------===//
1113 // Move Instructions.
1116 let neverHasSideEffects = 1 in
1117 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1118 "mov", ".w\t$dst, $src", []> {
1119 let Inst{31-27} = 0b11101;
1120 let Inst{26-25} = 0b01;
1121 let Inst{24-21} = 0b0010;
1122 let Inst{20} = ?; // The S bit.
1123 let Inst{19-16} = 0b1111; // Rn
1124 let Inst{14-12} = 0b000;
1125 let Inst{7-4} = 0b0000;
1128 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1129 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1130 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1131 "mov", ".w\t$dst, $src",
1132 [(set GPR:$dst, t2_so_imm:$src)]> {
1133 let Inst{31-27} = 0b11110;
1135 let Inst{24-21} = 0b0010;
1136 let Inst{20} = ?; // The S bit.
1137 let Inst{19-16} = 0b1111; // Rn
1141 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1142 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1143 "movw", "\t$dst, $src",
1144 [(set GPR:$dst, imm0_65535:$src)]> {
1145 let Inst{31-27} = 0b11110;
1147 let Inst{24-21} = 0b0010;
1148 let Inst{20} = 0; // The S bit.
1152 let Constraints = "$src = $dst" in
1153 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
1154 "movt", "\t$dst, $imm",
1156 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
1157 let Inst{31-27} = 0b11110;
1159 let Inst{24-21} = 0b0110;
1160 let Inst{20} = 0; // The S bit.
1164 def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
1166 //===----------------------------------------------------------------------===//
1167 // Extend Instructions.
1172 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1173 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1174 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1175 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1176 defm t2SXTB16 : T2I_unary_rrot_DO<0b010, "sxtb16">;
1178 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1179 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1180 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1181 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1182 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1184 // TODO: SXT(A){B|H}16 - done for disassembly only
1188 let AddedComplexity = 16 in {
1189 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1190 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1191 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1192 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1193 defm t2UXTB16 : T2I_unary_rrot<0b011, "uxtb16",
1194 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1196 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1197 (t2UXTB16r_rot GPR:$Src, 24)>;
1198 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1199 (t2UXTB16r_rot GPR:$Src, 8)>;
1201 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1202 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1203 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1204 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1205 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1208 //===----------------------------------------------------------------------===//
1209 // Arithmetic Instructions.
1212 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1213 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1214 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1215 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1217 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1218 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1219 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1220 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1221 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1223 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1224 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1225 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1226 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1227 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1228 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1229 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1230 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1233 defm t2RSB : T2I_rbin_is <0b1110, "rsb",
1234 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1235 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1236 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1238 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1239 let AddedComplexity = 1 in
1240 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1241 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1242 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1243 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1244 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1245 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1247 // Select Bytes -- for disassembly only
1249 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1250 "\t$dst, $a, $b", []> {
1251 let Inst{31-27} = 0b11111;
1252 let Inst{26-24} = 0b010;
1254 let Inst{22-20} = 0b010;
1255 let Inst{15-12} = 0b1111;
1257 let Inst{6-4} = 0b000;
1260 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1261 // And Miscellaneous operations -- for disassembly only
1262 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc>
1263 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
1264 "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> {
1265 let Inst{31-27} = 0b11111;
1266 let Inst{26-23} = 0b0101;
1267 let Inst{22-20} = op22_20;
1268 let Inst{15-12} = 0b1111;
1269 let Inst{7-4} = op7_4;
1272 // Saturating add/subtract -- for disassembly only
1274 def t2QADD : T2I_pam<0b000, 0b1000, "qadd">;
1275 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1276 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1277 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1278 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1279 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1280 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1281 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">;
1282 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1283 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1284 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1285 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1286 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1287 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1288 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1289 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1291 // Signed/Unsigned add/subtract -- for disassembly only
1293 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1294 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1295 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1296 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1297 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1298 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1299 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1300 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1301 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1302 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1303 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1304 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1306 // Signed/Unsigned halving add/subtract -- for disassembly only
1308 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1309 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1310 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1311 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1312 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1313 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1314 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1315 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1316 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1317 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1318 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1319 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1321 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1323 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1324 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1325 let Inst{15-12} = 0b1111;
1327 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst),
1328 (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8",
1329 "\t$dst, $a, $b, $acc", []>;
1331 // Signed/Unsigned saturate -- for disassembly only
1333 def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1334 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1335 [/* For disassembly only; pattern left blank */]> {
1336 let Inst{31-27} = 0b11110;
1337 let Inst{25-22} = 0b1100;
1340 let Inst{21} = 0; // sh = '0'
1343 def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1344 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1345 [/* For disassembly only; pattern left blank */]> {
1346 let Inst{31-27} = 0b11110;
1347 let Inst{25-22} = 0b1100;
1350 let Inst{21} = 1; // sh = '1'
1353 def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1354 "ssat16", "\t$dst, $bit_pos, $a",
1355 [/* For disassembly only; pattern left blank */]> {
1356 let Inst{31-27} = 0b11110;
1357 let Inst{25-22} = 0b1100;
1360 let Inst{21} = 1; // sh = '1'
1361 let Inst{14-12} = 0b000; // imm3 = '000'
1362 let Inst{7-6} = 0b00; // imm2 = '00'
1365 def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1366 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1367 [/* For disassembly only; pattern left blank */]> {
1368 let Inst{31-27} = 0b11110;
1369 let Inst{25-22} = 0b1110;
1372 let Inst{21} = 0; // sh = '0'
1375 def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
1376 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1377 [/* For disassembly only; pattern left blank */]> {
1378 let Inst{31-27} = 0b11110;
1379 let Inst{25-22} = 0b1110;
1382 let Inst{21} = 1; // sh = '1'
1385 def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
1386 "usat16", "\t$dst, $bit_pos, $a",
1387 [/* For disassembly only; pattern left blank */]> {
1388 let Inst{31-27} = 0b11110;
1389 let Inst{25-22} = 0b1110;
1392 let Inst{21} = 1; // sh = '1'
1393 let Inst{14-12} = 0b000; // imm3 = '000'
1394 let Inst{7-6} = 0b00; // imm2 = '00'
1397 //===----------------------------------------------------------------------===//
1398 // Shift and rotate Instructions.
1401 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1402 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1403 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1404 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1406 let Uses = [CPSR] in {
1407 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1408 "rrx", "\t$dst, $src",
1409 [(set GPR:$dst, (ARMrrx GPR:$src))]> {
1410 let Inst{31-27} = 0b11101;
1411 let Inst{26-25} = 0b01;
1412 let Inst{24-21} = 0b0010;
1413 let Inst{20} = ?; // The S bit.
1414 let Inst{19-16} = 0b1111; // Rn
1415 let Inst{14-12} = 0b000;
1416 let Inst{7-4} = 0b0011;
1420 let Defs = [CPSR] in {
1421 def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1422 "lsrs.w\t$dst, $src, #1",
1423 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
1424 let Inst{31-27} = 0b11101;
1425 let Inst{26-25} = 0b01;
1426 let Inst{24-21} = 0b0010;
1427 let Inst{20} = 1; // The S bit.
1428 let Inst{19-16} = 0b1111; // Rn
1429 let Inst{5-4} = 0b01; // Shift type.
1430 // Shift amount = Inst{14-12:7-6} = 1.
1431 let Inst{14-12} = 0b000;
1432 let Inst{7-6} = 0b01;
1434 def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1435 "asrs.w\t$dst, $src, #1",
1436 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
1437 let Inst{31-27} = 0b11101;
1438 let Inst{26-25} = 0b01;
1439 let Inst{24-21} = 0b0010;
1440 let Inst{20} = 1; // The S bit.
1441 let Inst{19-16} = 0b1111; // Rn
1442 let Inst{5-4} = 0b10; // Shift type.
1443 // Shift amount = Inst{14-12:7-6} = 1.
1444 let Inst{14-12} = 0b000;
1445 let Inst{7-6} = 0b01;
1449 //===----------------------------------------------------------------------===//
1450 // Bitwise Instructions.
1453 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1454 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1455 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1456 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1457 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1458 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1460 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1461 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1463 let Constraints = "$src = $dst" in
1464 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1465 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1466 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
1467 let Inst{31-27} = 0b11110;
1469 let Inst{24-20} = 0b10110;
1470 let Inst{19-16} = 0b1111; // Rn
1474 def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1475 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1476 let Inst{31-27} = 0b11110;
1478 let Inst{24-20} = 0b10100;
1482 def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1483 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1484 let Inst{31-27} = 0b11110;
1486 let Inst{24-20} = 0b11100;
1490 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1491 // Added for disassembler with the pattern field purposely left blank.
1492 // FIXME: Utilize this instruction in codgen.
1493 def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1494 IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> {
1495 let Inst{31-27} = 0b11110;
1497 let Inst{24-20} = 0b10110;
1501 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1504 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1505 let AddedComplexity = 1 in
1506 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1509 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
1510 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
1512 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1513 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
1514 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
1515 Requires<[IsThumb2]>;
1517 def : T2Pat<(t2_so_imm_not:$src),
1518 (t2MVNi t2_so_imm_not:$src)>;
1520 //===----------------------------------------------------------------------===//
1521 // Multiply Instructions.
1523 let isCommutable = 1 in
1524 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1525 "mul", "\t$dst, $a, $b",
1526 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
1527 let Inst{31-27} = 0b11111;
1528 let Inst{26-23} = 0b0110;
1529 let Inst{22-20} = 0b000;
1530 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1531 let Inst{7-4} = 0b0000; // Multiply
1534 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1535 "mla", "\t$dst, $a, $b, $c",
1536 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
1537 let Inst{31-27} = 0b11111;
1538 let Inst{26-23} = 0b0110;
1539 let Inst{22-20} = 0b000;
1540 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1541 let Inst{7-4} = 0b0000; // Multiply
1544 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1545 "mls", "\t$dst, $a, $b, $c",
1546 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
1547 let Inst{31-27} = 0b11111;
1548 let Inst{26-23} = 0b0110;
1549 let Inst{22-20} = 0b000;
1550 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1551 let Inst{7-4} = 0b0001; // Multiply and Subtract
1554 // Extra precision multiplies with low / high results
1555 let neverHasSideEffects = 1 in {
1556 let isCommutable = 1 in {
1557 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1558 "smull", "\t$ldst, $hdst, $a, $b", []> {
1559 let Inst{31-27} = 0b11111;
1560 let Inst{26-23} = 0b0111;
1561 let Inst{22-20} = 0b000;
1562 let Inst{7-4} = 0b0000;
1565 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
1566 "umull", "\t$ldst, $hdst, $a, $b", []> {
1567 let Inst{31-27} = 0b11111;
1568 let Inst{26-23} = 0b0111;
1569 let Inst{22-20} = 0b010;
1570 let Inst{7-4} = 0b0000;
1574 // Multiply + accumulate
1575 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1576 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1577 let Inst{31-27} = 0b11111;
1578 let Inst{26-23} = 0b0111;
1579 let Inst{22-20} = 0b100;
1580 let Inst{7-4} = 0b0000;
1583 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1584 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1585 let Inst{31-27} = 0b11111;
1586 let Inst{26-23} = 0b0111;
1587 let Inst{22-20} = 0b110;
1588 let Inst{7-4} = 0b0000;
1591 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
1592 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1593 let Inst{31-27} = 0b11111;
1594 let Inst{26-23} = 0b0111;
1595 let Inst{22-20} = 0b110;
1596 let Inst{7-4} = 0b0110;
1598 } // neverHasSideEffects
1600 // Rounding variants of the below included for disassembly only
1602 // Most significant word multiply
1603 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1604 "smmul", "\t$dst, $a, $b",
1605 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
1606 let Inst{31-27} = 0b11111;
1607 let Inst{26-23} = 0b0110;
1608 let Inst{22-20} = 0b101;
1609 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1610 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1613 def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1614 "smmulr", "\t$dst, $a, $b", []> {
1615 let Inst{31-27} = 0b11111;
1616 let Inst{26-23} = 0b0110;
1617 let Inst{22-20} = 0b101;
1618 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1619 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1622 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1623 "smmla", "\t$dst, $a, $b, $c",
1624 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
1625 let Inst{31-27} = 0b11111;
1626 let Inst{26-23} = 0b0110;
1627 let Inst{22-20} = 0b101;
1628 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1629 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1632 def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1633 "smmlar", "\t$dst, $a, $b, $c", []> {
1634 let Inst{31-27} = 0b11111;
1635 let Inst{26-23} = 0b0110;
1636 let Inst{22-20} = 0b101;
1637 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1638 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1641 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1642 "smmls", "\t$dst, $a, $b, $c",
1643 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
1644 let Inst{31-27} = 0b11111;
1645 let Inst{26-23} = 0b0110;
1646 let Inst{22-20} = 0b110;
1647 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1648 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1651 def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
1652 "smmlsr", "\t$dst, $a, $b, $c", []> {
1653 let Inst{31-27} = 0b11111;
1654 let Inst{26-23} = 0b0110;
1655 let Inst{22-20} = 0b110;
1656 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1657 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1660 multiclass T2I_smul<string opc, PatFrag opnode> {
1661 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1662 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1663 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1664 (sext_inreg GPR:$b, i16)))]> {
1665 let Inst{31-27} = 0b11111;
1666 let Inst{26-23} = 0b0110;
1667 let Inst{22-20} = 0b001;
1668 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1669 let Inst{7-6} = 0b00;
1670 let Inst{5-4} = 0b00;
1673 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1674 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1675 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1676 (sra GPR:$b, (i32 16))))]> {
1677 let Inst{31-27} = 0b11111;
1678 let Inst{26-23} = 0b0110;
1679 let Inst{22-20} = 0b001;
1680 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1681 let Inst{7-6} = 0b00;
1682 let Inst{5-4} = 0b01;
1685 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1686 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1687 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1688 (sext_inreg GPR:$b, i16)))]> {
1689 let Inst{31-27} = 0b11111;
1690 let Inst{26-23} = 0b0110;
1691 let Inst{22-20} = 0b001;
1692 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1693 let Inst{7-6} = 0b00;
1694 let Inst{5-4} = 0b10;
1697 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
1698 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1699 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1700 (sra GPR:$b, (i32 16))))]> {
1701 let Inst{31-27} = 0b11111;
1702 let Inst{26-23} = 0b0110;
1703 let Inst{22-20} = 0b001;
1704 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1705 let Inst{7-6} = 0b00;
1706 let Inst{5-4} = 0b11;
1709 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1710 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1711 [(set GPR:$dst, (sra (opnode GPR:$a,
1712 (sext_inreg GPR:$b, i16)), (i32 16)))]> {
1713 let Inst{31-27} = 0b11111;
1714 let Inst{26-23} = 0b0110;
1715 let Inst{22-20} = 0b011;
1716 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1717 let Inst{7-6} = 0b00;
1718 let Inst{5-4} = 0b00;
1721 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
1722 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1723 [(set GPR:$dst, (sra (opnode GPR:$a,
1724 (sra GPR:$b, (i32 16))), (i32 16)))]> {
1725 let Inst{31-27} = 0b11111;
1726 let Inst{26-23} = 0b0110;
1727 let Inst{22-20} = 0b011;
1728 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1729 let Inst{7-6} = 0b00;
1730 let Inst{5-4} = 0b01;
1735 multiclass T2I_smla<string opc, PatFrag opnode> {
1736 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1737 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1738 [(set GPR:$dst, (add GPR:$acc,
1739 (opnode (sext_inreg GPR:$a, i16),
1740 (sext_inreg GPR:$b, i16))))]> {
1741 let Inst{31-27} = 0b11111;
1742 let Inst{26-23} = 0b0110;
1743 let Inst{22-20} = 0b001;
1744 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1745 let Inst{7-6} = 0b00;
1746 let Inst{5-4} = 0b00;
1749 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1750 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1751 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1752 (sra GPR:$b, (i32 16)))))]> {
1753 let Inst{31-27} = 0b11111;
1754 let Inst{26-23} = 0b0110;
1755 let Inst{22-20} = 0b001;
1756 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1757 let Inst{7-6} = 0b00;
1758 let Inst{5-4} = 0b01;
1761 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1762 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1763 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1764 (sext_inreg GPR:$b, i16))))]> {
1765 let Inst{31-27} = 0b11111;
1766 let Inst{26-23} = 0b0110;
1767 let Inst{22-20} = 0b001;
1768 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1769 let Inst{7-6} = 0b00;
1770 let Inst{5-4} = 0b10;
1773 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1774 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1775 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1776 (sra GPR:$b, (i32 16)))))]> {
1777 let Inst{31-27} = 0b11111;
1778 let Inst{26-23} = 0b0110;
1779 let Inst{22-20} = 0b001;
1780 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1781 let Inst{7-6} = 0b00;
1782 let Inst{5-4} = 0b11;
1785 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1786 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1787 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1788 (sext_inreg GPR:$b, i16)), (i32 16))))]> {
1789 let Inst{31-27} = 0b11111;
1790 let Inst{26-23} = 0b0110;
1791 let Inst{22-20} = 0b011;
1792 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1793 let Inst{7-6} = 0b00;
1794 let Inst{5-4} = 0b00;
1797 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
1798 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1799 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1800 (sra GPR:$b, (i32 16))), (i32 16))))]> {
1801 let Inst{31-27} = 0b11111;
1802 let Inst{26-23} = 0b0110;
1803 let Inst{22-20} = 0b011;
1804 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1805 let Inst{7-6} = 0b00;
1806 let Inst{5-4} = 0b01;
1810 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1811 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1813 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
1814 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst),
1815 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1816 [/* For disassembly only; pattern left blank */]>;
1817 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst),
1818 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1819 [/* For disassembly only; pattern left blank */]>;
1820 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst),
1821 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
1822 [/* For disassembly only; pattern left blank */]>;
1823 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst),
1824 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
1825 [/* For disassembly only; pattern left blank */]>;
1827 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1828 // These are for disassembly only.
1830 def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1831 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
1832 let Inst{15-12} = 0b1111;
1834 def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1835 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
1836 let Inst{15-12} = 0b1111;
1838 def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1839 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
1840 let Inst{15-12} = 0b1111;
1842 def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1843 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
1844 let Inst{15-12} = 0b1111;
1846 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst),
1847 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad",
1848 "\t$dst, $a, $b, $acc", []>;
1849 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst),
1850 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx",
1851 "\t$dst, $a, $b, $acc", []>;
1852 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst),
1853 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd",
1854 "\t$dst, $a, $b, $acc", []>;
1855 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst),
1856 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx",
1857 "\t$dst, $a, $b, $acc", []>;
1858 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst),
1859 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald",
1860 "\t$ldst, $hdst, $a, $b", []>;
1861 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst),
1862 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx",
1863 "\t$ldst, $hdst, $a, $b", []>;
1864 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst),
1865 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld",
1866 "\t$ldst, $hdst, $a, $b", []>;
1867 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst),
1868 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx",
1869 "\t$ldst, $hdst, $a, $b", []>;
1871 //===----------------------------------------------------------------------===//
1872 // Misc. Arithmetic Instructions.
1875 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
1876 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1877 : T2I<oops, iops, itin, opc, asm, pattern> {
1878 let Inst{31-27} = 0b11111;
1879 let Inst{26-22} = 0b01010;
1880 let Inst{21-20} = op1;
1881 let Inst{15-12} = 0b1111;
1882 let Inst{7-6} = 0b10;
1883 let Inst{5-4} = op2;
1886 def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1887 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
1889 def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1890 "rbit", "\t$dst, $src",
1891 [(set GPR:$dst, (ARMrbit GPR:$src))]>;
1893 def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1894 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
1896 def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1897 "rev16", ".w\t$dst, $src",
1899 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1900 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1901 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1902 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
1904 def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1905 "revsh", ".w\t$dst, $src",
1908 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1909 (shl GPR:$src, (i32 8))), i16))]>;
1911 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1912 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
1913 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1914 (and (shl GPR:$src2, (i32 imm:$shamt)),
1916 let Inst{31-27} = 0b11101;
1917 let Inst{26-25} = 0b01;
1918 let Inst{24-20} = 0b01100;
1919 let Inst{5} = 0; // BT form
1923 // Alternate cases for PKHBT where identities eliminate some nodes.
1924 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1925 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
1926 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1927 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1929 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1930 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
1931 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1932 (and (sra GPR:$src2, imm16_31:$shamt),
1934 let Inst{31-27} = 0b11101;
1935 let Inst{26-25} = 0b01;
1936 let Inst{24-20} = 0b01100;
1937 let Inst{5} = 1; // TB form
1941 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1942 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1943 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1944 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
1945 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
1946 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1947 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1949 //===----------------------------------------------------------------------===//
1950 // Comparison Instructions...
1953 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
1954 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1955 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
1956 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1958 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
1959 // Compare-to-zero still works out, just not the relationals
1960 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
1961 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1962 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
1963 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1965 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1966 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1968 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1969 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
1971 defm t2TST : T2I_cmp_irs<0b0000, "tst",
1972 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1973 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
1974 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1976 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1977 // Short range conditional branch. Looks awesome for loops. Need to figure
1978 // out how to use this one.
1981 // Conditional moves
1982 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1983 // a two-value operand where a dag node expects two operands. :(
1984 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
1985 "mov", ".w\t$dst, $true",
1986 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1987 RegConstraint<"$false = $dst"> {
1988 let Inst{31-27} = 0b11101;
1989 let Inst{26-25} = 0b01;
1990 let Inst{24-21} = 0b0010;
1991 let Inst{20} = 0; // The S bit.
1992 let Inst{19-16} = 0b1111; // Rn
1993 let Inst{14-12} = 0b000;
1994 let Inst{7-4} = 0b0000;
1997 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1998 IIC_iCMOVi, "mov", ".w\t$dst, $true",
1999 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2000 RegConstraint<"$false = $dst"> {
2001 let Inst{31-27} = 0b11110;
2003 let Inst{24-21} = 0b0010;
2004 let Inst{20} = 0; // The S bit.
2005 let Inst{19-16} = 0b1111; // Rn
2009 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2010 string opc, string asm, list<dag> pattern>
2011 : T2I<oops, iops, itin, opc, asm, pattern> {
2012 let Inst{31-27} = 0b11101;
2013 let Inst{26-25} = 0b01;
2014 let Inst{24-21} = 0b0010;
2015 let Inst{20} = 0; // The S bit.
2016 let Inst{19-16} = 0b1111; // Rn
2017 let Inst{5-4} = opcod; // Shift type.
2019 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
2020 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2021 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2022 RegConstraint<"$false = $dst">;
2023 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
2024 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2025 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2026 RegConstraint<"$false = $dst">;
2027 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
2028 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2029 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2030 RegConstraint<"$false = $dst">;
2031 def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
2032 (ins GPR:$false, GPR:$true, i32imm:$rhs),
2033 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2034 RegConstraint<"$false = $dst">;
2036 //===----------------------------------------------------------------------===//
2037 // Atomic operations intrinsics
2040 // memory barriers protect the atomic sequences
2041 let hasSideEffects = 1 in {
2042 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
2043 Pseudo, NoItinerary,
2045 [(ARMMemBarrierV7)]>,
2046 Requires<[IsThumb2]> {
2047 let Inst{31-4} = 0xF3BF8F5;
2048 // FIXME: add support for options other than a full system DMB
2049 let Inst{3-0} = 0b1111;
2052 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
2053 Pseudo, NoItinerary,
2055 [(ARMSyncBarrierV7)]>,
2056 Requires<[IsThumb2]> {
2057 let Inst{31-4} = 0xF3BF8F4;
2058 // FIXME: add support for options other than a full system DSB
2059 let Inst{3-0} = 0b1111;
2063 // Helper class for multiclass T2MemB -- for disassembly only
2064 class T2I_memb<string opc, string asm>
2065 : T2I<(outs), (ins), NoItinerary, opc, asm,
2066 [/* For disassembly only; pattern left blank */]>,
2067 Requires<[IsThumb2, HasV7]> {
2068 let Inst{31-20} = 0xf3b;
2069 let Inst{15-14} = 0b10;
2073 multiclass T2MemB<bits<4> op7_4, string opc> {
2075 def st : T2I_memb<opc, "\tst"> {
2076 let Inst{7-4} = op7_4;
2077 let Inst{3-0} = 0b1110;
2080 def ish : T2I_memb<opc, "\tish"> {
2081 let Inst{7-4} = op7_4;
2082 let Inst{3-0} = 0b1011;
2085 def ishst : T2I_memb<opc, "\tishst"> {
2086 let Inst{7-4} = op7_4;
2087 let Inst{3-0} = 0b1010;
2090 def nsh : T2I_memb<opc, "\tnsh"> {
2091 let Inst{7-4} = op7_4;
2092 let Inst{3-0} = 0b0111;
2095 def nshst : T2I_memb<opc, "\tnshst"> {
2096 let Inst{7-4} = op7_4;
2097 let Inst{3-0} = 0b0110;
2100 def osh : T2I_memb<opc, "\tosh"> {
2101 let Inst{7-4} = op7_4;
2102 let Inst{3-0} = 0b0011;
2105 def oshst : T2I_memb<opc, "\toshst"> {
2106 let Inst{7-4} = op7_4;
2107 let Inst{3-0} = 0b0010;
2111 // These DMB variants are for disassembly only.
2112 defm t2DMB : T2MemB<0b0101, "dmb">;
2114 // These DSB variants are for disassembly only.
2115 defm t2DSB : T2MemB<0b0100, "dsb">;
2117 // ISB has only full system option -- for disassembly only
2118 def t2ISBsy : T2I_memb<"isb", ""> {
2119 let Inst{7-4} = 0b0110;
2120 let Inst{3-0} = 0b1111;
2123 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2124 InstrItinClass itin, string opc, string asm, string cstr,
2125 list<dag> pattern, bits<4> rt2 = 0b1111>
2126 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2127 let Inst{31-27} = 0b11101;
2128 let Inst{26-20} = 0b0001101;
2129 let Inst{11-8} = rt2;
2130 let Inst{7-6} = 0b01;
2131 let Inst{5-4} = opcod;
2132 let Inst{3-0} = 0b1111;
2134 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2135 InstrItinClass itin, string opc, string asm, string cstr,
2136 list<dag> pattern, bits<4> rt2 = 0b1111>
2137 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2138 let Inst{31-27} = 0b11101;
2139 let Inst{26-20} = 0b0001100;
2140 let Inst{11-8} = rt2;
2141 let Inst{7-6} = 0b01;
2142 let Inst{5-4} = opcod;
2145 let mayLoad = 1 in {
2146 def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2147 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2149 def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2150 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2152 def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
2153 Size4Bytes, NoItinerary,
2154 "ldrex", "\t$dest, [$ptr]", "",
2156 let Inst{31-27} = 0b11101;
2157 let Inst{26-20} = 0b0000101;
2158 let Inst{11-8} = 0b1111;
2159 let Inst{7-0} = 0b00000000; // imm8 = 0
2161 def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2162 AddrModeNone, Size4Bytes, NoItinerary,
2163 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2167 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2168 def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2169 AddrModeNone, Size4Bytes, NoItinerary,
2170 "strexb", "\t$success, $src, [$ptr]", "", []>;
2171 def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2172 AddrModeNone, Size4Bytes, NoItinerary,
2173 "strexh", "\t$success, $src, [$ptr]", "", []>;
2174 def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2175 AddrModeNone, Size4Bytes, NoItinerary,
2176 "strex", "\t$success, $src, [$ptr]", "",
2178 let Inst{31-27} = 0b11101;
2179 let Inst{26-20} = 0b0000100;
2180 let Inst{7-0} = 0b00000000; // imm8 = 0
2182 def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
2183 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2184 AddrModeNone, Size4Bytes, NoItinerary,
2185 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2189 // Clear-Exclusive is for disassembly only.
2190 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2191 [/* For disassembly only; pattern left blank */]>,
2192 Requires<[IsARM, HasV7]> {
2193 let Inst{31-20} = 0xf3b;
2194 let Inst{15-14} = 0b10;
2196 let Inst{7-4} = 0b0010;
2199 //===----------------------------------------------------------------------===//
2203 // __aeabi_read_tp preserves the registers r1-r3.
2205 Defs = [R0, R12, LR, CPSR] in {
2206 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2207 "bl\t__aeabi_read_tp",
2208 [(set R0, ARMthread_pointer)]> {
2209 let Inst{31-27} = 0b11110;
2210 let Inst{15-14} = 0b11;
2215 //===----------------------------------------------------------------------===//
2216 // SJLJ Exception handling intrinsics
2217 // eh_sjlj_setjmp() is an instruction sequence to store the return
2218 // address and save #0 in R0 for the non-longjmp case.
2219 // Since by its nature we may be coming from some other function to get
2220 // here, and we're using the stack frame for the containing function to
2221 // save/restore registers, we can't keep anything live in regs across
2222 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2223 // when we get here from a longjmp(). We force everthing out of registers
2224 // except for our own input by listing the relevant registers in Defs. By
2225 // doing so, we also cause the prologue/epilogue code to actively preserve
2226 // all of the callee-saved resgisters, which is exactly what we want.
2227 // The current SP is passed in $val, and we reuse the reg as a scratch.
2229 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2230 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2231 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2233 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val),
2234 AddrModeNone, SizeSpecial, NoItinerary,
2235 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
2237 "\tadds\t$val, #9\n"
2238 "\tstr\t$val, [$src, #4]\n"
2241 "\tmovs\tr0, #1\t@ end eh.setjmp\n"
2243 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>;
2248 //===----------------------------------------------------------------------===//
2249 // Control-Flow Instructions
2252 // FIXME: remove when we have a way to marking a MI with these properties.
2253 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2255 // FIXME: Should pc be an implicit operand like PICADD, etc?
2256 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2257 hasExtraDefRegAllocReq = 1 in
2258 def t2LDM_RET : T2XI<(outs),
2259 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
2260 IIC_Br, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb",
2262 let Inst{31-27} = 0b11101;
2263 let Inst{26-25} = 0b00;
2264 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2266 let Inst{21} = ?; // The W bit.
2267 let Inst{20} = 1; // Load
2270 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2271 let isPredicable = 1 in
2272 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2274 [(br bb:$target)]> {
2275 let Inst{31-27} = 0b11110;
2276 let Inst{15-14} = 0b10;
2280 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2283 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2284 IIC_Br, "mov\tpc, $target\n$jt",
2285 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2286 let Inst{31-27} = 0b11101;
2287 let Inst{26-20} = 0b0100100;
2288 let Inst{19-16} = 0b1111;
2289 let Inst{14-12} = 0b000;
2290 let Inst{11-8} = 0b1111; // Rd = pc
2291 let Inst{7-4} = 0b0000;
2294 // FIXME: Add a non-pc based case that can be predicated.
2297 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2298 IIC_Br, "tbb\t$index\n$jt", []> {
2299 let Inst{31-27} = 0b11101;
2300 let Inst{26-20} = 0b0001101;
2301 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2302 let Inst{15-8} = 0b11110000;
2303 let Inst{7-4} = 0b0000; // B form
2308 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2309 IIC_Br, "tbh\t$index\n$jt", []> {
2310 let Inst{31-27} = 0b11101;
2311 let Inst{26-20} = 0b0001101;
2312 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2313 let Inst{15-8} = 0b11110000;
2314 let Inst{7-4} = 0b0001; // H form
2317 // Generic versions of the above two instructions, for disassembly only
2319 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2320 "tbb", "\t[$a, $b]", []>{
2321 let Inst{31-27} = 0b11101;
2322 let Inst{26-20} = 0b0001101;
2323 let Inst{15-8} = 0b11110000;
2324 let Inst{7-4} = 0b0000; // B form
2327 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2328 "tbh", "\t[$a, $b, lsl #1]", []> {
2329 let Inst{31-27} = 0b11101;
2330 let Inst{26-20} = 0b0001101;
2331 let Inst{15-8} = 0b11110000;
2332 let Inst{7-4} = 0b0001; // H form
2334 } // isNotDuplicable, isIndirectBranch
2336 } // isBranch, isTerminator, isBarrier
2338 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2339 // a two-value operand where a dag node expects two operands. :(
2340 let isBranch = 1, isTerminator = 1 in
2341 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2343 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2344 let Inst{31-27} = 0b11110;
2345 let Inst{15-14} = 0b10;
2351 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2352 AddrModeNone, Size2Bytes, IIC_iALUx,
2353 "it$mask\t$cc", "", []> {
2354 // 16-bit instruction.
2355 let Inst{31-16} = 0x0000;
2356 let Inst{15-8} = 0b10111111;
2359 // Branch and Exchange Jazelle -- for disassembly only
2361 def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2362 [/* For disassembly only; pattern left blank */]> {
2363 let Inst{31-27} = 0b11110;
2365 let Inst{25-20} = 0b111100;
2366 let Inst{15-14} = 0b10;
2370 // Change Processor State is a system instruction -- for disassembly only.
2371 // The singleton $opt operand contains the following information:
2372 // opt{4-0} = mode from Inst{4-0}
2373 // opt{5} = changemode from Inst{17}
2374 // opt{8-6} = AIF from Inst{8-6}
2375 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2376 def t2CPS : T2XI<(outs),(ins i32imm:$opt), NoItinerary, "cps${opt:cps}",
2377 [/* For disassembly only; pattern left blank */]> {
2378 let Inst{31-27} = 0b11110;
2380 let Inst{25-20} = 0b111010;
2381 let Inst{15-14} = 0b10;
2385 // A6.3.4 Branches and miscellaneous control
2386 // Table A6-14 Change Processor State, and hint instructions
2387 // Helper class for disassembly only.
2388 class T2I_hint<bits<8> op7_0, string opc, string asm>
2389 : T2I<(outs), (ins), NoItinerary, opc, asm,
2390 [/* For disassembly only; pattern left blank */]> {
2391 let Inst{31-20} = 0xf3a;
2392 let Inst{15-14} = 0b10;
2394 let Inst{10-8} = 0b000;
2395 let Inst{7-0} = op7_0;
2398 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2399 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2400 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2401 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2402 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2404 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2405 [/* For disassembly only; pattern left blank */]> {
2406 let Inst{31-20} = 0xf3a;
2407 let Inst{15-14} = 0b10;
2409 let Inst{10-8} = 0b000;
2410 let Inst{7-4} = 0b1111;
2413 // Secure Monitor Call is a system instruction -- for disassembly only
2414 // Option = Inst{19-16}
2415 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2416 [/* For disassembly only; pattern left blank */]> {
2417 let Inst{31-27} = 0b11110;
2418 let Inst{26-20} = 0b1111111;
2419 let Inst{15-12} = 0b1000;
2422 // Store Return State is a system instruction -- for disassembly only
2423 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2424 [/* For disassembly only; pattern left blank */]> {
2425 let Inst{31-27} = 0b11101;
2426 let Inst{26-20} = 0b0000010; // W = 1
2429 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2430 [/* For disassembly only; pattern left blank */]> {
2431 let Inst{31-27} = 0b11101;
2432 let Inst{26-20} = 0b0000000; // W = 0
2435 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2436 [/* For disassembly only; pattern left blank */]> {
2437 let Inst{31-27} = 0b11101;
2438 let Inst{26-20} = 0b0011010; // W = 1
2441 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2442 [/* For disassembly only; pattern left blank */]> {
2443 let Inst{31-27} = 0b11101;
2444 let Inst{26-20} = 0b0011000; // W = 0
2447 // Return From Exception is a system instruction -- for disassembly only
2448 def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!",
2449 [/* For disassembly only; pattern left blank */]> {
2450 let Inst{31-27} = 0b11101;
2451 let Inst{26-20} = 0b0000011; // W = 1
2454 def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base",
2455 [/* For disassembly only; pattern left blank */]> {
2456 let Inst{31-27} = 0b11101;
2457 let Inst{26-20} = 0b0000001; // W = 0
2460 def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!",
2461 [/* For disassembly only; pattern left blank */]> {
2462 let Inst{31-27} = 0b11101;
2463 let Inst{26-20} = 0b0011011; // W = 1
2466 def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base",
2467 [/* For disassembly only; pattern left blank */]> {
2468 let Inst{31-27} = 0b11101;
2469 let Inst{26-20} = 0b0011001; // W = 0
2472 //===----------------------------------------------------------------------===//
2473 // Non-Instruction Patterns
2476 // Two piece so_imms.
2477 def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
2478 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2479 (t2_so_imm2part_2 imm:$RHS))>;
2480 def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
2481 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2482 (t2_so_imm2part_2 imm:$RHS))>;
2483 def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
2484 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2485 (t2_so_imm2part_2 imm:$RHS))>;
2486 def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS),
2487 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2488 (t2_so_neg_imm2part_2 imm:$RHS))>;
2490 // 32-bit immediate using movw + movt.
2491 // This is a single pseudo instruction to make it re-materializable. Remove
2492 // when we can do generalized remat.
2493 let isReMaterializable = 1 in
2494 def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2495 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2496 [(set GPR:$dst, (i32 imm:$src))]>;
2498 // ConstantPool, GlobalAddress, and JumpTable
2499 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2500 Requires<[IsThumb2, DontUseMovt]>;
2501 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2502 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2503 Requires<[IsThumb2, UseMovt]>;
2505 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2506 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2508 // Pseudo instruction that combines ldr from constpool and add pc. This should
2509 // be expanded into two instructions late to allow if-conversion and
2511 let canFoldAsLoad = 1, isReMaterializable = 1 in
2512 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2513 NoItinerary, "@ ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2514 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2516 Requires<[IsThumb2]>;
2518 //===----------------------------------------------------------------------===//
2519 // Move between special register and ARM core register -- for disassembly only
2523 def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2524 [/* For disassembly only; pattern left blank */]> {
2525 let Inst{31-27} = 0b11110;
2527 let Inst{25-21} = 0b11111;
2528 let Inst{20} = 0; // The R bit.
2529 let Inst{15-14} = 0b10;
2534 def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2535 [/* For disassembly only; pattern left blank */]> {
2536 let Inst{31-27} = 0b11110;
2538 let Inst{25-21} = 0b11111;
2539 let Inst{20} = 1; // The R bit.
2540 let Inst{15-14} = 0b10;
2544 // FIXME: mask is ignored for the time being.
2546 def t2MSR : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tcpsr, $src",
2547 [/* For disassembly only; pattern left blank */]> {
2548 let Inst{31-27} = 0b11110;
2550 let Inst{25-21} = 0b11100;
2551 let Inst{20} = 0; // The R bit.
2552 let Inst{15-14} = 0b10;
2556 // FIXME: mask is ignored for the time being.
2558 def t2MSRsys : T2I<(outs), (ins GPR:$src), NoItinerary, "msr", "\tspsr, $src",
2559 [/* For disassembly only; pattern left blank */]> {
2560 let Inst{31-27} = 0b11110;
2562 let Inst{25-21} = 0b11100;
2563 let Inst{20} = 1; // The R bit.
2564 let Inst{15-14} = 0b10;