1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
19 let PrintMethod = "printT2SOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
24 // described for t2_so_imm def below.
25 def t2_so_imm_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(
27 ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
30 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
31 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
32 return CurDAG->getTargetConstant(
33 ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
36 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
37 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(
39 ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
42 // t2_so_imm - Match a 32-bit immediate operand, which is an
43 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
44 // immediate splatted into multiple bytes of the word. t2_so_imm values are
45 // represented in the imm field in the same 12-bit form that they are encoded
46 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
47 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
48 def t2_so_imm : Operand<i32>,
50 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
51 }], t2_so_imm_XFORM> {
52 let PrintMethod = "printT2SOImmOperand";
55 // t2_so_imm_not - Match an immediate that is a complement
57 def t2_so_imm_not : Operand<i32>,
59 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60 }], t2_so_imm_not_XFORM> {
61 let PrintMethod = "printT2SOImmOperand";
64 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65 def t2_so_imm_neg : Operand<i32>,
67 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
68 }], t2_so_imm_neg_XFORM> {
69 let PrintMethod = "printT2SOImmOperand";
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
88 def imm0_65535 : PatLeaf<(i32 imm), [{
89 return (uint32_t)N->getZExtValue() < 65536;
92 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
94 def bf_inv_mask_imm : Operand<i32>,
96 uint32_t v = (uint32_t)N->getZExtValue();
99 // naive checker. should do better, but simple is best for now since it's
100 // more likely to be correct.
101 while (v & 1) v >>= 1; // shift off the leading 1's
104 while (!(v & 1)) v >>=1; // shift off the mask
105 while (v & 1) v >>= 1; // shift off the trailing 1's
107 // if this is a mask for clearing a bitfield, what's left should be zero.
110 let PrintMethod = "printBitfieldInvMaskImmOperand";
113 /// Split a 32-bit immediate into two 16 bit parts.
114 def t2_lo16 : SDNodeXForm<imm, [{
115 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
119 def t2_hi16 : SDNodeXForm<imm, [{
120 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
123 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
124 // Returns true if all low 16-bits are 0.
125 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
129 // Define Thumb2 specific addressing modes.
131 // t2addrmode_imm12 := reg + imm12
132 def t2addrmode_imm12 : Operand<i32>,
133 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
134 let PrintMethod = "printT2AddrModeImm12Operand";
135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
138 // t2addrmode_imm8 := reg - imm8
139 def t2addrmode_imm8 : Operand<i32>,
140 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
141 let PrintMethod = "printT2AddrModeImm8Operand";
142 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
145 def t2am_imm8_offset : Operand<i32> {
146 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
149 // t2addrmode_imm8s4 := reg + (imm8 << 2)
150 def t2addrmode_imm8s4 : Operand<i32>,
151 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
152 let PrintMethod = "printT2AddrModeImm8Operand";
153 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
156 // t2addrmode_so_reg := reg + reg << imm2
157 def t2addrmode_so_reg : Operand<i32>,
158 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
159 let PrintMethod = "printT2AddrModeSoRegOperand";
160 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
164 //===----------------------------------------------------------------------===//
165 // Multiclass helpers...
168 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
169 /// unary operation that produces a value. These are predicable and can be
170 /// changed to modify CPSR.
171 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
173 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
175 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
176 let isAsCheapAsAMove = Cheap;
177 let isReMaterializable = ReMat;
180 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
182 [(set GPR:$dst, (opnode GPR:$src))]>;
184 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
186 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
189 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
190 // binary operation that produces a value. These are predicable and can be
191 /// changed to modify CPSR.
192 multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
194 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
195 opc, " $dst, $lhs, $rhs",
196 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
198 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
199 opc, " $dst, $lhs, $rhs",
200 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
201 let isCommutable = Commutable;
204 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
205 opc, " $dst, $lhs, $rhs",
206 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
209 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
210 /// reversed. It doesn't define the 'rr' form since it's handled by its
211 /// T2I_bin_irs counterpart.
212 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
214 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
215 opc, " $dst, $rhs, $lhs",
216 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
218 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
219 opc, " $dst, $rhs, $lhs",
220 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
223 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
224 /// instruction modifies the CPSR register.
225 let Defs = [CPSR] in {
226 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
228 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
229 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
230 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
232 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
233 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
234 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
235 let isCommutable = Commutable;
238 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
239 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
240 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
244 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
245 /// patterns for a binary operation that produces a value.
246 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
248 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
249 opc, " $dst, $lhs, $rhs",
250 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
252 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
253 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
254 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
256 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
257 opc, " $dst, $lhs, $rhs",
258 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
259 let isCommutable = Commutable;
262 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
263 opc, " $dst, $lhs, $rhs",
264 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
267 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
268 /// binary operation that produces a value and use and define the carry bit.
269 /// It's not predicable.
270 let Uses = [CPSR] in {
271 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
273 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
274 opc, " $dst, $lhs, $rhs",
275 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
276 Requires<[IsThumb2, CarryDefIsUnused]>;
278 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
279 opc, " $dst, $lhs, $rhs",
280 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
281 Requires<[IsThumb2, CarryDefIsUnused]> {
282 let isCommutable = Commutable;
285 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
286 opc, " $dst, $lhs, $rhs",
287 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
288 Requires<[IsThumb2, CarryDefIsUnused]>;
289 // Carry setting variants
291 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
292 !strconcat(opc, "s $dst, $lhs, $rhs"),
293 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
294 Requires<[IsThumb2, CarryDefIsUsed]> {
298 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
299 !strconcat(opc, "s $dst, $lhs, $rhs"),
300 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
301 Requires<[IsThumb2, CarryDefIsUsed]> {
303 let isCommutable = Commutable;
306 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
307 !strconcat(opc, "s $dst, $lhs, $rhs"),
308 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
309 Requires<[IsThumb2, CarryDefIsUsed]> {
315 /// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
316 /// reversed. It doesn't define the 'rr' form since it's handled by its
317 /// T2I_adde_sube_irs counterpart.
318 let Defs = [CPSR], Uses = [CPSR] in {
319 multiclass T2I_rsc_is<string opc, PatFrag opnode> {
321 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
322 opc, " $dst, $rhs, $lhs",
323 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
324 Requires<[IsThumb2, CarryDefIsUnused]>;
326 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
327 opc, " $dst, $rhs, $lhs",
328 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
329 Requires<[IsThumb2, CarryDefIsUnused]>;
331 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
332 !strconcat(opc, "s $dst, $rhs, $lhs"),
333 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
334 Requires<[IsThumb2, CarryDefIsUsed]> {
338 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
339 !strconcat(opc, "s $dst, $rhs, $lhs"),
340 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
341 Requires<[IsThumb2, CarryDefIsUsed]> {
347 /// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
348 /// reversed. It doesn't define the 'rr' form since it's handled by its
349 /// T2I_bin_s_irs counterpart.
350 let Defs = [CPSR] in {
351 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
353 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
354 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
355 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
357 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
358 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
359 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
363 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
364 // rotate operation that produces a value.
365 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
367 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
368 opc, " $dst, $lhs, $rhs",
369 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
371 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
372 opc, " $dst, $lhs, $rhs",
373 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
376 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
377 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
378 /// a explicit result, only implicitly set CPSR.
379 let Uses = [CPSR] in {
380 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
382 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
384 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
386 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
388 [(opnode GPR:$lhs, GPR:$rhs)]>;
390 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
392 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
396 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
397 multiclass T2I_ld<string opc, PatFrag opnode> {
398 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
400 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
401 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
403 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
404 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
406 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
407 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
409 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
412 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
413 multiclass T2I_st<string opc, PatFrag opnode> {
414 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
416 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
417 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
419 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
420 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
422 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
425 /// T2I_picld - Defines the PIC load pattern.
426 class T2I_picld<string opc, PatFrag opnode> :
427 T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
428 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
429 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
431 /// T2I_picst - Defines the PIC store pattern.
432 class T2I_picst<string opc, PatFrag opnode> :
433 T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
434 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
435 [(opnode GPR:$src, addrmodepc:$addr)]>;
437 //===----------------------------------------------------------------------===//
439 //===----------------------------------------------------------------------===//
441 //===----------------------------------------------------------------------===//
442 // Miscellaneous Instructions.
445 let isNotDuplicable = 1 in
446 def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
447 "$cp:\n\tadd $dst, pc",
448 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
451 // LEApcrel - Load a pc-relative address into a register without offending the
453 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
454 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
455 "${:private}PCRELL${:uid}+8))\n"),
456 !strconcat("${:private}PCRELL${:uid}:\n\t",
457 "add$p $dst, pc, #PCRELV${:uid}")),
460 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
461 (ins i32imm:$label, i32imm:$id, pred:$p),
462 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
463 "${:private}PCRELL${:uid}+8))\n"),
464 !strconcat("${:private}PCRELL${:uid}:\n\t",
465 "add$p $dst, pc, #PCRELV${:uid}")),
468 // ADD rd, sp, #so_imm
469 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
470 "add $dst, $sp, $imm",
473 // ADD rd, sp, #imm12
474 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
475 "addw $dst, $sp, $imm",
478 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
479 "addw $dst, $sp, $rhs",
483 //===----------------------------------------------------------------------===//
484 // Load / store Instructions.
488 let canFoldAsLoad = 1 in
489 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
491 // Loads with zero extension
492 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
493 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
495 // Loads with sign extension
496 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
497 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
501 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
502 "ldrd", " $dst, $addr", []>;
503 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
504 "ldrd", " $dst, $addr", []>;
507 // zextload i1 -> zextload i8
508 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
509 (t2LDRBi12 t2addrmode_imm12:$addr)>;
510 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
511 (t2LDRBi8 t2addrmode_imm8:$addr)>;
512 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
513 (t2LDRBs t2addrmode_so_reg:$addr)>;
514 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
515 (t2LDRBpci tconstpool:$addr)>;
517 // extload -> zextload
518 // FIXME: Reduce the number of patterns by legalizing extload to zextload
520 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
521 (t2LDRBi12 t2addrmode_imm12:$addr)>;
522 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
523 (t2LDRBi8 t2addrmode_imm8:$addr)>;
524 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
525 (t2LDRBs t2addrmode_so_reg:$addr)>;
526 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
527 (t2LDRBpci tconstpool:$addr)>;
529 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
530 (t2LDRBi12 t2addrmode_imm12:$addr)>;
531 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
532 (t2LDRBi8 t2addrmode_imm8:$addr)>;
533 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
534 (t2LDRBs t2addrmode_so_reg:$addr)>;
535 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
536 (t2LDRBpci tconstpool:$addr)>;
538 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
539 (t2LDRHi12 t2addrmode_imm12:$addr)>;
540 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
541 (t2LDRHi8 t2addrmode_imm8:$addr)>;
542 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
543 (t2LDRHs t2addrmode_so_reg:$addr)>;
544 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
545 (t2LDRHpci tconstpool:$addr)>;
548 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
549 (ins t2addrmode_imm8:$addr),
550 AddrModeT2_i8, IndexModePre,
551 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
554 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
555 (ins GPR:$base, t2am_imm8_offset:$offset),
556 AddrModeT2_i8, IndexModePost,
557 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
560 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
561 (ins t2addrmode_imm8:$addr),
562 AddrModeT2_i8, IndexModePre,
563 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
565 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
566 (ins GPR:$base, t2am_imm8_offset:$offset),
567 AddrModeT2_i8, IndexModePost,
568 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
571 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
572 (ins t2addrmode_imm8:$addr),
573 AddrModeT2_i8, IndexModePre,
574 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
576 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
577 (ins GPR:$base, t2am_imm8_offset:$offset),
578 AddrModeT2_i8, IndexModePost,
579 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
583 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
584 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
585 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
589 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
590 "strd", " $src, $addr", []>;
593 // Address computation and loads and stores in PIC mode.
594 let isNotDuplicable = 1, AddedComplexity = 10 in {
595 let canFoldAsLoad = 1 in
596 def t2PICLDR : T2I_picld<"ldr", UnOpFrag<(load node:$Src)>>;
598 def t2PICLDRH : T2I_picld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
599 def t2PICLDRB : T2I_picld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
600 def t2PICLDRSH : T2I_picld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
601 def t2PICLDRSB : T2I_picld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
603 def t2PICSTR : T2I_picst<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
604 def t2PICSTRH : T2I_picst<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
605 def t2PICSTRB : T2I_picst<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
606 } // isNotDuplicable = 1, AddedComplexity = 10
608 //===----------------------------------------------------------------------===//
609 // Move Instructions.
612 let neverHasSideEffects = 1 in
613 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
614 "mov", " $dst, $src", []>;
616 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
617 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
618 "mov", " $dst, $src",
619 [(set GPR:$dst, t2_so_imm:$src)]>;
621 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
622 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
623 "movw", " $dst, $src",
624 [(set GPR:$dst, imm0_65535:$src)]>;
626 // FIXME: Also available in ARM mode.
627 let Constraints = "$src = $dst" in
628 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
629 "movt", " $dst, $imm",
631 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
633 //===----------------------------------------------------------------------===//
634 // Arithmetic Instructions.
637 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
638 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
640 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
641 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
642 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
644 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
645 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
648 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
649 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
650 defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
652 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
653 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
654 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
655 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
656 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
659 //===----------------------------------------------------------------------===//
660 // Shift and rotate Instructions.
663 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
664 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
665 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
666 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
668 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
669 "mov", " $dst, $src, rrx",
670 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
672 //===----------------------------------------------------------------------===//
673 // Bitwise Instructions.
676 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
677 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
678 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
680 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
682 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
683 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
685 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
687 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
688 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
690 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
691 let AddedComplexity = 1 in
692 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
694 def : T2Pat<(t2_so_imm_not:$src),
695 (t2MVNi t2_so_imm_not:$src)>;
697 // A8.6.17 BFC - Bitfield clear
698 // FIXME: Also available in ARM mode.
699 let Constraints = "$src = $dst" in
700 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
701 "bfc", " $dst, $imm",
702 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
704 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
706 //===----------------------------------------------------------------------===//
707 // Multiply Instructions.
709 let isCommutable = 1 in
710 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
711 "mul", " $dst, $a, $b",
712 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
714 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
715 "mla", " $dst, $a, $b, $c",
716 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
718 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
719 "mls", " $dst, $a, $b, $c",
720 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
722 // FIXME: SMULL, etc.
724 //===----------------------------------------------------------------------===//
725 // Misc. Arithmetic Instructions.
728 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
729 "clz", " $dst, $src",
730 [(set GPR:$dst, (ctlz GPR:$src))]>;
732 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
733 "rev", " $dst, $src",
734 [(set GPR:$dst, (bswap GPR:$src))]>;
736 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
737 "rev16", " $dst, $src",
739 (or (and (srl GPR:$src, (i32 8)), 0xFF),
740 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
741 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
742 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
747 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
748 "revsh", " $dst, $src",
751 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
752 (shl GPR:$src, (i32 8))), i16))]>;
756 //===----------------------------------------------------------------------===//
757 // Comparison Instructions...
760 defm t2CMP : T2I_cmp_is<"cmp",
761 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
762 defm t2CMPz : T2I_cmp_is<"cmp",
763 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
765 defm t2CMN : T2I_cmp_is<"cmn",
766 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
767 defm t2CMNz : T2I_cmp_is<"cmn",
768 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
770 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
771 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
773 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
774 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
776 defm t2TST : T2I_cmp_is<"tst",
777 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
778 defm t2TEQ : T2I_cmp_is<"teq",
779 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
781 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
782 // Short range conditional branch. Looks awesome for loops. Need to figure
783 // out how to use this one.
785 // FIXME: Conditional moves
787 //===----------------------------------------------------------------------===//
788 // Control-Flow Instructions
791 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
792 let isPredicable = 1 in
793 def t2B : T2XI<(outs), (ins brtarget:$target),
797 let isNotDuplicable = 1, isIndirectBranch = 1 in {
798 def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
799 "mov pc, $target \n$jt",
800 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
804 (ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id),
805 "ldr pc, $target \n$jt",
806 [(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt,
811 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
812 "add pc, $target, $idx \n$jt",
813 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>;
814 } // isNotDuplicate, isIndirectBranch
815 } // isBranch, isTerminator, isBarrier
817 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
818 // a two-value operand where a dag node expects two operands. :(
819 let isBranch = 1, isTerminator = 1 in
820 def t2Bcc : T2I<(outs), (ins brtarget:$target),
822 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
824 //===----------------------------------------------------------------------===//
825 // Non-Instruction Patterns
828 // ConstantPool, GlobalAddress, and JumpTable
829 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
830 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
831 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
832 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
834 // Large immediate handling.
836 def : T2Pat<(i32 imm:$src),
837 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;