1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let PrintMethod = "printT2SOOperand";
30 let MIOperandInfo = (ops GPR, i32imm);
33 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
34 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
35 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
38 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
39 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
43 // t2_so_imm - Match a 32-bit immediate operand, which is an
44 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
45 // immediate splatted into multiple bytes of the word. t2_so_imm values are
46 // represented in the imm field in the same 12-bit form that they are encoded
47 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
48 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
49 def t2_so_imm : Operand<i32>,
51 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
54 // t2_so_imm_not - Match an immediate that is a complement
56 def t2_so_imm_not : Operand<i32>,
58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
59 }], t2_so_imm_not_XFORM>;
61 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
62 def t2_so_imm_neg : Operand<i32>,
64 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
65 }], t2_so_imm_neg_XFORM>;
67 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
68 def imm1_31 : PatLeaf<(i32 imm), [{
69 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
72 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
73 def imm0_4095 : PatLeaf<(i32 imm), [{
74 return (uint32_t)N->getZExtValue() < 4096;
77 def imm0_4095_neg : PatLeaf<(i32 imm), [{
78 return (uint32_t)(-N->getZExtValue()) < 4096;
81 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
83 def imm0_65535 : PatLeaf<(i32 imm), [{
84 return (uint32_t)N->getZExtValue() < 65536;
87 /// Split a 32-bit immediate into two 16 bit parts.
88 def t2_lo16 : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
93 def t2_hi16 : SDNodeXForm<imm, [{
94 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
97 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
98 // Returns true if all low 16-bits are 0.
99 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
103 // Define Thumb2 specific addressing modes.
105 // t2addrmode_imm12 := reg + imm12
106 def t2addrmode_imm12 : Operand<i32>,
107 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
108 let PrintMethod = "printT2AddrModeImm12Operand";
109 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
112 // t2addrmode_imm8 := reg - imm8
113 def t2addrmode_imm8 : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
115 let PrintMethod = "printT2AddrModeImm8Operand";
116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
119 def t2am_imm8_offset : Operand<i32>,
120 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
121 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
124 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
125 def t2addrmode_imm8s4 : Operand<i32>,
126 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
127 let PrintMethod = "printT2AddrModeImm8s4Operand";
128 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
131 // t2addrmode_so_reg := reg + (reg << imm2)
132 def t2addrmode_so_reg : Operand<i32>,
133 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
134 let PrintMethod = "printT2AddrModeSoRegOperand";
135 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
139 //===----------------------------------------------------------------------===//
140 // Multiclass helpers...
143 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
144 /// unary operation that produces a value. These are predicable and can be
145 /// changed to modify CPSR.
146 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
148 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
150 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
151 let isAsCheapAsAMove = Cheap;
152 let isReMaterializable = ReMat;
155 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
157 [(set GPR:$dst, (opnode GPR:$src))]>;
159 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
161 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
164 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
165 // binary operation that produces a value. These are predicable and can be
166 /// changed to modify CPSR.
167 multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
169 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
170 opc, " $dst, $lhs, $rhs",
171 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
173 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
174 opc, " $dst, $lhs, $rhs",
175 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
176 let isCommutable = Commutable;
179 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
180 opc, " $dst, $lhs, $rhs",
181 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
184 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
185 /// reversed. It doesn't define the 'rr' form since it's handled by its
186 /// T2I_bin_irs counterpart.
187 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
189 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
190 opc, " $dst, $rhs, $lhs",
191 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
193 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
194 opc, " $dst, $rhs, $lhs",
195 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
198 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
199 /// instruction modifies the CPSR register.
200 let Defs = [CPSR] in {
201 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
203 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
204 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
205 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
207 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
208 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
209 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
210 let isCommutable = Commutable;
213 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
214 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
215 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
219 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
220 /// patterns for a binary operation that produces a value.
221 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
223 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
224 opc, " $dst, $lhs, $rhs",
225 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
227 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
228 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
229 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
231 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
232 opc, " $dst, $lhs, $rhs",
233 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
234 let isCommutable = Commutable;
237 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
238 opc, " $dst, $lhs, $rhs",
239 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
242 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
243 /// binary operation that produces a value and use and define the carry bit.
244 /// It's not predicable.
245 let Uses = [CPSR] in {
246 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
248 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
249 opc, " $dst, $lhs, $rhs",
250 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
251 Requires<[IsThumb2, CarryDefIsUnused]>;
253 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
254 opc, " $dst, $lhs, $rhs",
255 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
256 Requires<[IsThumb2, CarryDefIsUnused]> {
257 let isCommutable = Commutable;
260 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
261 opc, " $dst, $lhs, $rhs",
262 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
263 Requires<[IsThumb2, CarryDefIsUnused]>;
264 // Carry setting variants
266 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
267 !strconcat(opc, "s $dst, $lhs, $rhs"),
268 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
269 Requires<[IsThumb2, CarryDefIsUsed]> {
273 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
274 !strconcat(opc, "s $dst, $lhs, $rhs"),
275 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
276 Requires<[IsThumb2, CarryDefIsUsed]> {
278 let isCommutable = Commutable;
281 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
282 !strconcat(opc, "s $dst, $lhs, $rhs"),
283 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
284 Requires<[IsThumb2, CarryDefIsUsed]> {
290 /// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
291 /// reversed. It doesn't define the 'rr' form since it's handled by its
292 /// T2I_adde_sube_irs counterpart.
293 let Defs = [CPSR], Uses = [CPSR] in {
294 multiclass T2I_rsc_is<string opc, PatFrag opnode> {
296 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
297 opc, " $dst, $rhs, $lhs",
298 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
299 Requires<[IsThumb2, CarryDefIsUnused]>;
301 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
302 opc, " $dst, $rhs, $lhs",
303 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
304 Requires<[IsThumb2, CarryDefIsUnused]>;
306 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
307 !strconcat(opc, "s $dst, $rhs, $lhs"),
308 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
309 Requires<[IsThumb2, CarryDefIsUsed]> {
313 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
314 !strconcat(opc, "s $dst, $rhs, $lhs"),
315 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
316 Requires<[IsThumb2, CarryDefIsUsed]> {
322 /// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
323 /// reversed. It doesn't define the 'rr' form since it's handled by its
324 /// T2I_bin_s_irs counterpart.
325 let Defs = [CPSR] in {
326 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
328 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
329 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
330 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
332 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
333 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
334 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
338 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
339 // rotate operation that produces a value.
340 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
342 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
343 opc, " $dst, $lhs, $rhs",
344 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
346 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
347 opc, " $dst, $lhs, $rhs",
348 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
351 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
352 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
353 /// a explicit result, only implicitly set CPSR.
354 let Defs = [CPSR] in {
355 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
357 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
359 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
361 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
363 [(opnode GPR:$lhs, GPR:$rhs)]>;
365 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
367 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
371 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
372 multiclass T2I_ld<string opc, PatFrag opnode> {
373 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
375 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
376 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
378 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
379 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
381 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
382 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
384 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
387 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
388 multiclass T2I_st<string opc, PatFrag opnode> {
389 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
391 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
392 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
394 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
395 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
397 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
400 /// T2I_picld - Defines the PIC load pattern.
401 class T2I_picld<string opc, PatFrag opnode> :
402 T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
403 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
404 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
406 /// T2I_picst - Defines the PIC store pattern.
407 class T2I_picst<string opc, PatFrag opnode> :
408 T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
409 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
410 [(opnode GPR:$src, addrmodepc:$addr)]>;
413 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
414 /// register and one whose operand is a register rotated by 8/16/24.
415 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
416 def r : T2I<(outs GPR:$dst), (ins GPR:$Src),
418 [(set GPR:$dst, (opnode GPR:$Src))]>;
419 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
420 opc, " $dst, $Src, ror $rot",
421 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
424 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
425 /// register and one whose operand is a register rotated by 8/16/24.
426 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
427 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
428 opc, " $dst, $LHS, $RHS",
429 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
430 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
431 opc, " $dst, $LHS, $RHS, ror $rot",
432 [(set GPR:$dst, (opnode GPR:$LHS,
433 (rotr GPR:$RHS, rot_imm:$rot)))]>;
436 //===----------------------------------------------------------------------===//
438 //===----------------------------------------------------------------------===//
440 //===----------------------------------------------------------------------===//
441 // Miscellaneous Instructions.
444 let isNotDuplicable = 1 in
445 def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
446 "$cp:\n\tadd $dst, pc",
447 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
450 // LEApcrel - Load a pc-relative address into a register without offending the
452 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
453 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
454 "${:private}PCRELL${:uid}+8))\n"),
455 !strconcat("${:private}PCRELL${:uid}:\n\t",
456 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
459 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
460 (ins i32imm:$label, i32imm:$id, pred:$p),
461 !strconcat(!strconcat(".set ${:private}PCRELV${:uid},"
462 " (${label}_${id:no_hash}-(",
463 "${:private}PCRELL${:uid}+8))\n"),
464 !strconcat("${:private}PCRELL${:uid}:\n\t",
465 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
468 // ADD rd, sp, #so_imm
469 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
470 "add $dst, $sp, $imm",
473 // ADD rd, sp, #imm12
474 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
475 "addw $dst, $sp, $imm",
478 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
479 "addw $dst, $sp, $rhs",
483 //===----------------------------------------------------------------------===//
484 // Load / store Instructions.
488 let canFoldAsLoad = 1 in
489 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
491 // Loads with zero extension
492 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
493 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
495 // Loads with sign extension
496 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
497 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
501 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
502 "ldrd", " $dst, $addr", []>;
503 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
504 "ldrd", " $dst, $addr", []>;
507 // zextload i1 -> zextload i8
508 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
509 (t2LDRBi12 t2addrmode_imm12:$addr)>;
510 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
511 (t2LDRBi8 t2addrmode_imm8:$addr)>;
512 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
513 (t2LDRBs t2addrmode_so_reg:$addr)>;
514 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
515 (t2LDRBpci tconstpool:$addr)>;
517 // extload -> zextload
518 // FIXME: Reduce the number of patterns by legalizing extload to zextload
520 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
521 (t2LDRBi12 t2addrmode_imm12:$addr)>;
522 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
523 (t2LDRBi8 t2addrmode_imm8:$addr)>;
524 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
525 (t2LDRBs t2addrmode_so_reg:$addr)>;
526 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
527 (t2LDRBpci tconstpool:$addr)>;
529 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
530 (t2LDRBi12 t2addrmode_imm12:$addr)>;
531 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
532 (t2LDRBi8 t2addrmode_imm8:$addr)>;
533 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
534 (t2LDRBs t2addrmode_so_reg:$addr)>;
535 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
536 (t2LDRBpci tconstpool:$addr)>;
538 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
539 (t2LDRHi12 t2addrmode_imm12:$addr)>;
540 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
541 (t2LDRHi8 t2addrmode_imm8:$addr)>;
542 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
543 (t2LDRHs t2addrmode_so_reg:$addr)>;
544 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
545 (t2LDRHpci tconstpool:$addr)>;
549 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
550 (ins t2addrmode_imm8:$addr),
551 AddrModeT2_i8, IndexModePre,
552 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
555 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
556 (ins GPR:$base, t2am_imm8_offset:$offset),
557 AddrModeT2_i8, IndexModePost,
558 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
561 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
562 (ins t2addrmode_imm8:$addr),
563 AddrModeT2_i8, IndexModePre,
564 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
566 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
567 (ins GPR:$base, t2am_imm8_offset:$offset),
568 AddrModeT2_i8, IndexModePost,
569 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
572 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
573 (ins t2addrmode_imm8:$addr),
574 AddrModeT2_i8, IndexModePre,
575 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
577 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
578 (ins GPR:$base, t2am_imm8_offset:$offset),
579 AddrModeT2_i8, IndexModePost,
580 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
583 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
584 (ins t2addrmode_imm8:$addr),
585 AddrModeT2_i8, IndexModePre,
586 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
588 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
589 (ins GPR:$base, t2am_imm8_offset:$offset),
590 AddrModeT2_i8, IndexModePost,
591 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
594 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
595 (ins t2addrmode_imm8:$addr),
596 AddrModeT2_i8, IndexModePre,
597 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
599 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
600 (ins GPR:$base, t2am_imm8_offset:$offset),
601 AddrModeT2_i8, IndexModePost,
602 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
607 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
608 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
609 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
613 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
614 "strd", " $src, $addr", []>;
617 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
618 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
619 AddrModeT2_i8, IndexModePre,
620 "str", " $src, [$base, $offset]!", "$base = $base_wb",
622 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
624 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
625 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
626 AddrModeT2_i8, IndexModePost,
627 "str", " $src, [$base], $offset", "$base = $base_wb",
629 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
631 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
632 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
633 AddrModeT2_i8, IndexModePre,
634 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
636 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
638 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
639 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
640 AddrModeT2_i8, IndexModePost,
641 "strh", " $src, [$base], $offset", "$base = $base_wb",
643 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
645 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
646 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
647 AddrModeT2_i8, IndexModePre,
648 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
650 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
652 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
653 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
654 AddrModeT2_i8, IndexModePost,
655 "strb", " $src, [$base], $offset", "$base = $base_wb",
657 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
660 // Address computation and loads and stores in PIC mode.
661 let isNotDuplicable = 1, AddedComplexity = 10 in {
662 let canFoldAsLoad = 1 in
663 def t2PICLDR : T2I_picld<"ldr", UnOpFrag<(load node:$Src)>>;
665 def t2PICLDRH : T2I_picld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
666 def t2PICLDRB : T2I_picld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
667 def t2PICLDRSH : T2I_picld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
668 def t2PICLDRSB : T2I_picld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
670 def t2PICSTR : T2I_picst<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
671 def t2PICSTRH : T2I_picst<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
672 def t2PICSTRB : T2I_picst<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
673 } // isNotDuplicable = 1, AddedComplexity = 10
675 // FIXME: ldrd / strd pre / post variants
677 //===----------------------------------------------------------------------===//
678 // Load / store multiple Instructions.
682 def t2LDM : T2XI<(outs),
683 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
684 "ldm${addr:submode}${p} $addr, $dst1", []>;
687 def t2STM : T2XI<(outs),
688 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
689 "stm${addr:submode}${p} $addr, $src1", []>;
691 //===----------------------------------------------------------------------===//
692 // Move Instructions.
695 let neverHasSideEffects = 1 in
696 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
697 "mov", " $dst, $src", []>;
699 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
700 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
701 "mov", " $dst, $src",
702 [(set GPR:$dst, t2_so_imm:$src)]>;
704 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
705 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
706 "movw", " $dst, $src",
707 [(set GPR:$dst, imm0_65535:$src)]>;
709 // FIXME: Also available in ARM mode.
710 let Constraints = "$src = $dst" in
711 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
712 "movt", " $dst, $imm",
714 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
716 //===----------------------------------------------------------------------===//
717 // Extend Instructions.
722 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
723 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
725 defm t2SXTAB : T2I_bin_rrot<"sxtab",
726 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
727 defm t2SXTAH : T2I_bin_rrot<"sxtah",
728 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
730 // TODO: SXT(A){B|H}16
734 let AddedComplexity = 16 in {
735 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
736 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
737 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
739 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
740 (t2UXTB16r_rot GPR:$Src, 24)>;
741 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
742 (t2UXTB16r_rot GPR:$Src, 8)>;
744 defm t2UXTAB : T2I_bin_rrot<"uxtab",
745 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
746 defm t2UXTAH : T2I_bin_rrot<"uxtah",
747 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
750 //===----------------------------------------------------------------------===//
751 // Arithmetic Instructions.
754 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
755 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
757 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
758 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
759 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
761 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
762 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
765 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
766 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
767 defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
769 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
770 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
771 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
772 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
773 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
776 //===----------------------------------------------------------------------===//
777 // Shift and rotate Instructions.
780 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
781 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
782 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
783 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
785 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
786 "mov", " $dst, $src, rrx",
787 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
789 //===----------------------------------------------------------------------===//
790 // Bitwise Instructions.
793 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
794 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
795 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
797 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
799 let Constraints = "$src = $dst" in
800 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
801 "bfc", " $dst, $imm",
802 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
804 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
806 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
808 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
809 let AddedComplexity = 1 in
810 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
813 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
814 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
816 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
817 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
819 def : T2Pat<(t2_so_imm_not:$src),
820 (t2MVNi t2_so_imm_not:$src)>;
822 //===----------------------------------------------------------------------===//
823 // Multiply Instructions.
825 let isCommutable = 1 in
826 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
827 "mul", " $dst, $a, $b",
828 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
830 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
831 "mla", " $dst, $a, $b, $c",
832 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
834 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
835 "mls", " $dst, $a, $b, $c",
836 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
838 // Extra precision multiplies with low / high results
839 let neverHasSideEffects = 1 in {
840 let isCommutable = 1 in {
841 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
842 "smull", " $ldst, $hdst, $a, $b", []>;
844 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
845 "umull", " $ldst, $hdst, $a, $b", []>;
848 // Multiply + accumulate
849 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
850 "smlal", " $ldst, $hdst, $a, $b", []>;
852 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
853 "umlal", " $ldst, $hdst, $a, $b", []>;
855 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
856 "umaal", " $ldst, $hdst, $a, $b", []>;
857 } // neverHasSideEffects
859 // Most significant word multiply
860 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
861 "smmul", " $dst, $a, $b",
862 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
864 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
865 "smmla", " $dst, $a, $b, $c",
866 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
869 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
870 "smmls", " $dst, $a, $b, $c",
871 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
873 multiclass T2I_smul<string opc, PatFrag opnode> {
874 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
875 !strconcat(opc, "bb"), " $dst, $a, $b",
876 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
877 (sext_inreg GPR:$b, i16)))]>;
879 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
880 !strconcat(opc, "bt"), " $dst, $a, $b",
881 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
882 (sra GPR:$b, (i32 16))))]>;
884 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
885 !strconcat(opc, "tb"), " $dst, $a, $b",
886 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
887 (sext_inreg GPR:$b, i16)))]>;
889 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
890 !strconcat(opc, "tt"), " $dst, $a, $b",
891 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
892 (sra GPR:$b, (i32 16))))]>;
894 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
895 !strconcat(opc, "wb"), " $dst, $a, $b",
896 [(set GPR:$dst, (sra (opnode GPR:$a,
897 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
899 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
900 !strconcat(opc, "wt"), " $dst, $a, $b",
901 [(set GPR:$dst, (sra (opnode GPR:$a,
902 (sra GPR:$b, (i32 16))), (i32 16)))]>;
906 multiclass T2I_smla<string opc, PatFrag opnode> {
907 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
908 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
909 [(set GPR:$dst, (add GPR:$acc,
910 (opnode (sext_inreg GPR:$a, i16),
911 (sext_inreg GPR:$b, i16))))]>;
913 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
914 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
915 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
916 (sra GPR:$b, (i32 16)))))]>;
918 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
919 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
920 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
921 (sext_inreg GPR:$b, i16))))]>;
923 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
924 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
925 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
926 (sra GPR:$b, (i32 16)))))]>;
928 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
929 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
930 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
931 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
933 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
934 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
935 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
936 (sra GPR:$b, (i32 16))), (i32 16))))]>;
939 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
940 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
942 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
943 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
946 //===----------------------------------------------------------------------===//
947 // Misc. Arithmetic Instructions.
950 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
951 "clz", " $dst, $src",
952 [(set GPR:$dst, (ctlz GPR:$src))]>;
954 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
955 "rev", " $dst, $src",
956 [(set GPR:$dst, (bswap GPR:$src))]>;
958 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
959 "rev16", " $dst, $src",
961 (or (and (srl GPR:$src, (i32 8)), 0xFF),
962 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
963 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
964 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
966 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
967 "revsh", " $dst, $src",
970 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
971 (shl GPR:$src, (i32 8))), i16))]>;
973 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
974 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
975 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
976 (and (shl GPR:$src2, (i32 imm:$shamt)),
979 // Alternate cases for PKHBT where identities eliminate some nodes.
980 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
981 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
982 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
983 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
985 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
986 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
987 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
988 (and (sra GPR:$src2, imm16_31:$shamt),
991 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
992 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
993 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
994 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
995 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
996 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
997 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
999 //===----------------------------------------------------------------------===//
1000 // Comparison Instructions...
1003 defm t2CMP : T2I_cmp_is<"cmp",
1004 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1005 defm t2CMPz : T2I_cmp_is<"cmp",
1006 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1008 defm t2CMN : T2I_cmp_is<"cmn",
1009 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1010 defm t2CMNz : T2I_cmp_is<"cmn",
1011 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1013 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1014 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1016 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1017 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1019 defm t2TST : T2I_cmp_is<"tst",
1020 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1021 defm t2TEQ : T2I_cmp_is<"teq",
1022 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1024 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1025 // Short range conditional branch. Looks awesome for loops. Need to figure
1026 // out how to use this one.
1029 // Conditional moves
1030 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1031 // a two-value operand where a dag node expects two operands. :(
1032 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
1033 "mov", " $dst, $true",
1034 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1035 RegConstraint<"$false = $dst">;
1037 def t2MOVCCs : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_reg:$true),
1038 "mov", " $dst, $true",
1039 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1040 RegConstraint<"$false = $dst">;
1042 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1043 "mov", " $dst, $true",
1044 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1045 RegConstraint<"$false = $dst">;
1047 //===----------------------------------------------------------------------===//
1051 // __aeabi_read_tp preserves the registers r1-r3.
1053 Defs = [R0, R12, LR, CPSR] in {
1054 def t2TPsoft : T2XI<(outs), (ins),
1055 "bl __aeabi_read_tp",
1056 [(set R0, ARMthread_pointer)]>;
1059 //===----------------------------------------------------------------------===//
1060 // Control-Flow Instructions
1063 // FIXME: remove when we have a way to marking a MI with these properties.
1064 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1066 // FIXME: Should pc be an implicit operand like PICADD, etc?
1067 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
1068 def t2LDM_RET : T2XI<(outs),
1069 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
1070 "ldm${addr:submode}${p} $addr, $dst1",
1073 // On non-Darwin platforms R9 is callee-saved.
1075 Defs = [R0, R1, R2, R3, R12, LR,
1076 D0, D1, D2, D3, D4, D5, D6, D7,
1077 D16, D17, D18, D19, D20, D21, D22, D23,
1078 D24, D25, D26, D27, D28, D29, D31, D31, CPSR] in {
1079 def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
1081 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
1083 def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
1085 [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
1088 // On Darwin R9 is call-clobbered.
1090 Defs = [R0, R1, R2, R3, R9, R12, LR,
1091 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1092 def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
1094 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
1096 def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
1098 [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
1101 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1102 let isPredicable = 1 in
1103 def t2B : T2XI<(outs), (ins brtarget:$target),
1107 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1108 def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1109 "mov pc, $target \n$jt",
1110 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1114 (ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id),
1115 "ldr pc, $target \n$jt",
1116 [(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt,
1121 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1122 "add pc, $target, $idx \n$jt",
1123 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>;
1124 } // isNotDuplicate, isIndirectBranch
1125 } // isBranch, isTerminator, isBarrier
1127 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1128 // a two-value operand where a dag node expects two operands. :(
1129 let isBranch = 1, isTerminator = 1 in
1130 def t2Bcc : T2I<(outs), (ins brtarget:$target),
1132 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1136 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1137 AddrModeNone, Size2Bytes,
1138 "it$mask $cc", "", []>;
1140 //===----------------------------------------------------------------------===//
1141 // Non-Instruction Patterns
1144 // ConstantPool, GlobalAddress, and JumpTable
1145 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1146 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1147 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1148 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1150 // Large immediate handling.
1152 def : T2Pat<(i32 imm:$src),
1153 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;