1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
15 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
18 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
19 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
20 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
21 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
23 //===----------------------------------------------------------------------===//
24 // Operand Definitions.
27 // 8-bit floating-point immediate encodings.
28 def FPImmOperand : AsmOperandClass {
30 let ParserMethod = "parseFPImm";
33 def vfp_f32imm : Operand<f32>,
34 PatLeaf<(f32 fpimm), [{
35 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
36 }], SDNodeXForm<fpimm, [{
37 APFloat InVal = N->getValueAPF();
38 uint32_t enc = ARM_AM::getFP32Imm(InVal);
39 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
41 let PrintMethod = "printFPImmOperand";
42 let ParserMatchClass = FPImmOperand;
45 def vfp_f64imm : Operand<f64>,
46 PatLeaf<(f64 fpimm), [{
47 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
48 }], SDNodeXForm<fpimm, [{
49 APFloat InVal = N->getValueAPF();
50 uint32_t enc = ARM_AM::getFP64Imm(InVal);
51 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
53 let PrintMethod = "printFPImmOperand";
54 let ParserMatchClass = FPImmOperand;
57 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
58 return cast<LoadSDNode>(N)->getAlignment() >= 4;
61 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
62 (store node:$val, node:$ptr), [{
63 return cast<StoreSDNode>(N)->getAlignment() >= 4;
66 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
67 // (the number of fixed bits) differently than it appears in the assembly
68 // source. It's encoded as "Size - fbits" where Size is the size of the
69 // fixed-point representation (32 or 16) and fbits is the value appearing
70 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
71 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
72 def fbits32 : Operand<i32> {
73 let PrintMethod = "printFBits32";
74 let ParserMatchClass = fbits32_asm_operand;
77 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
78 def fbits16 : Operand<i32> {
79 let PrintMethod = "printFBits16";
80 let ParserMatchClass = fbits16_asm_operand;
83 //===----------------------------------------------------------------------===//
84 // Load / store Instructions.
87 let canFoldAsLoad = 1, isReMaterializable = 1 in {
89 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
90 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
91 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
93 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
94 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
95 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> {
96 // Some single precision VFP instructions may be executed on both NEON and VFP
98 let D = VFPNeonDomain;
101 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
103 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
104 IIC_fpStore64, "vstr", "\t$Dd, $addr",
105 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
107 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
108 IIC_fpStore32, "vstr", "\t$Sd, $addr",
109 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> {
110 // Some single precision VFP instructions may be executed on both NEON and VFP
112 let D = VFPNeonDomain;
115 //===----------------------------------------------------------------------===//
116 // Load / store multiple Instructions.
119 multiclass vfp_ldst_mult<string asm, bit L_bit,
120 InstrItinClass itin, InstrItinClass itin_upd> {
123 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
125 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
126 let Inst{24-23} = 0b01; // Increment After
127 let Inst{21} = 0; // No writeback
128 let Inst{20} = L_bit;
131 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
133 IndexModeUpd, itin_upd,
134 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
135 let Inst{24-23} = 0b01; // Increment After
136 let Inst{21} = 1; // Writeback
137 let Inst{20} = L_bit;
140 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
142 IndexModeUpd, itin_upd,
143 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
144 let Inst{24-23} = 0b10; // Decrement Before
145 let Inst{21} = 1; // Writeback
146 let Inst{20} = L_bit;
151 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
153 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
154 let Inst{24-23} = 0b01; // Increment After
155 let Inst{21} = 0; // No writeback
156 let Inst{20} = L_bit;
158 // Some single precision VFP instructions may be executed on both NEON and
160 let D = VFPNeonDomain;
163 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
165 IndexModeUpd, itin_upd,
166 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
167 let Inst{24-23} = 0b01; // Increment After
168 let Inst{21} = 1; // Writeback
169 let Inst{20} = L_bit;
171 // Some single precision VFP instructions may be executed on both NEON and
173 let D = VFPNeonDomain;
176 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
178 IndexModeUpd, itin_upd,
179 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
180 let Inst{24-23} = 0b10; // Decrement Before
181 let Inst{21} = 1; // Writeback
182 let Inst{20} = L_bit;
184 // Some single precision VFP instructions may be executed on both NEON and
186 let D = VFPNeonDomain;
190 let hasSideEffects = 0 in {
192 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
193 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
195 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
196 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
200 def : MnemonicAlias<"vldm", "vldmia">;
201 def : MnemonicAlias<"vstm", "vstmia">;
203 // FLDM/FSTM - Load / Store multiple single / double precision registers for
205 // These instructions are deprecated!
206 def : VFP2MnemonicAlias<"fldmias", "vldmia">;
207 def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;
208 def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;
209 def : VFP2MnemonicAlias<"fldmfds", "vldmia">;
210 def : VFP2MnemonicAlias<"fldmiad", "vldmia">;
211 def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">;
212 def : VFP2MnemonicAlias<"fldmead", "vldmdb">;
213 def : VFP2MnemonicAlias<"fldmfdd", "vldmia">;
215 def : VFP2MnemonicAlias<"fstmias", "vstmia">;
216 def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">;
217 def : VFP2MnemonicAlias<"fstmeas", "vstmia">;
218 def : VFP2MnemonicAlias<"fstmfds", "vstmdb">;
219 def : VFP2MnemonicAlias<"fstmiad", "vstmia">;
220 def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;
221 def : VFP2MnemonicAlias<"fstmead", "vstmia">;
222 def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
224 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
226 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
228 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
230 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
232 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
233 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
234 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
235 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
236 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
237 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
238 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
239 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
241 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
243 // These instruction are deprecated so we don't want them to get selected.
244 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
247 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
248 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
249 let Inst{24-23} = 0b01; // Increment After
250 let Inst{21} = 0; // No writeback
251 let Inst{20} = L_bit;
254 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
255 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
256 let Inst{24-23} = 0b01; // Increment After
257 let Inst{21} = 1; // Writeback
258 let Inst{20} = L_bit;
261 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
262 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
263 let Inst{24-23} = 0b10; // Decrement Before
264 let Inst{21} = 1; // Writeback
265 let Inst{20} = L_bit;
269 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
270 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
272 def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;
273 def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;
275 def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;
276 def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;
278 //===----------------------------------------------------------------------===//
279 // FP Binary Operations.
282 let TwoOperandAliasConstraint = "$Dn = $Dd" in
283 def VADDD : ADbI<0b11100, 0b11, 0, 0,
284 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
285 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
286 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
288 let TwoOperandAliasConstraint = "$Sn = $Sd" in
289 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
290 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
291 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
292 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
293 // Some single precision VFP instructions may be executed on both NEON and
294 // VFP pipelines on A8.
295 let D = VFPNeonA8Domain;
298 let TwoOperandAliasConstraint = "$Dn = $Dd" in
299 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
300 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
301 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
302 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
304 let TwoOperandAliasConstraint = "$Sn = $Sd" in
305 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
306 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
307 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
308 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
309 // Some single precision VFP instructions may be executed on both NEON and
310 // VFP pipelines on A8.
311 let D = VFPNeonA8Domain;
314 let TwoOperandAliasConstraint = "$Dn = $Dd" in
315 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
316 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
317 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
318 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
320 let TwoOperandAliasConstraint = "$Sn = $Sd" in
321 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
322 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
323 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
324 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
326 let TwoOperandAliasConstraint = "$Dn = $Dd" in
327 def VMULD : ADbI<0b11100, 0b10, 0, 0,
328 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
329 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
330 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
332 let TwoOperandAliasConstraint = "$Sn = $Sd" in
333 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
334 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
335 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
336 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
337 // Some single precision VFP instructions may be executed on both NEON and
338 // VFP pipelines on A8.
339 let D = VFPNeonA8Domain;
342 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
343 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
344 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
345 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
347 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
348 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
349 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
350 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
351 // Some single precision VFP instructions may be executed on both NEON and
352 // VFP pipelines on A8.
353 let D = VFPNeonA8Domain;
356 multiclass vsel_inst<string op, bits<2> opc, int CC> {
357 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
358 Uses = [CPSR], AddedComplexity = 4 in {
359 def S : ASbInp<0b11100, opc, 0,
360 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
361 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
362 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
363 Requires<[HasFPARMv8]>;
365 def D : ADbInp<0b11100, opc, 0,
366 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
367 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
368 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
369 Requires<[HasFPARMv8, HasDPVFP]>;
373 // The CC constants here match ARMCC::CondCodes.
374 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
375 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
376 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
377 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
379 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
380 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
381 def S : ASbInp<0b11101, 0b00, opc,
382 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
383 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
384 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
385 Requires<[HasFPARMv8]>;
387 def D : ADbInp<0b11101, 0b00, opc,
388 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
389 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
390 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
391 Requires<[HasFPARMv8, HasDPVFP]>;
395 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>;
396 defm VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>;
398 // Match reassociated forms only if not sign dependent rounding.
399 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
400 (VNMULD DPR:$a, DPR:$b)>,
401 Requires<[NoHonorSignDependentRounding,HasDPVFP]>;
402 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
403 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
405 // These are encoded as unary instructions.
406 let Defs = [FPSCR_NZCV] in {
407 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
408 (outs), (ins DPR:$Dd, DPR:$Dm),
409 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
410 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
412 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
413 (outs), (ins SPR:$Sd, SPR:$Sm),
414 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
415 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
416 // Some single precision VFP instructions may be executed on both NEON and
417 // VFP pipelines on A8.
418 let D = VFPNeonA8Domain;
421 // FIXME: Verify encoding after integrated assembler is working.
422 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
423 (outs), (ins DPR:$Dd, DPR:$Dm),
424 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
425 [/* For disassembly only; pattern left blank */]>;
427 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
428 (outs), (ins SPR:$Sd, SPR:$Sm),
429 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
430 [/* For disassembly only; pattern left blank */]> {
431 // Some single precision VFP instructions may be executed on both NEON and
432 // VFP pipelines on A8.
433 let D = VFPNeonA8Domain;
435 } // Defs = [FPSCR_NZCV]
437 //===----------------------------------------------------------------------===//
438 // FP Unary Operations.
441 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
442 (outs DPR:$Dd), (ins DPR:$Dm),
443 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
444 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
446 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
447 (outs SPR:$Sd), (ins SPR:$Sm),
448 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
449 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
450 // Some single precision VFP instructions may be executed on both NEON and
451 // VFP pipelines on A8.
452 let D = VFPNeonA8Domain;
455 let Defs = [FPSCR_NZCV] in {
456 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
457 (outs), (ins DPR:$Dd),
458 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
459 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
460 let Inst{3-0} = 0b0000;
464 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
465 (outs), (ins SPR:$Sd),
466 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
467 [(arm_cmpfp0 SPR:$Sd)]> {
468 let Inst{3-0} = 0b0000;
471 // Some single precision VFP instructions may be executed on both NEON and
472 // VFP pipelines on A8.
473 let D = VFPNeonA8Domain;
476 // FIXME: Verify encoding after integrated assembler is working.
477 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
478 (outs), (ins DPR:$Dd),
479 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
480 [/* For disassembly only; pattern left blank */]> {
481 let Inst{3-0} = 0b0000;
485 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
486 (outs), (ins SPR:$Sd),
487 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
488 [/* For disassembly only; pattern left blank */]> {
489 let Inst{3-0} = 0b0000;
492 // Some single precision VFP instructions may be executed on both NEON and
493 // VFP pipelines on A8.
494 let D = VFPNeonA8Domain;
496 } // Defs = [FPSCR_NZCV]
498 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
499 (outs DPR:$Dd), (ins SPR:$Sm),
500 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
501 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
502 // Instruction operands.
506 // Encode instruction operands.
507 let Inst{3-0} = Sm{4-1};
509 let Inst{15-12} = Dd{3-0};
510 let Inst{22} = Dd{4};
512 let Predicates = [HasVFP2, HasDPVFP];
515 // Special case encoding: bits 11-8 is 0b1011.
516 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
517 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
518 [(set SPR:$Sd, (fround DPR:$Dm))]> {
519 // Instruction operands.
523 // Encode instruction operands.
524 let Inst{3-0} = Dm{3-0};
526 let Inst{15-12} = Sd{4-1};
527 let Inst{22} = Sd{0};
529 let Inst{27-23} = 0b11101;
530 let Inst{21-16} = 0b110111;
531 let Inst{11-8} = 0b1011;
532 let Inst{7-6} = 0b11;
535 let Predicates = [HasVFP2, HasDPVFP];
538 // Between half, single and double-precision. For disassembly only.
540 // FIXME: Verify encoding after integrated assembler is working.
541 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
542 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
543 [/* For disassembly only; pattern left blank */]>,
546 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
547 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
548 [/* For disassembly only; pattern left blank */]>,
551 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
552 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
553 [/* For disassembly only; pattern left blank */]>,
556 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
557 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
558 [/* For disassembly only; pattern left blank */]>,
561 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
562 (outs DPR:$Dd), (ins SPR:$Sm),
563 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
564 []>, Requires<[HasFPARMv8, HasDPVFP]> {
565 // Instruction operands.
568 // Encode instruction operands.
569 let Inst{3-0} = Sm{4-1};
573 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
574 (outs SPR:$Sd), (ins DPR:$Dm),
575 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
576 []>, Requires<[HasFPARMv8, HasDPVFP]> {
577 // Instruction operands.
581 // Encode instruction operands.
582 let Inst{3-0} = Dm{3-0};
584 let Inst{15-12} = Sd{4-1};
585 let Inst{22} = Sd{0};
588 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
589 (outs DPR:$Dd), (ins SPR:$Sm),
590 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
591 []>, Requires<[HasFPARMv8, HasDPVFP]> {
592 // Instruction operands.
595 // Encode instruction operands.
596 let Inst{3-0} = Sm{4-1};
600 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
601 (outs SPR:$Sd), (ins DPR:$Dm),
602 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
603 []>, Requires<[HasFPARMv8, HasDPVFP]> {
604 // Instruction operands.
608 // Encode instruction operands.
609 let Inst{15-12} = Sd{4-1};
610 let Inst{22} = Sd{0};
611 let Inst{3-0} = Dm{3-0};
615 def : Pat<(fp_to_f16 SPR:$a),
616 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
618 def : Pat<(fp_to_f16 (f64 DPR:$a)),
619 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
621 def : Pat<(f16_to_fp GPR:$a),
622 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
624 def : Pat<(f64 (f16_to_fp GPR:$a)),
625 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
627 multiclass vcvt_inst<string opc, bits<2> rm,
628 SDPatternOperator node = null_frag> {
629 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
630 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
631 (outs SPR:$Sd), (ins SPR:$Sm),
632 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
634 Requires<[HasFPARMv8]> {
635 let Inst{17-16} = rm;
638 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
639 (outs SPR:$Sd), (ins SPR:$Sm),
640 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
642 Requires<[HasFPARMv8]> {
643 let Inst{17-16} = rm;
646 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
647 (outs SPR:$Sd), (ins DPR:$Dm),
648 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
650 Requires<[HasFPARMv8, HasDPVFP]> {
653 let Inst{17-16} = rm;
655 // Encode instruction operands
656 let Inst{3-0} = Dm{3-0};
661 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
662 (outs SPR:$Sd), (ins DPR:$Dm),
663 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
665 Requires<[HasFPARMv8, HasDPVFP]> {
668 let Inst{17-16} = rm;
670 // Encode instruction operands
671 let Inst{3-0} = Dm{3-0};
677 let Predicates = [HasFPARMv8] in {
678 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
680 (!cast<Instruction>(NAME#"SS") SPR:$a),
682 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
684 (!cast<Instruction>(NAME#"US") SPR:$a),
687 let Predicates = [HasFPARMv8, HasDPVFP] in {
688 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))),
690 (!cast<Instruction>(NAME#"SD") DPR:$a),
692 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))),
694 (!cast<Instruction>(NAME#"UD") DPR:$a),
699 defm VCVTA : vcvt_inst<"a", 0b00, frnd>;
700 defm VCVTN : vcvt_inst<"n", 0b01>;
701 defm VCVTP : vcvt_inst<"p", 0b10, fceil>;
702 defm VCVTM : vcvt_inst<"m", 0b11, ffloor>;
704 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
705 (outs DPR:$Dd), (ins DPR:$Dm),
706 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
707 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
709 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
710 (outs SPR:$Sd), (ins SPR:$Sm),
711 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
712 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
713 // Some single precision VFP instructions may be executed on both NEON and
714 // VFP pipelines on A8.
715 let D = VFPNeonA8Domain;
718 multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
719 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
720 (outs SPR:$Sd), (ins SPR:$Sm),
721 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
722 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
723 Requires<[HasFPARMv8]> {
727 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
728 (outs DPR:$Dd), (ins DPR:$Dm),
729 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
730 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
731 Requires<[HasFPARMv8, HasDPVFP]> {
736 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
737 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
738 Requires<[HasFPARMv8]>;
739 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
740 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
741 Requires<[HasFPARMv8,HasDPVFP]>;
744 defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>;
745 defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>;
746 defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
748 multiclass vrint_inst_anpm<string opc, bits<2> rm,
749 SDPatternOperator node = null_frag> {
750 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
751 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
752 (outs SPR:$Sd), (ins SPR:$Sm),
753 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
754 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
755 Requires<[HasFPARMv8]> {
756 let Inst{17-16} = rm;
758 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
759 (outs DPR:$Dd), (ins DPR:$Dm),
760 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
761 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
762 Requires<[HasFPARMv8, HasDPVFP]> {
763 let Inst{17-16} = rm;
767 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
768 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
769 Requires<[HasFPARMv8]>;
770 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
771 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
772 Requires<[HasFPARMv8,HasDPVFP]>;
775 defm VRINTA : vrint_inst_anpm<"a", 0b00, frnd>;
776 defm VRINTN : vrint_inst_anpm<"n", 0b01>;
777 defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>;
778 defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>;
780 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
781 (outs DPR:$Dd), (ins DPR:$Dm),
782 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
783 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
785 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
786 (outs SPR:$Sd), (ins SPR:$Sm),
787 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
788 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
790 let hasSideEffects = 0 in {
791 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
792 (outs DPR:$Dd), (ins DPR:$Dm),
793 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
795 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
796 (outs SPR:$Sd), (ins SPR:$Sm),
797 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
800 //===----------------------------------------------------------------------===//
801 // FP <-> GPR Copies. Int <-> FP Conversions.
804 def VMOVRS : AVConv2I<0b11100001, 0b1010,
805 (outs GPR:$Rt), (ins SPR:$Sn),
806 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
807 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
808 // Instruction operands.
812 // Encode instruction operands.
813 let Inst{19-16} = Sn{4-1};
815 let Inst{15-12} = Rt;
817 let Inst{6-5} = 0b00;
818 let Inst{3-0} = 0b0000;
820 // Some single precision VFP instructions may be executed on both NEON and VFP
822 let D = VFPNeonDomain;
825 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
826 def VMOVSR : AVConv4I<0b11100000, 0b1010,
827 (outs SPR:$Sn), (ins GPR:$Rt),
828 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
829 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
830 Requires<[HasVFP2, UseVMOVSR]> {
831 // Instruction operands.
835 // Encode instruction operands.
836 let Inst{19-16} = Sn{4-1};
838 let Inst{15-12} = Rt;
840 let Inst{6-5} = 0b00;
841 let Inst{3-0} = 0b0000;
843 // Some single precision VFP instructions may be executed on both NEON and VFP
845 let D = VFPNeonDomain;
848 let hasSideEffects = 0 in {
849 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
850 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
851 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
852 [/* FIXME: Can't write pattern for multiple result instr*/]> {
853 // Instruction operands.
858 // Encode instruction operands.
859 let Inst{3-0} = Dm{3-0};
861 let Inst{15-12} = Rt;
862 let Inst{19-16} = Rt2;
864 let Inst{7-6} = 0b00;
866 // Some single precision VFP instructions may be executed on both NEON and VFP
868 let D = VFPNeonDomain;
870 // This instruction is equivalent to
871 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
872 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
873 let isExtractSubreg = 1;
876 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
877 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
878 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
879 [/* For disassembly only; pattern left blank */]> {
884 // Encode instruction operands.
885 let Inst{3-0} = src1{4-1};
886 let Inst{5} = src1{0};
887 let Inst{15-12} = Rt;
888 let Inst{19-16} = Rt2;
890 let Inst{7-6} = 0b00;
892 // Some single precision VFP instructions may be executed on both NEON and VFP
894 let D = VFPNeonDomain;
895 let DecoderMethod = "DecodeVMOVRRS";
902 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
903 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
904 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
905 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
906 // Instruction operands.
911 // Encode instruction operands.
912 let Inst{3-0} = Dm{3-0};
914 let Inst{15-12} = Rt;
915 let Inst{19-16} = Rt2;
917 let Inst{7-6} = 0b00;
919 // Some single precision VFP instructions may be executed on both NEON and VFP
921 let D = VFPNeonDomain;
923 // This instruction is equivalent to
924 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
925 let isRegSequence = 1;
928 // Hoist an fabs or a fneg of a value coming from integer registers
929 // and do the fabs/fneg on the integer value. This is never a lose
930 // and could enable the conversion to float to be removed completely.
931 def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),
932 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
934 def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),
935 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
936 Requires<[IsThumb2]>;
937 def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),
938 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
940 def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),
941 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
942 Requires<[IsThumb2]>;
944 let hasSideEffects = 0 in
945 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
946 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
947 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
948 [/* For disassembly only; pattern left blank */]> {
949 // Instruction operands.
954 // Encode instruction operands.
955 let Inst{3-0} = dst1{4-1};
956 let Inst{5} = dst1{0};
957 let Inst{15-12} = src1;
958 let Inst{19-16} = src2;
960 let Inst{7-6} = 0b00;
962 // Some single precision VFP instructions may be executed on both NEON and VFP
964 let D = VFPNeonDomain;
966 let DecoderMethod = "DecodeVMOVSRR";
972 // FMRX: SPR system reg -> GPR
974 // FMXR: GPR -> VFP system reg
979 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
980 bits<4> opcod4, dag oops, dag iops,
981 InstrItinClass itin, string opc, string asm,
983 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
985 // Instruction operands.
989 // Encode instruction operands.
990 let Inst{3-0} = Sm{4-1};
992 let Inst{15-12} = Dd{3-0};
993 let Inst{22} = Dd{4};
995 let Predicates = [HasVFP2, HasDPVFP];
998 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
999 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
1000 string opc, string asm, list<dag> pattern>
1001 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1003 // Instruction operands.
1007 // Encode instruction operands.
1008 let Inst{3-0} = Sm{4-1};
1009 let Inst{5} = Sm{0};
1010 let Inst{15-12} = Sd{4-1};
1011 let Inst{22} = Sd{0};
1014 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1015 (outs DPR:$Dd), (ins SPR:$Sm),
1016 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
1018 let Inst{7} = 1; // s32
1021 let Predicates=[HasVFP2, HasDPVFP] in {
1022 def : VFPPat<(f64 (sint_to_fp GPR:$a)),
1023 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1025 def : VFPPat<(f64 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1026 (VSITOD (VLDRS addrmode5:$a))>;
1029 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1030 (outs SPR:$Sd),(ins SPR:$Sm),
1031 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1033 let Inst{7} = 1; // s32
1035 // Some single precision VFP instructions may be executed on both NEON and
1036 // VFP pipelines on A8.
1037 let D = VFPNeonA8Domain;
1040 def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)),
1041 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1043 def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1044 (VSITOS (VLDRS addrmode5:$a))>;
1046 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1047 (outs DPR:$Dd), (ins SPR:$Sm),
1048 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
1050 let Inst{7} = 0; // u32
1053 let Predicates=[HasVFP2, HasDPVFP] in {
1054 def : VFPPat<(f64 (uint_to_fp GPR:$a)),
1055 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1057 def : VFPPat<(f64 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1058 (VUITOD (VLDRS addrmode5:$a))>;
1061 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1062 (outs SPR:$Sd), (ins SPR:$Sm),
1063 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1065 let Inst{7} = 0; // u32
1067 // Some single precision VFP instructions may be executed on both NEON and
1068 // VFP pipelines on A8.
1069 let D = VFPNeonA8Domain;
1072 def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)),
1073 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1075 def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1076 (VUITOS (VLDRS addrmode5:$a))>;
1080 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1081 bits<4> opcod4, dag oops, dag iops,
1082 InstrItinClass itin, string opc, string asm,
1084 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1086 // Instruction operands.
1090 // Encode instruction operands.
1091 let Inst{3-0} = Dm{3-0};
1092 let Inst{5} = Dm{4};
1093 let Inst{15-12} = Sd{4-1};
1094 let Inst{22} = Sd{0};
1096 let Predicates = [HasVFP2, HasDPVFP];
1099 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1100 bits<4> opcod4, dag oops, dag iops,
1101 InstrItinClass itin, string opc, string asm,
1103 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1105 // Instruction operands.
1109 // Encode instruction operands.
1110 let Inst{3-0} = Sm{4-1};
1111 let Inst{5} = Sm{0};
1112 let Inst{15-12} = Sd{4-1};
1113 let Inst{22} = Sd{0};
1116 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
1117 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1118 (outs SPR:$Sd), (ins DPR:$Dm),
1119 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1121 let Inst{7} = 1; // Z bit
1124 let Predicates=[HasVFP2, HasDPVFP] in {
1125 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
1126 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
1128 def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
1129 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
1132 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1133 (outs SPR:$Sd), (ins SPR:$Sm),
1134 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1136 let Inst{7} = 1; // Z bit
1138 // Some single precision VFP instructions may be executed on both NEON and
1139 // VFP pipelines on A8.
1140 let D = VFPNeonA8Domain;
1143 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1144 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1146 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
1148 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1150 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1151 (outs SPR:$Sd), (ins DPR:$Dm),
1152 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1154 let Inst{7} = 1; // Z bit
1157 let Predicates=[HasVFP2, HasDPVFP] in {
1158 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
1159 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
1161 def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
1162 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
1165 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1166 (outs SPR:$Sd), (ins SPR:$Sm),
1167 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1169 let Inst{7} = 1; // Z bit
1171 // Some single precision VFP instructions may be executed on both NEON and
1172 // VFP pipelines on A8.
1173 let D = VFPNeonA8Domain;
1176 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1177 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1179 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
1181 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1183 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1184 let Uses = [FPSCR] in {
1185 // FIXME: Verify encoding after integrated assembler is working.
1186 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1187 (outs SPR:$Sd), (ins DPR:$Dm),
1188 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1189 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1190 let Inst{7} = 0; // Z bit
1193 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1194 (outs SPR:$Sd), (ins SPR:$Sm),
1195 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1196 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1197 let Inst{7} = 0; // Z bit
1200 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1201 (outs SPR:$Sd), (ins DPR:$Dm),
1202 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1203 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1204 let Inst{7} = 0; // Z bit
1207 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1208 (outs SPR:$Sd), (ins SPR:$Sm),
1209 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1210 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1211 let Inst{7} = 0; // Z bit
1215 // Convert between floating-point and fixed-point
1216 // Data type for fixed-point naming convention:
1217 // S16 (U=0, sx=0) -> SH
1218 // U16 (U=1, sx=0) -> UH
1219 // S32 (U=0, sx=1) -> SL
1220 // U32 (U=1, sx=1) -> UL
1222 let Constraints = "$a = $dst" in {
1224 // FP to Fixed-Point:
1226 // Single Precision register
1227 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1228 bit op5, dag oops, dag iops, InstrItinClass itin,
1229 string opc, string asm, list<dag> pattern>
1230 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1231 Sched<[WriteCvtFP]> {
1233 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1234 let Inst{22} = dst{0};
1235 let Inst{15-12} = dst{4-1};
1238 // Double Precision register
1239 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1240 bit op5, dag oops, dag iops, InstrItinClass itin,
1241 string opc, string asm, list<dag> pattern>
1242 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1243 Sched<[WriteCvtFP]> {
1245 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1246 let Inst{22} = dst{4};
1247 let Inst{15-12} = dst{3-0};
1249 let Predicates = [HasVFP2, HasDPVFP];
1252 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1253 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1254 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1255 // Some single precision VFP instructions may be executed on both NEON and
1256 // VFP pipelines on A8.
1257 let D = VFPNeonA8Domain;
1260 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1261 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1262 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1263 // Some single precision VFP instructions may be executed on both NEON and
1264 // VFP pipelines on A8.
1265 let D = VFPNeonA8Domain;
1268 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1269 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1270 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1271 // Some single precision VFP instructions may be executed on both NEON and
1272 // VFP pipelines on A8.
1273 let D = VFPNeonA8Domain;
1276 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1277 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1278 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1279 // Some single precision VFP instructions may be executed on both NEON and
1280 // VFP pipelines on A8.
1281 let D = VFPNeonA8Domain;
1284 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1285 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1286 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1288 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1289 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1290 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1292 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1293 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1294 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1296 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1297 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1298 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1300 // Fixed-Point to FP:
1302 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1303 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1304 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1305 // Some single precision VFP instructions may be executed on both NEON and
1306 // VFP pipelines on A8.
1307 let D = VFPNeonA8Domain;
1310 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1311 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1312 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1313 // Some single precision VFP instructions may be executed on both NEON and
1314 // VFP pipelines on A8.
1315 let D = VFPNeonA8Domain;
1318 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1319 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1320 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1321 // Some single precision VFP instructions may be executed on both NEON and
1322 // VFP pipelines on A8.
1323 let D = VFPNeonA8Domain;
1326 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1327 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1328 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1329 // Some single precision VFP instructions may be executed on both NEON and
1330 // VFP pipelines on A8.
1331 let D = VFPNeonA8Domain;
1334 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1335 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1336 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1338 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1339 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1340 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1342 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1343 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1344 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1346 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1347 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1348 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1350 } // End of 'let Constraints = "$a = $dst" in'
1352 //===----------------------------------------------------------------------===//
1353 // FP Multiply-Accumulate Operations.
1356 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1357 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1358 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1359 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1360 (f64 DPR:$Ddin)))]>,
1361 RegConstraint<"$Ddin = $Dd">,
1362 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1364 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1365 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1366 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1367 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1369 RegConstraint<"$Sdin = $Sd">,
1370 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1371 // Some single precision VFP instructions may be executed on both NEON and
1372 // VFP pipelines on A8.
1373 let D = VFPNeonA8Domain;
1376 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1377 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1378 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1379 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1380 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1381 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1383 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1384 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1385 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1386 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1387 (f64 DPR:$Ddin)))]>,
1388 RegConstraint<"$Ddin = $Dd">,
1389 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1391 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1392 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1393 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1394 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1396 RegConstraint<"$Sdin = $Sd">,
1397 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1398 // Some single precision VFP instructions may be executed on both NEON and
1399 // VFP pipelines on A8.
1400 let D = VFPNeonA8Domain;
1403 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1404 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1405 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1406 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1407 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1408 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1410 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1411 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1412 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1413 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1414 (f64 DPR:$Ddin)))]>,
1415 RegConstraint<"$Ddin = $Dd">,
1416 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1418 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1419 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1420 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1421 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1423 RegConstraint<"$Sdin = $Sd">,
1424 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1425 // Some single precision VFP instructions may be executed on both NEON and
1426 // VFP pipelines on A8.
1427 let D = VFPNeonA8Domain;
1430 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1431 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1432 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1433 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1434 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1435 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1437 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1438 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1439 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1440 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1441 (f64 DPR:$Ddin)))]>,
1442 RegConstraint<"$Ddin = $Dd">,
1443 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1445 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1446 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1447 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1448 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1449 RegConstraint<"$Sdin = $Sd">,
1450 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1451 // Some single precision VFP instructions may be executed on both NEON and
1452 // VFP pipelines on A8.
1453 let D = VFPNeonA8Domain;
1456 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1457 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1458 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1459 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1460 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1461 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1463 //===----------------------------------------------------------------------===//
1464 // Fused FP Multiply-Accumulate Operations.
1466 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1467 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1468 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1469 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1470 (f64 DPR:$Ddin)))]>,
1471 RegConstraint<"$Ddin = $Dd">,
1472 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1474 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1475 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1476 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1477 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1479 RegConstraint<"$Sdin = $Sd">,
1480 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1481 // Some single precision VFP instructions may be executed on both NEON and
1485 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1486 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1487 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1488 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1489 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1490 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1492 // Match @llvm.fma.* intrinsics
1493 // (fma x, y, z) -> (vfms z, x, y)
1494 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1495 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1496 Requires<[HasVFP4,HasDPVFP]>;
1497 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1498 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1499 Requires<[HasVFP4]>;
1501 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1502 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1503 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1504 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1505 (f64 DPR:$Ddin)))]>,
1506 RegConstraint<"$Ddin = $Dd">,
1507 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1509 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1510 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1511 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1512 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1514 RegConstraint<"$Sdin = $Sd">,
1515 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1516 // Some single precision VFP instructions may be executed on both NEON and
1520 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1521 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1522 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1523 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1524 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1525 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1527 // Match @llvm.fma.* intrinsics
1528 // (fma (fneg x), y, z) -> (vfms z, x, y)
1529 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1530 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1531 Requires<[HasVFP4,HasDPVFP]>;
1532 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1533 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1534 Requires<[HasVFP4]>;
1535 // (fma x, (fneg y), z) -> (vfms z, x, y)
1536 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1537 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1538 Requires<[HasVFP4,HasDPVFP]>;
1539 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1540 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1541 Requires<[HasVFP4]>;
1543 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1544 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1545 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1546 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1547 (f64 DPR:$Ddin)))]>,
1548 RegConstraint<"$Ddin = $Dd">,
1549 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1551 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1552 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1553 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1554 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1556 RegConstraint<"$Sdin = $Sd">,
1557 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1558 // Some single precision VFP instructions may be executed on both NEON and
1562 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1563 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1564 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1565 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1566 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1567 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1569 // Match @llvm.fma.* intrinsics
1570 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1571 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1572 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1573 Requires<[HasVFP4,HasDPVFP]>;
1574 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1575 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1576 Requires<[HasVFP4]>;
1577 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1578 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1579 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1580 Requires<[HasVFP4,HasDPVFP]>;
1581 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1582 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1583 Requires<[HasVFP4]>;
1585 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1586 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1587 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1588 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1589 (f64 DPR:$Ddin)))]>,
1590 RegConstraint<"$Ddin = $Dd">,
1591 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1593 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1594 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1595 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1596 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1597 RegConstraint<"$Sdin = $Sd">,
1598 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1599 // Some single precision VFP instructions may be executed on both NEON and
1603 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1604 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1605 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1606 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1607 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1608 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1610 // Match @llvm.fma.* intrinsics
1612 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1613 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1614 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1615 Requires<[HasVFP4,HasDPVFP]>;
1616 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1617 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1618 Requires<[HasVFP4]>;
1619 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1620 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1621 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1622 Requires<[HasVFP4,HasDPVFP]>;
1623 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1624 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1625 Requires<[HasVFP4]>;
1626 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1627 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1628 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1629 Requires<[HasVFP4,HasDPVFP]>;
1630 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1631 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1632 Requires<[HasVFP4]>;
1634 //===----------------------------------------------------------------------===//
1635 // FP Conditional moves.
1638 let hasSideEffects = 0 in {
1639 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
1641 [(set (f64 DPR:$Dd),
1642 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1643 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>;
1645 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1647 [(set (f32 SPR:$Sd),
1648 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1649 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
1652 //===----------------------------------------------------------------------===//
1653 // Move from VFP System Register to ARM core register.
1656 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1658 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1660 // Instruction operand.
1663 let Inst{27-20} = 0b11101111;
1664 let Inst{19-16} = opc19_16;
1665 let Inst{15-12} = Rt;
1666 let Inst{11-8} = 0b1010;
1668 let Inst{6-5} = 0b00;
1670 let Inst{3-0} = 0b0000;
1673 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1675 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1676 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1677 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1679 // Application level FPSCR -> GPR
1680 let hasSideEffects = 1, Uses = [FPSCR] in
1681 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1682 "vmrs", "\t$Rt, fpscr",
1683 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1685 // System level FPEXC, FPSID -> GPR
1686 let Uses = [FPSCR] in {
1687 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1688 "vmrs", "\t$Rt, fpexc", []>;
1689 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1690 "vmrs", "\t$Rt, fpsid", []>;
1691 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1692 "vmrs", "\t$Rt, mvfr0", []>;
1693 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1694 "vmrs", "\t$Rt, mvfr1", []>;
1695 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
1696 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
1697 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1698 "vmrs", "\t$Rt, fpinst", []>;
1699 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1700 "vmrs", "\t$Rt, fpinst2", []>;
1703 //===----------------------------------------------------------------------===//
1704 // Move from ARM core register to VFP System Register.
1707 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1709 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1711 // Instruction operand.
1714 // Encode instruction operand.
1715 let Inst{15-12} = src;
1717 let Inst{27-20} = 0b11101110;
1718 let Inst{19-16} = opc19_16;
1719 let Inst{11-8} = 0b1010;
1724 let Defs = [FPSCR] in {
1725 // Application level GPR -> FPSCR
1726 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1727 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1728 // System level GPR -> FPEXC
1729 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1730 "vmsr", "\tfpexc, $src", []>;
1731 // System level GPR -> FPSID
1732 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1733 "vmsr", "\tfpsid, $src", []>;
1735 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1736 "vmsr", "\tfpinst, $src", []>;
1737 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1738 "vmsr", "\tfpinst2, $src", []>;
1741 //===----------------------------------------------------------------------===//
1745 // Materialize FP immediates. VFP3 only.
1746 let isReMaterializable = 1 in {
1747 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1748 VFPMiscFrm, IIC_fpUNA64,
1749 "vmov", ".f64\t$Dd, $imm",
1750 [(set DPR:$Dd, vfp_f64imm:$imm)]>,
1751 Requires<[HasVFP3,HasDPVFP]> {
1755 let Inst{27-23} = 0b11101;
1756 let Inst{22} = Dd{4};
1757 let Inst{21-20} = 0b11;
1758 let Inst{19-16} = imm{7-4};
1759 let Inst{15-12} = Dd{3-0};
1760 let Inst{11-9} = 0b101;
1761 let Inst{8} = 1; // Double precision.
1762 let Inst{7-4} = 0b0000;
1763 let Inst{3-0} = imm{3-0};
1766 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1767 VFPMiscFrm, IIC_fpUNA32,
1768 "vmov", ".f32\t$Sd, $imm",
1769 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1773 let Inst{27-23} = 0b11101;
1774 let Inst{22} = Sd{0};
1775 let Inst{21-20} = 0b11;
1776 let Inst{19-16} = imm{7-4};
1777 let Inst{15-12} = Sd{4-1};
1778 let Inst{11-9} = 0b101;
1779 let Inst{8} = 0; // Single precision.
1780 let Inst{7-4} = 0b0000;
1781 let Inst{3-0} = imm{3-0};
1785 //===----------------------------------------------------------------------===//
1786 // Assembler aliases.
1788 // A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to
1789 // support them all, but supporting at least some of the basics is
1790 // good to be friendly.
1791 def : VFP2MnemonicAlias<"flds", "vldr">;
1792 def : VFP2MnemonicAlias<"fldd", "vldr">;
1793 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1794 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1795 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1796 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1797 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1798 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1799 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1800 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1801 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1802 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1803 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1804 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1805 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1806 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1807 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1808 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1809 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1810 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1811 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1812 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1813 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1814 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1815 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1816 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1817 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1818 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1819 def : VFP2MnemonicAlias<"fsts", "vstr">;
1820 def : VFP2MnemonicAlias<"fstd", "vstr">;
1821 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1822 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1823 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1824 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1825 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1826 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1827 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1828 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1829 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1830 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1832 // Be friendly and accept the old form of zero-compare
1833 def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1834 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1837 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1838 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1839 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1840 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
1841 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1842 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1843 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1844 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1845 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1847 // No need for the size suffix on VSQRT. It's implied by the register classes.
1848 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1849 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1851 // VLDR/VSTR accept an optional type suffix.
1852 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1853 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1854 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1855 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1856 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1857 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1858 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1859 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1861 // VMOV can accept optional 32-bit or less data type suffix suffix.
1862 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1863 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1864 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1865 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1866 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1867 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1868 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1869 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1870 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1871 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1872 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1873 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1875 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1876 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1877 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1878 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1880 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1882 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1883 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
1885 // FCONSTD/FCONSTS alias for vmov.f64/vmov.f32
1886 // These aliases provide added functionality over vmov.f instructions by
1887 // allowing users to write assembly containing encoded floating point constants
1888 // (e.g. #0x70 vs #1.0). Without these alises there is no way for the
1889 // assembler to accept encoded fp constants (but the equivalent fp-literal is
1890 // accepted directly by vmovf).
1891 def : VFP3InstAlias<"fconstd${p} $Dd, $val",
1892 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;
1893 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
1894 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;