1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
15 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
18 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
19 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
20 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
21 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
23 //===----------------------------------------------------------------------===//
24 // Operand Definitions.
27 // 8-bit floating-point immediate encodings.
28 def FPImmOperand : AsmOperandClass {
30 let ParserMethod = "parseFPImm";
33 def vfp_f32imm : Operand<f32>,
34 PatLeaf<(f32 fpimm), [{
35 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
36 }], SDNodeXForm<fpimm, [{
37 APFloat InVal = N->getValueAPF();
38 uint32_t enc = ARM_AM::getFP32Imm(InVal);
39 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
41 let PrintMethod = "printFPImmOperand";
42 let ParserMatchClass = FPImmOperand;
45 def vfp_f64imm : Operand<f64>,
46 PatLeaf<(f64 fpimm), [{
47 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
48 }], SDNodeXForm<fpimm, [{
49 APFloat InVal = N->getValueAPF();
50 uint32_t enc = ARM_AM::getFP64Imm(InVal);
51 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
53 let PrintMethod = "printFPImmOperand";
54 let ParserMatchClass = FPImmOperand;
57 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
58 return cast<LoadSDNode>(N)->getAlignment() >= 4;
61 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
62 (store node:$val, node:$ptr), [{
63 return cast<StoreSDNode>(N)->getAlignment() >= 4;
66 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
67 // (the number of fixed bits) differently than it appears in the assembly
68 // source. It's encoded as "Size - fbits" where Size is the size of the
69 // fixed-point representation (32 or 16) and fbits is the value appearing
70 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
71 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
72 def fbits32 : Operand<i32> {
73 let PrintMethod = "printFBits32";
74 let ParserMatchClass = fbits32_asm_operand;
77 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
78 def fbits16 : Operand<i32> {
79 let PrintMethod = "printFBits16";
80 let ParserMatchClass = fbits16_asm_operand;
83 //===----------------------------------------------------------------------===//
84 // Load / store Instructions.
87 let canFoldAsLoad = 1, isReMaterializable = 1 in {
89 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
90 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
91 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
93 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
94 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
95 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> {
96 // Some single precision VFP instructions may be executed on both NEON and VFP
98 let D = VFPNeonDomain;
101 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
103 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
104 IIC_fpStore64, "vstr", "\t$Dd, $addr",
105 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
107 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
108 IIC_fpStore32, "vstr", "\t$Sd, $addr",
109 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> {
110 // Some single precision VFP instructions may be executed on both NEON and VFP
112 let D = VFPNeonDomain;
115 //===----------------------------------------------------------------------===//
116 // Load / store multiple Instructions.
119 multiclass vfp_ldst_mult<string asm, bit L_bit,
120 InstrItinClass itin, InstrItinClass itin_upd> {
123 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
125 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
126 let Inst{24-23} = 0b01; // Increment After
127 let Inst{21} = 0; // No writeback
128 let Inst{20} = L_bit;
131 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
133 IndexModeUpd, itin_upd,
134 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
135 let Inst{24-23} = 0b01; // Increment After
136 let Inst{21} = 1; // Writeback
137 let Inst{20} = L_bit;
140 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
142 IndexModeUpd, itin_upd,
143 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
144 let Inst{24-23} = 0b10; // Decrement Before
145 let Inst{21} = 1; // Writeback
146 let Inst{20} = L_bit;
151 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
153 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
154 let Inst{24-23} = 0b01; // Increment After
155 let Inst{21} = 0; // No writeback
156 let Inst{20} = L_bit;
158 // Some single precision VFP instructions may be executed on both NEON and
160 let D = VFPNeonDomain;
163 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
165 IndexModeUpd, itin_upd,
166 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
167 let Inst{24-23} = 0b01; // Increment After
168 let Inst{21} = 1; // Writeback
169 let Inst{20} = L_bit;
171 // Some single precision VFP instructions may be executed on both NEON and
173 let D = VFPNeonDomain;
176 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
178 IndexModeUpd, itin_upd,
179 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
180 let Inst{24-23} = 0b10; // Decrement Before
181 let Inst{21} = 1; // Writeback
182 let Inst{20} = L_bit;
184 // Some single precision VFP instructions may be executed on both NEON and
186 let D = VFPNeonDomain;
190 let hasSideEffects = 0 in {
192 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
193 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
195 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
196 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
200 def : MnemonicAlias<"vldm", "vldmia">;
201 def : MnemonicAlias<"vstm", "vstmia">;
203 // FLDM/FSTM - Load / Store multiple single / double precision registers for
205 // These instructions are deprecated!
206 def : VFP2MnemonicAlias<"fldmias", "vldmia">;
207 def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;
208 def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;
209 def : VFP2MnemonicAlias<"fldmfds", "vldmia">;
210 def : VFP2MnemonicAlias<"fldmiad", "vldmia">;
211 def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">;
212 def : VFP2MnemonicAlias<"fldmead", "vldmdb">;
213 def : VFP2MnemonicAlias<"fldmfdd", "vldmia">;
215 def : VFP2MnemonicAlias<"fstmias", "vstmia">;
216 def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">;
217 def : VFP2MnemonicAlias<"fstmeas", "vstmia">;
218 def : VFP2MnemonicAlias<"fstmfds", "vstmdb">;
219 def : VFP2MnemonicAlias<"fstmiad", "vstmia">;
220 def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;
221 def : VFP2MnemonicAlias<"fstmead", "vstmia">;
222 def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
224 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
226 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
228 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
230 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
232 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
233 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
234 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
235 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
236 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
237 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
238 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
239 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
241 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
243 // These instruction are deprecated so we don't want them to get selected.
244 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
247 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
248 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
249 let Inst{24-23} = 0b01; // Increment After
250 let Inst{21} = 0; // No writeback
251 let Inst{20} = L_bit;
254 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
255 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
256 let Inst{24-23} = 0b01; // Increment After
257 let Inst{21} = 1; // Writeback
258 let Inst{20} = L_bit;
261 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
262 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
263 let Inst{24-23} = 0b10; // Decrement Before
264 let Inst{21} = 1; // Writeback
265 let Inst{20} = L_bit;
269 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
270 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
272 def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;
273 def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;
275 def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;
276 def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;
278 //===----------------------------------------------------------------------===//
279 // FP Binary Operations.
282 let TwoOperandAliasConstraint = "$Dn = $Dd" in
283 def VADDD : ADbI<0b11100, 0b11, 0, 0,
284 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
285 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
286 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
288 let TwoOperandAliasConstraint = "$Sn = $Sd" in
289 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
290 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
291 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
292 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
293 // Some single precision VFP instructions may be executed on both NEON and
294 // VFP pipelines on A8.
295 let D = VFPNeonA8Domain;
298 let TwoOperandAliasConstraint = "$Dn = $Dd" in
299 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
300 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
301 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
302 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
304 let TwoOperandAliasConstraint = "$Sn = $Sd" in
305 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
306 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
307 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
308 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
309 // Some single precision VFP instructions may be executed on both NEON and
310 // VFP pipelines on A8.
311 let D = VFPNeonA8Domain;
314 let TwoOperandAliasConstraint = "$Dn = $Dd" in
315 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
316 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
317 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
318 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
320 let TwoOperandAliasConstraint = "$Sn = $Sd" in
321 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
322 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
323 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
324 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
326 let TwoOperandAliasConstraint = "$Dn = $Dd" in
327 def VMULD : ADbI<0b11100, 0b10, 0, 0,
328 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
329 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
330 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
332 let TwoOperandAliasConstraint = "$Sn = $Sd" in
333 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
334 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
335 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
336 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
337 // Some single precision VFP instructions may be executed on both NEON and
338 // VFP pipelines on A8.
339 let D = VFPNeonA8Domain;
342 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
343 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
344 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
345 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
347 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
348 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
349 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
350 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
351 // Some single precision VFP instructions may be executed on both NEON and
352 // VFP pipelines on A8.
353 let D = VFPNeonA8Domain;
356 multiclass vsel_inst<string op, bits<2> opc, int CC> {
357 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
358 Uses = [CPSR], AddedComplexity = 4 in {
359 def S : ASbInp<0b11100, opc, 0,
360 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
361 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
362 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
363 Requires<[HasFPARMv8]>;
365 def D : ADbInp<0b11100, opc, 0,
366 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
367 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
368 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
369 Requires<[HasFPARMv8, HasDPVFP]>;
373 // The CC constants here match ARMCC::CondCodes.
374 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
375 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
376 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
377 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
379 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
380 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
381 def S : ASbInp<0b11101, 0b00, opc,
382 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
383 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
384 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
385 Requires<[HasFPARMv8]>;
387 def D : ADbInp<0b11101, 0b00, opc,
388 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
389 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
390 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
391 Requires<[HasFPARMv8, HasDPVFP]>;
395 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>;
396 defm VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>;
398 // Match reassociated forms only if not sign dependent rounding.
399 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
400 (VNMULD DPR:$a, DPR:$b)>,
401 Requires<[NoHonorSignDependentRounding,HasDPVFP]>;
402 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
403 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
405 // These are encoded as unary instructions.
406 let Defs = [FPSCR_NZCV] in {
407 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
408 (outs), (ins DPR:$Dd, DPR:$Dm),
409 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
410 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
412 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
413 (outs), (ins SPR:$Sd, SPR:$Sm),
414 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
415 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
416 // Some single precision VFP instructions may be executed on both NEON and
417 // VFP pipelines on A8.
418 let D = VFPNeonA8Domain;
421 // FIXME: Verify encoding after integrated assembler is working.
422 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
423 (outs), (ins DPR:$Dd, DPR:$Dm),
424 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
425 [/* For disassembly only; pattern left blank */]>;
427 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
428 (outs), (ins SPR:$Sd, SPR:$Sm),
429 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
430 [/* For disassembly only; pattern left blank */]> {
431 // Some single precision VFP instructions may be executed on both NEON and
432 // VFP pipelines on A8.
433 let D = VFPNeonA8Domain;
435 } // Defs = [FPSCR_NZCV]
437 //===----------------------------------------------------------------------===//
438 // FP Unary Operations.
441 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
442 (outs DPR:$Dd), (ins DPR:$Dm),
443 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
444 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
446 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
447 (outs SPR:$Sd), (ins SPR:$Sm),
448 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
449 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
450 // Some single precision VFP instructions may be executed on both NEON and
451 // VFP pipelines on A8.
452 let D = VFPNeonA8Domain;
455 let Defs = [FPSCR_NZCV] in {
456 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
457 (outs), (ins DPR:$Dd),
458 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
459 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
460 let Inst{3-0} = 0b0000;
464 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
465 (outs), (ins SPR:$Sd),
466 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
467 [(arm_cmpfp0 SPR:$Sd)]> {
468 let Inst{3-0} = 0b0000;
471 // Some single precision VFP instructions may be executed on both NEON and
472 // VFP pipelines on A8.
473 let D = VFPNeonA8Domain;
476 // FIXME: Verify encoding after integrated assembler is working.
477 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
478 (outs), (ins DPR:$Dd),
479 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
480 [/* For disassembly only; pattern left blank */]> {
481 let Inst{3-0} = 0b0000;
485 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
486 (outs), (ins SPR:$Sd),
487 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
488 [/* For disassembly only; pattern left blank */]> {
489 let Inst{3-0} = 0b0000;
492 // Some single precision VFP instructions may be executed on both NEON and
493 // VFP pipelines on A8.
494 let D = VFPNeonA8Domain;
496 } // Defs = [FPSCR_NZCV]
498 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
499 (outs DPR:$Dd), (ins SPR:$Sm),
500 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
501 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
502 // Instruction operands.
506 // Encode instruction operands.
507 let Inst{3-0} = Sm{4-1};
509 let Inst{15-12} = Dd{3-0};
510 let Inst{22} = Dd{4};
512 let Predicates = [HasVFP2, HasDPVFP];
515 // Special case encoding: bits 11-8 is 0b1011.
516 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
517 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
518 [(set SPR:$Sd, (fround DPR:$Dm))]> {
519 // Instruction operands.
523 // Encode instruction operands.
524 let Inst{3-0} = Dm{3-0};
526 let Inst{15-12} = Sd{4-1};
527 let Inst{22} = Sd{0};
529 let Inst{27-23} = 0b11101;
530 let Inst{21-16} = 0b110111;
531 let Inst{11-8} = 0b1011;
532 let Inst{7-6} = 0b11;
535 let Predicates = [HasVFP2, HasDPVFP];
538 // Between half, single and double-precision. For disassembly only.
540 // FIXME: Verify encoding after integrated assembler is working.
541 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
542 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
543 [/* For disassembly only; pattern left blank */]>;
545 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
546 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
547 [/* For disassembly only; pattern left blank */]>;
549 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
550 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
551 [/* For disassembly only; pattern left blank */]>;
553 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
554 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
555 [/* For disassembly only; pattern left blank */]>;
557 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
558 (outs DPR:$Dd), (ins SPR:$Sm),
559 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
560 []>, Requires<[HasFPARMv8, HasDPVFP]> {
561 // Instruction operands.
564 // Encode instruction operands.
565 let Inst{3-0} = Sm{4-1};
569 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
570 (outs SPR:$Sd), (ins DPR:$Dm),
571 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
572 []>, Requires<[HasFPARMv8, HasDPVFP]> {
573 // Instruction operands.
577 // Encode instruction operands.
578 let Inst{3-0} = Dm{3-0};
580 let Inst{15-12} = Sd{4-1};
581 let Inst{22} = Sd{0};
584 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
585 (outs DPR:$Dd), (ins SPR:$Sm),
586 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
587 []>, Requires<[HasFPARMv8, HasDPVFP]> {
588 // Instruction operands.
591 // Encode instruction operands.
592 let Inst{3-0} = Sm{4-1};
596 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
597 (outs SPR:$Sd), (ins DPR:$Dm),
598 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
599 []>, Requires<[HasFPARMv8, HasDPVFP]> {
600 // Instruction operands.
604 // Encode instruction operands.
605 let Inst{15-12} = Sd{4-1};
606 let Inst{22} = Sd{0};
607 let Inst{3-0} = Dm{3-0};
611 def : Pat<(fp_to_f16 SPR:$a),
612 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
614 def : Pat<(fp_to_f16 (f64 DPR:$a)),
615 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
617 def : Pat<(f16_to_fp GPR:$a),
618 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
620 def : Pat<(f64 (f16_to_fp GPR:$a)),
621 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
623 multiclass vcvt_inst<string opc, bits<2> rm,
624 SDPatternOperator node = null_frag> {
625 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
626 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
627 (outs SPR:$Sd), (ins SPR:$Sm),
628 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
630 Requires<[HasFPARMv8]> {
631 let Inst{17-16} = rm;
634 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
635 (outs SPR:$Sd), (ins SPR:$Sm),
636 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
638 Requires<[HasFPARMv8]> {
639 let Inst{17-16} = rm;
642 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
643 (outs SPR:$Sd), (ins DPR:$Dm),
644 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
646 Requires<[HasFPARMv8, HasDPVFP]> {
649 let Inst{17-16} = rm;
651 // Encode instruction operands
652 let Inst{3-0} = Dm{3-0};
657 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
658 (outs SPR:$Sd), (ins DPR:$Dm),
659 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
661 Requires<[HasFPARMv8, HasDPVFP]> {
664 let Inst{17-16} = rm;
666 // Encode instruction operands
667 let Inst{3-0} = Dm{3-0};
673 let Predicates = [HasFPARMv8] in {
674 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
676 (!cast<Instruction>(NAME#"SS") SPR:$a),
678 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
680 (!cast<Instruction>(NAME#"US") SPR:$a),
683 let Predicates = [HasFPARMv8, HasDPVFP] in {
684 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))),
686 (!cast<Instruction>(NAME#"SD") DPR:$a),
688 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))),
690 (!cast<Instruction>(NAME#"UD") DPR:$a),
695 defm VCVTA : vcvt_inst<"a", 0b00, frnd>;
696 defm VCVTN : vcvt_inst<"n", 0b01>;
697 defm VCVTP : vcvt_inst<"p", 0b10, fceil>;
698 defm VCVTM : vcvt_inst<"m", 0b11, ffloor>;
700 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
701 (outs DPR:$Dd), (ins DPR:$Dm),
702 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
703 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
705 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
706 (outs SPR:$Sd), (ins SPR:$Sm),
707 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
708 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
709 // Some single precision VFP instructions may be executed on both NEON and
710 // VFP pipelines on A8.
711 let D = VFPNeonA8Domain;
714 multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
715 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
716 (outs SPR:$Sd), (ins SPR:$Sm),
717 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
718 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
719 Requires<[HasFPARMv8]> {
723 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
724 (outs DPR:$Dd), (ins DPR:$Dm),
725 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
726 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
727 Requires<[HasFPARMv8, HasDPVFP]> {
732 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
733 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
734 Requires<[HasFPARMv8]>;
735 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
736 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
737 Requires<[HasFPARMv8,HasDPVFP]>;
740 defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>;
741 defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>;
742 defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
744 multiclass vrint_inst_anpm<string opc, bits<2> rm,
745 SDPatternOperator node = null_frag> {
746 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
747 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
748 (outs SPR:$Sd), (ins SPR:$Sm),
749 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
750 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
751 Requires<[HasFPARMv8]> {
752 let Inst{17-16} = rm;
754 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
755 (outs DPR:$Dd), (ins DPR:$Dm),
756 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
757 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
758 Requires<[HasFPARMv8, HasDPVFP]> {
759 let Inst{17-16} = rm;
763 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
764 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
765 Requires<[HasFPARMv8]>;
766 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
767 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
768 Requires<[HasFPARMv8,HasDPVFP]>;
771 defm VRINTA : vrint_inst_anpm<"a", 0b00, frnd>;
772 defm VRINTN : vrint_inst_anpm<"n", 0b01>;
773 defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>;
774 defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>;
776 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
777 (outs DPR:$Dd), (ins DPR:$Dm),
778 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
779 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
781 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
782 (outs SPR:$Sd), (ins SPR:$Sm),
783 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
784 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
786 let hasSideEffects = 0 in {
787 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
788 (outs DPR:$Dd), (ins DPR:$Dm),
789 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
791 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
792 (outs SPR:$Sd), (ins SPR:$Sm),
793 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
796 //===----------------------------------------------------------------------===//
797 // FP <-> GPR Copies. Int <-> FP Conversions.
800 def VMOVRS : AVConv2I<0b11100001, 0b1010,
801 (outs GPR:$Rt), (ins SPR:$Sn),
802 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
803 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
804 // Instruction operands.
808 // Encode instruction operands.
809 let Inst{19-16} = Sn{4-1};
811 let Inst{15-12} = Rt;
813 let Inst{6-5} = 0b00;
814 let Inst{3-0} = 0b0000;
816 // Some single precision VFP instructions may be executed on both NEON and VFP
818 let D = VFPNeonDomain;
821 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
822 def VMOVSR : AVConv4I<0b11100000, 0b1010,
823 (outs SPR:$Sn), (ins GPR:$Rt),
824 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
825 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
826 Requires<[HasVFP2, UseVMOVSR]> {
827 // Instruction operands.
831 // Encode instruction operands.
832 let Inst{19-16} = Sn{4-1};
834 let Inst{15-12} = Rt;
836 let Inst{6-5} = 0b00;
837 let Inst{3-0} = 0b0000;
839 // Some single precision VFP instructions may be executed on both NEON and VFP
841 let D = VFPNeonDomain;
844 let hasSideEffects = 0 in {
845 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
846 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
847 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
848 [/* FIXME: Can't write pattern for multiple result instr*/]> {
849 // Instruction operands.
854 // Encode instruction operands.
855 let Inst{3-0} = Dm{3-0};
857 let Inst{15-12} = Rt;
858 let Inst{19-16} = Rt2;
860 let Inst{7-6} = 0b00;
862 // Some single precision VFP instructions may be executed on both NEON and VFP
864 let D = VFPNeonDomain;
866 // This instruction is equivalent to
867 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
868 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
869 let isExtractSubreg = 1;
872 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
873 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
874 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
875 [/* For disassembly only; pattern left blank */]> {
880 // Encode instruction operands.
881 let Inst{3-0} = src1{4-1};
882 let Inst{5} = src1{0};
883 let Inst{15-12} = Rt;
884 let Inst{19-16} = Rt2;
886 let Inst{7-6} = 0b00;
888 // Some single precision VFP instructions may be executed on both NEON and VFP
890 let D = VFPNeonDomain;
891 let DecoderMethod = "DecodeVMOVRRS";
898 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
899 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
900 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
901 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
902 // Instruction operands.
907 // Encode instruction operands.
908 let Inst{3-0} = Dm{3-0};
910 let Inst{15-12} = Rt;
911 let Inst{19-16} = Rt2;
913 let Inst{7-6} = 0b00;
915 // Some single precision VFP instructions may be executed on both NEON and VFP
917 let D = VFPNeonDomain;
919 // This instruction is equivalent to
920 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
921 let isRegSequence = 1;
924 // Hoist an fabs or a fneg of a value coming from integer registers
925 // and do the fabs/fneg on the integer value. This is never a lose
926 // and could enable the conversion to float to be removed completely.
927 def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),
928 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
930 def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),
931 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
932 Requires<[IsThumb2]>;
933 def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),
934 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
936 def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),
937 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
938 Requires<[IsThumb2]>;
940 let hasSideEffects = 0 in
941 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
942 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
943 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
944 [/* For disassembly only; pattern left blank */]> {
945 // Instruction operands.
950 // Encode instruction operands.
951 let Inst{3-0} = dst1{4-1};
952 let Inst{5} = dst1{0};
953 let Inst{15-12} = src1;
954 let Inst{19-16} = src2;
956 let Inst{7-6} = 0b00;
958 // Some single precision VFP instructions may be executed on both NEON and VFP
960 let D = VFPNeonDomain;
962 let DecoderMethod = "DecodeVMOVSRR";
968 // FMRX: SPR system reg -> GPR
970 // FMXR: GPR -> VFP system reg
975 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
976 bits<4> opcod4, dag oops, dag iops,
977 InstrItinClass itin, string opc, string asm,
979 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
981 // Instruction operands.
985 // Encode instruction operands.
986 let Inst{3-0} = Sm{4-1};
988 let Inst{15-12} = Dd{3-0};
989 let Inst{22} = Dd{4};
991 let Predicates = [HasVFP2, HasDPVFP];
994 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
995 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
996 string opc, string asm, list<dag> pattern>
997 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
999 // Instruction operands.
1003 // Encode instruction operands.
1004 let Inst{3-0} = Sm{4-1};
1005 let Inst{5} = Sm{0};
1006 let Inst{15-12} = Sd{4-1};
1007 let Inst{22} = Sd{0};
1010 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1011 (outs DPR:$Dd), (ins SPR:$Sm),
1012 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
1014 let Inst{7} = 1; // s32
1017 let Predicates=[HasVFP2, HasDPVFP] in {
1018 def : VFPPat<(f64 (sint_to_fp GPR:$a)),
1019 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1021 def : VFPPat<(f64 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1022 (VSITOD (VLDRS addrmode5:$a))>;
1025 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1026 (outs SPR:$Sd),(ins SPR:$Sm),
1027 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1029 let Inst{7} = 1; // s32
1031 // Some single precision VFP instructions may be executed on both NEON and
1032 // VFP pipelines on A8.
1033 let D = VFPNeonA8Domain;
1036 def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)),
1037 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1039 def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1040 (VSITOS (VLDRS addrmode5:$a))>;
1042 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1043 (outs DPR:$Dd), (ins SPR:$Sm),
1044 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
1046 let Inst{7} = 0; // u32
1049 let Predicates=[HasVFP2, HasDPVFP] in {
1050 def : VFPPat<(f64 (uint_to_fp GPR:$a)),
1051 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1053 def : VFPPat<(f64 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1054 (VUITOD (VLDRS addrmode5:$a))>;
1057 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1058 (outs SPR:$Sd), (ins SPR:$Sm),
1059 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1061 let Inst{7} = 0; // u32
1063 // Some single precision VFP instructions may be executed on both NEON and
1064 // VFP pipelines on A8.
1065 let D = VFPNeonA8Domain;
1068 def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)),
1069 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1071 def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))),
1072 (VUITOS (VLDRS addrmode5:$a))>;
1076 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1077 bits<4> opcod4, dag oops, dag iops,
1078 InstrItinClass itin, string opc, string asm,
1080 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1082 // Instruction operands.
1086 // Encode instruction operands.
1087 let Inst{3-0} = Dm{3-0};
1088 let Inst{5} = Dm{4};
1089 let Inst{15-12} = Sd{4-1};
1090 let Inst{22} = Sd{0};
1092 let Predicates = [HasVFP2, HasDPVFP];
1095 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1096 bits<4> opcod4, dag oops, dag iops,
1097 InstrItinClass itin, string opc, string asm,
1099 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1101 // Instruction operands.
1105 // Encode instruction operands.
1106 let Inst{3-0} = Sm{4-1};
1107 let Inst{5} = Sm{0};
1108 let Inst{15-12} = Sd{4-1};
1109 let Inst{22} = Sd{0};
1112 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
1113 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1114 (outs SPR:$Sd), (ins DPR:$Dm),
1115 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1117 let Inst{7} = 1; // Z bit
1120 let Predicates=[HasVFP2, HasDPVFP] in {
1121 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
1122 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
1124 def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
1125 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
1128 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1129 (outs SPR:$Sd), (ins SPR:$Sm),
1130 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1132 let Inst{7} = 1; // Z bit
1134 // Some single precision VFP instructions may be executed on both NEON and
1135 // VFP pipelines on A8.
1136 let D = VFPNeonA8Domain;
1139 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1140 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1142 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
1144 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1146 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1147 (outs SPR:$Sd), (ins DPR:$Dm),
1148 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1150 let Inst{7} = 1; // Z bit
1153 let Predicates=[HasVFP2, HasDPVFP] in {
1154 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
1155 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
1157 def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
1158 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
1161 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1162 (outs SPR:$Sd), (ins SPR:$Sm),
1163 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1165 let Inst{7} = 1; // Z bit
1167 // Some single precision VFP instructions may be executed on both NEON and
1168 // VFP pipelines on A8.
1169 let D = VFPNeonA8Domain;
1172 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1173 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1175 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
1177 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1179 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1180 let Uses = [FPSCR] in {
1181 // FIXME: Verify encoding after integrated assembler is working.
1182 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1183 (outs SPR:$Sd), (ins DPR:$Dm),
1184 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1185 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1186 let Inst{7} = 0; // Z bit
1189 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1190 (outs SPR:$Sd), (ins SPR:$Sm),
1191 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1192 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1193 let Inst{7} = 0; // Z bit
1196 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1197 (outs SPR:$Sd), (ins DPR:$Dm),
1198 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1199 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1200 let Inst{7} = 0; // Z bit
1203 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1204 (outs SPR:$Sd), (ins SPR:$Sm),
1205 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1206 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1207 let Inst{7} = 0; // Z bit
1211 // Convert between floating-point and fixed-point
1212 // Data type for fixed-point naming convention:
1213 // S16 (U=0, sx=0) -> SH
1214 // U16 (U=1, sx=0) -> UH
1215 // S32 (U=0, sx=1) -> SL
1216 // U32 (U=1, sx=1) -> UL
1218 let Constraints = "$a = $dst" in {
1220 // FP to Fixed-Point:
1222 // Single Precision register
1223 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1224 bit op5, dag oops, dag iops, InstrItinClass itin,
1225 string opc, string asm, list<dag> pattern>
1226 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1227 Sched<[WriteCvtFP]> {
1229 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1230 let Inst{22} = dst{0};
1231 let Inst{15-12} = dst{4-1};
1234 // Double Precision register
1235 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1236 bit op5, dag oops, dag iops, InstrItinClass itin,
1237 string opc, string asm, list<dag> pattern>
1238 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1239 Sched<[WriteCvtFP]> {
1241 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1242 let Inst{22} = dst{4};
1243 let Inst{15-12} = dst{3-0};
1245 let Predicates = [HasVFP2, HasDPVFP];
1248 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1249 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1250 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1251 // Some single precision VFP instructions may be executed on both NEON and
1252 // VFP pipelines on A8.
1253 let D = VFPNeonA8Domain;
1256 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1257 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1258 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1259 // Some single precision VFP instructions may be executed on both NEON and
1260 // VFP pipelines on A8.
1261 let D = VFPNeonA8Domain;
1264 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1265 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1266 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1267 // Some single precision VFP instructions may be executed on both NEON and
1268 // VFP pipelines on A8.
1269 let D = VFPNeonA8Domain;
1272 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1273 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1274 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1275 // Some single precision VFP instructions may be executed on both NEON and
1276 // VFP pipelines on A8.
1277 let D = VFPNeonA8Domain;
1280 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1281 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1282 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1284 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1285 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1286 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1288 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1289 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1290 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1292 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1293 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1294 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1296 // Fixed-Point to FP:
1298 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1299 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1300 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1301 // Some single precision VFP instructions may be executed on both NEON and
1302 // VFP pipelines on A8.
1303 let D = VFPNeonA8Domain;
1306 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1307 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1308 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1309 // Some single precision VFP instructions may be executed on both NEON and
1310 // VFP pipelines on A8.
1311 let D = VFPNeonA8Domain;
1314 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1315 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1316 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1317 // Some single precision VFP instructions may be executed on both NEON and
1318 // VFP pipelines on A8.
1319 let D = VFPNeonA8Domain;
1322 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1323 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1324 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1325 // Some single precision VFP instructions may be executed on both NEON and
1326 // VFP pipelines on A8.
1327 let D = VFPNeonA8Domain;
1330 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1331 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1332 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1334 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1335 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1336 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1338 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1339 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1340 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1342 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1343 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1344 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1346 } // End of 'let Constraints = "$a = $dst" in'
1348 //===----------------------------------------------------------------------===//
1349 // FP Multiply-Accumulate Operations.
1352 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1353 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1354 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1355 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1356 (f64 DPR:$Ddin)))]>,
1357 RegConstraint<"$Ddin = $Dd">,
1358 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1360 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1361 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1362 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1363 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1365 RegConstraint<"$Sdin = $Sd">,
1366 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1367 // Some single precision VFP instructions may be executed on both NEON and
1368 // VFP pipelines on A8.
1369 let D = VFPNeonA8Domain;
1372 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1373 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1374 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1375 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1376 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1377 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1379 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1380 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1381 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1382 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1383 (f64 DPR:$Ddin)))]>,
1384 RegConstraint<"$Ddin = $Dd">,
1385 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1387 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1388 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1389 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1390 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1392 RegConstraint<"$Sdin = $Sd">,
1393 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1394 // Some single precision VFP instructions may be executed on both NEON and
1395 // VFP pipelines on A8.
1396 let D = VFPNeonA8Domain;
1399 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1400 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1401 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1402 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1403 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1404 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1406 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1407 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1408 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1409 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1410 (f64 DPR:$Ddin)))]>,
1411 RegConstraint<"$Ddin = $Dd">,
1412 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1414 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1415 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1416 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1417 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1419 RegConstraint<"$Sdin = $Sd">,
1420 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1421 // Some single precision VFP instructions may be executed on both NEON and
1422 // VFP pipelines on A8.
1423 let D = VFPNeonA8Domain;
1426 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1427 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1428 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1429 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1430 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1431 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1433 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1434 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1435 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1436 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1437 (f64 DPR:$Ddin)))]>,
1438 RegConstraint<"$Ddin = $Dd">,
1439 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1441 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1442 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1443 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1444 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1445 RegConstraint<"$Sdin = $Sd">,
1446 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1447 // Some single precision VFP instructions may be executed on both NEON and
1448 // VFP pipelines on A8.
1449 let D = VFPNeonA8Domain;
1452 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1453 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1454 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1455 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1456 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1457 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1459 //===----------------------------------------------------------------------===//
1460 // Fused FP Multiply-Accumulate Operations.
1462 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1463 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1464 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1465 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1466 (f64 DPR:$Ddin)))]>,
1467 RegConstraint<"$Ddin = $Dd">,
1468 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1470 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1471 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1472 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1473 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1475 RegConstraint<"$Sdin = $Sd">,
1476 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1477 // Some single precision VFP instructions may be executed on both NEON and
1481 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1482 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1483 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1484 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1485 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1486 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1488 // Match @llvm.fma.* intrinsics
1489 // (fma x, y, z) -> (vfms z, x, y)
1490 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1491 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1492 Requires<[HasVFP4,HasDPVFP]>;
1493 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1494 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1495 Requires<[HasVFP4]>;
1497 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1498 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1499 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1500 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1501 (f64 DPR:$Ddin)))]>,
1502 RegConstraint<"$Ddin = $Dd">,
1503 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1505 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1506 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1507 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1508 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1510 RegConstraint<"$Sdin = $Sd">,
1511 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1512 // Some single precision VFP instructions may be executed on both NEON and
1516 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1517 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1518 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1519 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1520 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1521 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1523 // Match @llvm.fma.* intrinsics
1524 // (fma (fneg x), y, z) -> (vfms z, x, y)
1525 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1526 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1527 Requires<[HasVFP4,HasDPVFP]>;
1528 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1529 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1530 Requires<[HasVFP4]>;
1531 // (fma x, (fneg y), z) -> (vfms z, x, y)
1532 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1533 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1534 Requires<[HasVFP4,HasDPVFP]>;
1535 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1536 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1537 Requires<[HasVFP4]>;
1539 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1540 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1541 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1542 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1543 (f64 DPR:$Ddin)))]>,
1544 RegConstraint<"$Ddin = $Dd">,
1545 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1547 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1548 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1549 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1550 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1552 RegConstraint<"$Sdin = $Sd">,
1553 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1554 // Some single precision VFP instructions may be executed on both NEON and
1558 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1559 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1560 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1561 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1562 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1563 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1565 // Match @llvm.fma.* intrinsics
1566 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1567 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1568 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1569 Requires<[HasVFP4,HasDPVFP]>;
1570 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1571 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1572 Requires<[HasVFP4]>;
1573 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1574 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1575 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1576 Requires<[HasVFP4,HasDPVFP]>;
1577 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1578 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1579 Requires<[HasVFP4]>;
1581 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1582 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1583 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1584 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1585 (f64 DPR:$Ddin)))]>,
1586 RegConstraint<"$Ddin = $Dd">,
1587 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1589 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1590 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1591 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1592 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1593 RegConstraint<"$Sdin = $Sd">,
1594 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1595 // Some single precision VFP instructions may be executed on both NEON and
1599 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1600 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1601 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1602 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1603 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1604 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1606 // Match @llvm.fma.* intrinsics
1608 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1609 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1610 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1611 Requires<[HasVFP4,HasDPVFP]>;
1612 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1613 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1614 Requires<[HasVFP4]>;
1615 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1616 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1617 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1618 Requires<[HasVFP4,HasDPVFP]>;
1619 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1620 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1621 Requires<[HasVFP4]>;
1622 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1623 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1624 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1625 Requires<[HasVFP4,HasDPVFP]>;
1626 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1627 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1628 Requires<[HasVFP4]>;
1630 //===----------------------------------------------------------------------===//
1631 // FP Conditional moves.
1634 let hasSideEffects = 0 in {
1635 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
1637 [(set (f64 DPR:$Dd),
1638 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1639 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>;
1641 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1643 [(set (f32 SPR:$Sd),
1644 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1645 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
1648 //===----------------------------------------------------------------------===//
1649 // Move from VFP System Register to ARM core register.
1652 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1654 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1656 // Instruction operand.
1659 let Inst{27-20} = 0b11101111;
1660 let Inst{19-16} = opc19_16;
1661 let Inst{15-12} = Rt;
1662 let Inst{11-8} = 0b1010;
1664 let Inst{6-5} = 0b00;
1666 let Inst{3-0} = 0b0000;
1669 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1671 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1672 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1673 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1675 // Application level FPSCR -> GPR
1676 let hasSideEffects = 1, Uses = [FPSCR] in
1677 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1678 "vmrs", "\t$Rt, fpscr",
1679 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1681 // System level FPEXC, FPSID -> GPR
1682 let Uses = [FPSCR] in {
1683 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1684 "vmrs", "\t$Rt, fpexc", []>;
1685 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1686 "vmrs", "\t$Rt, fpsid", []>;
1687 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1688 "vmrs", "\t$Rt, mvfr0", []>;
1689 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1690 "vmrs", "\t$Rt, mvfr1", []>;
1691 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
1692 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
1693 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1694 "vmrs", "\t$Rt, fpinst", []>;
1695 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1696 "vmrs", "\t$Rt, fpinst2", []>;
1699 //===----------------------------------------------------------------------===//
1700 // Move from ARM core register to VFP System Register.
1703 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1705 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1707 // Instruction operand.
1710 // Encode instruction operand.
1711 let Inst{15-12} = src;
1713 let Inst{27-20} = 0b11101110;
1714 let Inst{19-16} = opc19_16;
1715 let Inst{11-8} = 0b1010;
1720 let Defs = [FPSCR] in {
1721 // Application level GPR -> FPSCR
1722 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1723 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1724 // System level GPR -> FPEXC
1725 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1726 "vmsr", "\tfpexc, $src", []>;
1727 // System level GPR -> FPSID
1728 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1729 "vmsr", "\tfpsid, $src", []>;
1731 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1732 "vmsr", "\tfpinst, $src", []>;
1733 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1734 "vmsr", "\tfpinst2, $src", []>;
1737 //===----------------------------------------------------------------------===//
1741 // Materialize FP immediates. VFP3 only.
1742 let isReMaterializable = 1 in {
1743 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1744 VFPMiscFrm, IIC_fpUNA64,
1745 "vmov", ".f64\t$Dd, $imm",
1746 [(set DPR:$Dd, vfp_f64imm:$imm)]>,
1747 Requires<[HasVFP3,HasDPVFP]> {
1751 let Inst{27-23} = 0b11101;
1752 let Inst{22} = Dd{4};
1753 let Inst{21-20} = 0b11;
1754 let Inst{19-16} = imm{7-4};
1755 let Inst{15-12} = Dd{3-0};
1756 let Inst{11-9} = 0b101;
1757 let Inst{8} = 1; // Double precision.
1758 let Inst{7-4} = 0b0000;
1759 let Inst{3-0} = imm{3-0};
1762 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1763 VFPMiscFrm, IIC_fpUNA32,
1764 "vmov", ".f32\t$Sd, $imm",
1765 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1769 let Inst{27-23} = 0b11101;
1770 let Inst{22} = Sd{0};
1771 let Inst{21-20} = 0b11;
1772 let Inst{19-16} = imm{7-4};
1773 let Inst{15-12} = Sd{4-1};
1774 let Inst{11-9} = 0b101;
1775 let Inst{8} = 0; // Single precision.
1776 let Inst{7-4} = 0b0000;
1777 let Inst{3-0} = imm{3-0};
1781 //===----------------------------------------------------------------------===//
1782 // Assembler aliases.
1784 // A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to
1785 // support them all, but supporting at least some of the basics is
1786 // good to be friendly.
1787 def : VFP2MnemonicAlias<"flds", "vldr">;
1788 def : VFP2MnemonicAlias<"fldd", "vldr">;
1789 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1790 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1791 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1792 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1793 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1794 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1795 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1796 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1797 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1798 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1799 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1800 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1801 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1802 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1803 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1804 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1805 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1806 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1807 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1808 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1809 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1810 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1811 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1812 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1813 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1814 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1815 def : VFP2MnemonicAlias<"fsts", "vstr">;
1816 def : VFP2MnemonicAlias<"fstd", "vstr">;
1817 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1818 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1819 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1820 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1821 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1822 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1823 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1824 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1825 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1826 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1828 // Be friendly and accept the old form of zero-compare
1829 def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1830 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1833 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1834 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1835 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1836 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
1837 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1838 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1839 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1840 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1841 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1843 // No need for the size suffix on VSQRT. It's implied by the register classes.
1844 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1845 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1847 // VLDR/VSTR accept an optional type suffix.
1848 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1849 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1850 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1851 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1852 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1853 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1854 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1855 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1857 // VMOV can accept optional 32-bit or less data type suffix suffix.
1858 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1859 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1860 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1861 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1862 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1863 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1864 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1865 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1866 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1867 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1868 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1869 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1871 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1872 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1873 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1874 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1876 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1878 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1879 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
1881 // FCONSTD/FCONSTS alias for vmov.f64/vmov.f32
1882 // These aliases provide added functionality over vmov.f instructions by
1883 // allowing users to write assembly containing encoded floating point constants
1884 // (e.g. #0x70 vs #1.0). Without these alises there is no way for the
1885 // assembler to accept encoded fp constants (but the equivalent fp-literal is
1886 // accepted directly by vmovf).
1887 def : VFP3InstAlias<"fconstd${p} $Dd, $val",
1888 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;
1889 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
1890 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;