1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 // 8-bit floating-point immediate encodings.
35 def FPImmOperand : AsmOperandClass {
37 let ParserMethod = "parseFPImm";
40 def vfp_f32imm : Operand<f32>,
41 PatLeaf<(f32 fpimm), [{
42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
43 }], SDNodeXForm<fpimm, [{
44 APFloat InVal = N->getValueAPF();
45 uint32_t enc = ARM_AM::getFP32Imm(InVal);
46 return CurDAG->getTargetConstant(enc, MVT::i32);
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
52 def vfp_f64imm : Operand<f64>,
53 PatLeaf<(f64 fpimm), [{
54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
55 }], SDNodeXForm<fpimm, [{
56 APFloat InVal = N->getValueAPF();
57 uint32_t enc = ARM_AM::getFP64Imm(InVal);
58 return CurDAG->getTargetConstant(enc, MVT::i32);
60 let PrintMethod = "printFPImmOperand";
61 let ParserMatchClass = FPImmOperand;
64 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
65 // (the number of fixed bits) differently than it appears in the assembly
66 // source. It's encoded as "Size - fbits" where Size is the size of the
67 // fixed-point representation (32 or 16) and fbits is the value appearing
68 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
69 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
70 def fbits32 : Operand<i32> {
71 let PrintMethod = "printFBits32";
72 let ParserMatchClass = fbits32_asm_operand;
75 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
76 def fbits16 : Operand<i32> {
77 let PrintMethod = "printFBits16";
78 let ParserMatchClass = fbits16_asm_operand;
81 //===----------------------------------------------------------------------===//
82 // Load / store Instructions.
85 let canFoldAsLoad = 1, isReMaterializable = 1 in {
87 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
88 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
89 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
91 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
92 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
93 [(set SPR:$Sd, (load addrmode5:$addr))]> {
94 // Some single precision VFP instructions may be executed on both NEON and VFP
96 let D = VFPNeonDomain;
99 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
101 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
102 IIC_fpStore64, "vstr", "\t$Dd, $addr",
103 [(store (f64 DPR:$Dd), addrmode5:$addr)]>;
105 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
106 IIC_fpStore32, "vstr", "\t$Sd, $addr",
107 [(store SPR:$Sd, addrmode5:$addr)]> {
108 // Some single precision VFP instructions may be executed on both NEON and VFP
110 let D = VFPNeonDomain;
113 //===----------------------------------------------------------------------===//
114 // Load / store multiple Instructions.
117 multiclass vfp_ldst_mult<string asm, bit L_bit,
118 InstrItinClass itin, InstrItinClass itin_upd> {
121 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
123 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
124 let Inst{24-23} = 0b01; // Increment After
125 let Inst{21} = 0; // No writeback
126 let Inst{20} = L_bit;
129 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
131 IndexModeUpd, itin_upd,
132 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
133 let Inst{24-23} = 0b01; // Increment After
134 let Inst{21} = 1; // Writeback
135 let Inst{20} = L_bit;
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
140 IndexModeUpd, itin_upd,
141 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
142 let Inst{24-23} = 0b10; // Decrement Before
143 let Inst{21} = 1; // Writeback
144 let Inst{20} = L_bit;
149 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
151 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
152 let Inst{24-23} = 0b01; // Increment After
153 let Inst{21} = 0; // No writeback
154 let Inst{20} = L_bit;
156 // Some single precision VFP instructions may be executed on both NEON and
158 let D = VFPNeonDomain;
161 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
163 IndexModeUpd, itin_upd,
164 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
165 let Inst{24-23} = 0b01; // Increment After
166 let Inst{21} = 1; // Writeback
167 let Inst{20} = L_bit;
169 // Some single precision VFP instructions may be executed on both NEON and
171 let D = VFPNeonDomain;
174 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
176 IndexModeUpd, itin_upd,
177 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
178 let Inst{24-23} = 0b10; // Decrement Before
179 let Inst{21} = 1; // Writeback
180 let Inst{20} = L_bit;
182 // Some single precision VFP instructions may be executed on both NEON and
184 let D = VFPNeonDomain;
188 let neverHasSideEffects = 1 in {
190 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
191 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
193 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
194 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
196 } // neverHasSideEffects
198 def : MnemonicAlias<"vldm", "vldmia">;
199 def : MnemonicAlias<"vstm", "vstmia">;
201 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
203 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
205 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
207 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
209 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
210 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
211 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
212 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
213 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
214 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
215 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
216 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
218 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
220 //===----------------------------------------------------------------------===//
221 // FP Binary Operations.
224 let TwoOperandAliasConstraint = "$Dn = $Dd" in
225 def VADDD : ADbI<0b11100, 0b11, 0, 0,
226 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
227 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
228 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
230 let TwoOperandAliasConstraint = "$Sn = $Sd" in
231 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
232 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
233 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
234 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
235 // Some single precision VFP instructions may be executed on both NEON and
236 // VFP pipelines on A8.
237 let D = VFPNeonA8Domain;
240 let TwoOperandAliasConstraint = "$Dn = $Dd" in
241 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
242 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
243 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
244 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
246 let TwoOperandAliasConstraint = "$Sn = $Sd" in
247 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
248 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
249 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
250 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
251 // Some single precision VFP instructions may be executed on both NEON and
252 // VFP pipelines on A8.
253 let D = VFPNeonA8Domain;
256 let TwoOperandAliasConstraint = "$Dn = $Dd" in
257 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
258 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
259 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
260 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
262 let TwoOperandAliasConstraint = "$Sn = $Sd" in
263 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
264 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
265 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
266 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
268 let TwoOperandAliasConstraint = "$Dn = $Dd" in
269 def VMULD : ADbI<0b11100, 0b10, 0, 0,
270 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
271 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
272 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
274 let TwoOperandAliasConstraint = "$Sn = $Sd" in
275 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
276 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
277 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
278 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
279 // Some single precision VFP instructions may be executed on both NEON and
280 // VFP pipelines on A8.
281 let D = VFPNeonA8Domain;
284 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
285 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
286 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
287 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
289 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
290 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
291 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
292 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
293 // Some single precision VFP instructions may be executed on both NEON and
294 // VFP pipelines on A8.
295 let D = VFPNeonA8Domain;
298 // Match reassociated forms only if not sign dependent rounding.
299 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
300 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
301 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
302 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
304 // These are encoded as unary instructions.
305 let Defs = [FPSCR_NZCV] in {
306 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
307 (outs), (ins DPR:$Dd, DPR:$Dm),
308 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
309 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
311 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
312 (outs), (ins SPR:$Sd, SPR:$Sm),
313 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
314 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
315 // Some single precision VFP instructions may be executed on both NEON and
316 // VFP pipelines on A8.
317 let D = VFPNeonA8Domain;
320 // FIXME: Verify encoding after integrated assembler is working.
321 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
322 (outs), (ins DPR:$Dd, DPR:$Dm),
323 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
324 [/* For disassembly only; pattern left blank */]>;
326 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
327 (outs), (ins SPR:$Sd, SPR:$Sm),
328 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
329 [/* For disassembly only; pattern left blank */]> {
330 // Some single precision VFP instructions may be executed on both NEON and
331 // VFP pipelines on A8.
332 let D = VFPNeonA8Domain;
334 } // Defs = [FPSCR_NZCV]
336 //===----------------------------------------------------------------------===//
337 // FP Unary Operations.
340 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
341 (outs DPR:$Dd), (ins DPR:$Dm),
342 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
343 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
345 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
346 (outs SPR:$Sd), (ins SPR:$Sm),
347 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
348 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
349 // Some single precision VFP instructions may be executed on both NEON and
350 // VFP pipelines on A8.
351 let D = VFPNeonA8Domain;
354 let Defs = [FPSCR_NZCV] in {
355 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
356 (outs), (ins DPR:$Dd),
357 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
358 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
359 let Inst{3-0} = 0b0000;
363 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
364 (outs), (ins SPR:$Sd),
365 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
366 [(arm_cmpfp0 SPR:$Sd)]> {
367 let Inst{3-0} = 0b0000;
370 // Some single precision VFP instructions may be executed on both NEON and
371 // VFP pipelines on A8.
372 let D = VFPNeonA8Domain;
375 // FIXME: Verify encoding after integrated assembler is working.
376 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
377 (outs), (ins DPR:$Dd),
378 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
379 [/* For disassembly only; pattern left blank */]> {
380 let Inst{3-0} = 0b0000;
384 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
385 (outs), (ins SPR:$Sd),
386 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
387 [/* For disassembly only; pattern left blank */]> {
388 let Inst{3-0} = 0b0000;
391 // Some single precision VFP instructions may be executed on both NEON and
392 // VFP pipelines on A8.
393 let D = VFPNeonA8Domain;
395 } // Defs = [FPSCR_NZCV]
397 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
398 (outs DPR:$Dd), (ins SPR:$Sm),
399 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
400 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
401 // Instruction operands.
405 // Encode instruction operands.
406 let Inst{3-0} = Sm{4-1};
408 let Inst{15-12} = Dd{3-0};
409 let Inst{22} = Dd{4};
412 // Special case encoding: bits 11-8 is 0b1011.
413 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
414 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
415 [(set SPR:$Sd, (fround DPR:$Dm))]> {
416 // Instruction operands.
420 // Encode instruction operands.
421 let Inst{3-0} = Dm{3-0};
423 let Inst{15-12} = Sd{4-1};
424 let Inst{22} = Sd{0};
426 let Inst{27-23} = 0b11101;
427 let Inst{21-16} = 0b110111;
428 let Inst{11-8} = 0b1011;
429 let Inst{7-6} = 0b11;
433 // Between half-precision and single-precision. For disassembly only.
435 // FIXME: Verify encoding after integrated assembler is working.
436 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
437 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
438 [/* For disassembly only; pattern left blank */]>;
440 def : ARMPat<(f32_to_f16 SPR:$a),
441 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
443 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
444 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
445 [/* For disassembly only; pattern left blank */]>;
447 def : ARMPat<(f16_to_f32 GPR:$a),
448 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
450 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
451 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
452 [/* For disassembly only; pattern left blank */]>;
454 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
455 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
456 [/* For disassembly only; pattern left blank */]>;
458 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
459 (outs DPR:$Dd), (ins DPR:$Dm),
460 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
461 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
463 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
464 (outs SPR:$Sd), (ins SPR:$Sm),
465 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
466 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
467 // Some single precision VFP instructions may be executed on both NEON and
468 // VFP pipelines on A8.
469 let D = VFPNeonA8Domain;
472 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
473 (outs DPR:$Dd), (ins DPR:$Dm),
474 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
475 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
477 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
478 (outs SPR:$Sd), (ins SPR:$Sm),
479 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
480 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
482 let neverHasSideEffects = 1 in {
483 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
484 (outs DPR:$Dd), (ins DPR:$Dm),
485 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
487 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
488 (outs SPR:$Sd), (ins SPR:$Sm),
489 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
490 } // neverHasSideEffects
492 //===----------------------------------------------------------------------===//
493 // FP <-> GPR Copies. Int <-> FP Conversions.
496 def VMOVRS : AVConv2I<0b11100001, 0b1010,
497 (outs GPR:$Rt), (ins SPR:$Sn),
498 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
499 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
500 // Instruction operands.
504 // Encode instruction operands.
505 let Inst{19-16} = Sn{4-1};
507 let Inst{15-12} = Rt;
509 let Inst{6-5} = 0b00;
510 let Inst{3-0} = 0b0000;
512 // Some single precision VFP instructions may be executed on both NEON and VFP
514 let D = VFPNeonDomain;
517 def VMOVSR : AVConv4I<0b11100000, 0b1010,
518 (outs SPR:$Sn), (ins GPR:$Rt),
519 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
520 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
521 // Instruction operands.
525 // Encode instruction operands.
526 let Inst{19-16} = Sn{4-1};
528 let Inst{15-12} = Rt;
530 let Inst{6-5} = 0b00;
531 let Inst{3-0} = 0b0000;
533 // Some single precision VFP instructions may be executed on both NEON and VFP
535 let D = VFPNeonDomain;
538 let neverHasSideEffects = 1 in {
539 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
540 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
541 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
542 [/* FIXME: Can't write pattern for multiple result instr*/]> {
543 // Instruction operands.
548 // Encode instruction operands.
549 let Inst{3-0} = Dm{3-0};
551 let Inst{15-12} = Rt;
552 let Inst{19-16} = Rt2;
554 let Inst{7-6} = 0b00;
556 // Some single precision VFP instructions may be executed on both NEON and VFP
558 let D = VFPNeonDomain;
561 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
562 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
563 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
564 [/* For disassembly only; pattern left blank */]> {
569 // Encode instruction operands.
570 let Inst{3-0} = src1{3-0};
571 let Inst{5} = src1{4};
572 let Inst{15-12} = Rt;
573 let Inst{19-16} = Rt2;
575 let Inst{7-6} = 0b00;
577 // Some single precision VFP instructions may be executed on both NEON and VFP
579 let D = VFPNeonDomain;
580 let DecoderMethod = "DecodeVMOVRRS";
582 } // neverHasSideEffects
587 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
588 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
589 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
590 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
591 // Instruction operands.
596 // Encode instruction operands.
597 let Inst{3-0} = Dm{3-0};
599 let Inst{15-12} = Rt;
600 let Inst{19-16} = Rt2;
602 let Inst{7-6} = 0b00;
604 // Some single precision VFP instructions may be executed on both NEON and VFP
606 let D = VFPNeonDomain;
609 let neverHasSideEffects = 1 in
610 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
611 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
612 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
613 [/* For disassembly only; pattern left blank */]> {
614 // Instruction operands.
619 // Encode instruction operands.
620 let Inst{3-0} = dst1{3-0};
621 let Inst{5} = dst1{4};
622 let Inst{15-12} = src1;
623 let Inst{19-16} = src2;
625 let Inst{7-6} = 0b00;
627 // Some single precision VFP instructions may be executed on both NEON and VFP
629 let D = VFPNeonDomain;
631 let DecoderMethod = "DecodeVMOVSRR";
637 // FMRX: SPR system reg -> GPR
639 // FMXR: GPR -> VFP system reg
644 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
645 bits<4> opcod4, dag oops, dag iops,
646 InstrItinClass itin, string opc, string asm,
648 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
650 // Instruction operands.
654 // Encode instruction operands.
655 let Inst{3-0} = Sm{4-1};
657 let Inst{15-12} = Dd{3-0};
658 let Inst{22} = Dd{4};
661 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
662 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
663 string opc, string asm, list<dag> pattern>
664 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
666 // Instruction operands.
670 // Encode instruction operands.
671 let Inst{3-0} = Sm{4-1};
673 let Inst{15-12} = Sd{4-1};
674 let Inst{22} = Sd{0};
677 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
678 (outs DPR:$Dd), (ins SPR:$Sm),
679 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
680 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
681 let Inst{7} = 1; // s32
684 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
685 (outs SPR:$Sd),(ins SPR:$Sm),
686 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
687 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
688 let Inst{7} = 1; // s32
690 // Some single precision VFP instructions may be executed on both NEON and
691 // VFP pipelines on A8.
692 let D = VFPNeonA8Domain;
695 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
696 (outs DPR:$Dd), (ins SPR:$Sm),
697 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
698 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
699 let Inst{7} = 0; // u32
702 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
703 (outs SPR:$Sd), (ins SPR:$Sm),
704 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
705 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
706 let Inst{7} = 0; // u32
708 // Some single precision VFP instructions may be executed on both NEON and
709 // VFP pipelines on A8.
710 let D = VFPNeonA8Domain;
715 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
716 bits<4> opcod4, dag oops, dag iops,
717 InstrItinClass itin, string opc, string asm,
719 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
721 // Instruction operands.
725 // Encode instruction operands.
726 let Inst{3-0} = Dm{3-0};
728 let Inst{15-12} = Sd{4-1};
729 let Inst{22} = Sd{0};
732 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
733 bits<4> opcod4, dag oops, dag iops,
734 InstrItinClass itin, string opc, string asm,
736 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
738 // Instruction operands.
742 // Encode instruction operands.
743 let Inst{3-0} = Sm{4-1};
745 let Inst{15-12} = Sd{4-1};
746 let Inst{22} = Sd{0};
749 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
750 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
751 (outs SPR:$Sd), (ins DPR:$Dm),
752 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
753 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
754 let Inst{7} = 1; // Z bit
757 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
758 (outs SPR:$Sd), (ins SPR:$Sm),
759 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
760 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
761 let Inst{7} = 1; // Z bit
763 // Some single precision VFP instructions may be executed on both NEON and
764 // VFP pipelines on A8.
765 let D = VFPNeonA8Domain;
768 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
769 (outs SPR:$Sd), (ins DPR:$Dm),
770 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
771 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
772 let Inst{7} = 1; // Z bit
775 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
776 (outs SPR:$Sd), (ins SPR:$Sm),
777 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
778 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
779 let Inst{7} = 1; // Z bit
781 // Some single precision VFP instructions may be executed on both NEON and
782 // VFP pipelines on A8.
783 let D = VFPNeonA8Domain;
786 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
787 let Uses = [FPSCR] in {
788 // FIXME: Verify encoding after integrated assembler is working.
789 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
790 (outs SPR:$Sd), (ins DPR:$Dm),
791 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
792 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
793 let Inst{7} = 0; // Z bit
796 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
797 (outs SPR:$Sd), (ins SPR:$Sm),
798 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
799 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
800 let Inst{7} = 0; // Z bit
803 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
804 (outs SPR:$Sd), (ins DPR:$Dm),
805 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
806 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
807 let Inst{7} = 0; // Z bit
810 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
811 (outs SPR:$Sd), (ins SPR:$Sm),
812 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
813 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
814 let Inst{7} = 0; // Z bit
818 // Convert between floating-point and fixed-point
819 // Data type for fixed-point naming convention:
820 // S16 (U=0, sx=0) -> SH
821 // U16 (U=1, sx=0) -> UH
822 // S32 (U=0, sx=1) -> SL
823 // U32 (U=1, sx=1) -> UL
825 let Constraints = "$a = $dst" in {
827 // FP to Fixed-Point:
829 // Single Precision register
830 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
831 bit op5, dag oops, dag iops, InstrItinClass itin,
832 string opc, string asm, list<dag> pattern>
833 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
835 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
836 let Inst{22} = dst{0};
837 let Inst{15-12} = dst{4-1};
840 // Double Precision register
841 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
842 bit op5, dag oops, dag iops, InstrItinClass itin,
843 string opc, string asm, list<dag> pattern>
844 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
846 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
847 let Inst{22} = dst{4};
848 let Inst{15-12} = dst{3-0};
851 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
852 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
853 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
854 // Some single precision VFP instructions may be executed on both NEON and
855 // VFP pipelines on A8.
856 let D = VFPNeonA8Domain;
859 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
860 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
861 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
862 // Some single precision VFP instructions may be executed on both NEON and
863 // VFP pipelines on A8.
864 let D = VFPNeonA8Domain;
867 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
868 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
869 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
870 // Some single precision VFP instructions may be executed on both NEON and
871 // VFP pipelines on A8.
872 let D = VFPNeonA8Domain;
875 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
876 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
877 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
878 // Some single precision VFP instructions may be executed on both NEON and
879 // VFP pipelines on A8.
880 let D = VFPNeonA8Domain;
883 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
884 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
885 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
887 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
888 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
889 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
891 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
892 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
893 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
895 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
896 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
897 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
899 // Fixed-Point to FP:
901 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
902 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
903 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
904 // Some single precision VFP instructions may be executed on both NEON and
905 // VFP pipelines on A8.
906 let D = VFPNeonA8Domain;
909 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
910 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
911 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
912 // Some single precision VFP instructions may be executed on both NEON and
913 // VFP pipelines on A8.
914 let D = VFPNeonA8Domain;
917 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
918 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
919 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
920 // Some single precision VFP instructions may be executed on both NEON and
921 // VFP pipelines on A8.
922 let D = VFPNeonA8Domain;
925 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
926 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
927 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
928 // Some single precision VFP instructions may be executed on both NEON and
929 // VFP pipelines on A8.
930 let D = VFPNeonA8Domain;
933 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
934 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
935 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
937 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
938 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
939 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
941 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
942 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
943 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
945 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
946 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
947 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
949 } // End of 'let Constraints = "$a = $dst" in'
951 //===----------------------------------------------------------------------===//
952 // FP Multiply-Accumulate Operations.
955 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
956 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
957 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
958 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
960 RegConstraint<"$Ddin = $Dd">,
961 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
963 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
964 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
965 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
966 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
968 RegConstraint<"$Sdin = $Sd">,
969 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
970 // Some single precision VFP instructions may be executed on both NEON and
971 // VFP pipelines on A8.
972 let D = VFPNeonA8Domain;
975 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
976 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
977 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
978 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
979 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
980 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
982 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
983 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
984 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
985 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
987 RegConstraint<"$Ddin = $Dd">,
988 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
990 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
991 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
992 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
993 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
995 RegConstraint<"$Sdin = $Sd">,
996 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
997 // Some single precision VFP instructions may be executed on both NEON and
998 // VFP pipelines on A8.
999 let D = VFPNeonA8Domain;
1002 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1003 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1004 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1005 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1006 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1007 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1009 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1010 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1011 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1012 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1013 (f64 DPR:$Ddin)))]>,
1014 RegConstraint<"$Ddin = $Dd">,
1015 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1017 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1018 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1019 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1020 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1022 RegConstraint<"$Sdin = $Sd">,
1023 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1024 // Some single precision VFP instructions may be executed on both NEON and
1025 // VFP pipelines on A8.
1026 let D = VFPNeonA8Domain;
1029 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1030 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1031 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1032 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1033 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1034 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1036 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1037 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1038 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1039 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1040 (f64 DPR:$Ddin)))]>,
1041 RegConstraint<"$Ddin = $Dd">,
1042 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1044 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1045 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1046 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1047 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1048 RegConstraint<"$Sdin = $Sd">,
1049 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1050 // Some single precision VFP instructions may be executed on both NEON and
1051 // VFP pipelines on A8.
1052 let D = VFPNeonA8Domain;
1055 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1056 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1057 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1058 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1059 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1060 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1062 //===----------------------------------------------------------------------===//
1063 // Fused FP Multiply-Accumulate Operations.
1065 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1066 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1067 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1068 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1069 (f64 DPR:$Ddin)))]>,
1070 RegConstraint<"$Ddin = $Dd">,
1071 Requires<[HasVFP4,UseFusedMAC]>;
1073 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1074 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1075 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1076 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1078 RegConstraint<"$Sdin = $Sd">,
1079 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1080 // Some single precision VFP instructions may be executed on both NEON and
1084 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1085 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1086 Requires<[HasVFP4,UseFusedMAC]>;
1087 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1088 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1089 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1091 // Match @llvm.fma.* intrinsics
1092 // (fma x, y, z) -> (vfms z, x, y)
1093 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1094 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1095 Requires<[HasVFP4]>;
1096 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1097 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1098 Requires<[HasVFP4]>;
1100 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1101 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1102 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1103 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1104 (f64 DPR:$Ddin)))]>,
1105 RegConstraint<"$Ddin = $Dd">,
1106 Requires<[HasVFP4,UseFusedMAC]>;
1108 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1109 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1110 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1111 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1113 RegConstraint<"$Sdin = $Sd">,
1114 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1115 // Some single precision VFP instructions may be executed on both NEON and
1119 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1120 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1121 Requires<[HasVFP4,UseFusedMAC]>;
1122 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1123 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1124 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1126 // Match @llvm.fma.* intrinsics
1127 // (fma (fneg x), y, z) -> (vfms z, x, y)
1128 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1129 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1130 Requires<[HasVFP4]>;
1131 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1132 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1133 Requires<[HasVFP4]>;
1134 // (fma x, (fneg y), z) -> (vfms z, x, y)
1135 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1136 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1137 Requires<[HasVFP4]>;
1138 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1139 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1140 Requires<[HasVFP4]>;
1142 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1143 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1144 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1145 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1146 (f64 DPR:$Ddin)))]>,
1147 RegConstraint<"$Ddin = $Dd">,
1148 Requires<[HasVFP4,UseFusedMAC]>;
1150 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1151 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1152 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1153 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1155 RegConstraint<"$Sdin = $Sd">,
1156 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1157 // Some single precision VFP instructions may be executed on both NEON and
1161 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1162 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1163 Requires<[HasVFP4,UseFusedMAC]>;
1164 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1165 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1166 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1168 // Match @llvm.fma.* intrinsics
1169 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1170 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1171 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1172 Requires<[HasVFP4]>;
1173 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1174 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1175 Requires<[HasVFP4]>;
1176 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1177 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1178 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1179 Requires<[HasVFP4]>;
1180 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1181 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1182 Requires<[HasVFP4]>;
1184 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1185 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1186 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1187 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1188 (f64 DPR:$Ddin)))]>,
1189 RegConstraint<"$Ddin = $Dd">,
1190 Requires<[HasVFP4,UseFusedMAC]>;
1192 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1193 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1194 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1195 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1196 RegConstraint<"$Sdin = $Sd">,
1197 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1198 // Some single precision VFP instructions may be executed on both NEON and
1202 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1203 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1204 Requires<[HasVFP4,UseFusedMAC]>;
1205 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1206 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1207 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1209 // Match @llvm.fma.* intrinsics
1211 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1212 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1213 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1214 Requires<[HasVFP4]>;
1215 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1216 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1217 Requires<[HasVFP4]>;
1218 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1219 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1220 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1221 Requires<[HasVFP4]>;
1222 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1223 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1224 Requires<[HasVFP4]>;
1225 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1226 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1227 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1228 Requires<[HasVFP4]>;
1229 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1230 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1231 Requires<[HasVFP4]>;
1233 //===----------------------------------------------------------------------===//
1234 // FP Conditional moves.
1237 let neverHasSideEffects = 1 in {
1238 def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
1240 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
1241 RegConstraint<"$Dn = $Dd">;
1243 def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
1245 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
1246 RegConstraint<"$Sn = $Sd">;
1247 } // neverHasSideEffects
1249 //===----------------------------------------------------------------------===//
1250 // Move from VFP System Register to ARM core register.
1253 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1255 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1257 // Instruction operand.
1260 let Inst{27-20} = 0b11101111;
1261 let Inst{19-16} = opc19_16;
1262 let Inst{15-12} = Rt;
1263 let Inst{11-8} = 0b1010;
1265 let Inst{6-5} = 0b00;
1267 let Inst{3-0} = 0b0000;
1270 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1272 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1273 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1274 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1276 // Application level FPSCR -> GPR
1277 let hasSideEffects = 1, Uses = [FPSCR] in
1278 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1279 "vmrs", "\t$Rt, fpscr",
1280 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1282 // System level FPEXC, FPSID -> GPR
1283 let Uses = [FPSCR] in {
1284 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1285 "vmrs", "\t$Rt, fpexc", []>;
1286 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1287 "vmrs", "\t$Rt, fpsid", []>;
1288 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1289 "vmrs", "\t$Rt, mvfr0", []>;
1290 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1291 "vmrs", "\t$Rt, mvfr1", []>;
1294 //===----------------------------------------------------------------------===//
1295 // Move from ARM core register to VFP System Register.
1298 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1300 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1302 // Instruction operand.
1305 // Encode instruction operand.
1306 let Inst{15-12} = src;
1308 let Inst{27-20} = 0b11101110;
1309 let Inst{19-16} = opc19_16;
1310 let Inst{11-8} = 0b1010;
1315 let Defs = [FPSCR] in {
1316 // Application level GPR -> FPSCR
1317 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1318 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1319 // System level GPR -> FPEXC
1320 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1321 "vmsr", "\tfpexc, $src", []>;
1322 // System level GPR -> FPSID
1323 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1324 "vmsr", "\tfpsid, $src", []>;
1327 //===----------------------------------------------------------------------===//
1331 // Materialize FP immediates. VFP3 only.
1332 let isReMaterializable = 1 in {
1333 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1334 VFPMiscFrm, IIC_fpUNA64,
1335 "vmov", ".f64\t$Dd, $imm",
1336 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1340 let Inst{27-23} = 0b11101;
1341 let Inst{22} = Dd{4};
1342 let Inst{21-20} = 0b11;
1343 let Inst{19-16} = imm{7-4};
1344 let Inst{15-12} = Dd{3-0};
1345 let Inst{11-9} = 0b101;
1346 let Inst{8} = 1; // Double precision.
1347 let Inst{7-4} = 0b0000;
1348 let Inst{3-0} = imm{3-0};
1351 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1352 VFPMiscFrm, IIC_fpUNA32,
1353 "vmov", ".f32\t$Sd, $imm",
1354 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1358 let Inst{27-23} = 0b11101;
1359 let Inst{22} = Sd{0};
1360 let Inst{21-20} = 0b11;
1361 let Inst{19-16} = imm{7-4};
1362 let Inst{15-12} = Sd{4-1};
1363 let Inst{11-9} = 0b101;
1364 let Inst{8} = 0; // Single precision.
1365 let Inst{7-4} = 0b0000;
1366 let Inst{3-0} = imm{3-0};
1370 //===----------------------------------------------------------------------===//
1371 // Assembler aliases.
1373 // A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to
1374 // support them all, but supporting at least some of the basics is
1375 // good to be friendly.
1376 def : VFP2MnemonicAlias<"flds", "vldr">;
1377 def : VFP2MnemonicAlias<"fldd", "vldr">;
1378 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1379 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1380 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1381 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1382 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1383 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1384 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1385 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1386 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1387 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1388 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1389 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1390 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1391 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1392 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1393 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1394 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1395 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1396 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1397 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1398 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1399 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1400 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1401 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1402 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1403 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1404 def : VFP2MnemonicAlias<"fsts", "vstr">;
1405 def : VFP2MnemonicAlias<"fstd", "vstr">;
1406 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1407 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1408 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1409 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1410 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1411 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1412 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1413 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1414 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1415 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1417 // Be friendly and accept the old form of zero-compare
1418 def : VFP2InstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1419 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1422 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1423 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1424 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1425 def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm",
1426 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1427 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1428 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1429 def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1430 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1432 // No need for the size suffix on VSQRT. It's implied by the register classes.
1433 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1434 def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1436 // VLDR/VSTR accept an optional type suffix.
1437 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1438 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1439 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1440 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1441 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1442 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1443 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1444 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1446 // VMOV can accept optional 32-bit or less data type suffix suffix.
1447 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1448 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1449 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1450 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1451 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1452 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1453 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1454 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1455 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1456 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1457 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1458 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1460 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1461 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1462 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1463 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1465 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1467 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1468 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;