1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
15 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
17 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
19 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
21 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
24 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
25 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
26 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
27 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
28 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
29 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
30 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
31 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
33 //===----------------------------------------------------------------------===//
34 // Operand Definitions.
38 def vfp_f32imm : Operand<f32>,
39 PatLeaf<(f32 fpimm), [{
40 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
42 let PrintMethod = "printVFPf32ImmOperand";
45 def vfp_f64imm : Operand<f64>,
46 PatLeaf<(f64 fpimm), [{
47 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
49 let PrintMethod = "printVFPf64ImmOperand";
53 //===----------------------------------------------------------------------===//
54 // Load / store Instructions.
57 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
58 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
59 IIC_fpLoad64, "vldr", ".64\t$dst, $addr",
60 [(set DPR:$dst, (load addrmode5:$addr))]>;
62 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
63 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
64 [(set SPR:$dst, (load addrmode5:$addr))]>;
67 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
68 IIC_fpStore64, "vstr", ".64\t$src, $addr",
69 [(store DPR:$src, addrmode5:$addr)]>;
71 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
72 IIC_fpStore32, "vstr", ".32\t$src, $addr",
73 [(store SPR:$src, addrmode5:$addr)]>;
75 //===----------------------------------------------------------------------===//
76 // Load / store multiple Instructions.
79 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
80 def VLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
81 variable_ops), IIC_fpLoadm,
82 "vldm${addr:submode}${p}\t${addr:base}, $wb",
87 def VLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
88 variable_ops), IIC_fpLoadm,
89 "vldm${addr:submode}${p}\t${addr:base}, $wb",
93 } // mayLoad, hasExtraDefRegAllocReq
95 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
96 def VSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
97 variable_ops), IIC_fpStorem,
98 "vstm${addr:submode}${p}\t${addr:base}, $wb",
103 def VSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
104 variable_ops), IIC_fpStorem,
105 "vstm${addr:submode}${p}\t${addr:base}, $wb",
109 } // mayStore, hasExtraSrcRegAllocReq
111 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
113 //===----------------------------------------------------------------------===//
114 // FP Binary Operations.
117 def VADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
118 IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b",
119 [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
121 def VADDS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
122 IIC_fpALU32, "vadd", ".f32\t$dst, $a, $b",
123 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
125 // These are encoded as unary instructions.
126 let Defs = [FPSCR] in {
127 def VCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a, DPR:$b),
128 IIC_fpCMP64, "vcmpe", ".f64\t$a, $b",
129 [(arm_cmpfp DPR:$a, DPR:$b)]>;
131 def VCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a, SPR:$b),
132 IIC_fpCMP32, "vcmpe", ".f32\t$a, $b",
133 [(arm_cmpfp SPR:$a, SPR:$b)]>;
136 def VDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
137 IIC_fpDIV64, "vdiv", ".f64\t$dst, $a, $b",
138 [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
140 def VDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
141 IIC_fpDIV32, "vdiv", ".f32\t$dst, $a, $b",
142 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
144 def VMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
145 IIC_fpMUL64, "vmul", ".f64\t$dst, $a, $b",
146 [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
148 def VMULS : ASbIn<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
149 IIC_fpMUL32, "vmul", ".f32\t$dst, $a, $b",
150 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
152 def VNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
153 IIC_fpMUL64, "vnmul", ".f64\t$dst, $a, $b",
154 [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
158 def VNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
159 IIC_fpMUL32, "vnmul", ".f32\t$dst, $a, $b",
160 [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
164 // Match reassociated forms only if not sign dependent rounding.
165 def : Pat<(fmul (fneg DPR:$a), DPR:$b),
166 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
167 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
168 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
171 def VSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
172 IIC_fpALU64, "vsub", ".f64\t$dst, $a, $b",
173 [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]> {
177 def VSUBS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
178 IIC_fpALU32, "vsub", ".f32\t$dst, $a, $b",
179 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]> {
183 //===----------------------------------------------------------------------===//
184 // FP Unary Operations.
187 def VABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins DPR:$a),
188 IIC_fpUNA64, "vabs", ".f64\t$dst, $a",
189 [(set DPR:$dst, (fabs DPR:$a))]>;
191 def VABSS : ASuIn<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
192 IIC_fpUNA32, "vabs", ".f32\t$dst, $a",
193 [(set SPR:$dst, (fabs SPR:$a))]>;
195 let Defs = [FPSCR] in {
196 def VCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
197 IIC_fpCMP64, "vcmpe", ".f64\t$a, #0",
198 [(arm_cmpfp0 DPR:$a)]>;
200 def VCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
201 IIC_fpCMP32, "vcmpe", ".f32\t$a, #0",
202 [(arm_cmpfp0 SPR:$a)]>;
205 def VCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins SPR:$a),
206 IIC_fpCVTDS, "vcvt", ".f64.f32\t$dst, $a",
207 [(set DPR:$dst, (fextend SPR:$a))]>;
209 // Special case encoding: bits 11-8 is 0b1011.
210 def VCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
211 IIC_fpCVTSD, "vcvt", ".f32.f64\t$dst, $a",
212 [(set SPR:$dst, (fround DPR:$a))]> {
213 let Inst{27-23} = 0b11101;
214 let Inst{21-16} = 0b110111;
215 let Inst{11-8} = 0b1011;
216 let Inst{7-4} = 0b1100;
219 let neverHasSideEffects = 1 in {
220 def VMOVD: ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins DPR:$a),
221 IIC_fpUNA64, "vmov", ".f64\t$dst, $a", []>;
223 def VMOVS: ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins SPR:$a),
224 IIC_fpUNA32, "vmov", ".f32\t$dst, $a", []>;
225 } // neverHasSideEffects
227 def VNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins DPR:$a),
228 IIC_fpUNA64, "vneg", ".f64\t$dst, $a",
229 [(set DPR:$dst, (fneg DPR:$a))]>;
231 def VNEGS : ASuIn<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
232 IIC_fpUNA32, "vneg", ".f32\t$dst, $a",
233 [(set SPR:$dst, (fneg SPR:$a))]>;
235 def VSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
236 IIC_fpSQRT64, "vsqrt", ".f64\t$dst, $a",
237 [(set DPR:$dst, (fsqrt DPR:$a))]>;
239 def VSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
240 IIC_fpSQRT32, "vsqrt", ".f32\t$dst, $a",
241 [(set SPR:$dst, (fsqrt SPR:$a))]>;
243 //===----------------------------------------------------------------------===//
244 // FP <-> GPR Copies. Int <-> FP Conversions.
247 def VMOVRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
248 IIC_VMOVSI, "vmov", "\t$dst, $src",
249 [(set GPR:$dst, (bitconvert SPR:$src))]>;
251 def VMOVSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
252 IIC_VMOVIS, "vmov", "\t$dst, $src",
253 [(set SPR:$dst, (bitconvert GPR:$src))]>;
255 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
256 (outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
257 IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src",
258 [/* FIXME: Can't write pattern for multiple result instr*/]>;
263 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
264 (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
265 IIC_VMOVID, "vmov", "\t$dst, $src1, $src2",
266 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
271 // FMRX : SPR system reg -> GPR
275 // FMXR: GPR -> VFP Sstem reg
280 def VSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
281 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a",
282 [(set DPR:$dst, (arm_sitof SPR:$a))]> {
286 def VSITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),(ins SPR:$a),
287 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a",
288 [(set SPR:$dst, (arm_sitof SPR:$a))]> {
292 def VUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
293 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a",
294 [(set DPR:$dst, (arm_uitof SPR:$a))]>;
296 def VUITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),(ins SPR:$a),
297 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a",
298 [(set SPR:$dst, (arm_uitof SPR:$a))]>;
301 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
303 def VTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011,
304 (outs SPR:$dst), (ins DPR:$a),
305 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a",
306 [(set SPR:$dst, (arm_ftosi DPR:$a))]> {
307 let Inst{7} = 1; // Z bit
310 def VTOSIZS : AVConv1In<0b11101011, 0b1101, 0b1010,
311 (outs SPR:$dst), (ins SPR:$a),
312 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a",
313 [(set SPR:$dst, (arm_ftosi SPR:$a))]> {
314 let Inst{7} = 1; // Z bit
317 def VTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011,
318 (outs SPR:$dst), (ins DPR:$a),
319 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a",
320 [(set SPR:$dst, (arm_ftoui DPR:$a))]> {
321 let Inst{7} = 1; // Z bit
324 def VTOUIZS : AVConv1In<0b11101011, 0b1100, 0b1010,
325 (outs SPR:$dst), (ins SPR:$a),
326 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a",
327 [(set SPR:$dst, (arm_ftoui SPR:$a))]> {
328 let Inst{7} = 1; // Z bit
331 //===----------------------------------------------------------------------===//
332 // FP FMA Operations.
335 def VMLAD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
336 IIC_fpMAC64, "vmla", ".f64\t$dst, $a, $b",
337 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
338 RegConstraint<"$dstin = $dst">;
340 def VMLAS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
341 IIC_fpMAC32, "vmla", ".f32\t$dst, $a, $b",
342 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
343 RegConstraint<"$dstin = $dst">;
345 def VNMLSD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
346 IIC_fpMAC64, "vnmls", ".f64\t$dst, $a, $b",
347 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
348 RegConstraint<"$dstin = $dst">;
350 def VNMLSS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
351 IIC_fpMAC32, "vnmls", ".f32\t$dst, $a, $b",
352 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
353 RegConstraint<"$dstin = $dst">;
355 def VMLSD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
356 IIC_fpMAC64, "vmls", ".f64\t$dst, $a, $b",
357 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
358 RegConstraint<"$dstin = $dst"> {
362 def VMLSS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
363 IIC_fpMAC32, "vmls", ".f32\t$dst, $a, $b",
364 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
365 RegConstraint<"$dstin = $dst"> {
369 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, DPR:$b)),
370 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
371 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
372 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
374 def VNMLAD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
375 IIC_fpMAC64, "vnmla", ".f64\t$dst, $a, $b",
376 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
377 RegConstraint<"$dstin = $dst"> {
381 def VNMLAS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
382 IIC_fpMAC32, "vnmla", ".f32\t$dst, $a, $b",
383 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
384 RegConstraint<"$dstin = $dst"> {
388 //===----------------------------------------------------------------------===//
389 // FP Conditional moves.
392 def VMOVDcc : ADuI<0b11101011, 0b0000, 0b0100,
393 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
394 IIC_fpUNA64, "vmov", ".f64\t$dst, $true",
395 [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
396 RegConstraint<"$false = $dst">;
398 def VMOVScc : ASuI<0b11101011, 0b0000, 0b0100,
399 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
400 IIC_fpUNA32, "vmov", ".f32\t$dst, $true",
401 [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
402 RegConstraint<"$false = $dst">;
404 def VNEGDcc : ADuI<0b11101011, 0b0001, 0b0100,
405 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
406 IIC_fpUNA64, "vneg", ".f64\t$dst, $true",
407 [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
408 RegConstraint<"$false = $dst">;
410 def VNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
411 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
412 IIC_fpUNA32, "vneg", ".f32\t$dst, $true",
413 [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
414 RegConstraint<"$false = $dst">;
417 //===----------------------------------------------------------------------===//
421 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
423 let Defs = [CPSR], Uses = [FPSCR] in
424 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
425 "\tapsr_nzcv, fpscr",
427 let Inst{27-20} = 0b11101111;
428 let Inst{19-16} = 0b0001;
429 let Inst{15-12} = 0b1111;
430 let Inst{11-8} = 0b1010;
436 // Materialize FP immediates. VFP3 only.
437 let isReMaterializable = 1 in {
438 def FCONSTD : VFPAI<(outs DPR:$dst), (ins vfp_f64imm:$imm),
439 VFPMiscFrm, IIC_VMOVImm,
440 "vmov", ".f64\t$dst, $imm",
441 [(set DPR:$dst, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
442 let Inst{27-23} = 0b11101;
443 let Inst{21-20} = 0b11;
444 let Inst{11-9} = 0b101;
446 let Inst{7-4} = 0b0000;
449 def FCONSTS : VFPAI<(outs SPR:$dst), (ins vfp_f32imm:$imm),
450 VFPMiscFrm, IIC_VMOVImm,
451 "vmov", ".f32\t$dst, $imm",
452 [(set SPR:$dst, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
453 let Inst{27-23} = 0b11101;
454 let Inst{21-20} = 0b11;
455 let Inst{11-9} = 0b101;
457 let Inst{7-4} = 0b0000;