1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
15 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
17 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
19 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
21 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
24 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
25 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
26 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
27 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
28 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
29 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
30 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
31 def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
33 //===----------------------------------------------------------------------===//
34 // Load / store Instructions.
37 let canFoldAsLoad = 1 in {
38 def FLDD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
39 IIC_fpLoad, "fldd", " $dst, $addr",
40 [(set DPR:$dst, (load addrmode5:$addr))]>;
42 def FLDS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
43 IIC_fpLoad, "flds", " $dst, $addr",
44 [(set SPR:$dst, (load addrmode5:$addr))]>;
47 def FSTD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
48 IIC_fpStore, "fstd", " $src, $addr",
49 [(store DPR:$src, addrmode5:$addr)]>;
51 def FSTS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
52 IIC_fpStore, "fsts", " $src, $addr",
53 [(store SPR:$src, addrmode5:$addr)]>;
55 //===----------------------------------------------------------------------===//
56 // Load / store multiple Instructions.
60 def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
61 variable_ops), IIC_fpLoad,
62 "fldm${addr:submode}d${p} ${addr:base}, $dst1",
67 def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
68 variable_ops), IIC_fpLoad,
69 "fldm${addr:submode}s${p} ${addr:base}, $dst1",
76 def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
77 variable_ops), IIC_fpStore,
78 "fstm${addr:submode}d${p} ${addr:base}, $src1",
83 def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
84 variable_ops), IIC_fpStore,
85 "fstm${addr:submode}s${p} ${addr:base}, $src1",
91 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
93 //===----------------------------------------------------------------------===//
94 // FP Binary Operations.
97 def FADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
98 IIC_fpALU, "faddd", " $dst, $a, $b",
99 [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
101 def FADDS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
102 IIC_fpALU, "fadds", " $dst, $a, $b",
103 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
105 // These are encoded as unary instructions.
106 let Defs = [FPSCR] in {
107 def FCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a, DPR:$b),
108 IIC_fpALU, "fcmped", " $a, $b",
109 [(arm_cmpfp DPR:$a, DPR:$b)]>;
111 def FCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a, SPR:$b),
112 IIC_fpALU, "fcmpes", " $a, $b",
113 [(arm_cmpfp SPR:$a, SPR:$b)]>;
116 def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
117 IIC_fpALU, "fdivd", " $dst, $a, $b",
118 [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
120 def FDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
121 IIC_fpALU, "fdivs", " $dst, $a, $b",
122 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
124 def FMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
125 IIC_fpALU, "fmuld", " $dst, $a, $b",
126 [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
128 def FMULS : ASbIn<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
129 IIC_fpALU, "fmuls", " $dst, $a, $b",
130 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
132 def FNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
133 IIC_fpALU, "fnmuld", " $dst, $a, $b",
134 [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
138 def FNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
139 IIC_fpALU, "fnmuls", " $dst, $a, $b",
140 [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
144 // Match reassociated forms only if not sign dependent rounding.
145 def : Pat<(fmul (fneg DPR:$a), DPR:$b),
146 (FNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
147 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
148 (FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
151 def FSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
152 IIC_fpALU, "fsubd", " $dst, $a, $b",
153 [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]> {
157 def FSUBS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
158 IIC_fpALU, "fsubs", " $dst, $a, $b",
159 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]> {
163 //===----------------------------------------------------------------------===//
164 // FP Unary Operations.
167 def FABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins DPR:$a),
168 IIC_fpALU, "fabsd", " $dst, $a",
169 [(set DPR:$dst, (fabs DPR:$a))]>;
171 def FABSS : ASuIn<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
172 IIC_fpALU, "fabss", " $dst, $a",
173 [(set SPR:$dst, (fabs SPR:$a))]>;
175 let Defs = [FPSCR] in {
176 def FCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
177 IIC_fpALU, "fcmpezd", " $a",
178 [(arm_cmpfp0 DPR:$a)]>;
180 def FCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
181 IIC_fpALU, "fcmpezs", " $a",
182 [(arm_cmpfp0 SPR:$a)]>;
185 def FCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins SPR:$a),
186 IIC_fpALU, "fcvtds", " $dst, $a",
187 [(set DPR:$dst, (fextend SPR:$a))]>;
189 // Special case encoding: bits 11-8 is 0b1011.
190 def FCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
191 IIC_fpALU, "fcvtsd", " $dst, $a",
192 [(set SPR:$dst, (fround DPR:$a))]> {
193 let Inst{27-23} = 0b11101;
194 let Inst{21-16} = 0b110111;
195 let Inst{11-8} = 0b1011;
196 let Inst{7-4} = 0b1100;
199 let neverHasSideEffects = 1 in {
200 def FCPYD : ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins DPR:$a),
201 IIC_fpALU, "fcpyd", " $dst, $a", []>;
203 def FCPYS : ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins SPR:$a),
204 IIC_fpALU, "fcpys", " $dst, $a", []>;
205 } // neverHasSideEffects
207 def FNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins DPR:$a),
208 IIC_fpALU, "fnegd", " $dst, $a",
209 [(set DPR:$dst, (fneg DPR:$a))]>;
211 def FNEGS : ASuIn<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
212 IIC_fpALU, "fnegs", " $dst, $a",
213 [(set SPR:$dst, (fneg SPR:$a))]>;
215 def FSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
216 IIC_fpALU, "fsqrtd", " $dst, $a",
217 [(set DPR:$dst, (fsqrt DPR:$a))]>;
219 def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
220 IIC_fpALU, "fsqrts", " $dst, $a",
221 [(set SPR:$dst, (fsqrt SPR:$a))]>;
223 //===----------------------------------------------------------------------===//
224 // FP <-> GPR Copies. Int <-> FP Conversions.
227 def FMRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
228 IIC_fpALU, "fmrs", " $dst, $src",
229 [(set GPR:$dst, (bitconvert SPR:$src))]>;
231 def FMSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
232 IIC_fpALU, "fmsr", " $dst, $src",
233 [(set SPR:$dst, (bitconvert GPR:$src))]>;
235 def FMRRD : AVConv3I<0b11000101, 0b1011,
236 (outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
237 IIC_fpALU, "fmrrd", " $dst1, $dst2, $src",
238 [/* FIXME: Can't write pattern for multiple result instr*/]>;
243 def FMDRR : AVConv5I<0b11000100, 0b1011,
244 (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
245 IIC_fpALU, "fmdrr", " $dst, $src1, $src2",
246 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
251 // FMRX : SPR system reg -> GPR
255 // FMXR: GPR -> VFP Sstem reg
260 def FSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
261 IIC_fpALU, "fsitod", " $dst, $a",
262 [(set DPR:$dst, (arm_sitof SPR:$a))]> {
266 def FSITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
267 IIC_fpALU, "fsitos", " $dst, $a",
268 [(set SPR:$dst, (arm_sitof SPR:$a))]> {
272 def FUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
273 IIC_fpALU, "fuitod", " $dst, $a",
274 [(set DPR:$dst, (arm_uitof SPR:$a))]>;
276 def FUITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
277 IIC_fpALU, "fuitos", " $dst, $a",
278 [(set SPR:$dst, (arm_uitof SPR:$a))]>;
281 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
283 def FTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011,
284 (outs SPR:$dst), (ins DPR:$a),
285 IIC_fpALU, "ftosizd", " $dst, $a",
286 [(set SPR:$dst, (arm_ftosi DPR:$a))]> {
287 let Inst{7} = 1; // Z bit
290 def FTOSIZS : AVConv1I<0b11101011, 0b1101, 0b1010,
291 (outs SPR:$dst), (ins SPR:$a),
292 IIC_fpALU, "ftosizs", " $dst, $a",
293 [(set SPR:$dst, (arm_ftosi SPR:$a))]> {
294 let Inst{7} = 1; // Z bit
297 def FTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011,
298 (outs SPR:$dst), (ins DPR:$a),
299 IIC_fpALU, "ftouizd", " $dst, $a",
300 [(set SPR:$dst, (arm_ftoui DPR:$a))]> {
301 let Inst{7} = 1; // Z bit
304 def FTOUIZS : AVConv1I<0b11101011, 0b1100, 0b1010,
305 (outs SPR:$dst), (ins SPR:$a),
306 IIC_fpALU, "ftouizs", " $dst, $a",
307 [(set SPR:$dst, (arm_ftoui SPR:$a))]> {
308 let Inst{7} = 1; // Z bit
311 //===----------------------------------------------------------------------===//
312 // FP FMA Operations.
315 def FMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
316 IIC_fpALU, "fmacd", " $dst, $a, $b",
317 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
318 RegConstraint<"$dstin = $dst">;
320 def FMACS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
321 IIC_fpALU, "fmacs", " $dst, $a, $b",
322 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
323 RegConstraint<"$dstin = $dst">;
325 def FMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
326 IIC_fpALU, "fmscd", " $dst, $a, $b",
327 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
328 RegConstraint<"$dstin = $dst">;
330 def FMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
331 IIC_fpALU, "fmscs", " $dst, $a, $b",
332 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
333 RegConstraint<"$dstin = $dst">;
335 def FNMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
336 IIC_fpALU, "fnmacd", " $dst, $a, $b",
337 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
338 RegConstraint<"$dstin = $dst"> {
342 def FNMACS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
343 IIC_fpALU, "fnmacs", " $dst, $a, $b",
344 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
345 RegConstraint<"$dstin = $dst"> {
349 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, DPR:$b)),
350 (FNMACD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
351 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
352 (FNMACS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
354 def FNMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
355 IIC_fpALU, "fnmscd", " $dst, $a, $b",
356 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
357 RegConstraint<"$dstin = $dst"> {
361 def FNMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
362 IIC_fpALU, "fnmscs", " $dst, $a, $b",
363 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
364 RegConstraint<"$dstin = $dst"> {
368 //===----------------------------------------------------------------------===//
369 // FP Conditional moves.
372 def FCPYDcc : ADuI<0b11101011, 0b0000, 0b0100,
373 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
374 IIC_fpALU, "fcpyd", " $dst, $true",
375 [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
376 RegConstraint<"$false = $dst">;
378 def FCPYScc : ASuI<0b11101011, 0b0000, 0b0100,
379 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
380 IIC_fpALU, "fcpys", " $dst, $true",
381 [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
382 RegConstraint<"$false = $dst">;
384 def FNEGDcc : ADuI<0b11101011, 0b0001, 0b0100,
385 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
386 IIC_fpALU, "fnegd", " $dst, $true",
387 [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
388 RegConstraint<"$false = $dst">;
390 def FNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
391 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
392 IIC_fpALU, "fnegs", " $dst, $true",
393 [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
394 RegConstraint<"$false = $dst">;
397 //===----------------------------------------------------------------------===//
401 let Defs = [CPSR], Uses = [FPSCR] in
402 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpALU, "fmstat", "", [(arm_fmstat)]> {
403 let Inst{27-20} = 0b11101111;
404 let Inst{19-16} = 0b0001;
405 let Inst{15-12} = 0b1111;
406 let Inst{11-8} = 0b1010;