1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
15 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
17 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
19 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
21 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
24 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
25 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
26 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
27 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
28 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
29 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
30 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
31 def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
33 //===----------------------------------------------------------------------===//
34 // Load / store Instructions.
37 let canFoldAsLoad = 1 in {
38 def FLDD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
39 "fldd", " $dst, $addr",
40 [(set DPR:$dst, (load addrmode5:$addr))]>;
42 def FLDS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
43 "flds", " $dst, $addr",
44 [(set SPR:$dst, (load addrmode5:$addr))]>;
47 def FSTD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
48 "fstd", " $src, $addr",
49 [(store DPR:$src, addrmode5:$addr)]>;
51 def FSTS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
52 "fsts", " $src, $addr",
53 [(store SPR:$src, addrmode5:$addr)]>;
55 //===----------------------------------------------------------------------===//
56 // Load / store multiple Instructions.
60 def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
62 "fldm${addr:submode}d${p} ${addr:base}, $dst1",
67 def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
69 "fldm${addr:submode}s${p} ${addr:base}, $dst1",
76 def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
78 "fstm${addr:submode}d${p} ${addr:base}, $src1",
83 def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
85 "fstm${addr:submode}s${p} ${addr:base}, $src1",
91 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
93 //===----------------------------------------------------------------------===//
94 // FP Binary Operations.
97 def FADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
98 "faddd", " $dst, $a, $b",
99 [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
101 def FADDS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
102 "fadds", " $dst, $a, $b",
103 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
105 // These are encoded as unary instructions.
106 def FCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a, DPR:$b),
108 [(arm_cmpfp DPR:$a, DPR:$b)]>;
110 def FCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a, SPR:$b),
112 [(arm_cmpfp SPR:$a, SPR:$b)]>;
114 def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
115 "fdivd", " $dst, $a, $b",
116 [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
118 def FDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
119 "fdivs", " $dst, $a, $b",
120 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
122 def FMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
123 "fmuld", " $dst, $a, $b",
124 [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
126 def FMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
127 "fmuls", " $dst, $a, $b",
128 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
130 def FNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
131 "fnmuld", " $dst, $a, $b",
132 [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
136 def FNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
137 "fnmuls", " $dst, $a, $b",
138 [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
142 // Match reassociated forms only if not sign dependent rounding.
143 def : Pat<(fmul (fneg DPR:$a), DPR:$b),
144 (FNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
145 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
146 (FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
149 def FSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
150 "fsubd", " $dst, $a, $b",
151 [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]> {
155 def FSUBS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
156 "fsubs", " $dst, $a, $b",
157 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]> {
161 //===----------------------------------------------------------------------===//
162 // FP Unary Operations.
165 def FABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins DPR:$a),
166 "fabsd", " $dst, $a",
167 [(set DPR:$dst, (fabs DPR:$a))]>;
169 def FABSS : ASuI<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
170 "fabss", " $dst, $a",
171 [(set SPR:$dst, (fabs SPR:$a))]>;
173 def FCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
175 [(arm_cmpfp0 DPR:$a)]>;
177 def FCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
179 [(arm_cmpfp0 SPR:$a)]>;
181 def FCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins SPR:$a),
182 "fcvtds", " $dst, $a",
183 [(set DPR:$dst, (fextend SPR:$a))]>;
185 // Special case encoding: bits 11-8 is 0b1011.
186 def FCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
187 "fcvtsd", " $dst, $a",
188 [(set SPR:$dst, (fround DPR:$a))]> {
189 let Inst{27-23} = 0b11101;
190 let Inst{21-16} = 0b110111;
191 let Inst{11-8} = 0b1011;
192 let Inst{7-4} = 0b1100;
195 let neverHasSideEffects = 1 in {
196 def FCPYD : ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins DPR:$a),
197 "fcpyd", " $dst, $a", []>;
199 def FCPYS : ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins SPR:$a),
200 "fcpys", " $dst, $a", []>;
201 } // neverHasSideEffects
203 def FNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins DPR:$a),
204 "fnegd", " $dst, $a",
205 [(set DPR:$dst, (fneg DPR:$a))]>;
207 def FNEGS : ASuI<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
208 "fnegs", " $dst, $a",
209 [(set SPR:$dst, (fneg SPR:$a))]>;
211 def FSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
212 "fsqrtd", " $dst, $a",
213 [(set DPR:$dst, (fsqrt DPR:$a))]>;
215 def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
216 "fsqrts", " $dst, $a",
217 [(set SPR:$dst, (fsqrt SPR:$a))]>;
219 //===----------------------------------------------------------------------===//
220 // FP <-> GPR Copies. Int <-> FP Conversions.
223 def FMRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
224 "fmrs", " $dst, $src",
225 [(set GPR:$dst, (bitconvert SPR:$src))]>;
227 def FMSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
228 "fmsr", " $dst, $src",
229 [(set SPR:$dst, (bitconvert GPR:$src))]>;
231 def FMRRD : AVConv3I<0b11000101, 0b1011,
232 (outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
233 "fmrrd", " $dst1, $dst2, $src",
234 [/* FIXME: Can't write pattern for multiple result instr*/]>;
239 def FMDRR : AVConv5I<0b11000100, 0b1011,
240 (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
241 "fmdrr", " $dst, $src1, $src2",
242 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
247 // FMRX : SPR system reg -> GPR
251 // FMXR: GPR -> VFP Sstem reg
256 def FSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
257 "fsitod", " $dst, $a",
258 [(set DPR:$dst, (arm_sitof SPR:$a))]> {
262 def FSITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
263 "fsitos", " $dst, $a",
264 [(set SPR:$dst, (arm_sitof SPR:$a))]> {
268 def FUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
269 "fuitod", " $dst, $a",
270 [(set DPR:$dst, (arm_uitof SPR:$a))]>;
272 def FUITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
273 "fuitos", " $dst, $a",
274 [(set SPR:$dst, (arm_uitof SPR:$a))]>;
277 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
279 def FTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011,
280 (outs SPR:$dst), (ins DPR:$a),
281 "ftosizd", " $dst, $a",
282 [(set SPR:$dst, (arm_ftosi DPR:$a))]> {
283 let Inst{7} = 1; // Z bit
286 def FTOSIZS : AVConv1I<0b11101011, 0b1101, 0b1010,
287 (outs SPR:$dst), (ins SPR:$a),
288 "ftosizs", " $dst, $a",
289 [(set SPR:$dst, (arm_ftosi SPR:$a))]> {
290 let Inst{7} = 1; // Z bit
293 def FTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011,
294 (outs SPR:$dst), (ins DPR:$a),
295 "ftouizd", " $dst, $a",
296 [(set SPR:$dst, (arm_ftoui DPR:$a))]> {
297 let Inst{7} = 1; // Z bit
300 def FTOUIZS : AVConv1I<0b11101011, 0b1100, 0b1010,
301 (outs SPR:$dst), (ins SPR:$a),
302 "ftouizs", " $dst, $a",
303 [(set SPR:$dst, (arm_ftoui SPR:$a))]> {
304 let Inst{7} = 1; // Z bit
307 //===----------------------------------------------------------------------===//
308 // FP FMA Operations.
311 def FMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
312 "fmacd", " $dst, $a, $b",
313 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
314 RegConstraint<"$dstin = $dst">;
316 def FMACS : ASbI<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
317 "fmacs", " $dst, $a, $b",
318 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
319 RegConstraint<"$dstin = $dst">;
321 def FMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
322 "fmscd", " $dst, $a, $b",
323 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
324 RegConstraint<"$dstin = $dst">;
326 def FMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
327 "fmscs", " $dst, $a, $b",
328 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
329 RegConstraint<"$dstin = $dst">;
331 def FNMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
332 "fnmacd", " $dst, $a, $b",
333 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
334 RegConstraint<"$dstin = $dst"> {
338 def FNMACS : ASbI<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
339 "fnmacs", " $dst, $a, $b",
340 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
341 RegConstraint<"$dstin = $dst"> {
345 def FNMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
346 "fnmscd", " $dst, $a, $b",
347 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
348 RegConstraint<"$dstin = $dst"> {
352 def FNMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
353 "fnmscs", " $dst, $a, $b",
354 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
355 RegConstraint<"$dstin = $dst"> {
359 //===----------------------------------------------------------------------===//
360 // FP Conditional moves.
363 def FCPYDcc : ADuI<0b11101011, 0b0000, 0b0100,
364 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
365 "fcpyd", " $dst, $true",
366 [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
367 RegConstraint<"$false = $dst">;
369 def FCPYScc : ASuI<0b11101011, 0b0000, 0b0100,
370 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
371 "fcpys", " $dst, $true",
372 [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
373 RegConstraint<"$false = $dst">;
375 def FNEGDcc : ADuI<0b11101011, 0b0001, 0b0100,
376 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
377 "fnegd", " $dst, $true",
378 [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
379 RegConstraint<"$false = $dst">;
381 def FNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
382 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
383 "fnegs", " $dst, $true",
384 [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
385 RegConstraint<"$false = $dst">;
388 //===----------------------------------------------------------------------===//
393 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, "fmstat", "", [(arm_fmstat)]> {
394 let Inst{27-20} = 0b11101111;
395 let Inst{19-16} = 0b0001;
396 let Inst{15-12} = 0b1111;
397 let Inst{11-8} = 0b1010;