1 //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 def vfp_f32imm : Operand<f32>,
35 PatLeaf<(f32 fpimm), [{
36 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
38 let PrintMethod = "printVFPf32ImmOperand";
41 def vfp_f64imm : Operand<f64>,
42 PatLeaf<(f64 fpimm), [{
43 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
45 let PrintMethod = "printVFPf64ImmOperand";
49 //===----------------------------------------------------------------------===//
50 // Load / store Instructions.
53 let canFoldAsLoad = 1, isReMaterializable = 1 in {
55 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
56 IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
57 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
59 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
60 IIC_fpLoad32, "vldr", ".32\t$Sd, $addr",
61 [(set SPR:$Sd, (load addrmode5:$addr))]> {
62 // Some single precision VFP instructions may be executed on both NEON and VFP
64 let D = VFPNeonDomain;
67 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
69 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
70 IIC_fpStore64, "vstr", ".64\t$Dd, $addr",
71 [(store (f64 DPR:$Dd), addrmode5:$addr)]>;
73 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
74 IIC_fpStore32, "vstr", ".32\t$Sd, $addr",
75 [(store SPR:$Sd, addrmode5:$addr)]> {
76 // Some single precision VFP instructions may be executed on both NEON and VFP
78 let D = VFPNeonDomain;
81 //===----------------------------------------------------------------------===//
82 // Load / store multiple Instructions.
85 multiclass vfp_ldst_mult<string asm, bit L_bit,
86 InstrItinClass itin, InstrItinClass itin_upd> {
89 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
91 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
92 let Inst{24-23} = 0b01; // Increment After
93 let Inst{21} = 0; // No writeback
97 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
98 IndexModeUpd, itin_upd,
99 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
100 let Inst{24-23} = 0b01; // Increment After
101 let Inst{21} = 1; // Writeback
102 let Inst{20} = L_bit;
105 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
106 IndexModeUpd, itin_upd,
107 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
108 let Inst{24-23} = 0b10; // Decrement Before
109 let Inst{21} = 1; // Writeback
110 let Inst{20} = L_bit;
115 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
117 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
118 let Inst{24-23} = 0b01; // Increment After
119 let Inst{21} = 0; // No writeback
120 let Inst{20} = L_bit;
122 // Some single precision VFP instructions may be executed on both NEON and
124 let D = VFPNeonDomain;
127 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
128 IndexModeUpd, itin_upd,
129 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
130 let Inst{24-23} = 0b01; // Increment After
131 let Inst{21} = 1; // Writeback
132 let Inst{20} = L_bit;
134 // Some single precision VFP instructions may be executed on both NEON and
136 let D = VFPNeonDomain;
139 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
140 IndexModeUpd, itin_upd,
141 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
142 let Inst{24-23} = 0b10; // Decrement Before
143 let Inst{21} = 1; // Writeback
144 let Inst{20} = L_bit;
146 // Some single precision VFP instructions may be executed on both NEON and
148 let D = VFPNeonDomain;
152 let neverHasSideEffects = 1 in {
154 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
155 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
157 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
158 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
160 } // neverHasSideEffects
162 def : MnemonicAlias<"vldm", "vldmia">;
163 def : MnemonicAlias<"vstm", "vstmia">;
165 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
167 //===----------------------------------------------------------------------===//
168 // FP Binary Operations.
171 def VADDD : ADbI<0b11100, 0b11, 0, 0,
172 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
173 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
174 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
176 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
177 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
178 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
179 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
180 // Some single precision VFP instructions may be executed on both NEON and
181 // VFP pipelines on A8.
182 let D = VFPNeonA8Domain;
185 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
186 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
187 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
188 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
190 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
191 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
192 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
193 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
194 // Some single precision VFP instructions may be executed on both NEON and
195 // VFP pipelines on A8.
196 let D = VFPNeonA8Domain;
199 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
200 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
201 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
202 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
204 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
205 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
206 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
207 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
209 def VMULD : ADbI<0b11100, 0b10, 0, 0,
210 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
211 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
212 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
214 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
215 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
216 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
217 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
218 // Some single precision VFP instructions may be executed on both NEON and
219 // VFP pipelines on A8.
220 let D = VFPNeonA8Domain;
223 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
224 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
225 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
226 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
228 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
229 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
230 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
231 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
232 // Some single precision VFP instructions may be executed on both NEON and
233 // VFP pipelines on A8.
234 let D = VFPNeonA8Domain;
237 // Match reassociated forms only if not sign dependent rounding.
238 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
239 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
240 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
241 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
243 // These are encoded as unary instructions.
244 let Defs = [FPSCR] in {
245 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
246 (outs), (ins DPR:$Dd, DPR:$Dm),
247 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
248 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
250 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
251 (outs), (ins SPR:$Sd, SPR:$Sm),
252 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
253 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
254 // Some single precision VFP instructions may be executed on both NEON and
255 // VFP pipelines on A8.
256 let D = VFPNeonA8Domain;
259 // FIXME: Verify encoding after integrated assembler is working.
260 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
261 (outs), (ins DPR:$Dd, DPR:$Dm),
262 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
263 [/* For disassembly only; pattern left blank */]>;
265 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
266 (outs), (ins SPR:$Sd, SPR:$Sm),
267 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
268 [/* For disassembly only; pattern left blank */]> {
269 // Some single precision VFP instructions may be executed on both NEON and
270 // VFP pipelines on A8.
271 let D = VFPNeonA8Domain;
275 //===----------------------------------------------------------------------===//
276 // FP Unary Operations.
279 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
280 (outs DPR:$Dd), (ins DPR:$Dm),
281 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
282 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
284 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
285 (outs SPR:$Sd), (ins SPR:$Sm),
286 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
287 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
288 // Some single precision VFP instructions may be executed on both NEON and
289 // VFP pipelines on A8.
290 let D = VFPNeonA8Domain;
293 let Defs = [FPSCR] in {
294 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
295 (outs), (ins DPR:$Dd),
296 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
297 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
298 let Inst{3-0} = 0b0000;
302 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
303 (outs), (ins SPR:$Sd),
304 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
305 [(arm_cmpfp0 SPR:$Sd)]> {
306 let Inst{3-0} = 0b0000;
309 // Some single precision VFP instructions may be executed on both NEON and
310 // VFP pipelines on A8.
311 let D = VFPNeonA8Domain;
314 // FIXME: Verify encoding after integrated assembler is working.
315 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
316 (outs), (ins DPR:$Dd),
317 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
318 [/* For disassembly only; pattern left blank */]> {
319 let Inst{3-0} = 0b0000;
323 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
324 (outs), (ins SPR:$Sd),
325 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
326 [/* For disassembly only; pattern left blank */]> {
327 let Inst{3-0} = 0b0000;
330 // Some single precision VFP instructions may be executed on both NEON and
331 // VFP pipelines on A8.
332 let D = VFPNeonA8Domain;
336 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
337 (outs DPR:$Dd), (ins SPR:$Sm),
338 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
339 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
340 // Instruction operands.
344 // Encode instruction operands.
345 let Inst{3-0} = Sm{4-1};
347 let Inst{15-12} = Dd{3-0};
348 let Inst{22} = Dd{4};
351 // Special case encoding: bits 11-8 is 0b1011.
352 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
353 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
354 [(set SPR:$Sd, (fround DPR:$Dm))]> {
355 // Instruction operands.
359 // Encode instruction operands.
360 let Inst{3-0} = Dm{3-0};
362 let Inst{15-12} = Sd{4-1};
363 let Inst{22} = Sd{0};
365 let Inst{27-23} = 0b11101;
366 let Inst{21-16} = 0b110111;
367 let Inst{11-8} = 0b1011;
368 let Inst{7-6} = 0b11;
372 // Between half-precision and single-precision. For disassembly only.
374 // FIXME: Verify encoding after integrated assembler is working.
375 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
376 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
377 [/* For disassembly only; pattern left blank */]>;
379 def : ARMPat<(f32_to_f16 SPR:$a),
380 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
382 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
383 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a",
384 [/* For disassembly only; pattern left blank */]>;
386 def : ARMPat<(f16_to_f32 GPR:$a),
387 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
389 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
390 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a",
391 [/* For disassembly only; pattern left blank */]>;
393 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
394 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
395 [/* For disassembly only; pattern left blank */]>;
397 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
398 (outs DPR:$Dd), (ins DPR:$Dm),
399 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
400 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
402 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
403 (outs SPR:$Sd), (ins SPR:$Sm),
404 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
405 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
406 // Some single precision VFP instructions may be executed on both NEON and
407 // VFP pipelines on A8.
408 let D = VFPNeonA8Domain;
411 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
412 (outs DPR:$Dd), (ins DPR:$Dm),
413 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
414 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
416 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
417 (outs SPR:$Sd), (ins SPR:$Sm),
418 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
419 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
421 let neverHasSideEffects = 1 in {
422 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
423 (outs DPR:$Dd), (ins DPR:$Dm),
424 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
426 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
427 (outs SPR:$Sd), (ins SPR:$Sm),
428 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
429 } // neverHasSideEffects
431 //===----------------------------------------------------------------------===//
432 // FP <-> GPR Copies. Int <-> FP Conversions.
435 def VMOVRS : AVConv2I<0b11100001, 0b1010,
436 (outs GPR:$Rt), (ins SPR:$Sn),
437 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
438 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
439 // Instruction operands.
443 // Encode instruction operands.
444 let Inst{19-16} = Sn{4-1};
446 let Inst{15-12} = Rt;
448 let Inst{6-5} = 0b00;
449 let Inst{3-0} = 0b0000;
452 def VMOVSR : AVConv4I<0b11100000, 0b1010,
453 (outs SPR:$Sn), (ins GPR:$Rt),
454 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
455 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
456 // Instruction operands.
460 // Encode instruction operands.
461 let Inst{19-16} = Sn{4-1};
463 let Inst{15-12} = Rt;
465 let Inst{6-5} = 0b00;
466 let Inst{3-0} = 0b0000;
469 let neverHasSideEffects = 1 in {
470 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
471 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
472 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
473 [/* FIXME: Can't write pattern for multiple result instr*/]> {
474 // Instruction operands.
479 // Encode instruction operands.
480 let Inst{3-0} = Dm{3-0};
482 let Inst{15-12} = Rt;
483 let Inst{19-16} = Rt2;
485 let Inst{7-6} = 0b00;
488 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
489 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
490 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
491 [/* For disassembly only; pattern left blank */]> {
492 let Inst{7-6} = 0b00;
494 } // neverHasSideEffects
499 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
500 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
501 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
502 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
503 // Instruction operands.
508 // Encode instruction operands.
509 let Inst{3-0} = Dm{3-0};
511 let Inst{15-12} = Rt;
512 let Inst{19-16} = Rt2;
514 let Inst{7-6} = 0b00;
517 let neverHasSideEffects = 1 in
518 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
519 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
520 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
521 [/* For disassembly only; pattern left blank */]> {
522 let Inst{7-6} = 0b00;
528 // FMRX: SPR system reg -> GPR
530 // FMXR: GPR -> VFP system reg
535 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
536 bits<4> opcod4, dag oops, dag iops,
537 InstrItinClass itin, string opc, string asm,
539 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
541 // Instruction operands.
545 // Encode instruction operands.
546 let Inst{3-0} = Sm{4-1};
548 let Inst{15-12} = Dd{3-0};
549 let Inst{22} = Dd{4};
552 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
553 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
554 string opc, string asm, list<dag> pattern>
555 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
557 // Instruction operands.
561 // Encode instruction operands.
562 let Inst{3-0} = Sm{4-1};
564 let Inst{15-12} = Sd{4-1};
565 let Inst{22} = Sd{0};
568 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
569 (outs DPR:$Dd), (ins SPR:$Sm),
570 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
571 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
572 let Inst{7} = 1; // s32
575 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
576 (outs SPR:$Sd),(ins SPR:$Sm),
577 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
578 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
579 let Inst{7} = 1; // s32
581 // Some single precision VFP instructions may be executed on both NEON and
582 // VFP pipelines on A8.
583 let D = VFPNeonA8Domain;
586 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
587 (outs DPR:$Dd), (ins SPR:$Sm),
588 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
589 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
590 let Inst{7} = 0; // u32
593 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
594 (outs SPR:$Sd), (ins SPR:$Sm),
595 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
596 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
597 let Inst{7} = 0; // u32
599 // Some single precision VFP instructions may be executed on both NEON and
600 // VFP pipelines on A8.
601 let D = VFPNeonA8Domain;
606 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
607 bits<4> opcod4, dag oops, dag iops,
608 InstrItinClass itin, string opc, string asm,
610 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
612 // Instruction operands.
616 // Encode instruction operands.
617 let Inst{3-0} = Dm{3-0};
619 let Inst{15-12} = Sd{4-1};
620 let Inst{22} = Sd{0};
623 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
624 bits<4> opcod4, dag oops, dag iops,
625 InstrItinClass itin, string opc, string asm,
627 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
629 // Instruction operands.
633 // Encode instruction operands.
634 let Inst{3-0} = Sm{4-1};
636 let Inst{15-12} = Sd{4-1};
637 let Inst{22} = Sd{0};
640 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
641 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
642 (outs SPR:$Sd), (ins DPR:$Dm),
643 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
644 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
645 let Inst{7} = 1; // Z bit
648 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
649 (outs SPR:$Sd), (ins SPR:$Sm),
650 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
651 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
652 let Inst{7} = 1; // Z bit
654 // Some single precision VFP instructions may be executed on both NEON and
655 // VFP pipelines on A8.
656 let D = VFPNeonA8Domain;
659 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
660 (outs SPR:$Sd), (ins DPR:$Dm),
661 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
662 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
663 let Inst{7} = 1; // Z bit
666 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
667 (outs SPR:$Sd), (ins SPR:$Sm),
668 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
669 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
670 let Inst{7} = 1; // Z bit
672 // Some single precision VFP instructions may be executed on both NEON and
673 // VFP pipelines on A8.
674 let D = VFPNeonA8Domain;
677 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
678 let Uses = [FPSCR] in {
679 // FIXME: Verify encoding after integrated assembler is working.
680 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
681 (outs SPR:$Sd), (ins DPR:$Dm),
682 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
683 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
684 let Inst{7} = 0; // Z bit
687 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
688 (outs SPR:$Sd), (ins SPR:$Sm),
689 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
690 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
691 let Inst{7} = 0; // Z bit
694 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
695 (outs SPR:$Sd), (ins DPR:$Dm),
696 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
697 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
698 let Inst{7} = 0; // Z bit
701 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
702 (outs SPR:$Sd), (ins SPR:$Sm),
703 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
704 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
705 let Inst{7} = 0; // Z bit
709 // Convert between floating-point and fixed-point
710 // Data type for fixed-point naming convention:
711 // S16 (U=0, sx=0) -> SH
712 // U16 (U=1, sx=0) -> UH
713 // S32 (U=0, sx=1) -> SL
714 // U32 (U=1, sx=1) -> UL
716 // FIXME: Marking these as codegen only seems wrong. They are real
718 let Constraints = "$a = $dst", isCodeGenOnly = 1 in {
720 // FP to Fixed-Point:
722 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
723 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
724 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
725 [/* For disassembly only; pattern left blank */]> {
726 // Some single precision VFP instructions may be executed on both NEON and
727 // VFP pipelines on A8.
728 let D = VFPNeonA8Domain;
731 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
732 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
733 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
734 [/* For disassembly only; pattern left blank */]> {
735 // Some single precision VFP instructions may be executed on both NEON and
736 // VFP pipelines on A8.
737 let D = VFPNeonA8Domain;
740 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
741 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
742 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
743 [/* For disassembly only; pattern left blank */]> {
744 // Some single precision VFP instructions may be executed on both NEON and
745 // VFP pipelines on A8.
746 let D = VFPNeonA8Domain;
749 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
750 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
751 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
752 [/* For disassembly only; pattern left blank */]> {
753 // Some single precision VFP instructions may be executed on both NEON and
754 // VFP pipelines on A8.
755 let D = VFPNeonA8Domain;
758 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
759 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
760 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
761 [/* For disassembly only; pattern left blank */]>;
763 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
764 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
765 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
766 [/* For disassembly only; pattern left blank */]>;
768 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
769 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
770 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
771 [/* For disassembly only; pattern left blank */]>;
773 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
774 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
775 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
776 [/* For disassembly only; pattern left blank */]>;
778 // Fixed-Point to FP:
780 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
781 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
782 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
783 [/* For disassembly only; pattern left blank */]> {
784 // Some single precision VFP instructions may be executed on both NEON and
785 // VFP pipelines on A8.
786 let D = VFPNeonA8Domain;
789 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
790 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
791 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
792 [/* For disassembly only; pattern left blank */]> {
793 // Some single precision VFP instructions may be executed on both NEON and
794 // VFP pipelines on A8.
795 let D = VFPNeonA8Domain;
798 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
799 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
800 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
801 [/* For disassembly only; pattern left blank */]> {
802 // Some single precision VFP instructions may be executed on both NEON and
803 // VFP pipelines on A8.
804 let D = VFPNeonA8Domain;
807 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
808 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
809 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
810 [/* For disassembly only; pattern left blank */]> {
811 // Some single precision VFP instructions may be executed on both NEON and
812 // VFP pipelines on A8.
813 let D = VFPNeonA8Domain;
816 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
817 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
818 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
819 [/* For disassembly only; pattern left blank */]>;
821 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
822 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
823 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
824 [/* For disassembly only; pattern left blank */]>;
826 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
827 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
828 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
829 [/* For disassembly only; pattern left blank */]>;
831 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
832 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
833 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
834 [/* For disassembly only; pattern left blank */]>;
836 } // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in'
838 //===----------------------------------------------------------------------===//
839 // FP FMA Operations.
842 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
843 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
844 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
845 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
847 RegConstraint<"$Ddin = $Dd">,
848 Requires<[HasVFP2,UseFPVMLx]>;
850 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
851 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
852 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
853 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
855 RegConstraint<"$Sdin = $Sd">,
856 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
857 // Some single precision VFP instructions may be executed on both NEON and
858 // VFP pipelines on A8.
859 let D = VFPNeonA8Domain;
862 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
863 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
864 Requires<[HasVFP2,UseFPVMLx]>;
865 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
866 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
867 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>;
869 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
870 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
871 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
872 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
874 RegConstraint<"$Ddin = $Dd">,
875 Requires<[HasVFP2,UseFPVMLx]>;
877 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
878 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
879 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
880 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
882 RegConstraint<"$Sdin = $Sd">,
883 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
884 // Some single precision VFP instructions may be executed on both NEON and
885 // VFP pipelines on A8.
886 let D = VFPNeonA8Domain;
889 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
890 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
891 Requires<[HasVFP2,UseFPVMLx]>;
892 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
893 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
894 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
896 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
897 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
898 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
899 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
901 RegConstraint<"$Ddin = $Dd">,
902 Requires<[HasVFP2,UseFPVMLx]>;
904 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
905 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
906 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
907 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
909 RegConstraint<"$Sdin = $Sd">,
910 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
911 // Some single precision VFP instructions may be executed on both NEON and
912 // VFP pipelines on A8.
913 let D = VFPNeonA8Domain;
916 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
917 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
918 Requires<[HasVFP2,UseFPVMLx]>;
919 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
920 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
921 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
923 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
924 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
925 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
926 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
928 RegConstraint<"$Ddin = $Dd">,
929 Requires<[HasVFP2,UseFPVMLx]>;
931 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
932 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
933 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
934 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
935 RegConstraint<"$Sdin = $Sd">,
936 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
937 // Some single precision VFP instructions may be executed on both NEON and
938 // VFP pipelines on A8.
939 let D = VFPNeonA8Domain;
942 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
943 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
944 Requires<[HasVFP2,UseFPVMLx]>;
945 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
946 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
947 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
950 //===----------------------------------------------------------------------===//
951 // FP Conditional moves.
954 let neverHasSideEffects = 1 in {
955 def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
956 Size4Bytes, IIC_fpUNA64,
957 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
958 RegConstraint<"$Dn = $Dd">;
960 def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
961 Size4Bytes, IIC_fpUNA32,
962 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
963 RegConstraint<"$Sn = $Sd">;
964 } // neverHasSideEffects
966 //===----------------------------------------------------------------------===//
967 // Move from VFP System Register to ARM core register.
970 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
972 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
974 // Instruction operand.
977 let Inst{27-20} = 0b11101111;
978 let Inst{19-16} = opc19_16;
979 let Inst{15-12} = Rt;
980 let Inst{11-8} = 0b1010;
982 let Inst{6-5} = 0b00;
984 let Inst{3-0} = 0b0000;
987 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
989 let Defs = [CPSR], Uses = [FPSCR], Rt = 0b1111 /* apsr_nzcv */ in
990 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
991 "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>;
993 // Application level FPSCR -> GPR
994 let hasSideEffects = 1, Uses = [FPSCR] in
995 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
996 "vmrs", "\t$Rt, fpscr",
997 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
999 // System level FPEXC, FPSID -> GPR
1000 let Uses = [FPSCR] in {
1001 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1002 "vmrs", "\t$Rt, fpexc", []>;
1003 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1004 "vmrs", "\t$Rt, fpsid", []>;
1007 //===----------------------------------------------------------------------===//
1008 // Move from ARM core register to VFP System Register.
1011 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1013 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1015 // Instruction operand.
1018 // Encode instruction operand.
1019 let Inst{15-12} = src;
1021 let Inst{27-20} = 0b11101110;
1022 let Inst{19-16} = opc19_16;
1023 let Inst{11-8} = 0b1010;
1028 let Defs = [FPSCR] in {
1029 // Application level GPR -> FPSCR
1030 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1031 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1032 // System level GPR -> FPEXC
1033 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1034 "vmsr", "\tfpexc, $src", []>;
1035 // System level GPR -> FPSID
1036 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1037 "vmsr", "\tfpsid, $src", []>;
1040 //===----------------------------------------------------------------------===//
1044 // Materialize FP immediates. VFP3 only.
1045 let isReMaterializable = 1 in {
1046 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1047 VFPMiscFrm, IIC_fpUNA64,
1048 "vmov", ".f64\t$Dd, $imm",
1049 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1050 // Instruction operands.
1054 // Encode instruction operands.
1055 let Inst{15-12} = Dd{3-0};
1056 let Inst{22} = Dd{4};
1057 let Inst{19} = imm{31};
1058 let Inst{18-16} = imm{22-20};
1059 let Inst{3-0} = imm{19-16};
1061 // Encode remaining instruction bits.
1062 let Inst{27-23} = 0b11101;
1063 let Inst{21-20} = 0b11;
1064 let Inst{11-9} = 0b101;
1065 let Inst{8} = 1; // Double precision.
1066 let Inst{7-4} = 0b0000;
1069 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1070 VFPMiscFrm, IIC_fpUNA32,
1071 "vmov", ".f32\t$Sd, $imm",
1072 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1073 // Instruction operands.
1077 // Encode instruction operands.
1078 let Inst{15-12} = Sd{4-1};
1079 let Inst{22} = Sd{0};
1080 let Inst{19} = imm{31}; // The immediate is handled as a double.
1081 let Inst{18-16} = imm{22-20};
1082 let Inst{3-0} = imm{19-16};
1084 // Encode remaining instruction bits.
1085 let Inst{27-23} = 0b11101;
1086 let Inst{21-20} = 0b11;
1087 let Inst{11-9} = 0b101;
1088 let Inst{8} = 0; // Single precision.
1089 let Inst{7-4} = 0b0000;