1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
15 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
18 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
19 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
20 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
21 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
24 //===----------------------------------------------------------------------===//
25 // Operand Definitions.
28 // 8-bit floating-point immediate encodings.
29 def FPImmOperand : AsmOperandClass {
31 let ParserMethod = "parseFPImm";
34 def vfp_f32imm : Operand<f32>,
35 PatLeaf<(f32 fpimm), [{
36 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
37 }], SDNodeXForm<fpimm, [{
38 APFloat InVal = N->getValueAPF();
39 uint32_t enc = ARM_AM::getFP32Imm(InVal);
40 return CurDAG->getTargetConstant(enc, MVT::i32);
42 let PrintMethod = "printFPImmOperand";
43 let ParserMatchClass = FPImmOperand;
46 def vfp_f64imm : Operand<f64>,
47 PatLeaf<(f64 fpimm), [{
48 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
49 }], SDNodeXForm<fpimm, [{
50 APFloat InVal = N->getValueAPF();
51 uint32_t enc = ARM_AM::getFP64Imm(InVal);
52 return CurDAG->getTargetConstant(enc, MVT::i32);
54 let PrintMethod = "printFPImmOperand";
55 let ParserMatchClass = FPImmOperand;
58 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
59 return cast<LoadSDNode>(N)->getAlignment() >= 4;
62 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
63 (store node:$val, node:$ptr), [{
64 return cast<StoreSDNode>(N)->getAlignment() >= 4;
67 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
68 // (the number of fixed bits) differently than it appears in the assembly
69 // source. It's encoded as "Size - fbits" where Size is the size of the
70 // fixed-point representation (32 or 16) and fbits is the value appearing
71 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
72 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
73 def fbits32 : Operand<i32> {
74 let PrintMethod = "printFBits32";
75 let ParserMatchClass = fbits32_asm_operand;
78 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
79 def fbits16 : Operand<i32> {
80 let PrintMethod = "printFBits16";
81 let ParserMatchClass = fbits16_asm_operand;
84 //===----------------------------------------------------------------------===//
85 // Load / store Instructions.
88 let canFoldAsLoad = 1, isReMaterializable = 1 in {
90 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
91 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
92 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
94 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
95 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
96 [(set SPR:$Sd, (load addrmode5:$addr))]> {
97 // Some single precision VFP instructions may be executed on both NEON and VFP
99 let D = VFPNeonDomain;
102 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
104 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
105 IIC_fpStore64, "vstr", "\t$Dd, $addr",
106 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
108 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
109 IIC_fpStore32, "vstr", "\t$Sd, $addr",
110 [(store SPR:$Sd, addrmode5:$addr)]> {
111 // Some single precision VFP instructions may be executed on both NEON and VFP
113 let D = VFPNeonDomain;
116 //===----------------------------------------------------------------------===//
117 // Load / store multiple Instructions.
120 multiclass vfp_ldst_mult<string asm, bit L_bit,
121 InstrItinClass itin, InstrItinClass itin_upd> {
124 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
126 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
127 let Inst{24-23} = 0b01; // Increment After
128 let Inst{21} = 0; // No writeback
129 let Inst{20} = L_bit;
132 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
134 IndexModeUpd, itin_upd,
135 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
136 let Inst{24-23} = 0b01; // Increment After
137 let Inst{21} = 1; // Writeback
138 let Inst{20} = L_bit;
141 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
143 IndexModeUpd, itin_upd,
144 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
145 let Inst{24-23} = 0b10; // Decrement Before
146 let Inst{21} = 1; // Writeback
147 let Inst{20} = L_bit;
152 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
154 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
155 let Inst{24-23} = 0b01; // Increment After
156 let Inst{21} = 0; // No writeback
157 let Inst{20} = L_bit;
159 // Some single precision VFP instructions may be executed on both NEON and
161 let D = VFPNeonDomain;
164 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
166 IndexModeUpd, itin_upd,
167 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
168 let Inst{24-23} = 0b01; // Increment After
169 let Inst{21} = 1; // Writeback
170 let Inst{20} = L_bit;
172 // Some single precision VFP instructions may be executed on both NEON and
174 let D = VFPNeonDomain;
177 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
179 IndexModeUpd, itin_upd,
180 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
181 let Inst{24-23} = 0b10; // Decrement Before
182 let Inst{21} = 1; // Writeback
183 let Inst{20} = L_bit;
185 // Some single precision VFP instructions may be executed on both NEON and
187 let D = VFPNeonDomain;
191 let hasSideEffects = 0 in {
193 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
194 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
196 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
197 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
201 def : MnemonicAlias<"vldm", "vldmia">;
202 def : MnemonicAlias<"vstm", "vstmia">;
204 // FLDM/FSTM - Load / Store multiple single / double precision registers for
206 // These instructions are deprecated!
207 def : VFP2MnemonicAlias<"fldmias", "vldmia">;
208 def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;
209 def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;
210 def : VFP2MnemonicAlias<"fldmfds", "vldmia">;
211 def : VFP2MnemonicAlias<"fldmiad", "vldmia">;
212 def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">;
213 def : VFP2MnemonicAlias<"fldmead", "vldmdb">;
214 def : VFP2MnemonicAlias<"fldmfdd", "vldmia">;
216 def : VFP2MnemonicAlias<"fstmias", "vstmia">;
217 def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">;
218 def : VFP2MnemonicAlias<"fstmeas", "vstmia">;
219 def : VFP2MnemonicAlias<"fstmfds", "vstmdb">;
220 def : VFP2MnemonicAlias<"fstmiad", "vstmia">;
221 def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;
222 def : VFP2MnemonicAlias<"fstmead", "vstmia">;
223 def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
225 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
227 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
229 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
231 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
233 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
234 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
235 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
236 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
237 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
238 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
239 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
240 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
242 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
244 // These instruction are deprecated so we don't want them to get selected.
245 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
248 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
249 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
250 let Inst{24-23} = 0b01; // Increment After
251 let Inst{21} = 0; // No writeback
252 let Inst{20} = L_bit;
255 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
256 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
257 let Inst{24-23} = 0b01; // Increment After
258 let Inst{21} = 1; // Writeback
259 let Inst{20} = L_bit;
262 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
263 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
264 let Inst{24-23} = 0b10; // Decrement Before
265 let Inst{21} = 1; // Writeback
266 let Inst{20} = L_bit;
270 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
271 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
273 def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;
274 def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;
276 def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;
277 def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;
279 //===----------------------------------------------------------------------===//
280 // FP Binary Operations.
283 let TwoOperandAliasConstraint = "$Dn = $Dd" in
284 def VADDD : ADbI<0b11100, 0b11, 0, 0,
285 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
286 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
287 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
289 let TwoOperandAliasConstraint = "$Sn = $Sd" in
290 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
291 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
292 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
293 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
294 // Some single precision VFP instructions may be executed on both NEON and
295 // VFP pipelines on A8.
296 let D = VFPNeonA8Domain;
299 let TwoOperandAliasConstraint = "$Dn = $Dd" in
300 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
301 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
302 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
303 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
305 let TwoOperandAliasConstraint = "$Sn = $Sd" in
306 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
307 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
308 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
309 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
310 // Some single precision VFP instructions may be executed on both NEON and
311 // VFP pipelines on A8.
312 let D = VFPNeonA8Domain;
315 let TwoOperandAliasConstraint = "$Dn = $Dd" in
316 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
317 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
318 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
319 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
321 let TwoOperandAliasConstraint = "$Sn = $Sd" in
322 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
323 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
324 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
325 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
327 let TwoOperandAliasConstraint = "$Dn = $Dd" in
328 def VMULD : ADbI<0b11100, 0b10, 0, 0,
329 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
330 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
331 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
333 let TwoOperandAliasConstraint = "$Sn = $Sd" in
334 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
335 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
336 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
337 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
338 // Some single precision VFP instructions may be executed on both NEON and
339 // VFP pipelines on A8.
340 let D = VFPNeonA8Domain;
343 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
344 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
345 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
346 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
348 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
349 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
350 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
351 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
352 // Some single precision VFP instructions may be executed on both NEON and
353 // VFP pipelines on A8.
354 let D = VFPNeonA8Domain;
357 multiclass vsel_inst<string op, bits<2> opc, int CC> {
358 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
359 Uses = [CPSR], AddedComplexity = 4 in {
360 def S : ASbInp<0b11100, opc, 0,
361 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
362 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
363 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
364 Requires<[HasFPARMv8]>;
366 def D : ADbInp<0b11100, opc, 0,
367 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
368 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
369 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
370 Requires<[HasFPARMv8, HasDPVFP]>;
374 // The CC constants here match ARMCC::CondCodes.
375 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
376 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
377 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
378 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
380 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
381 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
382 def S : ASbInp<0b11101, 0b00, opc,
383 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
384 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
385 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
386 Requires<[HasFPARMv8]>;
388 def D : ADbInp<0b11101, 0b00, opc,
389 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
390 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
391 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
392 Requires<[HasFPARMv8, HasDPVFP]>;
396 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>;
397 defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>;
399 // Match reassociated forms only if not sign dependent rounding.
400 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
401 (VNMULD DPR:$a, DPR:$b)>,
402 Requires<[NoHonorSignDependentRounding,HasDPVFP]>;
403 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
404 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
406 // These are encoded as unary instructions.
407 let Defs = [FPSCR_NZCV] in {
408 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
409 (outs), (ins DPR:$Dd, DPR:$Dm),
410 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
411 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
413 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
414 (outs), (ins SPR:$Sd, SPR:$Sm),
415 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
416 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
417 // Some single precision VFP instructions may be executed on both NEON and
418 // VFP pipelines on A8.
419 let D = VFPNeonA8Domain;
422 // FIXME: Verify encoding after integrated assembler is working.
423 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
424 (outs), (ins DPR:$Dd, DPR:$Dm),
425 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
426 [/* For disassembly only; pattern left blank */]>;
428 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
429 (outs), (ins SPR:$Sd, SPR:$Sm),
430 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
431 [/* For disassembly only; pattern left blank */]> {
432 // Some single precision VFP instructions may be executed on both NEON and
433 // VFP pipelines on A8.
434 let D = VFPNeonA8Domain;
436 } // Defs = [FPSCR_NZCV]
438 //===----------------------------------------------------------------------===//
439 // FP Unary Operations.
442 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
443 (outs DPR:$Dd), (ins DPR:$Dm),
444 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
445 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
447 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
448 (outs SPR:$Sd), (ins SPR:$Sm),
449 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
450 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
451 // Some single precision VFP instructions may be executed on both NEON and
452 // VFP pipelines on A8.
453 let D = VFPNeonA8Domain;
456 let Defs = [FPSCR_NZCV] in {
457 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
458 (outs), (ins DPR:$Dd),
459 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
460 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
461 let Inst{3-0} = 0b0000;
465 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
466 (outs), (ins SPR:$Sd),
467 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
468 [(arm_cmpfp0 SPR:$Sd)]> {
469 let Inst{3-0} = 0b0000;
472 // Some single precision VFP instructions may be executed on both NEON and
473 // VFP pipelines on A8.
474 let D = VFPNeonA8Domain;
477 // FIXME: Verify encoding after integrated assembler is working.
478 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
479 (outs), (ins DPR:$Dd),
480 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
481 [/* For disassembly only; pattern left blank */]> {
482 let Inst{3-0} = 0b0000;
486 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
487 (outs), (ins SPR:$Sd),
488 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
489 [/* For disassembly only; pattern left blank */]> {
490 let Inst{3-0} = 0b0000;
493 // Some single precision VFP instructions may be executed on both NEON and
494 // VFP pipelines on A8.
495 let D = VFPNeonA8Domain;
497 } // Defs = [FPSCR_NZCV]
499 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
500 (outs DPR:$Dd), (ins SPR:$Sm),
501 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
502 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
503 // Instruction operands.
507 // Encode instruction operands.
508 let Inst{3-0} = Sm{4-1};
510 let Inst{15-12} = Dd{3-0};
511 let Inst{22} = Dd{4};
513 let Predicates = [HasVFP2, HasDPVFP];
516 // Special case encoding: bits 11-8 is 0b1011.
517 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
518 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
519 [(set SPR:$Sd, (fround DPR:$Dm))]> {
520 // Instruction operands.
524 // Encode instruction operands.
525 let Inst{3-0} = Dm{3-0};
527 let Inst{15-12} = Sd{4-1};
528 let Inst{22} = Sd{0};
530 let Inst{27-23} = 0b11101;
531 let Inst{21-16} = 0b110111;
532 let Inst{11-8} = 0b1011;
533 let Inst{7-6} = 0b11;
536 let Predicates = [HasVFP2, HasDPVFP];
539 // Between half, single and double-precision. For disassembly only.
541 // FIXME: Verify encoding after integrated assembler is working.
542 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
543 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
544 [/* For disassembly only; pattern left blank */]>;
546 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
547 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
548 [/* For disassembly only; pattern left blank */]>;
550 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
551 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
552 [/* For disassembly only; pattern left blank */]>;
554 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
555 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
556 [/* For disassembly only; pattern left blank */]>;
558 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
559 (outs DPR:$Dd), (ins SPR:$Sm),
560 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
561 []>, Requires<[HasFPARMv8, HasDPVFP]> {
562 // Instruction operands.
565 // Encode instruction operands.
566 let Inst{3-0} = Sm{4-1};
570 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
571 (outs SPR:$Sd), (ins DPR:$Dm),
572 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
573 []>, Requires<[HasFPARMv8, HasDPVFP]> {
574 // Instruction operands.
578 // Encode instruction operands.
579 let Inst{3-0} = Dm{3-0};
581 let Inst{15-12} = Sd{4-1};
582 let Inst{22} = Sd{0};
585 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
586 (outs DPR:$Dd), (ins SPR:$Sm),
587 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
588 []>, Requires<[HasFPARMv8, HasDPVFP]> {
589 // Instruction operands.
592 // Encode instruction operands.
593 let Inst{3-0} = Sm{4-1};
597 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
598 (outs SPR:$Sd), (ins DPR:$Dm),
599 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
600 []>, Requires<[HasFPARMv8, HasDPVFP]> {
601 // Instruction operands.
605 // Encode instruction operands.
606 let Inst{15-12} = Sd{4-1};
607 let Inst{22} = Sd{0};
608 let Inst{3-0} = Dm{3-0};
612 def : Pat<(fp_to_f16 SPR:$a),
613 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
615 def : Pat<(fp_to_f16 (f64 DPR:$a)),
616 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
618 def : Pat<(f16_to_fp GPR:$a),
619 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
621 def : Pat<(f64 (f16_to_fp GPR:$a)),
622 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
624 multiclass vcvt_inst<string opc, bits<2> rm,
625 SDPatternOperator node = null_frag> {
626 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
627 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
628 (outs SPR:$Sd), (ins SPR:$Sm),
629 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
631 Requires<[HasFPARMv8]> {
632 let Inst{17-16} = rm;
635 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
636 (outs SPR:$Sd), (ins SPR:$Sm),
637 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
639 Requires<[HasFPARMv8]> {
640 let Inst{17-16} = rm;
643 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
644 (outs SPR:$Sd), (ins DPR:$Dm),
645 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
647 Requires<[HasFPARMv8, HasDPVFP]> {
650 let Inst{17-16} = rm;
652 // Encode instruction operands
653 let Inst{3-0} = Dm{3-0};
658 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
659 (outs SPR:$Sd), (ins DPR:$Dm),
660 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
662 Requires<[HasFPARMv8, HasDPVFP]> {
665 let Inst{17-16} = rm;
667 // Encode instruction operands
668 let Inst{3-0} = Dm{3-0};
674 let Predicates = [HasFPARMv8] in {
675 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
677 (!cast<Instruction>(NAME#"SS") SPR:$a),
679 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
681 (!cast<Instruction>(NAME#"US") SPR:$a),
684 let Predicates = [HasFPARMv8, HasDPVFP] in {
685 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))),
687 (!cast<Instruction>(NAME#"SD") DPR:$a),
689 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))),
691 (!cast<Instruction>(NAME#"UD") DPR:$a),
696 defm VCVTA : vcvt_inst<"a", 0b00, frnd>;
697 defm VCVTN : vcvt_inst<"n", 0b01>;
698 defm VCVTP : vcvt_inst<"p", 0b10, fceil>;
699 defm VCVTM : vcvt_inst<"m", 0b11, ffloor>;
701 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
702 (outs DPR:$Dd), (ins DPR:$Dm),
703 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
704 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
706 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
707 (outs SPR:$Sd), (ins SPR:$Sm),
708 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
709 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
710 // Some single precision VFP instructions may be executed on both NEON and
711 // VFP pipelines on A8.
712 let D = VFPNeonA8Domain;
715 multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
716 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
717 (outs SPR:$Sd), (ins SPR:$Sm),
718 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
719 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
720 Requires<[HasFPARMv8]> {
724 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
725 (outs DPR:$Dd), (ins DPR:$Dm),
726 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
727 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
728 Requires<[HasFPARMv8, HasDPVFP]> {
733 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
734 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
735 Requires<[HasFPARMv8]>;
736 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
737 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
738 Requires<[HasFPARMv8,HasDPVFP]>;
741 defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>;
742 defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>;
743 defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
745 multiclass vrint_inst_anpm<string opc, bits<2> rm,
746 SDPatternOperator node = null_frag> {
747 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
748 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
749 (outs SPR:$Sd), (ins SPR:$Sm),
750 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
751 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
752 Requires<[HasFPARMv8]> {
753 let Inst{17-16} = rm;
755 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
756 (outs DPR:$Dd), (ins DPR:$Dm),
757 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
758 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
759 Requires<[HasFPARMv8, HasDPVFP]> {
760 let Inst{17-16} = rm;
764 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
765 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
766 Requires<[HasFPARMv8]>;
767 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
768 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
769 Requires<[HasFPARMv8,HasDPVFP]>;
772 defm VRINTA : vrint_inst_anpm<"a", 0b00, frnd>;
773 defm VRINTN : vrint_inst_anpm<"n", 0b01>;
774 defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>;
775 defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>;
777 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
778 (outs DPR:$Dd), (ins DPR:$Dm),
779 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
780 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
782 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
783 (outs SPR:$Sd), (ins SPR:$Sm),
784 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
785 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
787 let hasSideEffects = 0 in {
788 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
789 (outs DPR:$Dd), (ins DPR:$Dm),
790 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
792 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
793 (outs SPR:$Sd), (ins SPR:$Sm),
794 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
797 //===----------------------------------------------------------------------===//
798 // FP <-> GPR Copies. Int <-> FP Conversions.
801 def VMOVRS : AVConv2I<0b11100001, 0b1010,
802 (outs GPR:$Rt), (ins SPR:$Sn),
803 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
804 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
805 // Instruction operands.
809 // Encode instruction operands.
810 let Inst{19-16} = Sn{4-1};
812 let Inst{15-12} = Rt;
814 let Inst{6-5} = 0b00;
815 let Inst{3-0} = 0b0000;
817 // Some single precision VFP instructions may be executed on both NEON and VFP
819 let D = VFPNeonDomain;
822 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
823 def VMOVSR : AVConv4I<0b11100000, 0b1010,
824 (outs SPR:$Sn), (ins GPR:$Rt),
825 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
826 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
827 Requires<[HasVFP2, UseVMOVSR]> {
828 // Instruction operands.
832 // Encode instruction operands.
833 let Inst{19-16} = Sn{4-1};
835 let Inst{15-12} = Rt;
837 let Inst{6-5} = 0b00;
838 let Inst{3-0} = 0b0000;
840 // Some single precision VFP instructions may be executed on both NEON and VFP
842 let D = VFPNeonDomain;
845 let hasSideEffects = 0 in {
846 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
847 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
848 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
849 [/* FIXME: Can't write pattern for multiple result instr*/]> {
850 // Instruction operands.
855 // Encode instruction operands.
856 let Inst{3-0} = Dm{3-0};
858 let Inst{15-12} = Rt;
859 let Inst{19-16} = Rt2;
861 let Inst{7-6} = 0b00;
863 // Some single precision VFP instructions may be executed on both NEON and VFP
865 let D = VFPNeonDomain;
867 // This instruction is equivalent to
868 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
869 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
870 let isExtractSubreg = 1;
873 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
874 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
875 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
876 [/* For disassembly only; pattern left blank */]> {
881 // Encode instruction operands.
882 let Inst{3-0} = src1{4-1};
883 let Inst{5} = src1{0};
884 let Inst{15-12} = Rt;
885 let Inst{19-16} = Rt2;
887 let Inst{7-6} = 0b00;
889 // Some single precision VFP instructions may be executed on both NEON and VFP
891 let D = VFPNeonDomain;
892 let DecoderMethod = "DecodeVMOVRRS";
899 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
900 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
901 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
902 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
903 // Instruction operands.
908 // Encode instruction operands.
909 let Inst{3-0} = Dm{3-0};
911 let Inst{15-12} = Rt;
912 let Inst{19-16} = Rt2;
914 let Inst{7-6} = 0b00;
916 // Some single precision VFP instructions may be executed on both NEON and VFP
918 let D = VFPNeonDomain;
920 // This instruction is equivalent to
921 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
922 let isRegSequence = 1;
925 let hasSideEffects = 0 in
926 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
927 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
928 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
929 [/* For disassembly only; pattern left blank */]> {
930 // Instruction operands.
935 // Encode instruction operands.
936 let Inst{3-0} = dst1{4-1};
937 let Inst{5} = dst1{0};
938 let Inst{15-12} = src1;
939 let Inst{19-16} = src2;
941 let Inst{7-6} = 0b00;
943 // Some single precision VFP instructions may be executed on both NEON and VFP
945 let D = VFPNeonDomain;
947 let DecoderMethod = "DecodeVMOVSRR";
953 // FMRX: SPR system reg -> GPR
955 // FMXR: GPR -> VFP system reg
960 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
961 bits<4> opcod4, dag oops, dag iops,
962 InstrItinClass itin, string opc, string asm,
964 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
966 // Instruction operands.
970 // Encode instruction operands.
971 let Inst{3-0} = Sm{4-1};
973 let Inst{15-12} = Dd{3-0};
974 let Inst{22} = Dd{4};
976 let Predicates = [HasVFP2, HasDPVFP];
979 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
980 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
981 string opc, string asm, list<dag> pattern>
982 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
984 // Instruction operands.
988 // Encode instruction operands.
989 let Inst{3-0} = Sm{4-1};
991 let Inst{15-12} = Sd{4-1};
992 let Inst{22} = Sd{0};
995 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
996 (outs DPR:$Dd), (ins SPR:$Sm),
997 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
999 let Inst{7} = 1; // s32
1002 let Predicates=[HasVFP2, HasDPVFP] in {
1003 def : VFPPat<(f64 (sint_to_fp GPR:$a)),
1004 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1006 def : VFPPat<(f64 (sint_to_fp (i32 (load addrmode5:$a)))),
1007 (VSITOD (VLDRS addrmode5:$a))>;
1010 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1011 (outs SPR:$Sd),(ins SPR:$Sm),
1012 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1014 let Inst{7} = 1; // s32
1016 // Some single precision VFP instructions may be executed on both NEON and
1017 // VFP pipelines on A8.
1018 let D = VFPNeonA8Domain;
1021 def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)),
1022 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1024 def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (load addrmode5:$a)))),
1025 (VSITOS (VLDRS addrmode5:$a))>;
1027 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1028 (outs DPR:$Dd), (ins SPR:$Sm),
1029 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
1031 let Inst{7} = 0; // u32
1034 let Predicates=[HasVFP2, HasDPVFP] in {
1035 def : VFPPat<(f64 (uint_to_fp GPR:$a)),
1036 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1038 def : VFPPat<(f64 (uint_to_fp (i32 (load addrmode5:$a)))),
1039 (VUITOD (VLDRS addrmode5:$a))>;
1042 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1043 (outs SPR:$Sd), (ins SPR:$Sm),
1044 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1046 let Inst{7} = 0; // u32
1048 // Some single precision VFP instructions may be executed on both NEON and
1049 // VFP pipelines on A8.
1050 let D = VFPNeonA8Domain;
1053 def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)),
1054 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1056 def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (load addrmode5:$a)))),
1057 (VUITOS (VLDRS addrmode5:$a))>;
1061 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1062 bits<4> opcod4, dag oops, dag iops,
1063 InstrItinClass itin, string opc, string asm,
1065 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1067 // Instruction operands.
1071 // Encode instruction operands.
1072 let Inst{3-0} = Dm{3-0};
1073 let Inst{5} = Dm{4};
1074 let Inst{15-12} = Sd{4-1};
1075 let Inst{22} = Sd{0};
1077 let Predicates = [HasVFP2, HasDPVFP];
1080 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1081 bits<4> opcod4, dag oops, dag iops,
1082 InstrItinClass itin, string opc, string asm,
1084 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1086 // Instruction operands.
1090 // Encode instruction operands.
1091 let Inst{3-0} = Sm{4-1};
1092 let Inst{5} = Sm{0};
1093 let Inst{15-12} = Sd{4-1};
1094 let Inst{22} = Sd{0};
1097 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
1098 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1099 (outs SPR:$Sd), (ins DPR:$Dm),
1100 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1102 let Inst{7} = 1; // Z bit
1105 let Predicates=[HasVFP2, HasDPVFP] in {
1106 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
1107 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
1109 def : VFPPat<(store (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
1110 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
1113 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1114 (outs SPR:$Sd), (ins SPR:$Sm),
1115 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1117 let Inst{7} = 1; // Z bit
1119 // Some single precision VFP instructions may be executed on both NEON and
1120 // VFP pipelines on A8.
1121 let D = VFPNeonA8Domain;
1124 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1125 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1127 def : VFPNoNEONPat<(store (i32 (fp_to_sint (f32 SPR:$a))), addrmode5:$ptr),
1128 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1130 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1131 (outs SPR:$Sd), (ins DPR:$Dm),
1132 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1134 let Inst{7} = 1; // Z bit
1137 let Predicates=[HasVFP2, HasDPVFP] in {
1138 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
1139 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
1141 def : VFPPat<(store (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
1142 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
1145 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1146 (outs SPR:$Sd), (ins SPR:$Sm),
1147 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1149 let Inst{7} = 1; // Z bit
1151 // Some single precision VFP instructions may be executed on both NEON and
1152 // VFP pipelines on A8.
1153 let D = VFPNeonA8Domain;
1156 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1157 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1159 def : VFPNoNEONPat<(store (i32 (fp_to_uint (f32 SPR:$a))), addrmode5:$ptr),
1160 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1162 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1163 let Uses = [FPSCR] in {
1164 // FIXME: Verify encoding after integrated assembler is working.
1165 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1166 (outs SPR:$Sd), (ins DPR:$Dm),
1167 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1168 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1169 let Inst{7} = 0; // Z bit
1172 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1173 (outs SPR:$Sd), (ins SPR:$Sm),
1174 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1175 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1176 let Inst{7} = 0; // Z bit
1179 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1180 (outs SPR:$Sd), (ins DPR:$Dm),
1181 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1182 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1183 let Inst{7} = 0; // Z bit
1186 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1187 (outs SPR:$Sd), (ins SPR:$Sm),
1188 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1189 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1190 let Inst{7} = 0; // Z bit
1194 // Convert between floating-point and fixed-point
1195 // Data type for fixed-point naming convention:
1196 // S16 (U=0, sx=0) -> SH
1197 // U16 (U=1, sx=0) -> UH
1198 // S32 (U=0, sx=1) -> SL
1199 // U32 (U=1, sx=1) -> UL
1201 let Constraints = "$a = $dst" in {
1203 // FP to Fixed-Point:
1205 // Single Precision register
1206 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1207 bit op5, dag oops, dag iops, InstrItinClass itin,
1208 string opc, string asm, list<dag> pattern>
1209 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1210 Sched<[WriteCvtFP]> {
1212 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1213 let Inst{22} = dst{0};
1214 let Inst{15-12} = dst{4-1};
1217 // Double Precision register
1218 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1219 bit op5, dag oops, dag iops, InstrItinClass itin,
1220 string opc, string asm, list<dag> pattern>
1221 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1222 Sched<[WriteCvtFP]> {
1224 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1225 let Inst{22} = dst{4};
1226 let Inst{15-12} = dst{3-0};
1228 let Predicates = [HasVFP2, HasDPVFP];
1231 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1232 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1233 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1234 // Some single precision VFP instructions may be executed on both NEON and
1235 // VFP pipelines on A8.
1236 let D = VFPNeonA8Domain;
1239 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1240 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1241 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1242 // Some single precision VFP instructions may be executed on both NEON and
1243 // VFP pipelines on A8.
1244 let D = VFPNeonA8Domain;
1247 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1248 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1249 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1250 // Some single precision VFP instructions may be executed on both NEON and
1251 // VFP pipelines on A8.
1252 let D = VFPNeonA8Domain;
1255 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1256 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1257 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1258 // Some single precision VFP instructions may be executed on both NEON and
1259 // VFP pipelines on A8.
1260 let D = VFPNeonA8Domain;
1263 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1264 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1265 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1267 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1268 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1269 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1271 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1272 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1273 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1275 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1276 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1277 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1279 // Fixed-Point to FP:
1281 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1282 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1283 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1284 // Some single precision VFP instructions may be executed on both NEON and
1285 // VFP pipelines on A8.
1286 let D = VFPNeonA8Domain;
1289 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1290 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1291 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1292 // Some single precision VFP instructions may be executed on both NEON and
1293 // VFP pipelines on A8.
1294 let D = VFPNeonA8Domain;
1297 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1298 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1299 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1300 // Some single precision VFP instructions may be executed on both NEON and
1301 // VFP pipelines on A8.
1302 let D = VFPNeonA8Domain;
1305 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1306 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1307 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1308 // Some single precision VFP instructions may be executed on both NEON and
1309 // VFP pipelines on A8.
1310 let D = VFPNeonA8Domain;
1313 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1314 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1315 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1317 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1318 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1319 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1321 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1322 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1323 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1325 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1326 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1327 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1329 } // End of 'let Constraints = "$a = $dst" in'
1331 //===----------------------------------------------------------------------===//
1332 // FP Multiply-Accumulate Operations.
1335 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1336 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1337 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1338 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1339 (f64 DPR:$Ddin)))]>,
1340 RegConstraint<"$Ddin = $Dd">,
1341 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1343 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1344 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1345 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1346 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1348 RegConstraint<"$Sdin = $Sd">,
1349 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1350 // Some single precision VFP instructions may be executed on both NEON and
1351 // VFP pipelines on A8.
1352 let D = VFPNeonA8Domain;
1355 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1356 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1357 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1358 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1359 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1360 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1362 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1363 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1364 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1365 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1366 (f64 DPR:$Ddin)))]>,
1367 RegConstraint<"$Ddin = $Dd">,
1368 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1370 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1371 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1372 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1373 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1375 RegConstraint<"$Sdin = $Sd">,
1376 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1377 // Some single precision VFP instructions may be executed on both NEON and
1378 // VFP pipelines on A8.
1379 let D = VFPNeonA8Domain;
1382 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1383 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1384 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1385 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1386 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1387 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1389 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1390 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1391 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1392 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1393 (f64 DPR:$Ddin)))]>,
1394 RegConstraint<"$Ddin = $Dd">,
1395 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1397 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1398 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1399 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1400 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1402 RegConstraint<"$Sdin = $Sd">,
1403 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1404 // Some single precision VFP instructions may be executed on both NEON and
1405 // VFP pipelines on A8.
1406 let D = VFPNeonA8Domain;
1409 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1410 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1411 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1412 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1413 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1414 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1416 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1417 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1418 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1419 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1420 (f64 DPR:$Ddin)))]>,
1421 RegConstraint<"$Ddin = $Dd">,
1422 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1424 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1425 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1426 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1427 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1428 RegConstraint<"$Sdin = $Sd">,
1429 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1430 // Some single precision VFP instructions may be executed on both NEON and
1431 // VFP pipelines on A8.
1432 let D = VFPNeonA8Domain;
1435 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1436 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1437 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1438 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1439 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1440 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1442 //===----------------------------------------------------------------------===//
1443 // Fused FP Multiply-Accumulate Operations.
1445 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1446 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1447 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1448 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1449 (f64 DPR:$Ddin)))]>,
1450 RegConstraint<"$Ddin = $Dd">,
1451 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1453 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1454 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1455 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1456 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1458 RegConstraint<"$Sdin = $Sd">,
1459 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1460 // Some single precision VFP instructions may be executed on both NEON and
1464 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1465 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1466 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1467 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1468 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1469 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1471 // Match @llvm.fma.* intrinsics
1472 // (fma x, y, z) -> (vfms z, x, y)
1473 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1474 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1475 Requires<[HasVFP4,HasDPVFP]>;
1476 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1477 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1478 Requires<[HasVFP4]>;
1480 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1481 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1482 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1483 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1484 (f64 DPR:$Ddin)))]>,
1485 RegConstraint<"$Ddin = $Dd">,
1486 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1488 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1489 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1490 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1491 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1493 RegConstraint<"$Sdin = $Sd">,
1494 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1495 // Some single precision VFP instructions may be executed on both NEON and
1499 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1500 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1501 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1502 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1503 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1504 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1506 // Match @llvm.fma.* intrinsics
1507 // (fma (fneg x), y, z) -> (vfms z, x, y)
1508 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1509 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1510 Requires<[HasVFP4,HasDPVFP]>;
1511 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1512 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1513 Requires<[HasVFP4]>;
1514 // (fma x, (fneg y), z) -> (vfms z, x, y)
1515 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1516 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1517 Requires<[HasVFP4,HasDPVFP]>;
1518 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1519 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1520 Requires<[HasVFP4]>;
1522 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1523 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1524 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1525 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1526 (f64 DPR:$Ddin)))]>,
1527 RegConstraint<"$Ddin = $Dd">,
1528 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1530 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1531 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1532 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1533 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1535 RegConstraint<"$Sdin = $Sd">,
1536 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1537 // Some single precision VFP instructions may be executed on both NEON and
1541 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1542 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1543 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1544 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1545 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1546 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1548 // Match @llvm.fma.* intrinsics
1549 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1550 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1551 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1552 Requires<[HasVFP4,HasDPVFP]>;
1553 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1554 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1555 Requires<[HasVFP4]>;
1556 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1557 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1558 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1559 Requires<[HasVFP4,HasDPVFP]>;
1560 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1561 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1562 Requires<[HasVFP4]>;
1564 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1565 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1566 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1567 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1568 (f64 DPR:$Ddin)))]>,
1569 RegConstraint<"$Ddin = $Dd">,
1570 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1572 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1573 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1574 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1575 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1576 RegConstraint<"$Sdin = $Sd">,
1577 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1578 // Some single precision VFP instructions may be executed on both NEON and
1582 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1583 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1584 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1585 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1586 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1587 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1589 // Match @llvm.fma.* intrinsics
1591 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1592 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1593 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1594 Requires<[HasVFP4,HasDPVFP]>;
1595 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1596 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1597 Requires<[HasVFP4]>;
1598 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1599 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1600 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1601 Requires<[HasVFP4,HasDPVFP]>;
1602 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1603 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1604 Requires<[HasVFP4]>;
1605 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1606 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1607 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1608 Requires<[HasVFP4,HasDPVFP]>;
1609 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1610 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1611 Requires<[HasVFP4]>;
1613 //===----------------------------------------------------------------------===//
1614 // FP Conditional moves.
1617 let hasSideEffects = 0 in {
1618 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
1620 [(set (f64 DPR:$Dd),
1621 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1622 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>;
1624 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1626 [(set (f32 SPR:$Sd),
1627 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1628 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
1631 //===----------------------------------------------------------------------===//
1632 // Move from VFP System Register to ARM core register.
1635 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1637 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1639 // Instruction operand.
1642 let Inst{27-20} = 0b11101111;
1643 let Inst{19-16} = opc19_16;
1644 let Inst{15-12} = Rt;
1645 let Inst{11-8} = 0b1010;
1647 let Inst{6-5} = 0b00;
1649 let Inst{3-0} = 0b0000;
1652 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1654 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1655 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1656 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1658 // Application level FPSCR -> GPR
1659 let hasSideEffects = 1, Uses = [FPSCR] in
1660 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1661 "vmrs", "\t$Rt, fpscr",
1662 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1664 // System level FPEXC, FPSID -> GPR
1665 let Uses = [FPSCR] in {
1666 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1667 "vmrs", "\t$Rt, fpexc", []>;
1668 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1669 "vmrs", "\t$Rt, fpsid", []>;
1670 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1671 "vmrs", "\t$Rt, mvfr0", []>;
1672 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1673 "vmrs", "\t$Rt, mvfr1", []>;
1674 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
1675 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
1676 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1677 "vmrs", "\t$Rt, fpinst", []>;
1678 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1679 "vmrs", "\t$Rt, fpinst2", []>;
1682 //===----------------------------------------------------------------------===//
1683 // Move from ARM core register to VFP System Register.
1686 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1688 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1690 // Instruction operand.
1693 // Encode instruction operand.
1694 let Inst{15-12} = src;
1696 let Inst{27-20} = 0b11101110;
1697 let Inst{19-16} = opc19_16;
1698 let Inst{11-8} = 0b1010;
1703 let Defs = [FPSCR] in {
1704 // Application level GPR -> FPSCR
1705 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1706 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1707 // System level GPR -> FPEXC
1708 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1709 "vmsr", "\tfpexc, $src", []>;
1710 // System level GPR -> FPSID
1711 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1712 "vmsr", "\tfpsid, $src", []>;
1714 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1715 "vmsr", "\tfpinst, $src", []>;
1716 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1717 "vmsr", "\tfpinst2, $src", []>;
1720 //===----------------------------------------------------------------------===//
1724 // Materialize FP immediates. VFP3 only.
1725 let isReMaterializable = 1 in {
1726 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1727 VFPMiscFrm, IIC_fpUNA64,
1728 "vmov", ".f64\t$Dd, $imm",
1729 [(set DPR:$Dd, vfp_f64imm:$imm)]>,
1730 Requires<[HasVFP3,HasDPVFP]> {
1734 let Inst{27-23} = 0b11101;
1735 let Inst{22} = Dd{4};
1736 let Inst{21-20} = 0b11;
1737 let Inst{19-16} = imm{7-4};
1738 let Inst{15-12} = Dd{3-0};
1739 let Inst{11-9} = 0b101;
1740 let Inst{8} = 1; // Double precision.
1741 let Inst{7-4} = 0b0000;
1742 let Inst{3-0} = imm{3-0};
1745 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1746 VFPMiscFrm, IIC_fpUNA32,
1747 "vmov", ".f32\t$Sd, $imm",
1748 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1752 let Inst{27-23} = 0b11101;
1753 let Inst{22} = Sd{0};
1754 let Inst{21-20} = 0b11;
1755 let Inst{19-16} = imm{7-4};
1756 let Inst{15-12} = Sd{4-1};
1757 let Inst{11-9} = 0b101;
1758 let Inst{8} = 0; // Single precision.
1759 let Inst{7-4} = 0b0000;
1760 let Inst{3-0} = imm{3-0};
1764 //===----------------------------------------------------------------------===//
1765 // Assembler aliases.
1767 // A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to
1768 // support them all, but supporting at least some of the basics is
1769 // good to be friendly.
1770 def : VFP2MnemonicAlias<"flds", "vldr">;
1771 def : VFP2MnemonicAlias<"fldd", "vldr">;
1772 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1773 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1774 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1775 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1776 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1777 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1778 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1779 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1780 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1781 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1782 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1783 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1784 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1785 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1786 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1787 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1788 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1789 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1790 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1791 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1792 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1793 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1794 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1795 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1796 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1797 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1798 def : VFP2MnemonicAlias<"fsts", "vstr">;
1799 def : VFP2MnemonicAlias<"fstd", "vstr">;
1800 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1801 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1802 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1803 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1804 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1805 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1806 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1807 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1808 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1809 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1811 // Be friendly and accept the old form of zero-compare
1812 def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1813 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1816 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1817 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1818 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1819 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
1820 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1821 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1822 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1823 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1824 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1826 // No need for the size suffix on VSQRT. It's implied by the register classes.
1827 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1828 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1830 // VLDR/VSTR accept an optional type suffix.
1831 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1832 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1833 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1834 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1835 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1836 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1837 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1838 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1840 // VMOV can accept optional 32-bit or less data type suffix suffix.
1841 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1842 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1843 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1844 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1845 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1846 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1847 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1848 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1849 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1850 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1851 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1852 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1854 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1855 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1856 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1857 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1859 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1861 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1862 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
1864 // FCONSTD/FCONSTS alias for vmov.f64/vmov.f32
1865 // These aliases provide added functionality over vmov.f instructions by
1866 // allowing users to write assembly containing encoded floating point constants
1867 // (e.g. #0x70 vs #1.0). Without these alises there is no way for the
1868 // assembler to accept encoded fp constants (but the equivalent fp-literal is
1869 // accepted directly by vmovf).
1870 def : VFP3InstAlias<"fconstd${p} $Dd, $val",
1871 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;
1872 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
1873 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;